Pixel array, image sensor and electronic device

Abstract

The invention provides a pixel array, an image sensor and an electronic device. The pixel array includes: a plurality of pixels in a matrix, the plurality of pixels including: a first pixel, a second pixel, and a third pixel adjacent to the second pixel; and a plurality of microlenses including a first microlens and a second microlens. Each of the plurality of pixels includes a plurality of photoelectric conversion elements adjacent to each other in a first direction. A first microlens extends across the plurality of photoelectric conversion elements of the first pixel, and a second microlens extends in a first direction or a second direction across the second pixel and the third pixel.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0111143 filed on August 24, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a pixel array, an image sensor, and an electronic device. Background Art

[0003] The image sensor is a device that converts an optical signal into an electrical signal, and may include a charge coupled device (CCD) image sensor, a complementary metal oxide semiconductor (CMOS) image sensor, and the like.

[0004] An auto focus (AF) function that automatically focuses on a subject may be utilized in an image sensor. Phase difference auto focus (PAF) may be used to adjust focus based on a phase difference of light signals detected at different positions. Summary of the invention

[0005] The embodiment provides an image sensor operating in a plurality of auto focus modes in consideration of accuracy and speed, and an electronic device controlling the image sensor.

[0006] According to aspects of the embodiments, a pixel array includes: a plurality of pixels in a matrix, the plurality of pixels including a first pixel, a second pixel, and a third pixel adjacent to the second pixel; a plurality of microlenses, the plurality of microlenses including a first microlens and a second microlens. Each of the plurality of pixels includes a plurality of photoelectric conversion elements adjacent to each other in a first direction. The first microlens extends across the plurality of photoelectric conversion elements of the first pixel, and the second microlens extends across the second pixel and the third pixel in the first direction or the second direction.

[0007] According to another aspect of the embodiment, an image sensor includes: a pixel array including: a plurality of pixels in a matrix and a plurality of microlenses, the plurality of pixels including a first pixel, a second pixel, and a third pixel adjacent to the second pixel, and the plurality of microlenses including a first microlens and a second microlens; a row decoder circuit configured to: provide a transmission control signal to the pixel array through a plurality of control signal lines; a control logic circuit configured to: control the row decoder circuit; and an image signal processing logic circuit configured to: output image data and phase data based on the output of the pixel array. Each of the plurality of pixels includes a plurality of photoelectric conversion elements adjacent to each other in a first direction. The first microlens extends across the plurality of photoelectric conversion elements of the first pixel, and the second microlens extends across the second pixel and the third pixel in the first direction or the second direction.

[0008] According to another aspect of the embodiment, an electronic device includes: an image sensing device, including: a pixel array, the pixel array includes a plurality of pixels in a matrix, a plurality of microlenses, and a logic circuit configured to control the pixel array, and the image sensing device is configured to output image data and phase data based on the output of the pixel array; and a processor, configured to: receive image data and phase data from the image sensing device, obtain parallax of the phase data based on the phase data, and provide a control signal to the image sensing device based on the parallax. The pixel array includes a plurality of pixel groups, the plurality of pixel groups include the plurality of pixels. The plurality of pixels include a first pixel, a second pixel, and a third pixel adjacent to the second pixel. The plurality of microlenses include a first microlens and a second microlens. Each of the plurality of pixels includes a plurality of photoelectric conversion elements adjacent to each other in a first direction. The first microlens extends across the plurality of photoelectric conversion elements of the first pixel, and the second microlens extends across the second pixel and the third pixel in the first direction or the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features will become more apparent from the following description of embodiments with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram of an image sensor according to an embodiment.

[0011] Figure 2 A pixel array according to an embodiment is shown.

[0012] Figure 3 is a cross-sectional view of a pixel array according to an embodiment.

[0013] Figure 4 is a circuit diagram of a pixel according to an embodiment.

[0014] Figure 5A and Figure 5B is a diagram for describing the operation of an image sensor according to an embodiment.

[0015] Fig. 6A and Figure 6B is a diagram for describing the operation of an image sensor according to an embodiment.

[0016] Fig. 7A and Figure 7B is a diagram for describing the operation of an image sensor according to an embodiment.

[0017] Figure 8 is a block diagram depicting image signal processing logic according to an embodiment.

[0018] Fig. 9 and Fig.10 is a diagram for describing an output operation of an image sensor according to an embodiment.

[0019] Figures 11 to 15 A pixel array according to an embodiment is shown.

[0020] Fig.16 and Fig.17 is a block diagram of an image sensor according to an embodiment.

[0021] Fig.18 is a block diagram of an electronic device according to an embodiment.

[0022] Fig.19 is a block diagram of an application processor according to an embodiment.

[0023] Fig. 20 is a block diagram of a camera module of an electronic device according to an embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described in conjunction with the accompanying drawings. The embodiments described herein are example embodiments, and therefore the present disclosure is not limited thereto, and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of other examples or other embodiments that are also provided herein or not provided herein but consistent with the present disclosure. When a statement such as "at least one of ..." is after a column of elements, the entire column of elements is modified rather than the individual elements in the modified column. For example, the statement "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all a, b, and c. It will also be understood that even if a particular step or operation of a manufacturing device or structure is described as later than another step or operation, unless another step or operation is described as being performed after the step or operation, the step or operation may also be performed earlier than another step or operation.

[0025] Figure 1 1 is a block diagram illustrating an image sensor 100 according to an embodiment. Figure 1 The image sensor 100 may include a pixel array 110 , a row driver (or row decoder circuit) 120 , a timing controller (or control logic circuit) 130 , a readout circuit 140 , an image signal processing logic 150 , and an interface circuit 160 .

[0026] The pixel array 110 includes a plurality of pixels. The plurality of pixels may be arranged, for example, in a matrix. The pixel array 110 may receive a plurality of pixel drive signals CSn (such as a selection signal, a reset signal, and a transfer control signal) from a row driver 120 (for example, through a plurality of control signal lines). The pixel array 110 may operate under the control of the received pixel drive signal CSn. Each of the pixels of the image sensor 100 may convert an optical signal into an electrical signal through a photoelectric conversion element. The electrical signals respectively generated by the pixels may be provided to a readout circuit 140 through a plurality of column lines CLm. The readout circuit 140 includes an analog-to-digital converter.

[0027] The photoelectric conversion element may be a photodiode (PD). The photodiode may be a photoelectric conversion element that generates a charge in proportion to a light signal incident on a pixel. Each pixel may accumulate a corresponding charge. The photoelectric conversion element may include one or a combination of a photodiode (PD), a photocapacitor, a photogate, a pinned photodiode (PPD), a partially pinned photodiode, an organic photodiode (OPD), and a quantum diode (QD). The embodiment will be described under the condition that the photoelectric conversion element is a photodiode (PD). However, other photoelectric conversion elements including the above-mentioned photoelectric conversion elements may be used as the photoelectric conversion element, and the photoelectric conversion element is not limited to the photodiode (PD).

[0028] Each of the plurality of pixels of the image sensor 100 according to the embodiment includes a plurality of photoelectric conversion elements. Each of the pixels includes at least two photoelectric conversion elements. The plurality of photoelectric conversion elements of each pixel may be disposed adjacent to each other in one of the row direction and the column direction of the pixel array 110.

[0029] At least two photoelectric conversion elements of each pixel may generate photoelectrons independently of each other. Depending on the autofocus mode, the photoelectric conversion elements of the pixels may generate separate pixel signals respectively, or may generate integrated pixel signals. For example, in one mode, the pixel may generate a single integrated pixel signal. For example, in another mode, the pixel may generate a plurality of pixel signals corresponding to the photoelectric conversion elements respectively.

[0030] In a portion of the plurality of pixels, a plurality of photoelectric conversion elements of one pixel share the same microlens. For example, in the first pixel PXa, at least one first photoelectric conversion element PDL disposed in the left direction (or upper direction) of the microlens ML1 relative to the optical axis and at least one second photoelectric conversion element PDR disposed in the right direction (or lower direction) of the microlens ML1 relative to the optical axis may share the same single microlens ML1. For example, the microlens ML1 may extend across the first photoelectric conversion element PDL and the second photoelectric conversion element PDR of the first pixel PXa.

[0031] In other pixels among the plurality of pixels, two pixels share one microlens. Therefore, at least four photoelectric conversion elements share one microlens. For example, the first photoelectric conversion element PDL and the second photoelectric conversion element PDR of the second pixel PXb may be disposed in the left direction of the microlens ML2 relative to the optical axis. The first photoelectric conversion element PDL and the second photoelectric conversion element PDR of the third pixel PXc may be disposed in the right direction of the microlens ML2 relative to the optical axis. Therefore, the third pixel PXc may be disposed adjacent to the second pixel PXb in the row direction. The second pixel PXb and the third pixel PXc may share the same single microlens ML2. For example, the microlens ML2 may span the second pixel PXb and the third pixel PXc in the first direction D1 (such as Figure 2 ) or the second direction D2 (as shown in Figure 2 ) as shown in the figure.

[0032] Figure 1 2 shows an example in which the third pixel PXc is disposed adjacent to the second pixel PXb in the row direction. However, according to an embodiment, the third pixel PXc may be disposed adjacent to the second pixel PXb in the column direction.

[0033] When multiple photoelectric conversion elements of a pixel share a microlens, the pixel may be referred to as a dual photodiode pixel. For example, the first pixel PXa may be referred to as a dual photodiode pixel. When multiple pixels share a microlens, the multiple pixels may constitute a super photodiode pixel. For example, the second pixel PXb and the third pixel PXc may be collectively referred to as a super photodiode pixel SPD.

[0034] The plurality of pixels constituting the super photodiode pixel may be disposed adjacent to each other in a row direction or a column direction. One of the plurality of pixels constituting the super photodiode pixel may be disposed adjacent to the dual photodiode pixel.

[0035] The row driver 120 may select one of the rows of the pixel array 110 under the control of the timing controller 130. The row driver 120 may generate a selection signal for the purpose of selecting one of the plurality of rows. The row driver 120 may activate the pixels corresponding to the selected row. The pixel signals sampled from the pixels of the selected row may be transmitted to the analog-to-digital converter of the readout circuit 140. The pixel signal may include a reset level signal and a pixel level signal.

[0036] The row driver 120 of the image sensor 100 according to the embodiment may allow a plurality of photoelectric conversion elements of each pixel to operate differently according to the auto focus mode control signal AF_MODE. The image sensor 100 may operate in a plurality of auto focus modes.

[0037] For example, in the first autofocus mode, the row driver 120 may control the multiple photoelectric conversion elements of each pixel to operate independently of each other. Therefore, pixel data may be generated based on the photoelectrons of the multiple photoelectric conversion elements of each pixel. In this case, phase data may be generated based on the pixel data of the dual photodiode pixel. That is, phase data may be generated based on the photoelectrons generated by each of the first photoelectric conversion element PDL and the second photoelectric conversion element PDR of the first pixel PXa.

[0038] For example, in the second auto focus mode, the row driver 120 may control a plurality of photoelectric conversion elements of each pixel to operate simultaneously for each pixel. Therefore, pixel data may be generated in units of pixels. In this case, phase data may be generated based on pixel data of the second pixel PXb and the third pixel PXc constituting the super photodiode pixel SPD. That is, each of the second pixel PXb and the third pixel PXc may not generate pixel data for each photoelectric conversion element. Phase data may be generated based on pixel data generated from the second pixel PXb and pixel data generated from the third pixel PXc.

[0039] In the first auto focus mode, the focus of the camera can be adjusted by using phase data based on each of a plurality of photoelectric conversion elements of a dual photodiode pixel. Therefore, auto focus can be accurately performed. In the second auto focus mode, the focus of the camera can be adjusted by using phase data based on each of pixels constituting a super photodiode pixel. Therefore, auto focus can be performed at high speed, and image data can be provided at a high frame rate. Therefore, an auto focus mode suitable for the characteristics of an application or a shooting environment can be selected from a plurality of auto focus modes.

[0040] The analog-to-digital converter of the readout circuit 140 may convert the reset level signal and the pixel level signal into digital signals. For example, the analog-to-digital converter may sample the reset level signal and the pixel level signal in a correlated double sampling manner, and may convert the sampling result into pixel data as a digital signal. To this end, a correlated double sampler (CDS) may also be provided in front of the analog-to-digital converter.

[0041] In the pixels of the image sensor 100 according to the embodiment, the pixel level signal may be sampled for each photoelectric conversion element or for each pixel. In addition, the reset level signal may be sampled for each photoelectric conversion element or for each pixel.

[0042] The readout circuit 140 may include an output buffer. The output buffer may latch the digitally converted pixel data for each column so as to be provided to the image signal processing logic 150. The output buffer may temporarily store the pixel data under the control of the timing controller 130, and may provide the sequentially stored pixel data to the image signal processing logic 150.

[0043] The timing controller 130 may control the pixel array 110, the row driver 120, the readout circuit 140, and the image signal processing logic 150. The timing controller 130 may provide a timing control signal TC to the row driver 120. The timing controller 130 may provide a reference code RC to the readout circuit 140. The timing controller 130 may provide a control signal PC and an auto focus mode control signal AF_MODE to the image signal processing logic 150. The timing controller 130 may include a logic control circuit, a phase locked loop (PLL) circuit, and / or a timing control circuit, etc.

[0044] The image signal processing logic 150 may process the pixel data to generate image data and phase data. The image signal processing logic 150 may output the image data and phase data through the interface circuit 160.

[0045] In response to the auto focus mode control signal AF_MODE, the image signal processing logic 150 according to the embodiment may generate phase data based on the outputs of different pixels. For example, in the first auto focus mode, the image signal processing logic 150 may generate phase data based on the pixel data of the dual photodiode pixel PXa. In the second auto focus mode, the image signal processing logic 150 may generate phase data based on the pixel data of the pixels PXb and PXc constituting the super photodiode pixel SPD. Figure 8 This is described in detail.

[0046] The application processor may be provided with image data and phase data from the image signal processing logic 150 through the interface circuit 160. The application processor may process the image data to be displayed on a display or to be stored as an image file. The application processor may calculate the parallax by calculating the phase difference based on the phase data. The application processor may perform an auto focus function of the camera based on the parallax.

[0047] Figure 2 A portion of a pixel array according to an embodiment is shown.

[0048] Reference Figure 2 , the pixel array 110_2 according to the embodiment may include a plurality of pixel groups PXG1 and PXG2. Figure 21 and 2 as an example, but the pixel array 110_2 may further include pixel groups other than the pixel groups PXG1 and PXG2. Some of the further included pixel groups may have the same pixel layout as the pixel groups PXG1 and PXG2, or may have the same pixel layout as that of the pixel groups PXG1 and PXG2. Figures 11 to 14 One of the pixel layouts of the described embodiments has a similar pixel layout. Figure 2 The pixel array 110_2 shown in FIG.

[0049] The pixel array 110_2 will be described as including a Bayer pattern color filter. However, embodiments are not limited to the Bayer pattern color filter. For example, various color filter structures such as RGBW (red, green, blue, white), RYB (red, yellow, blue), and CMYG (cyan, magenta, yellow, green) may be included.

[0050] For example, each of the pixel groups PXG1 and PXG2 may include a plurality of sub-pixel groups. For example, the pixel group PXG1 may include four sub-pixel groups SPXG1, SPXG2, SPXG3, and SPXG4, and the pixel group PXG2 may include four sub-pixel groups SPXG5, SPXG6, SPXG7, and SPXG8.

[0051] Each of the sub-pixel groups SPXG1, . . . , SPXG8 includes a plurality of pixels arranged in an M×N matrix (M and N are natural numbers of 2 or more). Figure 2 , in each of the sub-pixel groups SPXG1, ..., SPXG8, two pixels may be disposed adjacent to each other in the first direction D1, and two pixels may be disposed adjacent to each other in the second direction D2. In other embodiments, in each sub-pixel group, three or more pixels may be disposed adjacent to each other in the first direction D1, and three or more pixels may be disposed adjacent to each other in the second direction D2.

[0052] According to an embodiment, one of the plurality of sub-pixel groups SPXG1, ..., SPXG8 may include at least one of the pixels constituting the super photodiode pixel. For example, the sub-pixel group SPXG4 of the sub-pixel groups SPXG1, SPXG2, SPXG3, and SPXG4 constituting the pixel group PXG1 may include two pixels belonging to the super photodiode pixels SPD1 and SPD2 (that is, one of the pixels constituting the super photodiode pixel SPD1 and one of the pixels constituting the super photodiode pixel SPD2). In addition, the sub-pixel group SPXG7 of the sub-pixel groups SPXG5, SPXG6, SPXG7, and SPXG8 constituting the pixel group PXG2 may include two pixels belonging to the super photodiode pixels SPD1 and SPD2. That is, the sub-pixel group SPXG4 and the sub-pixel group SPXG7 share two super photodiode pixels SPD1 and SPD2. The sub-pixel group SPXG4 and the sub-pixel group SPXG7 may be included in different pixel groups PXG1 and PGX2, respectively.

[0053] Pixels constituting the same single super photodiode pixel may be respectively arranged in different pixel groups. Pixel groups in which pixels constituting the same single super photodiode pixel are arranged may be adjacent to each other. For example, two pixels constituting a super photodiode pixel SPD1 may be respectively arranged in a pixel group PXG1 and a pixel group PXG2. Two pixels PXb and PXc constituting a super photodiode pixel SPD2 may be respectively arranged in a pixel group PXG1 and a pixel group PXG2. Pixel groups PXG1 and PXG2 in which pixels constituting super photodiode pixel SPD1 or super photodiode pixel SPD2 are arranged may be adjacent to each other. As described above, pixels constituting a super photodiode pixel may be respectively arranged in different sub-pixel groups. Different sub-pixel groups may be arranged adjacent to each other and may be included in different pixel groups.

[0054] Figure 2 An example is shown in which two pixel groups PXG1 and PXG2 of the pixel array 110_2 share super photodiode pixels SPD1 and SPD2. However, the above description does not mean that super photodiode pixels are shared in all pixel groups of the pixel array 110_2. According to an embodiment, super photodiode pixels may be shared in all pixel groups of the pixel array 110_2, or super photodiode pixels may be shared in some pixel groups. That is, any pixel group may not include pixels belonging to super photodiode pixels. For example, the pixels of one or more pixel groups may be completely composed of dual photodiode pixels.

[0055] A subpixel group not provided with a super photodiode pixel from among a plurality of subpixel groups constituting a pixel group (i.e., a subpixel group including pixels completely composed of dual photodiode pixels) may include a color filter for transmitting light of a relevant wavelength band. For example, pixels constituting super photodiode pixels SPD1 and SPD2 may not be provided in subpixel groups SPXG1, SPXG2, and SPXG3 of pixel group PXG1. Subpixel group SPXG1 may include a green color filter "G", subpixel group SPXG2 may include a red color filter "R", and subpixel group SPXG3 may include a blue color filter "B". In pixel group PXG2, subpixel group SPXG5 may include a green color filter "G", subpixel group SPXG6 may include a red color filter "R", and subpixel group SPXG8 may include a green color filter "G".

[0056] A sub-pixel group provided with a super photodiode pixel from among a plurality of sub-pixel groups constituting a pixel group may include a color filter for transmitting light of a related wavelength band, or may include a color filter for transmitting light of a plurality of wavelength bands. For example, the sub-pixel group SPXG4 of the pixel group PXG1 may include only a green color filter "G". The sub-pixel group SPXG7 of the pixel group PXG2 may include a green color filter "G" and a blue color filter "B". For example, the pixel group PXG1 including the pixel PXb and the pixel group PXG2 including the pixel PXc may include different numbers of pixels corresponding to a common color filter (e.g., a green color filter "G"). For example, each of the pixel PXb and the pixel PXc may include a color filter (e.g., a green color filter "G") that transmits light of a common wavelength band.

[0057] Therefore, sub-pixel groups that include pixels constituting the same super photodiode pixel and are adjacent to each other may differ in the number of pixels including the same color filter. For example, in the pixel array 110_2, the sub-pixel group SPXG4 among the sub-pixel groups SPXG4 and SPXG7 in which the pixels constituting the super photodiode pixels SPD1 and SPD2 are arranged may include four pixels each including a green color filter "G". In contrast, the sub-pixel group SPXG7 may include two pixels each including a green color filter "G" and two pixels each including a blue color filter "B".

[0058] In this regard, color filters from a sub-pixel group not provided with a super photodiode pixel among sub-pixel groups constituting a pixel group may be set based on a Bayer pattern. In contrast, the number of pixels according to the Bayer pattern included in a sub-pixel group provided with a super photodiode pixel may be different from the number of remaining sub-pixel groups. For example, according to the Bayer pattern, the sub-pixel group SPXG7 should include four pixels each including a blue color filter "B"; however, when super photodiode pixels SPD1 and SPD2 are set, the number of sub-pixels each including a blue color filter "B" of the pixel group SPXG7 may not be "4".

[0059] Each of the pixels constituting the super photodiode pixel according to the embodiment may include a color filter for transmitting light of the same wavelength band. That is, the pixels constituting the super photodiode pixel may include the same color filter.

[0060] For example, refer to Figure 2 , the plurality of pixel groups PXG1 and PXG2 may include two super photodiode pixels SPD1 and SPD2. The pixels constituting the super photodiode pixel SPD1 may include the same green color filter "G", respectively. The pixels PXb and PXc constituting the super photodiode pixel SPD2 may include the same green color filter "G", respectively.

[0061] The pixels constituting the super photodiode pixel according to the embodiment may be arranged adjacent to each other in the same direction as the direction in which the photoelectric conversion elements are arranged adjacent to each other. Figure 2 The plurality of photoelectric conversion elements in each pixel of may be disposed adjacent to each other in the second direction D2. In addition, the pixels PXb and PXc constituting the super photodiode pixel SPD2 may be disposed adjacent to each other in the second direction D2. The pixels constituting the super photodiode pixel SPD1 are disposed in the same manner as described.

[0062] The dual photodiode pixels adjacent to the super photodiode pixels may include different color filters. The dual photodiode pixels may be disposed adjacent to the super photodiode pixels in a direction in which the pixels of the super photodiode pixels are adjacent to each other. For example, the pixels PXb and PXc constituting the super photodiode pixel SPD2 are disposed adjacent to each other in the second direction D2. The dual photodiode pixels PXa and PXd are disposed adjacent to the super photodiode pixel SPD2 in the second direction D2. The dual photodiode pixels PXa and PXd include color filters for transmitting light of different wavelength bands. For example, Figure 2 As shown in FIG. 1 , the pixel PXa includes a green color filter “G”, and the pixel PXd includes a blue color filter “B”.

[0063] Figure 3 Shown is a view taken along line A-A' Figure 2 A portion corresponding to pixels PXa, PXb, PXc, PXd, PXe, and PXf in a vertical cross section of the pixel array 110_2.

[0064] The pixel array 110_2 according to an embodiment may include a first chip S1 and a second chip S2 .

[0065] The first chip S1 may include a first substrate SUB1, a circuit element LG, a first wiring structure WS1, and a first insulating layer PSV1. The first substrate SUB1 may be a semiconductor substrate. The circuit element LG may include a circuit transistor, each of which includes a gate electrode layer, a gate insulating layer, and a source / drain region. The circuit element LG may constitute a logic circuit. Part of the circuit element LG may be used to implement a reference Figure 1 At least one of the row driver 120 , the timing controller 130 , the readout circuit 140 , the image signal processing logic 150 , and the interface circuit 160 is described.

[0066] For example, the image signal processing logic 150 may be formed in the first chip S1. The image signal processing logic 150 may output image data and phase data based on pixel signals of the pixels PXa, PXb, PXc, PXd, PXe, and PXf of the second chip S2.

[0067] The second chip S2 may be stacked on the first chip S1 and may be electrically connected to the first chip S1. In one embodiment, the first chip S1 and the second chip S2 may be electrically connected through an intra-cell contact (CT) inside the pixel array 110_2. The intra-cell contact may be, for example, a Cu-Cu bonding contact. According to an embodiment, the first chip S1 and the second chip S2 may be electrically connected through a pad and a through silicon via (or through silicon via, TSV) provided in an area outside the pixel array 110_2, which will be referred to as Fig.16 Give a description.

[0068] The second chip S2 may include a second substrate SUB2, a second wiring structure WS2, a circuit element TR, and a second insulating layer PSV2.

[0069] The second substrate SUB2 may be a semiconductor substrate. The second substrate SUB2 may include a first surface FS and a second surface BS that are opposite to each other (or away from each other). The first surface FS may be a front surface of the second substrate SUB2, and the second surface BS may be a back surface of the second substrate SUB2. For example, the image sensor 100 may be a back-illuminated (BSI) CMOS image sensor in which light is incident on the back surface of the second substrate SUB2.

[0070] The circuit element TR may provide a control signal to each of the pixels PXa, PXb, PXc, PXd, PXe, and PXf, or may transmit an output of each of the pixels PXa, PXb, PXc, PXd, PXe, and PXf to the first chip S1. For example, the circuit element TR may include a reference Figure 4 At least part of the transfer transistors LTX and RTX, the reset transistor RX, the drive transistor DX, and the select transistor SX are described.

[0071] In one embodiment, in response to control signals of the row driver 120 and the timing controller 130 provided in the first chip S1 or the second chip S2, the circuit element TR may allow the pixels PXa, PXb, PXc, PXd, PXe, and PXf to operate differently according to a plurality of auto focus modes. For example, in a first auto focus mode, a plurality of photoelectric conversion elements PDL and PDR may be controlled to transfer photoelectrons to the floating diffusion region FD in different readout time periods. In a second auto focus mode, a plurality of photoelectric conversion elements PDL and PDR may be controlled to simultaneously transfer photoelectrons to the floating diffusion region FD in the same readout time period.

[0072] The pixels PXa, PXb, PXc, PXd, PXe, and PXf of the pixel array 110_2 may be formed in a second chip S2 .

[0073] A plurality of pixel isolation layers DTI extending from the second surface BS to the first surface FS may be formed in the second substrate SUB2. The pixels PXa, PXb, PXc, PXd, PXe, and PXf may be separated from each other by the pixel isolation layers DTI.

[0074] Alternatively, a plurality of element separation parts SEP extending from the first surface FS to the second surface BS to a given depth may be formed in the second substrate SUB2. The element separation part SEP may include an insulating material.

[0075] The pixel array 110_2 according to an embodiment may include pixels PXb and PXc constituting a super photodiode pixel SPD2 and a plurality of dual photodiode pixels PXa, PXd, PXe, and PXf.

[0076] Each of the pixels PXa, PXb, PXc, PXd, PXe, and PXf includes a plurality of photoelectric conversion elements PDL and PDR. Regions where the plurality of photoelectric conversion elements PDL and PDR are formed may be separated from each other by a plurality of device isolation layers TI extending from the second surface BS of the second substrate SUB2 to the first surface FS of the second substrate SUB2. The plurality of photoelectric conversion elements PDL and PDR of each of the pixels PXa, PXb, PXc, PXd, PXe, and PXf may share one floating diffusion region FD for each pixel.

[0077] The plurality of pixels PXb and PXc constituting the super photodiode pixel SPD2 share the same single microlens MLbc. Therefore, at least four photoelectric conversion elements of the plurality of pixels PXb and PXc may share the same single microlens MLbc. Each of the plurality of pixels PXb and PXc constituting the super photodiode pixel SPD2 may include a color filter for transmitting light of the same wavelength band. For example, the color filters CFb and CFc may be color filters for transmitting light of the same wavelength band.

[0078] The dual photodiode pixels PXa, PXd, PXe, and PXf include microlenses MLa, MLd, MLe, and MLf, respectively, and color filters CFa, CFd, CFe, and CFf, respectively.

[0079] The plurality of photoelectric conversion elements PDL and PDR of each of the pixels PXa, PXb, PXc, PXd, PXe, and PXf may be disposed adjacent to each other in the second direction D2. The dual photodiode pixels PXa and PXe adjacent to the super photodiode pixel SPD2 in the second direction D2 may include color filters for transmitting light of different wavelength bands, respectively. For example, the color filters CFa and CFe may be different color filters for transmitting light of different wavelength bands.

[0080] In one embodiment, according to the autofocus mode, the image signal processing logic 150 of the first chip S1 may output phase data based on the pixel signal of the super photodiode pixel SPD2 from the second chip S2, or may output phase data based on the pixel signal from the dual photodiode pixels PXa, PXd, PXe and PXf.

[0081] Figure 4 The circuit configuration of the pixels of the pixel array 110_2 is shown. Figure 4 The pixel PX can be used with Figure 2 corresponds to one of the pixels PXa, PXb, PXc, PXd, PXe and PXf.

[0082] Reference Figure 4 , the pixel PX may include a plurality of photoelectric conversion elements PDL and PDR, a plurality of transfer transistors LTX and RTX, a floating diffusion region FD, a reset transistor RX, a drive transistor DX, and a selection transistor SX.

[0083] The transfer transistor LTX electrically connects the first photoelectric conversion element PDL to the floating diffusion region FD, and the transfer transistor RTX electrically connects the second photoelectric conversion element PDR to the floating diffusion region FD.

[0084] The transfer transistors LTX and RTX according to the embodiment operate differently according to the auto focus mode. The control signals LTG and RTG, which respectively control the transfer transistors LTX and RTX, are turned into a high level or a low level in different time periods.

[0085] For example, in the first auto focus mode, the transfer transistors LTX and RTX may be turned on in different readout periods, respectively. In the second auto focus mode, the transfer transistors LTX and RTX may be turned on simultaneously in the same readout period. This will be described in detail with reference to FIGS. 5 to 7.

[0086] The reset transistor RX electrically connects the floating diffusion region FD and a reset voltage VRD. The reset voltage VRD may be the same as or different from the pixel voltage VDD.

[0087] The pixel voltage VDD is used to drive the driving transistor DX. The driving transistor DX outputs an output voltage Vout corresponding to the potential formed at the floating diffusion region FD. The driving transistor DX outputs the output voltage Vout to the column line CLi through the selection transistor SX.

[0088] FIG. 5A to FIG. 7B Show according to Figure 2 The operation of the pixels of the pixel array 110_2 will be described with reference to the super photodiode pixel SPD2 and the dual photodiode pixels PXa and PXe adjacent to the super photodiode pixel SPD2. FIG. 5A to FIG. 7B .exist FIG. 5A to FIG. 7B In the example, each pixel can be represented by Figure 4 The circuit representation of FIG. 1 is described under the condition that the first photoelectric conversion element PDL and the second photoelectric conversion element PDR of each of the pixels PXa, PXb, PXc, and PXe are sequentially arranged in the second direction D2. FIG. 5A to FIG. 7B .

[0089] FIG. 5A to FIG. 6B A pixel driving method in a first auto focus mode based on dual photodiode pixels PXa and PXe to provide phase data is described. Fig. 7A and Figure 7B A pixel driving method in a second auto-focus mode based on providing phase data by a super photodiode pixel SPD2 is described.

[0090] Figure 5A and Figure 5B A pixel driving method according to an embodiment of a first automatic focusing mode is described.

[0091] Reference Figure 5A and Figure 5BAt T0, the reset signal RG and the selection signal SEL provided to the pixels PXb and PXc of the super photodiode pixel SPD2 and the dual photodiode pixels PXa and PXe are at a high level. Therefore, the reset voltage VRD is provided to the floating diffusion area FD through the reset transistor RX. The floating diffusion area FD is reset by the reset voltage level provided by the reset voltage VRD.

[0092] In the pixel driving method according to the embodiment, at T1, reset level signals R_a, R_b, R_c, and R_e of the pixels PXa, PXb, PXc, and PXe are sampled. Thereafter, at T2, the reset signal RG is turned to a low level.

[0093] At T3, in each of the pixels PXa, PXb, PXc, and PXe, the transfer transistor LTX connecting the first photoelectric conversion element PDL and the floating diffusion region FD is turned on. In each of the pixels PXa, PXb, PXc, and PXe, photoelectrons accumulated by the first photoelectric conversion element PDL are transferred to the floating diffusion region FD.

[0094] At T4, pixel level signals P_aL, P_bL, P_cL and P_eL corresponding to the potentials of the floating diffusion regions FD of the corresponding pixels PXa, PXb, PXc and PXe are output to the column line CLi. After that, the transfer transistor LTX of each of the pixels PXa, PXb, PXc and PXe is turned off.

[0095] At T5, in each of the pixels PXa, PXb, PXc, and PXe, the transfer transistor RTX connecting the second photoelectric conversion element PDR and the floating diffusion region FD is turned on. In each of the pixels PXa, PXb, PXc, and PXe, the photoelectrons accumulated by the second photoelectric conversion element PDR are transferred to the floating diffusion region FD.

[0096] At T6, pixel level signals P_aS, P_bS, P_cS, and P_eS corresponding to the potentials of the floating diffusion regions FD of the corresponding pixels PXa, PXb, PXc, and PXe, respectively, are output to the column line CLi. Each of the pixel level signals P_aS, P_bS, P_cS, and P_eS is a pixel level signal corresponding to the sum of the photoelectrons of the first photoelectric conversion element PDL and the photoelectrons of the second photoelectric conversion element PDR. After that, the transfer transistor RTX of each of the pixels PXa, PXb, PXc, and PXe is turned off.

[0097] The readout circuit 140 outputs pixel data based on the pixel level signals P_aS, P_bS, P_cS, and P_eS and the reset level signals R_a, R_b, R_c, and R_e.

[0098] The image signal processing logic 150 may generate pixel data based on the second photoelectric conversion element PDR by subtracting the value of the pixel data based on the pixel level signals P_aL and P_eL of the first photoelectric conversion element PDL from the pixel data based on the pixel level signals P_aS and P_eS. The image signal processing logic 150 may output phase data by using the pixel data based on the first photoelectric conversion element PDL and the pixel data based on the second photoelectric conversion element PDR.

[0099] The image signal processing logic 150 according to an embodiment may output phase data by using pixel data respectively corresponding to the photoelectric conversion elements of the dual photodiode pixels. Therefore, the image sensor 100 may provide accurate phase data.

[0100] Fig. 6A and Figure 6B A pixel driving method according to another embodiment of the first automatic focusing mode is described. Figure 5A and Figure 5B Additional descriptions given that the descriptions are the same will be omitted to avoid redundancy.

[0101] and Figure 5A and Figure 5B Compared with reference Fig. 6A and Figure 6B , in the driving method of the image sensor according to the embodiment, the pixel level signals P_aL, P_aR, P_bL, P_bR, P_cL, P_cR, P_eL and P_eR of the photoelectric conversion elements PDL and PDR of the pixels PXa, PXb, PXc and PXe are sampled separately. In this way, the reset level signals R_aL, R_aR, R_bL, R_bR, R_cL, R_cR, R_eL and R_eR are sampled separately. For example, the row driver may output a transmission control signal to each of the plurality of pixels in the first autofocus mode to control the pixel signal based on the photodiode of each of the plurality of pixels sampled in different output time periods. Each of the pixel signals from the same pixel is based on the pixel level signal "based on each photodiode in the same pixel", and each of the pixel level signals from the same pixel is sampled in different output time periods. For example, the pixel level signals P_aL and P_aR of PXa are both sampled and output as pixel signals in different output time periods.

[0102] At T0 , the reset transistor RX is turned on so that the floating diffusion area FD is reset; at T1 , reset level signals R_aL, R_bL, R_cL, and R_eL of the floating diffusion areas FD of the pixels PXa, PXb, PXc, and PXe are sampled.

[0103] Afterwards, at T3, the transfer transistor LTX is turned on, and thus the photoelectrons of the first photoelectric conversion elements PDL of the pixels PXa, PXb, PXc, and PXe are transferred to the corresponding floating diffusion region FD. At T4, the pixel level signals P_aL, P_bL, P_cL, and P_eL of the photoelectric conversion elements PDL of the pixels PXa, PXb, PXc, and PXe are sampled.

[0104] At T5, the floating diffusion region FD is reset again, and the reset level signals R_aR, R_bR, R_cR and R_eR of the floating diffusion regions FD of the pixels PXa, PXb, PXc and PXe are subsequently sampled. After that, at T8, the transfer transistor RTX is turned on; at T9, the photoelectrons of the second photoelectric conversion elements PDR of the pixels PXa, PXb, PXc and PXe are sampled.

[0105] The readout circuit 140 outputs pixel data based on the pixel level signals P_aL, P_aR, P_bL, P_bR, P_cL, P_cR, P_eL and P_eR and the reset level signals R_aL, R_aR, R_bL, R_bR, R_cL, R_cR, R_eL and R_eR.

[0106] The image signal processing logic 150 may output phase data by using pixel data based on the first photoelectric conversion element PDL and the second photoelectric conversion element PDR of each of the dual photodiode pixels PXa and PXe.

[0107] therefore, Fig. 6A and Figure 6B The image signal processing logic 150 may output phase data by using pixel data based on the photoelectric conversion element of each of the dual photodiode pixels PXa and PXe. The image signal processing logic 150 may output phase data without using pixel data of pixels PXb and PXc constituting the super photodiode pixel SPD2.

[0108] Fig. 7A and Figure 7B A pixel driving method according to an embodiment of the second automatic focusing mode is described. FIG. 5A to FIG. 6B Additional descriptions given that the descriptions are the same will be omitted to avoid redundancy.

[0109] and FIG. 5A to FIG. 6B Different, refer to Fig. 7A and Figure 7B, in the driving method of the image sensor according to the embodiment, the pixel level signals P_aS, P_bS, P_cS and P_eS of the pixels PXa, PXb, PXc and PXe are sampled for each pixel. In this way, the reset level signals R_aS, R_bS, R_cS and R_eS of the pixels PXa, PXb, PXc and PXe are sampled for each pixel. For example, the row driver may output a transmission control signal to each of the plurality of pixels in the second autofocus mode to control the pixel signal based on the photodiode of each of the plurality of pixels sampled simultaneously in a common output time period. For example, photons from the two photodiodes of PXa are transmitted to the floating diffusion area FD in the same output time period and are output as a pixel signal P_aS.

[0110] At T0, in each of the pixels PXa, PXb, PXc, and PXe, the floating diffusion area FD is reset by the reset voltage VRD. At T1, reset level signals R_aS, R_bS, R_cS, and R_eS of the floating diffusion areas FD of the pixels PXa, PXb, PXc, and PXe are sampled.

[0111] Afterwards, at T3, in each of the pixels PXa, PXb, PXc, and PXe, the transfer transistors LTX and RTX respectively connected to the photoelectric conversion elements PDL and PDR are turned on at the same time. In each of the pixels PXa, PXb, PXc, and PXe, the photoelectrons of the first photoelectric conversion element PDL and the second photoelectric conversion element PDR are simultaneously transferred to the floating diffusion region FD. At T4, the pixel level signals P_aS, P_bS, P_cS, and P_eS of the pixels PXa, PXb, PXc, and PXe are sampled.

[0112] The readout circuit 140 may output pixel data by using pixel level signals P_bS and P_cS and reset level signals R_bS and R_cS of the pixels PXb and PXc constituting the super photodiode pixel SPD2.

[0113] The image signal processing logic 150 can output phase data by using pixel data of pixels PXb and PXc constituting the super photodiode pixel SPD2. Phase data can be output based on pixel data of each pixel instead of pixel data of each photodiode. In addition, the image signal processing logic 150 can output phase data without using pixel data of dual photodiode pixels PXa and PXe. Therefore, autofocus can be performed at high speed. In addition, image data can also be generated based on pixel level signals and reset level signals sampled for each pixel. Therefore, even while performing autofocus, the frame rate of the captured image can be improved.

[0114] Figure 8 is a block diagram describing image signal processing logic according to an embodiment. Figure 8 The image signal processing logic described can be Figure 1 The image signal processing logic 150. Figure 8 , the image signal processing logic 150 may include a front end (FE) image signal processing logic 151 , an imaging chain block 153 , and a phase detection auto focus (PDAF) chain block 155 .

[0115] The front-end image signal processing logic 151 is provided with pixel data. The front-end image signal processing logic 151 may perform pre-processing on the pixel data so as to be suitable for the pixel data processing format of the imaging chain block 153 and the PDAF chain block 155, and the pre-processing may include crosstalk correction, automatic dark level compensation (ADLC), digital gain processing, etc.

[0116] The imaging chain block 153 processes the pre-processed pixel data to generate image data.

[0117] The imaging chain block 153 according to an embodiment may generate image data by performing a bad pixel correction (BPC) process on pixel data corresponding to a super photodiode pixel from among the pixel data. In both the first autofocus mode based on the dual photodiode pixel and the second autofocus mode based on the super photodiode pixel, the imaging chain block 153 may generate image data by performing the BPC process on pixel data associated with the super photodiode pixel.

[0118] The imaging chain block 153 may refer to the bad pixel (BP) memory 170 for BPC processing. The BP memory 170 may be implemented with a memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a resistive memory, a one-time programmable (OTP) memory, a flash memory, or may be implemented with a register. The BP memory 170 may store information about the coordinates of the bad pixels detected in the process of testing the image sensor and the coordinates of the pixels constituting the super photodiode pixel. According to an embodiment, the information about the coordinates of the pixels constituting the super photodiode pixel may be stored in a storage space different from the storage space storing the information about the coordinates of the bad pixels.

[0119] Refer to Figure 5B and Figure 8 , the imaging chain block 153 may perform BPC processing on the pixel data of the pixels PXb and PXc constituting the super photodiode pixel SPD2.

[0120] The imaging chain block 153 may correct the pixel data of the pixels PXb and PXc based on the pixel data of the neighboring pixels of the pixels PXb and PXc. For example, the BPC process may be performed based on the average value of the pixel data of the pixels from among the neighboring pixels, each of which includes the same color filter as the pixels PXb and PXc. Alternatively, the BPC process may be performed on the pixel data based on various filtering methods (such as a median filtering method and a weighted filtering method). In addition, various BPC processing methods known in the art may be used.

[0121] As described above, the imaging chain block 153 can also be used to constitute Figure 6B The pixels PXb and PXc of the super photodiode pixel SPD2 and the components Figure 7B The BPC process is performed on the pixels PXb and PXc of the super photodiode pixel SPD2. Therefore, the imaging chain block 153 can perform the BPC process on the pixel data based on the super photodiode pixels in both the first auto focus mode and the second auto focus mode.

[0122] The imaging chain block 153 may generate image data based on the pixel data of each pixel.

[0123] For example, refer to Figure 5B , the imaging chain block 153 may generate image data based on pixel data according to the pixel level signals P_aS and PeS of the dual photodiode pixels PXa and PXe and pixel data obtained by performing BPC processing on the pixels PXb and PXc. Figure 6B , the imaging chain block 153 may calculate the pixel data of the pixel PXa based on the sum of the pixel data according to the pixel level signals P_aL and P_aR. Similarly, the imaging chain block 153 may calculate the pixel data of the pixel PXe based on the sum of the pixel data according to the pixel level signals P_eL and P_eR. The imaging chain block 153 may generate image data based on the pixel data of the pixels PXa and PXe and the pixel data obtained by performing the BPC process on the pixels PXb and PXc. In addition, referring to Figure 7B The imaging chain block 153 may generate image data based on pixel data according to the pixel level signals P_aS and PeS of the pixels PXa and PXe and pixel data obtained by performing the BPC process on the pixels PXb and PXc.

[0124] The PDAF chain block 155 according to an embodiment may generate phase data by differently processing pre-processed pixel data according to auto focus modes.

[0125] In the first auto focus mode for generating phase data based on dual photodiode pixels, the PDAF chain block 155 may generate phase data based on pixel data of a plurality of photoelectric conversion elements of the dual photodiode pixels. Figure 5B and Figure 8 , the PDAF chain block 155 may generate phase data based on pixel data of the first photoelectric conversion element PDL according to the pixels PXa and PXe and pixel data of the second photoelectric conversion element PDR according to the pixels PXa and PXe. The application processor may calculate the parallax based on the difference between the phase data of the first photoelectric conversion element PDL and the phase data of the second photoelectric conversion element PDR. According to an embodiment, the PDAF chain block 155 may generate phase data by reducing the pixel data of each of the plurality of photoelectric conversion elements of the dual photodiode pixel.

[0126] In the second auto focus mode for generating phase data based on super photodiode pixels, the PDAF chain block 155 may generate phase data based on pixel data of a plurality of pixels of the super photodiode pixels. Figure 7B and Figure 8 The PDAF chain block 155 may generate phase data based on the pixel data of the pixels PXb and PXc. The application processor may calculate the disparity based on the difference between the phase data of the pixel PXb and the phase data of the pixel PXc.

[0127] According to an embodiment, in the second auto focus mode, the PDAF chain block 155 may distinguish pixel data of a plurality of pixels constituting a super photodiode pixel from pixel data preprocessed by the reference BP memory 170. Alternatively, the front-end image signal processing logic 151 may separate pixel data of pixels constituting a super photodiode pixel so as to be provided to the PDAF chain block 155. Alternatively, the timing controller may control the readout circuit so that pixel data of pixels constituting a super photodiode pixel is selected and provided to the PDAF chain block 155.

[0128] The image signal processing logic 150 transmits the image data and the phase data to the outside of the image sensor 100 through the interface circuit 160 .

[0129] Fig. 9 and Fig.10 2 is a diagram for describing an output operation of an image sensor according to an embodiment. The image sensor outputs image data and phase data. Figure 1 The interface circuit 160 may output image data and phase data. The interface circuit 160 may be an interface circuit for sending data and receiving control signals. For example, the interface circuit 160 may comply with the Mobile Industry Processor Interface Alliance (MIPI) standard.

[0130] The interface circuit 160 according to an embodiment may transmit image data and phase data in different methods according to an auto focusing mode.

[0131] Reference Fig. 9 In the first automatic focusing mode, the interface circuit 160 can send the image data and the phase data to the outside through different virtual channels. The virtual channel can be a MIPI virtual channel.

[0132] The interface circuit 160 may send image data through the first virtual channel VC0, and may send phase data through the second virtual channel VC1. The phase data may be data reduced based on the pixel data of each of the plurality of photoelectric conversion elements of the dual photodiode pixel. For example, the phase data of one row may be generated based on the pixel data of each of the plurality of photoelectric conversion elements of the dual photodiode pixels belonging to "n" rows. Similarly, the phase data of one column may be generated based on the pixel data of each of the plurality of photoelectric conversion elements of the dual photodiode pixels belonging to "n" columns.

[0133] The interface circuit 160 may send the image data and the phase data to different virtual channels alternately in different time periods.

[0134] Reference Fig.10 In the second auto-focus mode, the interface circuit 160 may send the image data and the phase data to the outside through the same virtual channel. The virtual channel may be a MIPI virtual channel. The phase data may be phase data based on the pixel data of the pixels constituting the super photodiode pixel.

[0135] The interface circuit 160 may add phase data (e.g., phase data corresponding to the super photodiode pixel SPD) as a tail of the image data, and may send the phase data to the same virtual channel as the image data (e.g., a common virtual channel). The interface circuit 160 may add a packet header and a packet trailer to the image data. The interface circuit 160 may also add a packet header and a packet trailer to the phase data.

[0136] Fig.11 is a diagram for describing a pixel array according to another embodiment. Fig.11 Some pixel groups of the pixel array are shown. Additional descriptions that are the same as those given with reference to the above drawings will be omitted to avoid redundancy.

[0137] With reference Figure 2 Unlike the pixel array 110_2 described above, in the pixel array 110_3 according to the exemplary embodiment, as shown in FIG. Fig.11 As shown in FIG. 1 , a plurality of pixel groups PXG1 and PXG2 adjacent to each other may share one super photodiode pixel SPD.

[0138] The pixel group PXG1 includes pixels PXb constituting super photodiode pixels SPD. The pixel group PXG2 includes pixels PXc constituting super photodiode pixels SPD.

[0139] Each of the pixels of the pixel array 110_3 includes a plurality of photoelectric conversion elements.

[0140] The pixels PXb and PXc constituting the super photodiode pixel SPD are disposed adjacent to each other in the same direction as the direction in which the plurality of photoelectric conversion elements are adjacent to each other.

[0141] The pixels PXb and PXc constituting the super photodiode pixel SPD may respectively include color filters for transmitting light of the same wavelength band.

[0142] The pixels PXb and PXc constituting the super photodiode pixel SPD share the same single microlens. In a dual photodiode pixel (eg, PXa), a plurality of photoelectric conversion elements share the same single microlens.

[0143] According to an embodiment, super photodiode pixels may be shared in all pixel groups of the pixel array 110_3, or may be shared in some pixel groups.

[0144] Fig.12 is a diagram for describing a pixel array according to another embodiment. Fig.12 Some pixel groups of the pixel array are shown. Additional descriptions that are the same as those given with reference to the above drawings will be omitted to avoid redundancy.

[0145] In the pixel array 110_4 according to the embodiment, as shown in FIG. Fig.12 As shown in FIG, one super photodiode pixel SPD may include four pixels PXb1, PXc1, PXb2, and PXc2.

[0146] The pixels PXb1, PXc1, PXb2, and PXc2 constituting the super photodiode pixel SPD share the same single microlens. The pixels PXb1, PXc1, PXb2, and PXc2 may respectively include color filters for transmitting light of the same wavelength band.

[0147] Part of the pixels PXb1 , PXc1 , PXb2 , and PXc2 are disposed in the pixel group PXG1 , and the remainder thereof are disposed in the pixel group PXG2 adjacent to the pixel group PXG1 .

[0148] Each of the pixels of the pixel array 110_4 includes a plurality of photoelectric conversion elements.

[0149] According to an embodiment, super photodiode pixels may be shared in all pixel groups of the pixel array 110_4, or may be shared in some pixel groups.

[0150] Fig.13 is a diagram for describing a pixel array according to another embodiment. Fig.13 Some pixel groups of the pixel array are shown. Additional descriptions that are the same as those given with reference to the above drawings will be omitted to avoid redundancy.

[0151] In the pixel array 110_5 according to the embodiment, as Fig.13 As shown in , the pixels constituting each of the super photodiode pixels SPD1 and SPD2 may be adjacent to each other in a direction different from the direction in which the plurality of photoelectric conversion elements are adjacent to each other. For example, each of the pixels of the pixel array 110_5 includes a plurality of photoelectric conversion elements adjacent to each other in the second direction D2. Each of the super photodiode pixels SPD1 and SPD2 may be disposed adjacent to each other in the first direction D1.

[0152] exist Fig.13 2 shows an example in which pixel groups PXG1 and PXG3 adjacent to each other in the first direction D1 share two super photodiode pixels SPD1 and SPD2; however, according to an embodiment, the pixel groups PXG1 and PXG3 may share one super photodiode pixel.

[0153] According to an embodiment, super photodiode pixels may be shared in all pixel groups of the pixel array 110_5, or may be shared in some pixel groups.

[0154] Fig.14 is a diagram for describing a pixel array according to another embodiment. Fig.14 Some pixel groups of the pixel array are shown. Additional descriptions that are the same as those given with reference to the above drawings will be omitted to avoid redundancy.

[0155] exist Fig.14 In the pixel array 110_6 according to the embodiment shown in , directions in which pixels of the super photodiode pixels are adjacent to each other may be different from each other.

[0156] For example, the pixels of each of the super photodiode pixels SPD1 and SPD2 may be disposed adjacent to each other in the second direction D2. The pixels of each of the super photodiode pixels SPD3 and SPD4 may be disposed adjacent to each other in the first direction D1.

[0157] In addition, the directions in which the pixel groups sharing the super photodiode pixel are adjacent to each other are different from each other. For example, the pixel groups sharing the super photodiode pixels SPD1 and SPD2 may be disposed adjacent to each other in the second direction D2. The pixel groups sharing the super photodiode pixels SPD3 and SPD4 may be disposed adjacent to each other in the first direction D1.

[0158] According to an embodiment, super photodiode pixels may be shared in all pixel groups of the pixel array 110_6, or may be shared in some pixel groups.

[0159] Fig.15 is a diagram for describing a pixel array according to another embodiment. Fig.15 Some pixel groups of the pixel array are shown. Additional descriptions that are the same as those given with reference to the above drawings will be omitted to avoid redundancy.

[0160] Fig.15 The pixel array 110_7 according to the embodiment shown in includes a plurality of pixel groups. Unlike the embodiments discussed above, each pixel group does not include a sub-pixel group. Each pixel group may include a color filter of a Bayer pattern. According to the embodiment, each pixel group may include various color filter structures (such as RGBW, RYB, and CMYG).

[0161] In one embodiment, the pixel array 110_7 may include a super photodiode pixel SPD1 composed of pixels disposed adjacent to each other in the second direction D2 and a super photodiode pixel SPD2 composed of pixels disposed adjacent to each other in the first direction D1. Therefore, the pixel groups PXG1 and PXG2 sharing the super photodiode pixel SPD1 may be adjacent to each other in the second direction D2. The pixel groups PXG3 and PXG4 sharing the super photodiode pixel SPD2 are adjacent to each other in the first direction D1.

[0162] According to an embodiment, the pixel array 110_7 may include only super photodiode pixels each consisting of pixels disposed adjacent to each other in the first direction D1. Alternatively, the pixel array 110_7 may include only super photodiode pixels each consisting of pixels disposed adjacent to each other in the second direction D2.

[0163] According to an embodiment, super photodiode pixels may be shared in all pixel groups of the pixel array 110_7, or may be shared in some pixel groups.

[0164] Fig.16 is a block diagram of an image sensor according to an embodiment. Additional descriptions identical to those given with reference to the above drawings will be omitted to avoid redundancy.

[0165] The image sensor 100_2 may include a first chip 10_2 and a second chip 20_2 .

[0166] For example, the first chip 10_2 may be stacked on the second chip 20_2 in the third direction D3. The first chip 10_2 and the second chip 20_2 may be electrically connected. For example, the first chip 10_2 and the second chip 20_2 may exchange pixel signals or control signals through through silicon vias (or through silicon vias, TSVs) placed between pads in the chip peripheral area. Figure 3 As described above, the first chip 10_2 and the second chip 20_2 may be electrically connected via intra-cell contacts. The pixel signal (or pixel data) of the first chip 10_2 may be sent to a readout circuit (or image signal processing logic) of the second chip 20_2.

[0167] The first chip 10_2 according to the embodiment may include one of the above-mentioned pixel arrays 110, 110_2, 110_3, 110_4, 110_5, 110_6 and 110_7. Each of the pixels PXa, PXb and PXc of the pixel array may include a plurality of photoelectric conversion elements PDL and PDR. The pixel array may include a dual photodiode pixel PXa and a super photodiode pixel SPD. The dual photodiode pixel PXa may include a microlens ML1. The pixels PXb and PXc constituting the super photodiode pixel SPD may share a microlens ML2. The pixels PXa, PXb and PXc of the pixel array may operate differently according to the auto focus mode and may output pixel signals.

[0168] The second chip 20_2 may include logic (such as a readout circuit, a timing controller, and an image signal processing logic) and an interface circuit. The second chip 20_2 may provide a control signal for controlling the dual photodiode pixel PXa of the pixel array or the pixels PXb and PXc constituting the super photodiode pixel to the first chip 10_2.

[0169] The image signal processing logic of the second chip 20_2 may output phase data differently according to the auto focus mode. The image signal processing logic may output phase data based on dual photodiode pixels in the first auto focus mode, and may output phase data of super photodiode pixels in the second auto focus mode.

[0170] Fig.17 is a block diagram of an image sensor according to an embodiment. Additional descriptions identical to those given with reference to the above drawings will be omitted to avoid redundancy.

[0171] Reference Fig.17, the image sensor 100_3 may further include a third chip 30_3. The third chip 30_3, the second chip 20_3, and the first chip 10_3 may be sequentially stacked in the third direction D3. The third chip 30_3 may include a memory device. For example, the third chip 30_3 may include a volatile memory device (such as a DRAM or an SRAM). The third chip 30_3 may receive signals from the first chip 10_3 and the second chip 20_3, and may process the received signals through the memory device.

[0172] Fig.18 is a block diagram of an electronic device according to an embodiment. Additional descriptions identical to those given with reference to the above drawings will be omitted to avoid redundancy.

[0173] The electronic device 1000 may include a lens 1100, an image sensor 1200, and a processor 1300. The electronic device 1000 may perform auto focusing based on phase data provided from the image sensor 1200 to the processor 1300.

[0174] The processor 1300 may control the overall operation of the electronic device 1000. The processor 1300 may provide a control signal to the lens driving part 1120 to control the position of the lens 1110. Thus, the focal length may be controlled.

[0175] The lens 1100, which is a component receiving light, may include a lens 1110 and a lens driving part 1120. The lens 1110 may include a plurality of lenses.

[0176] The lens driving part 1120 may move the lens 1110 (ie, one or more of the plurality of lenses) in a direction in which a distance from the object “S” increases or decreases based on a control signal of the processor 1300 .

[0177] The image sensor 1200 may generate image data and phase data based on incident light. The image sensor 1200 may include a pixel array 1210 , a timing controller 1220 , and an image signal processor 1230 .

[0178] The pixel array 1210 may be one of the above-described pixel arrays 110 , 110_2 , 110_3 , 110_4 , 110_5 , 110_6 , and 110_7 .

[0179] The pixel array 1210 may include dual photodiode pixels and super photodiode pixels. Each of the pixels of the pixel array 1210 includes a plurality of photoelectric conversion elements.

[0180] The pixel array 1210 according to the embodiment may operate in a plurality of auto focus modes. In the first auto focus mode, the pixel array 1210 may provide phase data based on dual photo diode pixels to the processor 1300. In the second auto focus mode, the pixel array 1210 may provide phase data based on super photo diode pixels to the processor 1300. Therefore, the electronic device 1000 according to the embodiment may selectively perform accurate auto focus or high speed auto focus according to the shooting environment.

[0181] The processor 1300 may calculate the parallax by using the phase data. Based on the parallax calculation result, the processor 1300 may provide a control signal to the lens driving part 1120 so as to move the position of the lens 1110.

[0182] The processor 1300 may provide an operation mode control signal INFO_MD and an automatic focus mode control signal AF_MODE to the timing controller 1220. The timing controller 1220 may control the operation of the pixel array 1210 based on the operation mode control signal INFO_MD and the automatic focus mode control signal AF_MODE. The automatic focus mode control signal AF_MODE is a signal that controls the image sensor 1200 to operate in a first automatic focus mode or in a second automatic focus mode.

[0183] Fig.19 is a block diagram of an application processor according to an embodiment. Additional descriptions identical to those given with reference to the above drawings will be omitted to avoid redundancy.

[0184] The application processor 1300_2 may include an image signal processing device 1310. The image signal processing device 1310 may include a plurality of image signal processors ISP1, ISP2, and ISP3, a camera module controller 1314, and a camera interface 1315. For example, the image signal processor ISP3 may receive image data from the image generator 1500.

[0185] The camera module controller 1314 may transmit control signals CSa, CSb, and CSc to the plurality of camera modules based on a mode signal and an auto focus (AF) mode signal. Fig.19 , an example in which control signals CSa, CSb, and CSc are sent to three camera modules is shown, but the present disclosure is not limited thereto. Depending on the embodiment, the camera module controller 1314 may send a control signal to one camera module, may send a control signal to two camera modules, or may send a control signal to four or more camera modules.

[0186] Image signals ISa, ISb, and ISc may be provided from a plurality of cameras through the camera interface 1315 and may be stored in the external memory 1400. The image signal processors ISP1 and ISP2 may process the image signals ISa, ISb, and ISc stored in the external memory 1400 and may control the processing result to be displayed on the display, or the image signal processors ISP1 and ISP2 may process the image signals ISa, ISb, and ISc stored in the external memory 1400 and may perform autofocus based on the processed result. The image signals ISa, ISb, and ISc may include image data and phase data. The image signals ISa, ISb, and ISc stored in the external memory 1400 may be encoded image signals. The image signal processors ISP1 and ISP2 may read the encoded image signal from the external memory 1400, may decode the encoded image signal thus read, and may display image data generated based on the decoded image signal.

[0187] Will refer to Fig. 20 The configuration of the camera module is described in detail.

[0188] Reference Fig. 20 , the camera module 1600 may include a prism 1610 , an optical path folding element (OPFE) 1620 , an actuator 1630 , an image sensing device 1640 , and a storage device 1650 .

[0189] The prism 1610 may include a reflective plane 1613 of a light reflective material, and may change the path of light "L" incident from the outside. The prism 1610 may change the path of light "L" incident in a first direction "X" to a second direction "Y" by rotating the reflective plane 1613 of the light reflective material in a direction "A" or a direction "B" around the central axis 1106. The second direction "Y" may be perpendicular to the first direction "X". When the central axis 1106 rotates, the OPFE 1620 may also move in a third direction "Z" perpendicular to the first direction "X" and the second direction "Y".

[0190] For example, the OPFE 1620 may include a plurality of optical lens groups. The plurality of lenses may be movable in the second direction “Y” to change the optical zoom ratio of the camera module 1600.

[0191] The actuator 1630 may move at least some of the OPFE 1620 or the optical lens to a specific position. The actuator 1630 may control the position of the lens based on a control signal CS provided from the processor.

[0192] The image sensing device 1640 may include an image sensor 1641, logic 1643, and a memory 1645. The image sensor 1641 may generate an electrical signal based on light 'L' provided through an optical lens.

[0193] Each of the pixels of the image sensor 1641 according to the embodiment includes a plurality of photoelectric conversion elements. In some pixels each corresponding to a dual photodiode pixel, the plurality of photoelectric conversion elements may share one microlens. Some pixels constitute super photodiode pixels. The pixels constituting the super photodiode pixels may share one microlens.

[0194] The memory 1645 may store data required for the operation of the camera module 1600. For example, the memory 1645 may store calibration data 1646. The calibration data 1646 may include information about focal length, information about an optical axis, etc. According to an embodiment, the calibration data 1646 may include a focal length value for each optical lens position and information about autofocus.

[0195] The memory 1645 according to an embodiment may store coordinate information of pixels constituting a super photodiode pixel.

[0196] The storage device 1650 may store image data sensed by the image sensor 1641. The storage device 1650 may be provided outside the image sensing device 1640 and may be stored in a manner such as Fig.17 A shape in which the storage device 1650 and the sensor chips constituting the image sensing device 1640 are stacked is implemented.

[0197] The logic 1643 according to the embodiment may be an image signal processing logic. The logic 1643 may control the overall operation of the camera module 1600. The logic 1643 may control the operation of the camera module 1600 in response to a control signal CS from the outside. The logic 1643 may process the image data sensed by the image sensor 1641. For example, the logic 1643 may perform crosstalk correction, automatic dark compensation, etc. with respect to the image data. The logic 1643 may generate phase data in different auto focus modes with reference to the coordinate information of the super photodiode pixel stored in the memory 1645. The logic 1643 may generate phase data based on a dual photodiode pixel in a first auto focus mode. The logic 1643 may generate phase data based on a super photodiode pixel in a second auto focus mode. The logic 1643 may operate in a first auto focus mode or a second auto focus mode based on a control signal CS from a processor.

[0198] The camera module 1600 may transmit an image signal including image data and phase data to the outside.

[0199] In some embodiments, the camera module 1600 may be provided with a sink signal SS from the application processor 1300_2. The sink signal SS may be provided differently to a plurality of cameras constituting the camera module group.

[0200] Considering accuracy and speed, the image sensor according to the present disclosure may operate in multiple autofocus modes.

[0201] Considering accuracy and speed, the electronic device according to the present disclosure may allow an image sensor to operate in a plurality of auto focus modes.

[0202] In some example embodiments, according to example embodiments, Figure 1 , Figure 8 as well as Figures 18 to 20 Each of the components represented by the boxes shown in the figure may be implemented as various numbers of hardware and / or firmware structures that perform the above-mentioned corresponding functions. For example, at least one of these components may include various hardware components (including digital circuits, programmable or non-programmable logic devices or arrays, application-specific integrated circuits (ASICs), transistors, capacitors, logic gates, or other circuits using direct circuit structures (such as memories, processors, logic circuits, lookup tables, etc.)) configured to perform the corresponding functions through the control of one or more microprocessors or other control devices. In addition, at least one of these components may also include a processor (such as a central processing unit (CPU), a microprocessor, etc. that performs the corresponding functions), or may be implemented by a processor (such as a central processing unit (CPU), a microprocessor, etc. that performs the corresponding functions).

[0203] While aspects of the embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A pixel array, comprising: A plurality of pixels in a matrix, the plurality of pixels comprising a first pixel, a second pixel, and a third pixel adjacent to the second pixel; a plurality of microlenses, the plurality of microlenses comprising a first microlens and a second microlens, wherein each of the plurality of pixels includes a plurality of photoelectric conversion elements adjacent to each other in a first direction, wherein the first microlens extends across the plurality of photoelectric conversion elements of the first pixel, and The second microlens extends across the second pixel and the third pixel in the first direction or the second direction.

2. The pixel array according to claim 1, wherein: The plurality of pixels are divided into a plurality of pixel groups, and The second pixel and the third pixel are respectively arranged in different pixel groups adjacent to each other from among the plurality of pixel groups.

3. The pixel array according to claim 2, wherein: Each of the plurality of pixel groups includes a plurality of sub-pixel groups, Each of the plurality of sub-pixel groups includes pixels arranged in an m×n matrix from among the plurality of pixels, where m and n are natural numbers of 2 or greater, The pixel group including the second pixel and the pixel group including the third pixel include different numbers of pixels corresponding to a common color filter.

4. The pixel array according to claim 2, wherein: Each of the second pixel and the third pixel includes a color filter configured to transmit light of a common wavelength band.

5. The pixel array according to claim 1, wherein: The plurality of pixels include a fourth pixel and a fifth pixel adjacent to the fourth pixel, wherein the plurality of microlenses include a third microlens extending across the fourth pixel and the fifth pixel, and The fourth pixel and the fifth pixel are arranged in a direction different from the second pixel and the third pixel.

6. The pixel array according to claim 1, wherein: The plurality of pixels include a fourth pixel and a fifth pixel adjacent to the fourth pixel, wherein the plurality of microlenses include a third microlens extending across the fourth pixel and the fifth pixel, The fourth pixel and the fifth pixel are arranged in the same direction as the second pixel and the third pixel. The fourth pixel and the fifth pixel are respectively arranged adjacent to the second pixel and the third pixel.

7. The pixel array according to claim 6, wherein: The third microlens extends across the second pixel, the third pixel, the fourth pixel, and the fifth pixel.

8. An image sensor, comprising: A pixel array, comprising: a plurality of pixels and a plurality of microlenses in a matrix, the plurality of pixels comprising a first pixel, a second pixel and a third pixel adjacent to the second pixel, and the plurality of microlenses comprising a first microlens and a second microlens; A row decoder circuit is configured to: provide a transmission control signal to the pixel array via a plurality of control signal lines; a control logic circuit configured to: control the row decoder circuit; and An image signal processing logic circuit is configured to: output image data and phase data based on the output of the pixel array, wherein each of the plurality of pixels includes a plurality of photoelectric conversion elements adjacent to each other in a first direction, wherein the first microlens extends across the plurality of photoelectric conversion elements of the first pixel, and The second microlens extends across the second pixel and the third pixel in the first direction or the second direction.

9. The image sensor according to claim 8, wherein: The image signal processing logic circuit is configured to output image data based on a result of performing bad pixel correction processing on the second pixel and the third pixel.

10. The image sensor according to claim 8, further comprising: The memory device is configured to store coordinate information of the second pixel and the third pixel.

11. The image sensor according to claim 8, wherein: The image signal processing logic circuit is configured to output phase data based on outputs of different pixels among the plurality of pixels in a plurality of autofocus modes.

12. The image sensor according to claim 11, wherein: The plurality of auto focus modes are switched based on a first mode signal and a second mode signal, and Wherein, the row decoder circuit is configured as: outputting a transmission control signal to each of the plurality of pixels in response to a first mode signal to control pixel signals of the plurality of pixels to be sampled in different output time periods; and A transmission control signal is output to each of the plurality of pixels in response to a second mode signal to control pixel signals of the plurality of pixels to be sampled simultaneously in a common output period.

13. The image sensor according to claim 11, wherein: The image signal processing logic circuit is configured as follows: outputting phase data based on an output of a first pixel in a first mode among the plurality of automatic focus modes; as well as In a second mode among the plurality of automatic focus modes, phase data is output based on outputs of the second pixel and the third pixel.

14. The image sensor according to claim 11, wherein: Each of the plurality of pixels includes a floating diffusion region, charges accumulated by the plurality of photoelectric conversion elements are transferred to the floating diffusion region, and In a first mode among the plurality of automatic focusing modes, the first pixel is controlled so that the plurality of photoelectric conversion elements of the first pixel transfer charges to a floating diffusion region of the first pixel in different output time periods.

15. The image sensor according to claim 11, wherein: Each of the plurality of pixels includes a floating diffusion region, charges accumulated by the plurality of photoelectric conversion elements are transferred to the floating diffusion region, and In a second mode among the plurality of automatic focusing modes, the first pixel is controlled so that the plurality of photoelectric conversion elements of the first pixel transfer charges to a floating diffusion region of the first pixel in a common output period.

16. The image sensor according to any one of claims 8 to 15, wherein: The second pixel and the third pixel are adjacent to each other in the first direction or the second direction, and The second direction intersects with the first direction.

17. The image sensor according to any one of claims 8 to 15, further comprising: An interface circuit is configured to: send the image data and the phase data to an external device, and The interface circuit is configured to send phase data based on outputs of different pixels in multiple automatic focusing modes.

18. The image sensor according to claim 17, wherein: The interface circuit is configured as: In a first mode among the plurality of autofocus modes, sending image data and phase data generated based on an output of the first pixel to different virtual channels; and In a second mode among the plurality of autofocus modes, phase data generated based on outputs of the second and third pixels is added as a tail to image data generated based on output of the first pixel, and the image data and the phase data are transmitted to a common virtual channel.

19. An electronic device comprising: An image sensing device including a pixel array including a plurality of pixels in a matrix, a plurality of micro lenses, and a logic circuit configured to control the pixel array, and the image sensing device is configured to output image data and phase data based on an output of the pixel array; as well as a processor configured to: receive image data and phase data from an image sensing device, obtain a parallax of the phase data based on the phase data, and provide a control signal to the image sensing device based on the parallax, The pixel array includes a plurality of pixel groups, and the plurality of pixel groups include the plurality of pixels. The plurality of pixels include a first pixel, a second pixel, and a third pixel adjacent to the second pixel. The plurality of microlenses include a first microlens and a second microlens. wherein each of the plurality of pixels includes a plurality of photoelectric conversion elements adjacent to each other in a first direction, wherein the first microlens extends across the plurality of photoelectric conversion elements of the first pixel, and The second microlens extends across the second pixel and the third pixel in the first direction or the second direction.

20. The electronic device according to claim 19, wherein: The processor is configured as: selectively sending a first control signal and a second control signal to an image sensing device to control a mode from among a plurality of modes for generating phase data, wherein the first control signal indicates that phase data is to be output based on the output of the first pixel, and The second control signal indicates that the phase data is to be output based on the outputs of the second pixel and the third pixel.

Images