Array substrate, manufacturing method thereof and display panel

Abstract

The embodiment of the present application discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises a thin film transistor, the thin film transistor comprises an active layer, a gate insulating layer and a gate electrode, the active layer comprises a channel, the channel comprises a main body part and an edge part, the gate insulating layer covers at least one side of the channel away from the substrate, and the gate electrode is arranged at the side of the gate insulating layer away from the substrate. The defect state density of the edge part is greater than that of the main body part. The defect state density of the edge part is greater than that of the main body part, so that the edge part is more difficult to open under the same gate voltage, the edge thin film transistor is inhibited, and the hump effect of the thin film transistor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] Low temperature poly-silicon thin film transistor is a key component of active driving, peripheral circuit of display devices such as liquid crystal display and organic light emitting diode. At present, low temperature poly-silicon thin film transistor has hump effect, and the electrical property in sub-threshold region is poor, so that the charging capacity of high-specification product is limited; the cause of hump effect: the low temperature poly-silicon thin film transistor manufactured by current process can be regarded as being composed of edge thin film transistors on both sides and a main body thin film transistor in the middle in parallel, the threshold voltage (Vth) of the edge thin film transistor is relatively negative to the main body thin film transistor, resulting in abnormal increase of current in sub-threshold region of the main body thin film transistor. SUMMARY

[0003] Embodiments of the present application provide an array substrate and a preparation method thereof and a display panel, which can reduce the risk of hump effect of thin film transistor.

[0004] In one aspect, embodiments of the present application provide an array substrate, comprising:

[0005] a substrate; and

[0006] a thin film transistor disposed on the substrate, the thin film transistor comprising an active layer, a gate insulating layer, a gate, a source and a drain, the active layer comprising a channel, a first contact portion and a second contact portion, the channel comprising a main body portion and an edge portion, the gate insulating layer covering at least one side of the channel away from the substrate, the gate being disposed on one side of the gate insulating layer away from the substrate, the source being connected to the first contact portion, and the drain being connected to the second contact portion.

[0007] In a plan view of the array substrate, the edge portion is located on one side of the main body portion.

[0008] In the second direction, the edge portion has a slope angle less than 90 degrees; and the defect state density of the edge portion is greater than the defect state density of the main body portion.

[0009] Optionally, in some embodiments of the present application, the defect state density of the edge portion is greater than or equal to 5 times the defect state density of the main body portion.

[0010] Optionally, in some embodiments of the present application, the defect state density of the main body portion is between 1x10 20 and 3x10 20 .

[0011] Optionally, in some embodiments of the present application, the carrier mobility of the edge portion is less than the carrier mobility of the main portion.

[0012] Optionally, in some embodiments of the present application, the material of the channel comprises polysilicon, and the crystallinity of the edge portion is less than the crystallinity of the main portion.

[0013] Optionally, in some embodiments of the present application, the slope angle of the edge portion is between 30 degrees and 80 degrees.

[0014] Optionally, in some embodiments of the present application, the thickness of the main portion is between 300 angstroms and 600 angstroms.

[0015] Optionally, in some embodiments of the present application, one edge portion is located on one side of the main portion, and another edge portion is located on another side of the main portion.

[0016] Optionally, in some embodiments of the present application, in a plan view of the array substrate, the first contact portion, the channel and the second contact portion are sequentially arranged in a first direction, and one edge portion is located on one side of the main portion and another edge portion is located on another side of the main portion in a second direction perpendicular to the first direction.

[0017] Optionally, in some embodiments of the present application, the array substrate further comprises a light shielding layer, a buffer layer, an interlayer dielectric layer, a planarization layer and a pixel electrode, the light shielding layer is located on the substrate, the buffer layer covers the light shielding layer and the substrate, the active layer is arranged on a side of the buffer layer away from the substrate, the gate insulating layer covers the active layer, the interlayer dielectric layer covers the gate, the source and the drain are arranged on a side of the interlayer dielectric layer away from the substrate, the planarization layer covers the source and the drain, the pixel electrode is arranged on a side of the planarization layer away from the substrate, and the pixel electrode is connected to the source or the drain.

[0018] In another aspect, the embodiments of the present application also provide a preparation method of an array substrate, comprising the following steps:

[0019] forming a semiconductor layer and a photoresist layer on the substrate in sequence;

[0020] patterning the photoresist layer to form a photoresist pattern;

[0021] etching the semiconductor layer to form an active layer with the photoresist pattern as a mask, the active layer comprising a channel, a first contact portion and a second contact portion, the channel comprising a main portion and an edge portion, the edge portion having a slope angle less than 90 degrees, the main portion being covered by the photoresist pattern, and the edge portion being exposed.

[0022] ion bombardment is performed on the edge portion of the active layer to make the defect state density of the edge portion greater than the defect state density of the main body portion;

[0023] the photoresist pattern is removed, and a gate insulating layer and a gate are sequentially formed on the active layer, the gate insulating layer at least covering a side of the channel away from the substrate, and the gate being disposed on a side of the gate insulating layer away from the substrate;

[0024] a source and a drain are formed on the gate and are insulated from the gate, the source being connected to the first contact portion, and the drain being connected to the second contact portion.

[0025] Optionally, in some embodiments of the present application, the activity of the ions is less than that of oxygen plasma.

[0026] In another aspect, the embodiments of the present application further provide a display panel, which comprises the array substrate as described in any one of the above embodiments.

[0027] The array substrate of the embodiments of the present application comprises a thin film transistor, which comprises an active layer, a gate insulating layer, a gate, a source and a drain, the active layer comprising a channel, a first contact portion and a second contact portion, the channel comprising a main body portion and an edge portion, the gate insulating layer at least covering a side of the channel away from the substrate, the gate being disposed on a side of the gate insulating layer away from the substrate, the source being connected to the first contact portion, and the drain being connected to the second contact portion; the edge portion has a slope angle less than 90 degrees; and the defect state density of the edge portion is greater than the defect state density of the main body portion.

[0028] The embodiments of the present application make the defect state density of the edge portion greater than the defect state density of the main body portion, so that the edge portion is more difficult to be turned on under the same gate voltage, and the edge thin film transistor is inhibited, thereby improving the hump effect of the thin film transistor. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a plane schematic diagram of the array substrate provided by one or more embodiments of the present application;

[0030] Figure 2 is a plane schematic diagram of the array substrate provided by one or more embodiments of the present application; Figure 1 is a cross-sectional structural schematic diagram along the A-A line in the array substrate;

[0031] Figure 3 is a cross-sectional structural schematic diagram along the A-A line in the array substrate; Figure 1 is a cross-sectional structural schematic diagram along the B-B line in the array substrate;

[0032] Figure 4FIG. 1 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application;

[0033] Figure 5 FIG. 2 is a schematic diagram of step B1 of the method for manufacturing an array substrate according to an embodiment of the present application;

[0034] Figure 6 FIG. 3 is a schematic diagram of step B2 of the method for manufacturing an array substrate according to an embodiment of the present application;

[0035] Figure 7 FIG. 4 is a schematic diagram of step B3 of the method for manufacturing an array substrate according to an embodiment of the present application;

[0036] Figure 8 FIG. 5 is a schematic diagram of step B4 of the method for manufacturing an array substrate according to an embodiment of the present application;

[0037] Figure 9a FIG. 6 is a schematic diagram of step B51 of the method for manufacturing an array substrate according to an embodiment of the present application;

[0038] Figure 9b FIG. 7 is a schematic diagram of step B52 of the method for manufacturing an array substrate according to an embodiment of the present application;

[0039] Figure 9c FIG. 8 is a schematic diagram of step B53 of the method for manufacturing an array substrate according to an embodiment of the present application;

[0040] Figure 10 FIG. 9 is a schematic diagram of step B6 of the method for manufacturing an array substrate according to an embodiment of the present application;

[0041] Figure 11 FIG. 10 is a schematic diagram of step B7 of the method for manufacturing an array substrate according to an embodiment of the present application;

[0042] Figure 12 FIG. 11 is a comparison diagram of transfer curves of thin film transistors at a drain voltage Vd = 0.1 volt and a drain voltage Vd = 10 volt for Comparative Example 1, Comparative Example 2, and Experimental Example of the present application;

[0043] Figure 13 FIG. 12 is a schematic diagram of a display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application. In addition, it should be understood that the specific implementation described herein is only used for illustrating and explaining the present application, and is not used for limiting the present application. In the present application, the embodiments can be combined with each other but are not described one by one, and the positional words such as "upper" and "lower" are used for indicating the upper and lower in the actual use or working state of the device, and the specific is the direction of the drawing surface in the drawings; and the words "inner" and "outer" are used for indicating the contour of the device; the words "first", "second", "third" and the like are only used for indicating, and do not impose the number requirement or establish the sequence.

[0045] The present application provides an array substrate and a preparation method thereof and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0046] Please refer to Figures 1 to 3 , Figure 1 is a schematic plan view of the array substrate provided by one or more embodiments of the present application, Figure 2 is Figure 1 is a schematic cross-sectional view along the line A-A in Figure 3 is Figure 1 is a schematic cross-sectional view along the line B-B in

[0047] In Figures 1 to 3 , the first direction DR1 can be a direction parallel to one side of the array substrate 100 in a plan view, for example, can be a longitudinal direction of the array substrate 100, but is not limited thereto. The second direction DR2 can be a direction parallel to the other side of the array substrate 100 in a plan view, for example, can be a transverse direction of the array substrate 100, but is not limited thereto. The third direction DR3 can be a thickness direction of the array substrate 100.

[0048] One or more embodiments of the present application provide an array substrate 100, which includes a substrate su and a thin film transistor tft. The thin film transistor tft is disposed on the substrate su.

[0049] The thin film transistor tft includes an active layer py, a gate insulating layer gi, a gate electrode g01, a source electrode s01, and a drain electrode d01. The active layer py includes a channel gd, a first contact portion p1, and a second contact portion p2. The channel gd includes a main body portion gd1 and an edge portion gd2. The gate insulating layer gi covers at least one side of the channel gd away from the substrate su. The gate electrode g01 is disposed on the side of the gate insulating layer gi away from the substrate su. The source electrode s01 is connected to the first contact portion p1, and the drain electrode d01 is connected to the second contact portion p2.

[0050] Figure 1 Only one plan view of the embodiment of the present application is shown, but the present application is not limited thereto. Based on the above description, other plan views of the embodiment of the present application can be obtained. Figure 1 In the plan view of the array substrate 100, in the first direction DR1, the first contact portion p1, the channel gd, and the second contact portion p2 are sequentially arranged; in the second direction DR2 perpendicular to the first direction DR1, the edge portion gd2 is located on one side of the main body portion gd1.

[0051] In the second direction DR2, the edge portion gd2 has a slope angle a less than 90 degrees. The defect state density of the edge portion gd2 is greater than that of the main body portion gd1.

[0052] The embodiment of the present application adopts the setting that the defect state density of the edge portion gd2 is greater than that of the main body portion gd1. Since the defect state density of the edge portion gd2 is greater, the edge portion gd2 is more difficult to open at the same gate voltage, and the edge thin film transistor is inhibited, thereby achieving the effect of improving the camel effect of the thin film transistor tft.

[0053] It needs to be explained that the defect state density is a concept in the physical energy band theory of semiconductors. After the semiconductor deviates from the ideal crystal (due to various defects), electron orbits (energy states) are generated in the forbidden band. The state density refers to the number of energy states in a unit energy interval in the energy band.

[0054] The defect state density can be measured by deep level transient spectroscopy and charge pumping method, and can also be indirectly measured by X-ray diffraction test crystallinity.

[0055] For example, the test method of deep level transient spectroscopy is: first, non-equilibrium carriers are injected into the semiconductor material, then the carriers are excited to the conduction band or valence band by light excitation or electric field excitation, and then the change of the optical spectrum is measured to study the electron transition process and the properties of deep level defects.

[0056] For example, the charge-pumping technique can be referred to the article "Local oxide capacitance as a crucial parameter for characterization of hot-carrier degradation in long-channel n-MOSFETs", authors: I Starkov, H Enichlmair; journal: Journal of Vacuum Science & Technology. B, Microelectronics and Nanometer Structures: Processing, Measurement, and Phenomena; journal volume: 31; page(s) 1180-1187; publication date: 2013; DOI: 10.1116 / 1.4774106.

[0057] In addition, please refer to Figure 1 The thin film transistor tft includes a main thin film transistor t1 and edge thin film transistors t2 located on both sides of the main thin film transistor t1. The main thin film transistor t1 and the edge thin film transistors t2 have a common gate, a common source and a common drain. The channel of the main thin film transistor t1 is a main part gd1, and the channel of the edge thin film transistor t2 is an edge part gd2.

[0058] Optionally, the thin film transistor tft can be an N-type thin film transistor or a P-type thin film transistor.

[0059] In the thin film transistor tft disclosed in the embodiments of the present application, the gate g01 is a metal layer, and the source s01 and the drain d01 are disposed in the same layer as a metal layer, which is taken as an example for illustration, but is not limited thereto. For example, the gate g10, the source s01 and the drain d01 can be disposed in the same layer, that is, they are prepared and formed by using the same mask plate; or one of the source s01 and the drain d01 can be disposed in the same layer as the gate g01; or all of them can be disposed in different layers.

[0060] It should be understood that the array substrate 100 of the embodiments of the present application is used for a liquid crystal panel, and the array substrate 100 of the embodiments of the present application can be based on a driving architecture of a fringe field switching (FFS) technology, or based on a driving architecture of an in-plane switching (IPS) technology, or based on a driving architecture of a vertical alignment (VA) technology, etc.

[0061] In some embodiments, the array substrate 100 can also be used in electroluminescent display panels, such as organic light-emitting diode display panels, micro light-emitting diode display panels, sub-millimeter light-emitting diode display panels, quantum dot light-emitting diode display panels, and the like. In addition, in other embodiments, the array substrate 100 can also be used in electrophoretic panels and the like.

[0062] The array substrate 100 of the embodiments of the present application is described below based on an FFS architecture, but is not limited thereto.

[0063] Please refer to Figure 2 and Figure 3 In one or more embodiments of the present application, the array substrate 100 further includes a light-shielding layer Ls, a buffer layer buf, an interlayer dielectric layer Ld, a planarization layer Pn, and a pixel electrode pix.

[0064] The light-shielding layer Ls is located on the substrate su. The buffer layer buf covers the light-shielding layer Ls and the substrate su. The active layer py is disposed on the side of the buffer layer buf away from the substrate su. The gate insulating layer gi covers the active layer py, and the interlayer dielectric layer Ld covers the gate g01. The source s01 and the drain d01 are disposed on the side of the interlayer dielectric layer Ld away from the substrate su. The planarization layer Pn covers the source s01 and the drain d01, and the pixel electrode pix is disposed on the side of the planarization layer Pn away from the substrate su. The pixel electrode pix is connected to the source s01 or the drain d01.

[0065] Optionally, in one or more embodiments, the array substrate 100 can further include a common electrode layer com disposed on the side of the planarization layer Pn away from the substrate su, and a passivation layer Pv covering the common electrode layer com. The pixel electrode pix is disposed on the side of the passivation layer Pv away from the substrate su.

[0066] Optionally, in some embodiments, the substrate su can be a rigid substrate or a flexible substrate. The material of the substrate su includes one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyether sulfone, aromatic fluorine-containing toluene containing polyarylate, polycyclic olefin, polyimide, or polyurethane.

[0067] In some embodiments, the material of the light-shielding layer Ls can be an inorganic metal material, such as chromium, molybdenum, manganese, and the like, or a metal oxide material, such as CrO x , MoO x , MnO2, or a mixed film layer formed by a metal and a metal oxide; or an organic black resin material, such as black polystyrene, black photoresist, and the like.

[0068] In some embodiments, the buffer layer buf, the gate insulating layer gi, the interlayer dielectric layer Ld, and the passivation layer Pv can be formed of a plurality of inorganic layers stacked in an alternating manner. For example, the buffer layer buf, the gate insulating layer gi, the interlayer dielectric layer Ld, and the passivation layer Pv can be formed as a bilayer formed by stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide, or a multilayer formed by alternately stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium oxide, and titanium oxide. However, the present disclosure is not limited thereto, and the buffer layer buf, the gate insulating layer gi, the interlayer dielectric layer Ld, and the passivation layer Pv can be formed as a single-layer inorganic layer containing the above-described insulating material.

[0069] Further, in one or more embodiments, the interlayer dielectric layer Ld can be made of an organic insulating material such as polyimide (PI) or the like.

[0070] In some embodiments, the material of the active layer py can include polysilicon or single-crystal silicon. The first contact portion p1 and the second contact portion p2 are N-type contact portions. The first contact portion p1 and the second contact portion p2 each include a heavily doped region and a lightly doped region. The heavily doped region is located on a side of the lightly doped region away from the channel gd. The source s01 is connected to the heavily doped region of the first contact portion p1, and the drain d01 is connected to the heavily doped region of the second contact portion p2.

[0071] In some embodiments, the gate g01, the source s01, and the drain d01 can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, neodymium, cobalt, an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements, and the like. Further, the gate, the source and the drain can have a single-layer structure or a laminated structure of two or more layers.

[0072] In some embodiments, the material of the planarization layer Pn can be an organic transparent film layer, such as a transparent photoresist, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, and the like.

[0073] In some embodiments, the material of the pixel electrode pix and the common electrode layer com can be an oxide such as indium tin oxide, indium zinc oxide, or the like; and can also be a metal, an alloy, and a compound of various conductive properties, and a mixture thereof, for example, gold, silver, or platinum, and the like can be used.

[0074] In one or more embodiments of the present application, the thickness of the edge portion gd2 has a gradual change trend, and the thickness of the main body portion gd1 has a uniform trend. From the edge of the edge portion gd2 to the main body portion gd1, the thickness of the edge portion gd2 increases.

[0075] It should be understood that the thickness of the edge portion gd2 is not increased by 100% because the thickness of the edge portion gd2 cannot be accurately controlled to 100% due to limitations of the manufacturing process. The thickness of the main body portion gd1 is also not required to be uniform based on the limitations of the manufacturing process.

[0076] In one or more embodiments of the present application, the defect density of the edge portion gd2 is greater than or equal to 5 times the defect density of the main body portion gd1.

[0077] It should be understood that the greater the defect density of the edge portion gd2, the better the effect of suppressing the turn-on of the edge thin film transistor t2, and thus the better the effect of suppressing the camel effect. Conversely, the effect is worse.

[0078] Therefore, in order to significantly suppress the camel effect, the defect density of the edge portion gd2 is selected to be greater than or equal to 5 times the defect density of the main body portion gd1.

[0079] For example, the defect density of the edge portion gd2 can be 5 times, 6 times, 7 times, 8 times, 9 times, or 10 times the defect density of the main body portion gd1.

[0080] In some embodiments of the present application, the defect density of the main body portion gd1 is between 1 x 10 20 6 / eV (electron volts) and 3 x 10 20 6 / eV, such as 1 x 10 20 6 / eV, 2 x 10 20 6 / eV, 3 x 10 20 6 / eV, and the like.

[0081] In some embodiments of the present application, the carrier mobility of the edge portion gd2 is less than the carrier mobility of the main body portion gd1.

[0082] It can be understood that the smaller the carrier mobility of the edge portion gd2, the longer the time for the carrier to cross the base region, and the lower the switching speed of the thin film transistor, thereby suppressing the turn-on of the edge thin film transistor t2.

[0083] In some embodiments of the present application, the material of the channel gd includes polycrystalline silicon, and the crystallinity of the edge portion gd2 is less than the crystallinity of the main body portion gd1.

[0084] It can be understood that the crystallinity of the channel refers to the degree of order of the lattice structure arrangement within the polycrystalline silicon material. A small crystallinity means that there are a large number of grain boundaries, defects, and disordered structures in the material.

[0085] In the embodiments of the present application, the defect degree of the edge portion gd2 is greater than that of the main body portion gd1, and the increase of defects causes the migration speed of the carrier channel to decrease, which means that a greater gate voltage is needed for control in the same time. Therefore, the crystallinity of the edge portion gd2 is less than that of the main body portion gd1, which can inhibit the start of the edge thin film transistor t2, so as to achieve the effect of inhibiting the hump effect of the thin film transistor tft.

[0086] In some embodiments of the present application, the thickness of the main body portion gd1 is between 300 angstroms and 600 angstroms, for example, 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms or 600 angstroms.

[0087] It can be understood that if the thickness of the channel gd is too thin, it will cause uneven film formation, and if it is too thick, it will be difficult to crystallize, resulting in poor crystalline quality of the polysilicon. Therefore, based on the above considerations, the thickness of the channel gd is selected to be between 300 angstroms and 600 angstroms.

[0088] In some embodiments of the present application, the slope angle a of the edge portion gd2 is between 30 degrees and 80 degrees.

[0089] It should be noted that since the thickness of the main body portion gd1 of the active layer py is small, if the slope angle a of the edge portion gd2 is too steep, it will be difficult for the edge portion gd2 to be hit by ions in the subsequent ion bombardment step, making it difficult for the edge portion gd2 to have a large degree of defects on the side close to the gate g01. If the slope angle a is too flat, it will occupy too much space.

[0090] Therefore, considering the difficulty of defect formation and space occupation requirements of the edge portion gd2, the slope angle a of the edge portion gd2 is set to be between 30 degrees and 80 degrees, for example, 30 degrees, 35 degrees, 40 degrees, 45 degrees, 50 degrees, 55 degrees, 65 degrees, 70 degrees, 75 degrees or 80 degrees.

[0091] In some embodiments of the present application, in the second direction DR2, one edge portion gd2 is located on one side of the main body portion gd1, and the other edge portion gd2 is located on the other side of the main body portion gd1. Of course, in some embodiments, only one edge portion gd2 can be included.

[0092] Optionally, the slope angles of the two edge portions gd2 can be the same or different, which is not limited in the present application.

[0093] In some embodiments, the main body portion gd1 includes a first portion and a second portion, and the first portion is located between the second portion and the edge portion gd2. The defect state density of the first portion is between the defect state density of the edge portion gd2 and the defect state density of the second portion.

[0094] Understandably, the first part serves as a transition, reducing the risk of mutual interference between the edge thin-film transistor t2 and the main thin-film transistor t1 at the moment the thin-film transistor tft is turned on.

[0095] Optional, such as Figure 3 As shown, the width of the first part is smaller than the width of the edge part gd2 in order to reduce the impact on the main thin-film transistor t1.

[0096] Please refer to Figure 4 This application also provides a method for fabricating an array substrate 100, which includes the following steps:

[0097] Step B1: A semiconductor layer act and a photoresist layer pr are sequentially formed on the substrate su.

[0098] Step B2: Pattern the photoresist layer pr to form a photoresist pattern pr1.

[0099] Step B3: Using the photoresist pattern pr1 as a mask, the semiconductor layer act is etched to form the active layer py. The active layer py includes a channel gd, a first contact portion and a second contact portion. The channel gd includes a main portion gd1 and an edge portion gd2. The edge portion gd2 has a slope angle α of less than 90 degrees. The main portion gd1 is covered by the photoresist pattern pr1, and the edge portion gd2 is exposed.

[0100] Step B4: Using the photoresist pattern pr1 as a mask, ion bombardment is performed on the edge gd2 of the active layer py to make the defect state density of the edge gd2 greater than that of the main body gd1.

[0101] Step B5: Remove the photoresist pattern pr1, and sequentially form a gate insulating layer gi and a gate g01 on the active layer py. The gate insulating layer gi at least covers the side of the channel gd away from the substrate su, and the gate g01 is disposed on the side of the gate insulating layer gi away from the substrate su.

[0102] Step B6: A source electrode s01 and a drain electrode d01, which are insulated from the gate electrode g01, are formed on the gate electrode g01. The source electrode s01 is connected to the first contact portion p1, and the drain electrode d01 is connected to the second contact portion p2.

[0103] It should be understood that the fabrication method of the array substrate 100 in this embodiment of the application uses a photoresist pattern to protect the main body gd1 of the channel gd from ion bombardment, while simultaneously bombarding the edge gd2 of the channel gd with ions to increase the defect state density of the edge gd2. Since the defect state density of the edge gd2 is greater than that of the main body gd1, the turn-on of the edge thin-film transistor t2 can be suppressed under the same gate voltage, thereby suppressing the peak effect of the thin-film transistor tft.

[0104] The following is based on Figures 1 to 3 The preparation method of the corresponding embodiment is described, but is not limited thereto.

[0105] Please refer to Figure 5 , step B1, sequentially forming a semiconductor layer act and a photoresist layer pr on the substrate su.

[0106] Optionally, the material of the semiconductor layer act can be polysilicon.

[0107] Optionally, before forming the semiconductor layer act on the substrate su, it further includes the step of: forming a light shielding layer Ls and a buffer layer buf on the substrate su. The semiconductor layer act is formed on the buffer layer buf.

[0108] Then turn to step B2.

[0109] Please refer to Figure 6 , step B2, patterning the photoresist layer pr to form a photoresist pattern pr1.

[0110] The photoresist pattern pr1 is used to form the subsequent active layer py.

[0111] Then turn to step B3.

[0112] Please refer to Figure 7 , step B3, etching the semiconductor layer act to form the active layer py with the photoresist pattern pr1 as a mask. The active layer py includes a channel gd, a first contact portion and a second contact portion, the channel gd includes a main body portion gd1 and an edge portion gd2, the edge portion gd2 has a slope angle α less than 90 degrees, the main body portion gd1 is covered by the photoresist pattern pr1, and the edge portion gd2 is exposed.

[0113] Optionally, in the process of etching the semiconductor layer act, the side edge portion of the photoresist pattern pr1 forms a structure with a slope angle. The side surface of the side edge portion is flush with the side surface of the edge portion gd2.

[0114] Then turn to step B4.

[0115] Please refer to Figure 8 , step B4, ion bombardment of the edge portion gd2 of the active layer py with the photoresist pattern pr1 as a mask to make the defect state density of the edge portion gd2 greater than that of the main body portion gd1.

[0116] Optionally, the activity of the ions is less than that of oxygen plasma. Such as noble gas or less reactive gas, such as Ar, Ne, Kr, Xe or N2.

[0117] In comparison with the comparative example in which oxygen plasma is used for bombardment, the oxygen plasma is more active and more likely to react with silicon. In the experimental example of the present application, argon plasma Ar + is used for bombardment. Since the relative atomic mass of Ar is large, the physical bombardment effect is good, and the defect density of the edge portion gd2 can be increased quickly, and the crystallinity of the edge portion gd2 can be reduced. In addition, argon is an inert gas, and it has little chemical reaction with silicon and little side effect.

[0118] In addition, it should be understood that since the side edge portion of the photoresist pattern pr1 corresponds to the side of the main body portion gd1 close to the edge portion gd2, and the thickness of the side edge portion increases gradually. When the plasma is bombarded, the plasma can penetrate the side edge portion with a thin thickness and damage the first portion of the main body portion gd1, and the damage degree of the first portion of the main body portion gd1 gradually decreases with the increase of the thickness of the side edge portion of the photoresist pattern pr1, and based on this, the defect density of the first portion of the main body portion gd1 is between the edge portion gd2 and the second portion of the main body portion gd1.

[0119] Of course, in some embodiments, the thickness of the side edge portion of the photoresist pattern pr1 is equal to the thickness of other portions, that is, the photoresist pattern pr1 has no inclined slope angle.

[0120] Then turn to step B5.

[0121] Please refer to Figures 9a to 9c , step B5, remove the photoresist pattern pr1, and sequentially form a gate insulating layer gi and a gate g01 on the active layer py, the gate insulating layer gi at least covers the side of the channel gd away from the substrate su, and the gate g01 is arranged on the side of the gate insulating layer gi away from the substrate su.

[0122] Optionally, after removing the photoresist pattern pr1, step B5 further comprises:

[0123] Please refer to Figure 9a , step B51, performing a first light doping treatment on the entire surface of the active layer py.

[0124] Please refer to Figure 9b , step B52, performing a heavy doping treatment on the heavy doping region of the active layer py.

[0125] Please refer to Figure 9c , step B53, sequentially forming a gate insulating layer gi and a gate g01 on the active layer py, and then performing a second light doping treatment on the light doping region of the active layer py with the gate g01 as a mask, to form a first contact portion p1, a second contact portion p2 and a channel gd.

[0126] Then turn to step B6.

[0127] Please refer to Figure 10 , step B6, forming the source s01 and the drain d01 on the gate g01, the source s01 is connected to the first contact p1, and the drain d01 is connected to the second contact p2.

[0128] Optionally, step B6 includes: forming an interlayer dielectric layer Ld on the gate g01; and then forming the source s01 and the drain d01 on the interlayer dielectric layer Ld.

[0129] In addition, the preparation method of the array substrate 100 of the embodiment of the present application further includes the following steps:

[0130] Please refer to Figure 11 , step B7, sequentially forming the planarization layer Pn, the common electrode layer com, the passivation layer pv and the pixel electrode pix on the source s01 and the drain d01. The pixel electrode pix is connected to the drain d01 through a via.

[0131] It should be noted that, please refer to Figure 12 , Figure 12 is a comparison diagram of the transfer curves of the thin film transistors of the preparation method of the present application, the comparative example 1 and the comparative example 2 under the conditions of the drain voltage Vd = 0.1 volt and the drain voltage Vd = 10 volts.

[0132] Among them, the comparative example 1, the comparative example 2 and the experimental example only differ in whether the plasma bombardment edge portion gd2 is used in the process. That is, the low-temperature polysilicon thin film transistor of the comparative example 1 is a thin film transistor without plasma bombardment, the low-temperature polysilicon thin film transistor of the comparative example 2 is a thin film transistor subjected to bombardment by oxygen plasma, and the experimental example is a low-temperature polysilicon thin film transistor prepared by the preparation method of the array substrate of the embodiment of the present application, which is a thin film transistor tft subjected to bombardment by argon plasma.

[0133] According to Figure 12 It can be known that, compared with the comparative example 1, the comparative example 2 subjected to bombardment by oxygen plasma has no obvious improvement on the hump effect under the conditions of the drain voltage Vd = 0.1 volt and the drain voltage Vd = 10 volts; and the experimental example subjected to bombardment by argon plasma has a good improvement effect on the hump effect.

[0134] In another aspect, please refer to Figure 13 The embodiment of the present application further provides a display panel 1000, which comprises the array substrate as described in any one of the above embodiments.

[0135] The display panel 1000 of the embodiments of the present application can be one of a liquid crystal panel, an electroluminescent display panel and an electrophoretic panel, such as an FFS liquid crystal display panel, an IPS liquid crystal display panel, a VA liquid crystal display panel, an organic light-emitting diode display panel, a micro light-emitting diode display panel, a sub-millimeter light-emitting diode display panel, a quantum dot light-emitting diode display panel or an electrophoretic panel, etc.

[0136] It should be noted that the structure of the thin film transistor of the array substrate 100 of the display panel 1000 of the embodiments of the present application is similar or identical to the structure of the thin film transistor tft of the array substrate 100 of any of the above embodiments.

[0137] Optionally, Figure 13 Shown is the display panel 1000 of one embodiment of the present application, which is a liquid crystal panel. The display panel 1000 includes an array substrate 100, an opposite substrate 200 disposed opposite to the array substrate 100, and a liquid crystal layer 300 disposed between the array substrate 100 and the opposite substrate 200.

[0138] The display panel of the embodiments of the present application includes a thin film transistor, which includes an active layer, a gate insulating layer, a gate, a source and a drain, the active layer includes a channel, a first contact part and a second contact part, the channel includes a main part and an edge part, the gate insulating layer covers at least one side of the channel away from the substrate su, the gate is disposed at the side of the gate insulating layer away from the substrate, the source is connected to the first contact part, and the drain is connected to the second contact part; the edge part has a slope angle less than 90 degrees; wherein the defect state density of the edge part is greater than the defect state density of the main part.

[0139] The embodiments of the present application adopt the setting that the defect state density of the edge part is greater than the defect state density of the main part. Since the defect state density of the edge part is greater, the edge part is more difficult to open under the same gate voltage, and the edge thin film transistor is inhibited, thereby achieving the effect of improving the hump effect of the thin film transistor.

[0140] The above has introduced in detail the array substrate and the preparation method thereof and the display panel provided by the embodiments of the present application. The principles and implementation manners of the present application are described by applying specific examples in the text. The above embodiment descriptions are only for helping to understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application. In summary, the content of the specification should not be understood as limiting the present application.

Claims

1. An array substrate, characterized in that, include: substrate; as well as A thin-film transistor is disposed on the substrate. The thin-film transistor includes an active layer, a gate insulating layer, and a gate. The active layer includes a channel, which includes a main body portion and an edge portion. The gate insulating layer at least covers the side of the channel away from the substrate. The gate is disposed on the side of the gate insulating layer away from the substrate. The gate and the channel are correspondingly disposed. In a plan view of the array substrate, one of the edge portions is located on one side of the main body portion, and the arrangement direction of the main body portion and the edge portion is parallel to the extension direction of the gate. Wherein, the defect state density of the edge portion is greater than the defect state density of the main body portion; The main body includes a first part and a second part. In the width direction of the active layer, the first part is located between the second part and the edge part, wherein the defect state density of the first part is between the defect state density of the edge part and the defect state density of the second part.

2. The array substrate according to claim 1, characterized in that, The defect state density of the edge portion is greater than or equal to 5 times the defect state density of the main body portion.

3. The array substrate according to claim 2, characterized in that, The defect state density of the main body is between 1×10⁻⁶. 20 Units / eV up to 3×10 20 Between 1 / eV.

4. The array substrate according to claim 1, characterized in that, The carrier mobility at the edge is less than that at the main body.

5. The array substrate according to claim 1, characterized in that, The channel is made of polycrystalline silicon, and the crystallinity of the edge portion is less than that of the main body portion.

6. The array substrate according to any one of claims 1 to 5, characterized in that, The slope angle of the edge is between 30 degrees and 80 degrees.

7. The array substrate according to claim 6, characterized in that, The thickness of the main body is between 300 angstroms and 600 angstroms.

8. The array substrate according to claim 6, characterized in that, One of the edge portions is located on one side of the main body portion, and the other edge portion is located on the other side of the main body portion.

9. The array substrate according to claim 8, characterized in that, The thin-film transistor includes a source and a drain, and the active layer includes a first contact portion and a second contact portion. The source is connected to the first contact portion, and the drain is connected to the second contact portion. In a plan view of the array substrate, in a first direction, the first contact portion, the channel, and the second contact portion are arranged sequentially. In a second direction perpendicular to the first direction, one edge portion is located on one side of the main body portion, and the other edge portion is located on the other side of the main body portion.

10. The array substrate according to any one of claims 1 to 5, characterized in that, The array substrate further includes a light-shielding layer, a buffer layer, an interlayer dielectric layer, a planarization layer, and a pixel electrode. The thin-film transistor includes a source and a drain. The light-shielding layer is located on the substrate. The buffer layer covers the light-shielding layer and the substrate. The active layer is disposed on the side of the buffer layer away from the substrate. The gate insulating layer covers the active layer. The interlayer dielectric layer covers the gate. The source and the drain are disposed on the side of the interlayer dielectric layer away from the substrate. The planarization layer covers the source and the drain. The pixel electrode is disposed on the side of the planarization layer away from the substrate. The pixel electrode is connected to the source or the drain.

11. A method for fabricating an array substrate, characterized in that, Includes the following steps: A semiconductor layer and a photoresist layer are sequentially formed on the substrate; The photoresist layer is patterned to form a photoresist pattern; Using the photoresist pattern as a mask, the semiconductor layer is etched to form an active layer. The active layer includes a channel, which includes a main body and an edge. The main body is covered by the photoresist pattern, and the edge is exposed. Using the photoresist pattern as a mask, ion bombardment is performed on the edge of the active layer to make the defect state density at the edge greater than the defect state density at the main body. The photoresist pattern is removed, and a gate insulating layer and a gate are sequentially formed on the active layer. The gate insulating layer at least covers the side of the channel away from the substrate. The gate is disposed on the side of the gate insulating layer away from the substrate. The gate and the channel are correspondingly disposed. In a plan view of the array substrate, an edge portion is located on one side of the main body portion. The arrangement direction of the main body portion and the edge portion is parallel to the extension direction of the gate to form a source and a drain on the substrate. The main body portion includes a first portion and a second portion. In the width direction of the active layer, the first portion is located between the second portion and the edge portion. The defect state density of the first portion is between the defect state density of the edge portion and the defect state density of the second portion.

12. The method for fabricating an array substrate according to claim 11, characterized in that, The reactivity of the ions is less than that of the oxygen plasma.

13. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-10.

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