Display device and electronic device including the same

Abstract

The invention relates to a display device and an electronic device including the same. A display device includes: a display panel including a display area and a non-display area; and an input sensor disposed on the display panel. The display panel includes: a base layer including a resin layer; a pixel disposed on the base layer and overlapping the display area; a charging electrode disposed under the at least one resin layer and overlapping the display area; and a first shield pattern disposed on the base layer and overlapping the display area, the first shield pattern having a first thickness and having at least one slit dividing the first shield pattern into a plurality of segments. The first thickness corresponds to a thickness satisfying a relationship of the following formula: # imgabs0 # wherein T1 represents the first thickness, A is [pi], B is a magnetic permeability of the first shield pattern, C is a frequency of a current flowing through the first shield pattern, and D is a resistivity of the first shield pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0113799 filed in the Korean Intellectual Property Office on August 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device and an electronic device including the same, and more particularly, to a display device including a sensing electrode, a charging electrode, and a shielding pattern. Background Art

[0004] Various display devices are being developed for use in multimedia devices such as mobile phones, tablet computers, car navigation units, game consoles, etc. The display device includes a keyboard or a mouse as an input device. The display device includes an input sensor as an input device.

[0005] The input sensor may sense a mutual capacitance type user input, or may sense a self capacitance type user input. The input sensor may sense an input of a stylus pen using an electromagnetic induction method. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device for preventing a magnetic field generated by a shielding electrode from reducing charging efficiency of a charging electrode.

[0007] Embodiments of the present disclosure provide a display device for preventing interference with pixels when driving a charging electrode.

[0008] An embodiment of the present disclosure provides an electronic device including the display device.

[0009] According to one aspect of the present disclosure, a display device includes: a display panel including a display area and a non-display area around the display area; and an input sensor disposed on the display panel, the input sensor including a sensing electrode configured to sense an electromagnetic induction current. The display panel includes: a base layer including a plurality of resin layers; a plurality of pixels disposed on the base layer and overlapping the display area; a charging electrode disposed under at least one resin layer among the plurality of resin layers and overlapping the display area; and a first shielding pattern disposed on the base layer and overlapping the display area, the first shielding pattern having a first thickness and having at least one slit that divides the first shielding pattern into a plurality of segments. The first thickness corresponds to a thickness that satisfies the relationship of the following formula:

[0010]

[0011] Here, T1 represents the first thickness, A is pi (π), B is the magnetic permeability of the first shield pattern, C is the frequency of the current flowing through the first shield pattern, and D is the resistivity of the first shield pattern.

[0012] When viewed in a plan view, the first shield pattern overlaps the charging electrode.

[0013] Each of the plurality of pixels may include a light emitting element and at least one transistor connected to the light emitting element, and the first shielding pattern may overlap the transistor when viewed in a plan view.

[0014] The first shielding pattern includes: a plurality of unit patterns including a first unit pattern covering the transistor; and a plurality of connection patterns, each of the plurality of connection patterns connecting two adjacent unit patterns among the plurality of unit patterns.

[0015] When viewed in a plan view, the entire transistor is covered by the first unit pattern.

[0016] The charging electrode is disposed in a space between two adjacent slits among the at least one slit when viewed in a plan view.

[0017] The at least one slit includes a plurality of slits, and the plurality of slits extend in a first direction and are spaced apart from each other in a second direction crossing the first direction.

[0018] The at least one slit includes a plurality of slits, and the plurality of slits extend radially with respect to a center of the first shield pattern.

[0019] At least one slit has a single slit including a plurality of first slit portions extending in a first direction and a plurality of second slit portions extending in a second direction crossing the first direction, and each of the plurality of second slit portions connects two adjacent first slit portions of the plurality of first slit portions.

[0020] The plurality of resin layers may include: a first resin layer; and a second resin layer disposed on the first resin layer. The charging electrode may be disposed on the first resin layer and may be covered by the second resin layer, and the first shielding pattern may be disposed on the second resin layer.

[0021] The display panel may further include: an insulating layer covering the first shielding pattern; and a second shielding pattern disposed on the insulating layer and overlapping the display area.

[0022] The second thickness of the second shielding pattern corresponds to a thickness that satisfies the relationship of the following formula:

[0023]

[0024] Wherein, T2 represents the second thickness.

[0025] One of the first shield pattern and the second shield pattern may cover transistors of a plurality of pixels when viewed from above the plane, and the other of the first shield pattern and the second shield pattern may cover the charging electrode when viewed from above the plane.

[0026] The sensing electrodes may include: a first electrode of a first group, extending in a first direction; a second electrode of the first group, extending in a second direction intersecting the first direction and capacitively coupled to the first electrode of the first group; a first electrode of the second group, extending in the first direction and sensing an electromagnetically induced current; a second electrode of the second group, extending in the second direction and sensing an electromagnetically induced current; a first signal line of the first group, connected to one end of the first electrode of the first group; a second signal line of the first group, connected to one end of the second electrode of the first group; a first signal line of the second group, connected to one end of the first electrode of the second group; and a second signal line of the second group, connected to one end of the second electrode of the second group.

[0027] The first shielding pattern may include at least one of rhodium (Rh), tungsten (W), and molybdenum (Mo).

[0028] According to an embodiment of the present disclosure, a display device includes: a display panel including a display area and a non-display area around the display area; and an input sensor disposed on the display panel, the input sensor including a sensing electrode for sensing an electromagnetically induced current. The display panel includes: a plurality of pixels overlapping the display area, each pixel including a light-emitting element and at least one transistor connected to the light-emitting element; a charging electrode spaced apart from the sensing electrode with a plurality of pixels between them, and overlapping the display area, wherein the charging electrode is below a first pixel among the plurality of pixels; and a shielding pattern disposed above the charging electrode and overlapping the display area, the shielding pattern being divided into a plurality of segments by at least one slit, and the shielding pattern being disposed between the charging electrode and the first pixel. The plurality of segments are configured to form a current path for generating a magnetic field.

[0029] The first thickness of the shielding pattern satisfies the following relationship:

[0030]

[0031] Here, T1 is the first thickness, A is pi (π), B is the magnetic permeability of the shielding pattern, C is the frequency of the current flowing through the shielding pattern, and D is the resistivity of the shielding pattern.

[0032] When viewed in a plan view, the shielding pattern may cover the charging electrode.

[0033] When viewed in a plan view, the shielding pattern may cover the transistor.

[0034] According to one aspect of the present disclosure, an electronic device includes: a housing; an electronic module disposed in the housing; a display device disposed to overlap the electronic module; and a stylus including a resonant circuit. The display device includes: a display panel including a display area and a non-display area around the display area; and an input sensor disposed on the display panel and configured to sense a resonant signal transmitted from the stylus. The display panel includes: a base layer including a plurality of resin layers; a plurality of pixels disposed on the base layer and overlapping the display area; a charging electrode disposed under at least one of the plurality of resin layers and charging the stylus; and a first shielding pattern disposed on the base layer and overlapping the display area, the first shielding pattern having a first thickness. The first thickness corresponds to a thickness that satisfies the relationship of the following formula:

[0035]

[0036] Here, T1 represents the first thickness, A is pi (π), B is the magnetic permeability of the first shield pattern, C is the frequency of the current flowing through the first shield pattern, and D is the resistivity of the first shield pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0038] Figures 1A to 1C is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0039] Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0040] Figure 3 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0041] Figure 4 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0042] Figure 5 is a plan view of a display panel according to an embodiment of the present disclosure.

[0043] Figure 6 is an enlarged cross-sectional view of a display module according to an embodiment of the present disclosure.

[0044] Fig. 7A and Figure 7B is a cross-sectional view of a portion of a display module according to an embodiment of the present disclosure.

[0045] Figure 8 is a plan view of a charging electrode included in a display device according to an embodiment of the present disclosure.

[0046] 9A to 9C is a plan view showing a charging electrode included in a display device according to an embodiment of the present disclosure during a charging period of an operation period.

[0047] FIG. 10A to FIG. 10E is a plan view of a shielding pattern according to an embodiment of the present disclosure.

[0048] FIG. 11A to FIG. 11C is a plan view of a shielding pattern and a charging electrode according to an embodiment of the present disclosure.

[0049] Fig.12 is a cross-sectional view of a portion of a display module according to an embodiment of the present disclosure.

[0050] FIG. 13A to FIG. 13E is a plan view of a transistor and a shielding pattern according to an embodiment of the present disclosure.

[0051] Fig.14A and Fig. 14B is a cross-sectional view of a portion of a display module according to an embodiment of the present disclosure.

[0052] Fig.15 is a plan view of an input sensor according to an embodiment of the present disclosure.

[0053] Fig.16 is an enlarged plan view of a portion of an input sensor according to an embodiment of the present disclosure.

[0054] Fig.17 and Fig.18 is a cross-sectional view of a portion of an input sensor according to an embodiment of the present disclosure.

[0055] Fig.19 is an enlarged plan view of a portion of an input sensor according to an embodiment of the present disclosure.

[0056] Fig. 20 is a plan view showing electrodes included in an input sensor according to an embodiment of the present disclosure during a first sensing period.

[0057] Fig.21 is a plan view showing electrodes included in an input sensor according to an embodiment of the present disclosure during a second sensing period. DETAILED DESCRIPTION

[0058] In this specification, when a component (or region, layer, component, etc.) is referred to as being "on," "connected to" or "coupled to" another component, this means that the component may be directly on, directly connected to, or directly coupled to the other component, or a third component may be present therebetween.

[0059] The same reference numerals represent the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for effective description. As used herein, the term "and / or" includes all of one or more combinations defined by the relevant components.

[0060] Terms such as first, second, etc. can be used to describe various components, but these components should not be limited by these terms. These terms can only be used to distinguish one component from other components. For example, without departing from the scope of the present disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component. Unless otherwise specified, terms in the singular may include plural forms.

[0061] In addition, terms such as "below", "beneath", "above", and "over" are used to describe the relationship of components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0062] It should be understood that when used herein, terms such as “comprises,” “includes,” and “having” indicate the presence of stated features, quantities, steps, operations, components, parts, or a combination thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or a combination thereof.

[0063] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which the present disclosure belongs. Those terms defined in commonly used dictionaries will be interpreted as having the same meanings as the contextual meanings in the relevant field, and should not be interpreted as having ideal or overly formal meanings, unless clearly defined as having such meanings in this application.

[0064] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0065] Figures 1A to 1C is a perspective view of an electronic device ED according to an embodiment of the present disclosure. Figure 1A The electronic device ED is shown in its unfolded state, and Figure 1B and Figure 1C The folded state of the electronic device ED is shown.

[0066] refer to Figures 1A to 1C , the electronic device ED according to an embodiment of the present disclosure may include a display surface DS defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. The electronic device ED may provide an image IM to a user through the display surface DS.

[0067] The display surface DS may include a display area DA and a non-display area NDA around the display area DA. In an embodiment, the non-display area NDA may surround the display area DA. The display area DA may display an image IM, and the non-display area NDA may not display the image IM. Although it is shown that the non-display area NDA may surround the display area DA, it is not limited thereto, and the shape of the display area DA and the shape of the non-display area NDA may be modified.

[0068] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. The third direction DR3 is a basis for distinguishing between the front surface and the rear surface of a member. The expression "when viewed from above a plane" or "when viewed in a plan view" used herein may mean that it is viewed in the third direction DR3. Hereinafter, the first direction DR1, the second direction DR2, and the third direction DR3 are directions indicated by the first direction axis to the third direction axis, respectively, and are given the same reference numerals as the reference numerals of the first direction axis to the third direction axis.

[0069] The electronic device ED may include a folding area FA and a plurality of non-folding areas NFA1 and NFA2. The non-folding areas NFA1 and NFA2 may include a first non-folding area NFA1 and a second non-folding area NFA2. The folding area FA may be disposed between the first non-folding area NFA1 and the second non-folding area NFA2 in the second direction DR2. In this embodiment, a foldable electronic device ED is shown as an example. However, the present disclosure is not limited thereto. The electronic device ED may be a bar-type electronic device, a rollable electronic device, or a slidable electronic device.

[0070] The electronic device ED can sense the input of the stylus pen STP and the input made by the user's body FG. A finger is shown as an example of the user's body FG. The electronic device ED can sense the input of the user's body FG during the first mode period and sense the input of the stylus pen STP during the second mode period by time division driving.

[0071] like Figure 1B As shown, the folding area FA can be folded along a folding axis FX parallel to the first direction DR1. The folding area FA has a certain curvature and a curvature radius R1. The electronic device ED can be folded in an inward folding manner so that the first non-folding area NFA1 and the second non-folding area NFA2 face each other and the display surface DS is not exposed to the outside.

[0072] In an embodiment of the present disclosure, the electronic device ED can be folded in an outward folding manner so that the display surface DS is exposed to the outside. In an embodiment of the present disclosure, the electronic device ED can be configured so that the inward folding operation and the outward folding operation are repeatedly performed in the unfolded state. However, the present disclosure is not limited thereto. In an embodiment of the present disclosure, the electronic device ED can be configured to select one of the unfolding operation, the inward folding operation, and the outward folding operation.

[0073] like Figure 1B As shown, the distance between the first non-folding area NFA1 and the second non-folding area NFA2 may be substantially equal to twice the radius of curvature R1. Figure 1C As shown, the distance between the first non-folding area NFA1 and the second non-folding area NFA2 may be less than twice the curvature radius R1. Figure 1B and Figure 1C The housing HM (refer to FIG. 1 ) which is shown based on the display surface DS and forms the appearance of the electronic device ED Figure 2 ) may contact distal end regions of the first non-folding area NFA1 and the second non-folding area NFA2.

[0074] Figure 2 is an exploded perspective view of an electronic device ED according to an embodiment of the present disclosure.

[0075] like Figure 2 As shown, the electronic device ED may include a display device DD, an electronic module EM, a power module PSM, and a housing HM. Although not shown separately, the electronic device ED may also include a mechanical structure for controlling the folding operation of the display device DD. Figure 2 In the drawings, the adhesive layer that couples the components to each other is not shown.

[0076] The display device DD generates an image and senses an external input. The display device DD includes a window WM and a display module DM. The window WM provides a front surface of the electronic device ED. The display device DD may further include additional components between the window WM and the display module DM, or may further include additional components below the display module DM.

[0077] The display module DM may include at least one display panel 100. Figure 2 Only the display panel 100 is shown in the stack structure of the display module DM, but the display module DM may further include a plurality of components disposed on the display panel 100. A detailed description of the stack structure of the display module DM will be given below.

[0078] The display panel 100 is not particularly limited, and may be, for example, an emissive display panel such as an organic light emitting display panel and an inorganic light emitting display panel.

[0079] The display panel 100 includes a display area 100-DA and a non-display area 100-NDA, which correspond to the display area DA of the electronic device ED (refer to Figure 1A ) and non-display area NDA (reference Figure 1A ). The pixel PX is disposed in the display area 100-DA. The pixel PX is not disposed in the non-display area 100-NDA, and a signal line for supplying a voltage to the pixel PX is disposed in the non-display area 100-NDA. The expression "one area / portion corresponds to another area / portion" used herein means that these areas / portions overlap each other and are not limited to having the same area.

[0080] like Figure 2 As shown, a driver integrated circuit (IC) DIC may be disposed on the non-display area 100-NDA of the display panel 100. A flexible circuit board FCB may be coupled to the non-display area 100-NDA of the display panel 100. The flexible circuit board FCB may be connected to a main circuit board. The main circuit board may be an electronic component constituting the electronic module EM. The electronic module EM may further include a control module (e.g., an application processor), a wireless communication module, an image input module, etc. At the same time, Figure 2 Differently, a portion of the flexible circuit board FCB may be disposed under the display panel 100. In the electronic device ED of one embodiment, as a portion of the display module DM or a portion of the flexible circuit board FCB is bent, a portion of the flexible circuit board FCB may be disposed under the display panel 100.

[0081] The driver IC DIC may include a driving element (eg, a data driving circuit) for driving the pixels PX of the display panel 100. Figure 2 A structure in which the driver IC DIC is mounted on the display panel 100 is shown, but the present disclosure is not limited thereto. For example, the driver IC DIC may be mounted on a flexible circuit board FCB.

[0082] refer to Figure 2, the electronic module EM can be respectively arranged in the first shell HM1 and the second shell HM2, and the power supply module PSM can be respectively arranged in the first shell HM1 and the second shell HM2. Although not shown, the electronic module EM arranged in the first shell HM1 and the electronic module EM arranged in the second shell HM2 can be electrically connected to each other through a flexible circuit board. The shells HM1 and HM2 are connected to the display device DD to accommodate other modules. For example, the shells HM1 and HM2 can be connected to the window WM of the display device DD and accommodate other modules. Although the shell HM is shown as including a first shell HM1 and a second shell HM2 separated from each other, the present disclosure is not limited to this. Although not shown, the electronic device ED may also include a hinge structure for connecting the first shell HM1 and the second shell HM2.

[0083] Figure 3 is a cross-sectional view of a display device according to an embodiment of the present disclosure. Figure 3 is corresponding to Figure 2 1 is a cross-sectional view of the display device DD taken along line II'.

[0084] refer to Figure 3 , the display device DD may include a window WM, a display module DM, a panel protection layer PPL, a cushion layer CSL, a first conductive sheet CTL1, a second conductive sheet CTL2, and first to fifth adhesive layers AL1 to AL5. Each of the first to fifth adhesive layers AL1 to AL5 connects two components stacked adjacent to each other among these components. The first to fifth adhesive layers AL1 to AL5 may include a pressure sensitive adhesive (PSA) or an optically clear adhesive (OCA). However, the type of the adhesive layer is not limited thereto.

[0085] The window WM provides the outer surface of the display device DD. The window WM may include a base layer BS, a window protection layer WP, a hard coating layer HC, and a printed layer PIT (or a black matrix layer). The base layer BS may have an optically transparent property. The base layer BS may include or may be formed of a glass or synthetic resin film. The window protection layer WP is attached to the base layer BS by an adhesive layer AL. The window protection layer WP may include or may be formed of a flexible plastic material such as polyimide and polyethylene terephthalate. The hard coating layer HC may be provided on the upper surface of the window protection layer WP.

[0086] The printed layer PIT may be disposed on the lower surface of the window protection layer WP. The printed layer PIT may be a black matrix layer. The color of the printed layer PIT may be black. However, the color of the printed layer PIT is not limited thereto. The printed layer PIT may be adjacent to the periphery of the window protection layer WP. The printed layer PIT may overlap with the non-display area NDA. However, the stacking structure of the window WM is not necessarily limited to the structure described above.

[0087] The panel protection layer PPL may be disposed below the display module DM. The panel protection layer PPL may protect the bottom of the display module DM. The panel protection layer PPL may include a flexible plastic material, or may be formed of a flexible plastic material. For example, the panel protection layer PPL may include polyethylene terephthalate (PET), or may be formed of polyethylene terephthalate (PET). In an embodiment of the present disclosure, the panel protection layer PPL may be omitted.

[0088] The cushion layer CSL is disposed under the panel protection layer PPL. The cushion layer CSL absorbs external impact. The cushion layer CSL may include or may be formed of foamed plastic. In an embodiment of the present disclosure, the cushion layer CSL may be omitted.

[0089] The first conductive sheet CTL1 may be disposed below the cushion layer CSL. The first conductive sheet CTL1 may include a material having high magnetic permeability, or may be formed of a material having high magnetic permeability. The first conductive sheet CTL1 may include a ferromagnetic material, or may be formed of a ferromagnetic material. For example, the first conductive sheet CTL1 may include a magnetic metal powder layer, or may be a magnetic metal powder layer. The magnetic metal powder layer may include a base resin and a magnetic metal powder mixed in the base resin. In an embodiment of the present disclosure, the first conductive sheet CTL1 may be omitted.

[0090] The second conductive sheet CTL2 may be disposed below the first conductive sheet CTL1. Figure 2 The second conductive sheet CTL2 may include or be formed of a diamagnetic material. In addition, the second conductive sheet CTL2 may radiate electromagnetic waves generated by the electronic module EM of the display module DM (eg, the driver IC DIC (refer to FIG. 2 )). Figure 2 ))The heat generated.

[0091] The second conductive sheet CTL2 may include a metal layer such as copper, aluminum, gold, and titanium. The second conductive sheet CTL2 may include a metal oxide layer such as indium tin oxide (ITO) and indium zinc oxide (IZO). The second conductive sheet CTL2 may include carbon nanotubes, carbon nanotubes coated with a conductive polymer, or graphite.

[0092] Figure 4 is a cross-sectional view of a display module DM according to an embodiment of the present disclosure. Figure 4 , the display module DM may include a display panel 100 , an input sensor 200 , and an anti-reflector 300 .

[0093] The display panel 100 may include a base layer 110, a driving element layer 120, a light emitting element layer 130, and an encapsulation layer 140. The base layer 110 may provide a base surface on which the driving element layer 120 is disposed.

[0094] The base layer 110 may be a rigid substrate. In an embodiment, the base layer 110 may be a flexible substrate that may be bent, folded, or rolled.

[0095] The base layer 110 has a multilayer structure. In an embodiment, the base layer 110 may include a plurality of resin layers. The base layer 110 may include a plurality of resin layers and an inorganic layer, the inorganic layer being disposed between the plurality of resin layers and having a single layer structure or a multilayer structure. The specific structure of the base layer 110 will be described below.

[0096] The driving element layer 120 may be disposed on the base layer 110. The driving element layer 120 may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. The driving element layer 120 includes a reference Figure 2 The light emitting element layer 130 may be disposed on the driving element layer 120. The light emitting element layer 130 may include a reference Figure 2 The light emitting element of the pixel PX is described.

[0097] The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may protect the light emitting element layer 130 from foreign matter such as moisture, oxygen, and dust particles. The encapsulation layer 140 may include at least one inorganic layer. The encapsulation layer 140 may include a stacked structure of inorganic layer / organic layer / inorganic layer.

[0098] The input sensor 200 may be disposed on the display panel 100. The input sensor 200 may sense Figure 1A The input of the stylus STP shown (for example, a resonant signal transmitted from the stylus STP) and the input by the user's body FG. The input sensor 200 may be formed on the display panel 100 by a continuous process. In an embodiment, the continuous process may represent two or more processes performed on the display panel 100 in a multi-chamber system without being exposed to the atmospheric environment. In this case, the input sensor 200 may be directly disposed on the display panel 100. The input sensor 200 may be directly disposed on the encapsulation layer 140. As used herein, the expression “component A is directly disposed on component B” means that an adhesive layer is not disposed between component A and component B.

[0099] The anti-reflector 300 may be disposed on the input sensor 200. The anti-reflector 300 may reduce reflectivity of external light. The anti-reflector 300 may be directly disposed on the input sensor 200 through a continuous process.

[0100] The anti-reflector 300 may include a color filter. The color filter has a color corresponding to the color of the source light. For example, a red color filter is disposed on a light emitting element that generates red light. The anti-reflector 300 may further include a light blocking pattern disposed between the color filters.

[0101] Figure 5 is a plan view of a display panel 100 according to an embodiment of the present disclosure.

[0102] refer to Figure 5 , the display panel 100 may include a plurality of pixels PX, a scan drive circuit SDV, an emission drive circuit EDV, a plurality of signal lines, and a plurality of first pads PD1. The driver IC DIC mounted on the non-display area 100-NDA may include a data drive circuit. In an embodiment of the present disclosure, the data drive circuit may be integrated into the display panel 100 like the scan drive circuit SDV and the emission drive circuit EDV.

[0103] The plurality of signal lines may include a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, first and second control lines SL-C1 and SL-C2, and first and second power lines PL1 and PL2. Here, "m" and "n" are natural numbers of 2 or more.

[0104] The scan lines SL1 to SLm may extend in the first direction DR1 and may be connected to the pixels PX and the scan driving circuit SDV. The data lines DL1 to DLn may extend in the second direction DR2 and may be connected to the pixels PX and the driver IC DIC. The emission lines EL1 to ELm may extend in the first direction DR1 and may be connected to the pixels PX and the emission driving circuit EDV.

[0105] The first power line PL1 receives a first power voltage, and the second power line PL2 receives a second power voltage having a level lower than the first power voltage. In an embodiment, the second power voltage may be a ground level voltage. Although not shown, the second electrode (ie, cathode) of the light emitting element is connected to the second power line PL2.

[0106] The first control line SL-C1 may be connected to the scan driving circuit SDV and may extend toward the lower end of the display panel 100. The second control line SL-C2 may be connected to the emission driving circuit EDV and may extend toward the lower end of the display panel 100. The first pad PD1 may be disposed in the non-display area 100-NDA adjacent to the lower end of the display panel 100 and may be closer to the lower end of the display panel 100 than the driver IC DIC. The first pad PD1 may be connected to the driver IC DIC and some of the signal lines.

[0107] The scan driving circuit SDV may generate a plurality of scan signals, and the scan signals may be applied to the pixels PX through the scan lines SL1 to SLm. The driver IC DIC may generate a plurality of data voltages, and the data voltages may be applied to the pixels PX through the data lines DL1 to DLn. The emission driving circuit EDV may generate a plurality of emission signals, and the emission signals may be applied to the pixels PX through the emission lines EL1 to ELm.

[0108] The pixel PX may receive a data voltage in response to the scan signal, and the pixel PX may display an image by emitting light having brightness corresponding to the data voltage in response to the emission signal.

[0109] Figure 6 is an enlarged cross-sectional view of a display module DM according to an embodiment of the present disclosure.

[0110] exist Figure 6 , a cross section corresponding to one emission area LA and a non-emission area NLA around the one emission area LA is shown. Figure 6 , a light emitting element LD included in one pixel PX and a transistor TFT connected to the light emitting element LD are shown. The transistor TFT may be one of a plurality of transistors included in a driving circuit of the pixel PX. In this embodiment, the transistor TFT is described as a silicon transistor. However, the transistor TFT may be a metal oxide transistor.

[0111] The base layer 110 has a multi-layer structure. In an embodiment, the base layer 110 may include a plurality of resin layers. In an embodiment, the base layer 110 may further include an inorganic layer disposed between the plurality of resin layers. In an embodiment, the base layer 110 may be a single-layer structure.

[0112] The base layer 110 may be a multilayer structure including a first resin layer 110-1 and a second resin layer 110-2. The second resin layer 110-2 may be disposed on the first resin layer 110-1. Each of the first resin layer 110-1 and the second resin layer 110-2 may include a polymer resin or may be formed of a polymer resin. For example, each of the first resin layer 110-1 and the second resin layer 110-2 may include an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose resin, a siloxane-based resin, a polyimide resin, a polyamide resin, or a perylene-based resin, or may be formed of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose resin, a siloxane-based resin, a polyimide resin, a polyamide resin, or a perylene-based resin. Each of the first resin layer 110 - 1 and the second resin layer 110 - 2 may include polyimide or may be formed of polyimide.

[0113] Although not shown, the base layer 110 may further include an inorganic layer disposed between the first resin layer 110-1 and the second resin layer 110-2. For example, the inorganic layer may include silicon oxide, silicon nitride, or silicon oxynitride, or may be formed of silicon oxide, silicon nitride, or silicon oxynitride. In an embodiment, the base layer 110 may be a single-layer structure.

[0114] In an embodiment, the display panel 100 includes a charging electrode PCE. The charging electrode PCE is disposed under at least one of the plurality of resin layers 110-1 and 110-2 included in the base layer 110. Figure 6 As shown, the charging electrode PCE may be disposed under the second resin layer 110-2. The charging electrode PCE may be disposed on the first resin layer 110-1 and may be covered by the second resin layer 110-2. Meanwhile, when the base layer 110 includes an inorganic layer disposed between the first resin layer 110-1 and the second resin layer 110-2, the charging electrode PCE may be disposed on the inorganic layer.

[0115] The charging electrode PCE charges the stylus STP (reference Figure 1A ) is charged by a resonant circuit. The charging electrode PCE can generate a magnetic field by forming a coil-shaped current path through a constant voltage applied from the outside, and the stylus pen STP (reference Figure 1A ) can be charged by receiving the generated magnetic field. A description of this will be given below.

[0116] refer to Figure 5 and Figure 6, when viewed from above the plane, the charging electrode PCE overlaps the display area 100-DA. When viewed from above the plane, the charging electrode PCE may overlap the pixel PX disposed in the display area 100-DA. When viewed from above the plane, at least a portion of the charging electrode PCE may overlap the light emitting element LD. For example, at least a portion of the charging electrode PCE may overlap the emission area LA. Unlike the conductive pattern layers 200-CL1 and 200-CL2 of the input sensor 200 to be described below, since the charging electrode PCE is disposed below the driving element layer 120 and the light emitting element layer 130, even if the charging electrode PCE overlaps the emission area LA, the charging electrode PCE does not degrade the emission efficiency of the light emitting element LD.

[0117] The charging electrode PCE may have a single-layer structure, or may have a multi-layer structure stacked in the third direction DR3. The conductive pattern having a multi-layer structure may include at least one metal layer. The multi-layer conductive pattern may also include a transparent conductive layer. The multi-layer conductive pattern may include a metal layer containing different metals. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires or graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum or an alloy thereof, or may be formed of molybdenum, silver, titanium, copper, aluminum or an alloy thereof.

[0118] The buffer layer 10br may be disposed on the base layer 110. The buffer layer 10br may prevent metal atoms or impurities from the base layer 110 from diffusing into the semiconductor pattern on the upper side of the buffer layer 10br. The semiconductor pattern includes an active region AC1 of the transistor TFT.

[0119] The shielding pattern BMLa may be disposed under the transistor TFT. The shielding pattern BMLa may block external light from reaching the transistor TFT. The shielding pattern BMLa may be disposed between the base layer 110 and the buffer layer 10br. In an embodiment of the present disclosure, an inorganic barrier layer may be additionally disposed between the shielding pattern BMLa and the buffer layer 10br. The shielding pattern BMLa may be connected to an electrode or a wire, and may receive a constant voltage or signal from the electrode or the wire.

[0120] When viewed from above the plane, the shielding pattern BMLa may overlap with the charging electrode PCE. The shielding pattern BMLa may be disposed on the second resin layer 110-2 and may be disposed to completely overlap with the charging electrode PCE when viewed from above the plane. In an embodiment, the shielding pattern BMLa may be disposed on the uppermost resin layer of the base layer 110. In an embodiment, the shielding pattern BMLa may be disposed in the space between the charging electrode PCE and the transistor TFT. For example, the shielding pattern BMLa may be disposed to cover the top of the charging electrode PCE. However, not limited to this, the shielding pattern BMLa may be disposed to overlap only a portion of the charging electrode PCE. The shielding pattern BMLa may be disposed above the charging electrode PCE, and may prevent the parasitic capacitance generated by the charging electrode PCE from degrading the characteristics of the semiconductor pattern, the conductive pattern, and the signal line included in the driving element layer 120. The specific arrangement of the shielding pattern BMLa and its shape will be described below.

[0121] The semiconductor pattern may be disposed on the buffer layer 10br. The semiconductor pattern may include a silicon semiconductor material, or may be formed of a silicon semiconductor material. For example, the silicon semiconductor material may include amorphous silicon or polycrystalline silicon, or may be formed of amorphous silicon or polycrystalline silicon. For example, the semiconductor pattern may include low-temperature polycrystalline silicon, or may be formed of low-temperature polycrystalline silicon.

[0122] The semiconductor pattern may include a first region having high conductivity and a second region having low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a doped region doped with a P-type dopant, and the N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region, or may be a region that is doped more lightly than the first region.

[0123] The conductivity of the first region may be higher than that of the second region, and the first region may be used as an electrode or a signal line. The second region may correspond to an active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be an active region of a transistor, another portion may be a source or drain of the transistor, and another portion may be a connecting electrode or a connecting signal line.

[0124] The source region SA1, active region AC1 and drain region DA1 of the transistor TFT may be formed of a semiconductor pattern. In a cross-sectional view of the transistor TFT, the source region SA1 and the drain region DA1 may extend from the active region AC1 in opposite directions.

[0125] The first insulating layer 10 may be disposed on the buffer layer 10br. The first insulating layer 10 may be commonly connected to the plurality of pixels PX (refer to Figure 2) overlap, and may cover the semiconductor pattern. The first insulating layer 10 may include an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may be a single silicon oxide layer. Not only the first insulating layer 10 but also the insulating layer of the driving element layer 120 to be described below may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, but is not limited thereto.

[0126] The gate electrode GT1 of the transistor TFT is disposed on the first insulating layer 10. The gate electrode GT1 may be a part of the metal pattern. The gate electrode GT1 overlaps with the active region AC1. The gate electrode GT1 may be used as a mask in the process of doping the semiconductor pattern. The gate electrode GT1 may include titanium (Ti), silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO) or indium zinc oxide (IZO), or may be formed of titanium (Ti), silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO) or indium zinc oxide (IZO), but is not particularly limited thereto.

[0127] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate GT1. The third insulating layer 30 may be disposed on the second insulating layer 20. The second electrode CE20 of the storage capacitor Cst may be disposed between the second insulating layer 20 and the third insulating layer 30. In addition, the first electrode CE10 of the storage capacitor Cst may be disposed between the first insulating layer 10 and the second insulating layer 20.

[0128] The first connection electrode CN1 may be disposed on the third insulating layer 30. The first connection electrode CN1 may be connected to the drain area DA1 of the transistor TFT through a contact hole passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0129] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The second connection electrode CN2 may be disposed on the fourth insulating layer 40. The second connection electrode CN2 may be connected to the first connection electrode CN1 through a contact hole passing through the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the second connection electrode CN2. The stacked structure of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 is only illustrative, and an additional conductive layer and an additional insulating layer may be further disposed in addition to the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50.

[0130] The fourth insulating layer 40 and the fifth insulating layer 50 may be organic layers. For example, the organic layer may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), and polystyrene (PS), a polymer derivative having a phenolic group, an acrylate-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, an acetylene-based polymer, or a blend thereof.

[0131] The light emitting element LD may include a first electrode (or pixel electrode) AE, an emission layer EL, and a second electrode (or common electrode) CE. The first electrode AE ​​may be disposed on the fifth insulating layer 50. The first electrode AE ​​may be a semi-transparent electrode, a transparent electrode, or a reflective electrode. The first electrode AE ​​may include a reflective layer and a transparent or semi-transparent electrode layer formed on the reflective layer, or may be a reflective layer and a transparent or semi-transparent electrode layer formed on the reflective layer, wherein the reflective layer is formed of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, Yb, W, or a compound or mixture thereof (e.g., AgMg, AgYb, or MgAg) or a material having a multilayer structure such as LiF / Ca or LiF / Al. The transparent or semi-transparent electrode layer may include a material selected from indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and aluminum-doped zinc oxide (AZO), or may be selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3) and aluminum-doped zinc oxide (AZO) are formed of at least one of the group consisting of. For example, the first electrode AE ​​may include a stack structure of ITO / Ag / ITO, or may be a stack structure of ITO / Ag / ITO.

[0132] The pixel defining layer PDL may be disposed on the fifth insulating layer 50. According to an embodiment, the pixel defining layer PDL may include a material that absorbs light, or may be formed of a material that absorbs light. For example, the color of the pixel defining layer PDL may be black. For example, the pixel defining layer PDL may include a black colorant, or may be formed of a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The pixel defining layer PDL may correspond to a light blocking pattern having a light blocking characteristic.

[0133] The pixel defining layer PDL may cover a portion of the first electrode AE ​​(e.g., an anode). In an embodiment, the pixel defining layer PDL may cover an edge portion of the first electrode AE. For example, the pixel defining layer PDL may have an opening PDL-OP exposing a portion of the first electrode AE. The opening PDL-OP of the pixel defining layer PDL may define an emission area LA.

[0134] The pixel defining layer PDL may increase the distance between the edge of the first electrode AE ​​and the second electrode CE (eg, cathode). Therefore, the pixel defining layer PDL may serve to prevent an arc from occurring at the edge of the first electrode AE.

[0135] Although not shown, a hole control layer may be provided between the first electrode AE ​​and the emission layer EL. The hole control layer may include a hole transport layer. In an embodiment, the hole control layer may further include a hole injection layer. An electron control layer may be provided between the emission layer EL and the second electrode CE. The electron control layer may include an electron transport layer. In an embodiment, the electron control layer may further include an electron injection layer.

[0136] The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may include an inorganic layer 141, an organic layer 142, and an inorganic layer 143 sequentially stacked on one another. However, the layers constituting the encapsulation layer 140 are not limited thereto.

[0137] The inorganic layers 141 and 143 may protect the light emitting element layer 130 from moisture and oxygen, and the organic layer 142 may protect the light emitting element layer 130 from foreign matter such as dust particles. The inorganic layers 141 and 143 may include or be formed of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer 142 may include or be formed of an acrylic organic layer, but is not limited thereto.

[0138] The input sensor 200 may be disposed on the display panel 100. The input sensor 200 may include a first insulating layer 200-IL1, a first conductive pattern layer 200-CL1, a second insulating layer 200-IL2, a second conductive pattern layer 200-CL2, and a third insulating layer 200-IL3. The first insulating layer 200-IL1 may be disposed directly on the encapsulation layer 140.

[0139] In an embodiment of the present disclosure, the first insulating layer 200-IL1 and / or the third insulating layer 200-IL3 may be omitted. When the first insulating layer 200-IL1 is omitted, the first conductive pattern layer 200-CL1 may be disposed on the uppermost insulating layer of the encapsulation layer 140. The third insulating layer 200-IL3 may be replaced with an adhesive layer or an insulating layer of the anti-reflector 300 disposed on the input sensor 200.

[0140] The first conductive pattern layer 200-CL1 may include a first conductive pattern, and the second conductive pattern layer 200-CL2 may include a second conductive pattern. The first conductive pattern layer 200-CL1 is disposed on the first insulating layer 200-IL1. The second conductive pattern layer 200-CL2 is disposed on the second insulating layer 200-IL2. Hereinafter, the first conductive pattern layer 200-CL1 and the first conductive pattern are represented by the same reference numerals, and the second conductive pattern layer 200-CL2 and the second conductive pattern are represented by the same reference numerals. At the same time, the first conductive pattern 200-CL1 and the second conductive pattern 200-CL2 may correspond to the sensing electrodes to be described below.

[0141] Each of the first conductive pattern 200-CL1 and the second conductive pattern 200-CL2 may have a single layer structure, or may have a multilayer structure stacked in the third direction DR3. The conductive pattern having a multilayer structure may include at least two of a transparent conductive layer and a metal layer. The multilayer conductive pattern may include a metal layer containing different metals. The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, or graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof.

[0142] Each of the first conductive pattern 200-CL1 and the second conductive pattern 200-CL2 may have a thickness selected from the range of 0.1 μm to 1 μm. When each of the first conductive pattern 200-CL1 and the second conductive pattern 200-CL2 has a thickness less than 0.1 μm, wiring resistance may be increased, and thus the input sensing performance of the input sensor 200 may be reduced. When each of the first conductive pattern 200-CL1 and the second conductive pattern 200-CL2 has a thickness greater than 1 μm, the input sensor 200 may cause the electronic device ED (reference Figure 1A ) is increased to such an extent that the folding characteristics of the electronic device ED may be deteriorated.

[0143] In this embodiment, each of the first insulating layer 200-IL1, the second insulating layer 200-IL2, and the third insulating layer 200-IL3 may include an inorganic layer or an organic layer. In this embodiment, the first insulating layer 200-IL1, the second insulating layer 200-IL2, and the third insulating layer 200-IL3 may include an inorganic layer. The inorganic layer may include silicon oxide, silicon nitride, or silicon oxynitride.

[0144] In an embodiment of the present disclosure, at least one of the first insulating layer 200-IL1, the second insulating layer 200-IL2, and the third insulating layer 200-IL3 may be an organic layer. For example, the third insulating layer 200-IL3 may include an organic layer, or may be an organic layer. The organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane-based resin, cellulose resin, siloxane-based resin, polyimide resin, polyamide resin, and perylene-based resin.

[0145] The anti-reflector 300 may be disposed on the input sensor 200. The anti-reflector 300 may include a light blocking pattern 310, a color filter 320, and a planarization layer 330. In an embodiment of the present disclosure, the light blocking pattern 310 may be omitted.

[0146] The material constituting the light blocking pattern 310 is not particularly limited as long as it is a material capable of absorbing light. The light blocking pattern 310 may be a layer having a black color. In an embodiment, the light blocking pattern 310 may include a black colorant, or may be formed of a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof.

[0147] When viewed from above a plane, the light blocking pattern 310 may overlap the first conductive pattern 200-CL1 and the second conductive pattern 200-CL2. The light blocking pattern 310 may prevent external light from being reflected by the first conductive pattern 200-CL1 and the second conductive pattern 200-CL2. The light blocking pattern 310 may have an opening 310-OP defined therein. The opening 310-OP of the light blocking pattern 310 may overlap the first electrode AE ​​and may have an area larger than the opening PDL-OP of the pixel defining layer PDL. The opening 310-OP of the light blocking pattern 310 may define a pixel area PXA. The pixel area PXA may be defined as an area through which light generated by the light emitting element LD is emitted to the outside. As the area of ​​the pixel area PXA increases, the brightness of the image may increase.

[0148] The color filter 320 may overlap the pixel area PXA. In an embodiment, the color filter 320 may overlap the pixel area PXA and the non-pixel area NPXA. A portion of the color filter 320 may be disposed on the light blocking pattern 310. The color filter 320 may transmit the light generated by the light emitting element LD and may block external light of some wavelength bands. Therefore, the color filter 320 may reduce the reflection of the first electrode AE ​​or the second electrode CE to the external light.

[0149] The planarization layer 330 may cover the light blocking pattern 310 and the color filter 320. The planarization layer 330 may include an organic material, or may be formed of an organic material. The planarization layer 330 may provide a flat upper surface.

[0150] Fig. 7A and Figure 7B is a cross-sectional view of a portion of a display module DM according to an embodiment of the present disclosure. Fig. 7A and Figure 7B In FIG. 1 , a cross section of three light emitting elements LD and transistors TFT connected thereto is shown. Fig. 7A and Figure 7B , a stacked structure of a display panel 100 and an input sensor 200 included in a display module DM is shown, and the anti-reflection film 300 (refer to Figure 6 ).

[0151] Reference together Figure 6 and Fig. 7A The display panel 100 may include a plurality of pixels, and the pixels may include a plurality of light emitting elements LD-1, LD-2, and LD-3 disposed in the light emitting element layer 130 and transistors TFT-1, TFT-2, and TFT-3 respectively connected to the light emitting elements LD-1, LD-2, and LD-3.

[0152] The display module DM may include a non-emission area NLA and emission areas LA-1, LA-2, and LA-3. The emission areas LA-1, LA-2, and LA-3 may be areas through which light generated by the light emitting elements LD-1, LD-2, and LD-3 is emitted. When viewed from above a plane, the emission areas LA-1, LA-2, and LA-3 may be spaced apart from each other.

[0153] The emission areas LA-1, LA-2 and LA-3 may be areas separated from each other by the pixel defining layer PDL. The non-emission area NLA may correspond to an area between the emission areas LA-1, LA-2 and LA-3, and may be an area corresponding to the pixel defining layer PDL. The pixel defining layer PDL may separate the light emitting elements LD-1, LD-2 and LD-3 from each other. The emission layers EL1, EL2 and EL3 of the light emitting elements LD-1, LD-2 and LD-3 may be separated from each other by being arranged in an opening PDL-OP defined in the pixel defining layer PDL.

[0154] The emission areas LA-1, LA-2, and LA-3 may be divided into a plurality of groups according to the colors of the lights generated by the light emitting elements LD-1, LD-2, and LD-3. Fig. 7A and Figure 7B In the illustrated embodiment, the display device DD may include three emission areas LA-1, LA-2 and LA-3 that emit red light, green light and blue light. For example, the display device DD may include a first emission area LA-1, a second emission area LA-2 and a third emission area LA-3 that are separated from each other.

[0155] In the display device DD according to the embodiment, a plurality of light emitting elements LD-1, LD-2 and LD-3 may emit light of different wavelength ranges. For example, in the embodiment, the display device DD may include a first light emitting element LD-1 emitting red light, a second light emitting element LD-2 emitting green light, and a third light emitting element LD-3 emitting blue light. That is, the first emission area LA-1, the second emission area LA-2 and the third emission area LA-3 of the display device DD may correspond to the first light emitting element LD-1, the second light emitting element LD-2 and the third light emitting element LD-3, respectively.

[0156] However, the embodiments of the present disclosure are not limited thereto, and the first light-emitting element LD-1, the second light-emitting element LD-2, and the third light-emitting element LD-3 may emit light in the same wavelength range, or at least one of the first light-emitting element LD-1, the second light-emitting element LD-2, and the third light-emitting element LD-3 may emit light in different wavelength ranges. For example, the first light-emitting element LD-1, the second light-emitting element LD-2, and the third light-emitting element LD-3 may all emit blue light.

[0157] The first light-emitting element LD-1, the second light-emitting element LD-2 and the third light-emitting element LD-3 may include a first electrode AE, emission layers EL1, EL2 and EL3, and a second electrode CE (or a common electrode). The first electrode AE ​​may be disposed on the fifth insulating layer 50. The first electrode AE ​​may be a semi-transparent electrode, a transparent electrode or a reflective electrode. The first electrode AE ​​may include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include a layer selected from indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and aluminum-doped zinc oxide (AZO) of at least one of the group consisting of. For example, the first electrode AE ​​may include a stack structure of ITO / Ag / ITO, or may be a stack structure of ITO / Ag / ITO.

[0158] The emission layers EL1, EL2, and EL3 may have a single-layer structure formed of a single material, a single-layer structure formed of a plurality of different materials, or a multilayer structure having a plurality of layers formed of a plurality of different materials. The emission layers EL1, EL2, and EL3 may include a well-known host and a dopant for emitting light within the wavelength range described above. For example, the light-emitting elements LD-1, LD-2, and LD-3 may include an organic light-emitting diode (such as tris(8-hydroxyquinolinato)aluminum (Alq 3 ) and rubrene), polymer light-emitting diodes, or quantum dots.

[0159] The second electrode CE may be provided as a common layer and may be a transparent electrode or a semi-transmissive and semi-reflective electrode. The second electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, Yb, W or a compound or mixture thereof (e.g., AgMg, AgYb or MgYb) or a material having a multilayer structure such as LiF / Ca or LiF / Al.

[0160] In an embodiment, the display panel 100 may include a charging electrode PCE, and the charging electrode PCE may overlap with a pixel. When viewed from above a plane, at least a portion of the charging electrode PCE may overlap with at least a portion of the plurality of light emitting elements LD-1, LD-2, and LD-3. For example, a portion of the charging electrode PCE may overlap with at least a portion of the first emission region LA-1, the second emission region LA-2, and the third emission region LA-3. Fig. 7A and Figure 7B, the charging electrode PCE is shown as overlapping the first emission area LA-1 and the third emission area LA-3. However, not limited to this, the charging electrode PCE may overlap only one of the first emission area LA-1, the second emission area LA-2 and the third emission area LA-3, or may overlap the first emission area LA-1, the second emission area LA-2 and the third emission area LA-3.

[0161] The base layer 110 includes a plurality of resin layers, and the charging electrode PCE is disposed under at least one of the plurality of resin layers. For example, the charging electrode PCE may be disposed in a space between two adjacent resin layers of the plurality of resin layers. Fig. 7A As shown, the base layer 110 may include a first resin layer 110-1 and a second resin layer 110-2, and the charging electrode PCE may be disposed below the second resin layer 110-2. For example, the charging electrode PCE may be disposed in the space between the first resin layer 110-1 and the second resin layer 110-2. The upper surface of the charging electrode PCE may be covered by the second resin layer 110-2. Meanwhile, when the base layer 110 includes an inorganic layer disposed between the first resin layer 110-1 and the second resin layer 110-2 and having a single-layer structure or a multi-layer structure, the charging electrode PCE may be disposed on the inorganic layer.

[0162] The charging electrode PCE may be disposed between the plurality of resin layers 110-1 and 110-2 of the display panel 100, and may be spaced apart from the conductive pattern layers 200-CL1 and 200-CL2 included in the input sensor 200. The charging electrode PCE may be spaced apart from the conductive pattern layers 200-CL1 and 200-CL2 with a plurality of pixels therebetween. The charging electrode PCE may be spaced apart from the conductive pattern layers 200-CL1 and 200-CL2 with the driving element layer 120 and the light emitting element layer 130 therebetween. The driving element layer 120, the light emitting element layer 130, and the encapsulation layer 140 may be disposed between the charging electrode PCE and the conductive pattern layers 200-CL1 and 200-CL2 in the third direction DR3.

[0163] The charging electrode PCE may form a magnetic field MF1 by forming a current path in a coil shape. The magnetic field MF1 formed by the charging electrode PCE may be transmitted to the stylus pen STP (refer to Fig. 9B ) resonant circuit, and can be used for stylus STP (reference Fig. 9B )Charge.

[0164] The shielding pattern BMLa may be disposed on the second resin layer 110-2 and may be covered by the buffer layer 10br. The shielding pattern BMLa may include a conductive material or may be formed of a conductive material. The shielding pattern BMLa may be aligned with the display area 100-DA (reference Figure 5)overlapping.

[0165] Since the shielding pattern BMLa is a conductive metal, an eddy current can be induced by the magnetic field MF1 formed by the charging electrode PCE. Here, the eddy current is a current loop induced in the second conductor adjacent to the first conductor by the electromagnetic induction phenomenon when the magnetic field applied to the first conductor changes with time. An eddy current flowing in a direction opposite to the direction of the current applied to the first conductor is formed in the second conductor. Therefore, a magnetic field opposite to the magnetic field formed in the first conductor is formed in the second conductor, and thus the intensity of the magnetic field formed in the first conductor is reduced.

[0166] The eddy current of the shielding pattern BMLa may form a canceling magnetic field MF2 that cancels the magnetic field MF1 formed by the charging electrode PCE. In an embodiment, the magnetic field MF1 formed by the charging electrode PCE may be canceled by the canceling magnetic field MF2 formed by the shielding pattern BMLa, so that the actual magnetic field MF3 (whose intensity is reduced compared to the intensity of the magnetic field MF1) may be transmitted to the stylus pen STP (reference Fig. 9B ). Thus, the charging efficiency of the charging electrode PCE may be reduced. The reduction in charging efficiency may be prevented by the shielding pattern BMLa having a first thickness T1, and a specific thickness of the first thickness T1 is set based on Formula 1 described below.

[0167] The shielding pattern BMLa may have a first thickness T1, and slits SLT (refer to Fig. 10A ). The first thickness T1 of the shielding pattern BMLa may satisfy the range of the following formula 1. The first thickness T1 of the shielding pattern BMLa may be the thickness of the shielding pattern BMLa in the third direction DR3. In the following formula 1, A is pi (π), B is the magnetic permeability of the shielding pattern BMLa, C is the frequency of the current flowing through the shielding pattern BMLa, and D is the resistivity of the shielding pattern BMLa.

[0168] [Formula 1]

[0169]

[0170] The first thickness T1 of the shielding pattern BMLa for ensuring the charging efficiency of the charging electrode PCE may depend on the composition of the material constituting the shielding pattern BMLa and the frequency of the current flowing through the shielding pattern BMLa. In the following, the maximum value of the first thickness T1 expressed on the right side of Formula 1 is referred to as the critical thickness. As the magnetic permeability of the shielding pattern BMLa and the frequency of the current flowing through the shielding pattern BMLa increase, the critical thickness may decrease. The critical thickness may increase as the resistivity of the shielding pattern BMLa increases. In an embodiment, the first thickness T1 of the shielding pattern BMLa for ensuring the charging efficiency of the charging electrode PCE may be greater than or equal to the minimum thickness and less than the critical thickness, and the minimum thickness is greater than zero. For example, the first thickness T1 may have a thickness selected from the range of the minimum thickness to the critical thickness.

[0171] When the first thickness T1 is greater than the critical thickness, the skin effect of the shielding pattern BMLa may be increased, and thus the elimination magnetic field MF2 generated by the shielding pattern BMLa may be increased. Therefore, the elimination magnetic field MF2 may be minimized by making the first thickness T1 less than the critical thickness. By reducing the elimination magnetic field MF2, the amount of the magnetic field MF1 generated by the charging electrode PCE transmitted to the stylus STP (reference Fig. 9B ) of the actual magnetic field MF3. Therefore, the charging efficiency of the charging electrode PCE can be improved.

[0172] The shielding pattern BMLa may include at least one of silver (Ag), copper (Cu), aluminum (Al), rhodium (Rh), tungsten (W), and molybdenum (Mo). When a metal having a high resistivity is used as the shielding pattern BMLa, the size of the elimination magnetic field MF2 formed by the shielding pattern BMLa can be reduced, and the charging efficiency of the charging electrode PCE can be increased. In an embodiment, the shielding pattern BMLa may include at least one of rhodium, tungsten, and molybdenum having a relatively high resistivity compared to silver, copper, or aluminum having a relatively low resistivity, or may be formed of at least one of these rhodium, tungsten, and molybdenum having a relatively high resistivity. This can be confirmed by referring to Formula 2 below.

[0173] In the following Formula 2, S is the shielding factor of the shielding pattern BMLa, A is pi (π), B is the magnetic permeability in a vacuum state, C is the frequency of the current flowing through the shielding pattern BMLa, D is the resistivity of the shielding pattern BMLa, T is the thickness of the shielding pattern BMLa, and L is the length of the current path of the eddy current formed in the shielding pattern BMLa.

[0174] [Formula 2]

[0175]

[0176] Referring to Formula 2, when the resistivity of the shielding pattern BMLa increases, the shielding factor of the shielding pattern BMLa can be reduced. Therefore, the magnitude of the canceling magnetic field MF2 formed in the shielding pattern BMLa can be reduced, and the magnitude of the magnetic field transmitted to the stylus pen STP (refer to Fig. 9B ) of the resonant circuit. Therefore, the charging efficiency of the charging electrode PCE can be improved. In Formula 2, as the thickness of the shielding pattern BMLa increases, its shielding factor increases. However, as described above, when the thickness exceeds the critical thickness, the magnetic field transmitted to the stylus STP (reference Fig. 9B )'s actual magnetic field MF3 of the resonant circuit can be reduced.

[0177] The display panel 100 of one embodiment may further include a connection line CNE1 connected to the charging electrode PCE and applying a ground voltage to the charging electrode PCE. The connection line CNE1 may pass through a resin layer disposed on the charging electrode PCE and may be connected to the charging electrode PCE. In an embodiment, the connection line CNE1 may be connected to the charging electrode PCE through a contact hole CNH1 passing through the second resin layer 110-2.

[0178] The connection line CNE1 may be disposed on the same layer as the shielding pattern BMLa. The connection line CNE1 may be disposed on the second resin layer 110-2 like the shielding pattern BMLa, and may include the same material as the shielding pattern BMLa. The connection line CNE1 may be formed by the same process as that of the shielding pattern BMLa. For example, the connection line CNE1 and the shielding pattern BMLa may be formed by forming a conductive layer on the second resin layer 110-2 and then patterning the conductive layer.

[0179] At the same time, despite Figure 6 and Fig. 7A An example is shown in which the base layer 110 has a structure in which two resin layers 110 - 1 and 110 - 2 are stacked on each other, but the present disclosure is not limited thereto, and the base layer 110 may have a structure in which three or more resin layers are stacked on each other.

[0180] refer to Figure 7B, the base layer 110 may include a first resin layer 110-1, a second resin layer 110-2, and a third resin layer 110-3. The second resin layer 110-2 may be disposed on the first resin layer 110-1, and the third resin layer 110-3 may be disposed on the second resin layer 110-2. Each of the first resin layer 110-1, the second resin layer 110-2, and the third resin layer 110-3 may include a polymer resin, or may be formed of a polymer resin. Each of the first resin layer 110-1, the second resin layer 110-2, and the third resin layer 110-3 may include, for example, an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose resin, a siloxane-based resin, a polyimide resin, a polyamide resin, or a perylene-based resin, or may be formed of, for example, an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose resin, a siloxane-based resin, a polyimide resin, a polyamide resin, or a perylene-based resin. Each of the first resin layer 110-1, the second resin layer 110-2, and the third resin layer 110-3 may include, or may be formed of, polyimide.

[0181] Although not shown, the base layer 110 may further include an inorganic layer disposed between the first resin layer 110-1 and the second resin layer 110-2 and between the second resin layer 110-2 and the third resin layer 110-3, and having a single-layer structure or a multi-layer structure. The inorganic layer may include, for example, silicon oxide, silicon nitride, or silicon oxynitride, or may be formed of, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0182] The charging electrode PCE is disposed under at least one of the plurality of resin layers 110-1, 110-2, and 110-3. Figure 7B As shown, the charging electrode PCE may be disposed below the second resin layer 110-2 and the third resin layer 110-3. The charging electrode PCE may be disposed on the first resin layer 110-1, and the upper surface of the charging electrode PCE may be covered by the second resin layer 110-2. For example, the charging electrode PCE may be disposed in the space between the first resin layer 110-1 and the second resin layer 110-2. Meanwhile, when the base layer 110 includes an inorganic layer disposed between the first resin layer 110-1 and the third resin layer 110-3 and having a single-layer structure or a multi-layer structure, the charging electrode PCE may be disposed on the inorganic layer.

[0183] The charging electrode PCE may be electrically connected to the flexible circuit board FCB. The flexible circuit board FCB may be disposed under at least a portion of the display panel 100 and connected to the charging electrode PCE, and a ground voltage may be applied to the charging electrode PCE. In an embodiment, a resin layer disposed under the charging electrode PCE may be penetrated, and the charging electrode PCE and the flexible circuit board FCB may be electrically connected accordingly. In an embodiment, the charging electrode PCE may be connected to the flexible circuit board FCB through a contact hole CNH2 penetrating the first resin layer 110-1. The charging electrode PCE may be electrically connected to a connection line CNE2 included in the flexible circuit board FCB. At the same time, Figure 7B Different from what is shown, the charging electrode PCE may be electrically connected to the flexible circuit board FCB via a separate additional connection line.

[0184] The charging electrode PCE may have a thickness selected from the range of 0.1 μm to 1 μm. When the charging electrode PCE has a thickness less than 0.1 μm, wiring resistance may be increased, and thus the stylus pen STP (reference Figure 1A When the charging electrode PCE has a thickness greater than 1 μm, the thickness of the charging electrode PCE and the base layer 110 in which the charging electrode PCE is disposed may increase the thickness of the electronic device ED (reference Figure 1A ) is increased to the extent that the folding characteristics of the electronic device ED may be deteriorated.

[0185] The shielding pattern BMLa may be disposed on the third resin layer 110-3 and may be covered by the buffer layer 10br. The shielding pattern BMLa may be disposed above the charging electrode PCE. However, the position of the shielding pattern BMLa is not limited thereto, and the shielding pattern BMLa may be disposed in various positions. For example, the shielding pattern BMLa may be disposed on the second resin layer 110-2 and may be covered by the third resin layer 110-3.

[0186] Figure 8 is a plan view of a charging electrode PCE included in the display device DD according to an embodiment of the present disclosure. 9A to 9C is shown during the charging period of the operating cycle Figure 8 Plan view of the charging electrode PCE.

[0187] Reference together Figures 6 to 8 , the charging electrode PCE may be disposed under at least one of the plurality of resin layers 110 - 1 and 110 - 2 included in the base layer 110 . Fig. 7A As shown, the charging electrode PCE may be disposed on the first resin layer 110-1 and may be covered by the second resin layer 110-2. Figure 7BAs shown, the charging electrode PCE may be disposed on the first resin layer 110 - 1 and may be covered by the second resin layer 110 - 2 .

[0188] The charging electrode PCE may include a first local electrode PCE-U (i.e., a finger electrode) extending in the second direction DR2 and having a strip shape and a second local electrode PCE-L (i.e., a connection electrode) extending in the first direction DR1 and having a strip shape. The first local electrodes PCE-U may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. Figure 8 An example is shown in which the charging electrode PCE includes six first local electrodes PCE-U having a strip shape, but the present disclosure is not limited thereto, and the number of first local electrodes PCE-U may be provided differently according to the shape and size of the electronic device. The upper end of the first local electrode PCE-U may be connected to the second local electrode PCE-L. The second local electrode PCE-L may connect the upper ends of the first local electrodes PCE-U to each other and may extend in the first direction DR1. A portion of the second local electrode PCE-L may overlap the non-display area 100-NDA.

[0189] The display panel 100 may further include a signal line connected to the charging electrode PCE. In an embodiment, the display panel 100 may include a first voltage line PCL1 connected to an end of the first local electrode PCE-U and a second voltage line PCL2 connected to an opposite end of the second local electrode PCE-L. The second voltage line PCL2 may include: a first portion PCL2-1 extending in a first direction DR1 and connected to an opposite end of the second local electrode PCE-L; a second portion PCL2-2 bent from one of the first portions PCL2-1 and connected to the first voltage pad PPD1; and a third portion PCL2-3 bent from another of the first portions PCL2-1 and connected to the second voltage pad PPD2.

[0190] At least a portion of the charging electrode PCE may overlap the display area 100-DA. The first voltage line PCL1 and the second voltage line PCL2 may be disposed in the non-display area 100-NDA. The charging electrode PCE, the first voltage line PCL1, and the second voltage line PCL2 may be disposed on the same layer, or may be disposed on different layers. In an embodiment, each of the first voltage line PCL1 and the second voltage line PCL2 may be as follows: Fig. 7A The connection line CNE1 shown, or it can be as shown Figure 7B The connection line CNE2 shown is connected to the flexible circuit board FCB.

[0191] The display panel 100 may include a first voltage pad PPD1 and a second voltage pad PPD2. The first voltage pad PPD1 and the second voltage pad PPD2 may be disposed in a region spaced apart from each other along the first direction DR1. Each of the first voltage line PCL1 and the second voltage line PCL2 may be connected to at least one corresponding pad among the first voltage pad PPD1 and the second voltage pad PPD2. When viewed from above a plane, the first voltage pad PPD1 and the second voltage pad PPD2 may be adjacent to a lower end of the display panel 100. When viewed from above a plane, Figure 5 The illustrated first pad PD1 may be disposed in a space between a region where the first voltage pad PPD1 is formed and a region where the second voltage pad PPD2 is formed.

[0192] although Figure 8 An example is shown in which the charging electrode PCE includes a strip-shaped first local electrode PCE-U extending in the second direction DR2 and a strip-shaped second local electrode PCE-L extending in the first direction DR1, but the charging electrode PCE may have any shape capable of forming a coil-shaped current path. FIG. 11A to FIG. 11C Describe the various shapes of the charging electrode PCE.

[0193] 9A to 9C is shown during the charging period of the operating cycle Figure 8 Plan view of the charging electrode PCE.

[0194] exist 9A to 9C For convenience of description, among the three first voltage lines PCL1, the left first voltage line PCL1 is denoted by reference mark PCL1-1, the middle first voltage line PCL1 is denoted by reference mark PCL1-2, and the right first voltage line PCL1 is denoted by reference mark PCL1-3.

[0195] During the charging cycle, the second voltage line PCL2 may receive a drive signal or a ground voltage from at least one of the first voltage pad PPD1 and the second voltage pad PPD2. One of the voltage lines PCL1-1, PCL1-2, and PCL1-3 may be selected to receive a ground voltage, and the remaining voltage lines may not be selected. The selected voltage line may receive a drive signal or a ground voltage. The charging electrode PCE connected to the selected voltage line may also receive a drive signal or a ground voltage. The unselected voltage lines may float. Some of the second voltage line PCL2, the charging electrode PCE, and the first voltage line PCL1 may be selected so that a current path is formed in the coil (or the coil is defined).

[0196] refer to Fig. 9A, during the first section of the charging cycle, the driving circuit of the display module may select the first voltage pad PPD1 connected to the second voltage line PCL2 and the first voltage pad PPD1 connected to the middle first voltage line PCL1-2. The driving circuit of the display module may apply a driving signal to the first voltage pad PPD1 connected to the second voltage line PCL2, and may apply a ground voltage to the first voltage pad PPD1 connected to the middle first voltage line PCL1-2. At this time, the left first voltage line PCL1-1 and the right first voltage line PCL1-3 may float. The second voltage line PCL2, the second local electrode PCE-L, the first local electrode PCE-U of the charging electrode PCE disposed in the center, and the middle first voltage line PCL1-2 define a coil-shaped current path. The coil-shaped current path may generate a magnetic field.

[0197] refer to Fig. 9B , during the second segment of the charging cycle, the driving circuit of the display module may select the first voltage pad PPD1 connected to the left first voltage line PCL1-1 and the second voltage pad PPD2 connected to the right first voltage line PCL1-3. The driving circuit of the display module may apply a driving signal to the first voltage pad PPD1 connected to the left first voltage line PCL1-1, and may apply a ground voltage to the second voltage pad PPD2 connected to the right first voltage line PCL1-3. The left first voltage line PCL1-1, the first local electrode PCE-U of the charging electrode PCE disposed on the left side, the second local electrode PCE-L, the first local electrode PCE-U of the charging electrode PCE disposed on the right side, and the right first voltage line PCL1-3 define a coil-shaped current path. The coil-shaped current path may generate a magnetic field.

[0198] refer to Fig. 9C , during the third segment of the charging cycle, the driving circuit of the display module may select the first voltage pad PPD1 connected to the middle first voltage line PCL1-2 and the second voltage pad PPD2 connected to the second voltage line PCL2. The driving circuit of the display module may apply a driving signal to the first voltage pad PPD1 connected to the middle first voltage line PCL1-2, and may apply a ground voltage to the second voltage pad PPD2 connected to the second voltage line PCL2. The middle first voltage line PCL1-2, the first local electrode PCE-U disposed in the center of the charging electrode PCE, the second local electrode PCE-L, and the second voltage line PCL2 define a coil-shaped current path. The coil-shaped current path may generate a magnetic field.

[0199] In reference Fig. 9A and Fig. 9CDuring the described charging period, a constant voltage may be applied to a portion of the first local electrode PCE-U and the second local electrode PCE-L of the charging electrode PCE through the first voltage line PCL1 and the second voltage line PCL2. 9A to 9C The driving order of the described charging cycle is only an embodiment, and the present disclosure is not necessarily limited thereto. The operation order of the first segment to the third segment may be changed. In addition, the two first local electrodes PCE-U closest to each other of the charging electrode PCE, and a portion of the second local electrode PCE-L may define a portion of the coil-shaped current path.

[0200] refer to Fig. 9B , the resonant circuit of the stylus STP can be charged during the second segment of the charging cycle. Fig. 9B As described above, the resonant circuit of the stylus pen STP disposed on the first local electrode PCE-U disposed in the center receives the magnetic field formed in the current path. Fig. 9B As described above, the resonant circuit of the stylus pen STP resonates using a signal received by a change in a magnetic field in a current path. The resonant circuit of the stylus pen STP may include an inductor L and a capacitor C connected to the inductor L. The LC resonant circuit may be formed by the inductor L and the capacitor C. The capacitor C may be a variable capacitor whose capacitance varies.

[0201] FIG. 10A to FIG. 10E is a plan view of the shielding pattern BMLa according to an embodiment of the present disclosure.

[0202] refer to FIG. 10A to FIG. 10E , the shielding pattern BMLa may have a slit SLT defined therein. The shielding pattern BMLa may be divided into a plurality of sections by the slit SLT. The slits SLT defined in the shielding pattern BMLa may reduce the area of ​​a continuous region or a flat region of the shielding pattern BMLa to reduce the intensity of a magnetic field formed by eddy currents. For example, a coil-shaped current path of an eddy current EDC may be formed into a small loop, and thus the shielding pattern BMLa divided by the slits SLT may suppress the eddy current EDC in the small loop from forming a large loop. In the following, reference will be made to FIG. 10A to FIG. 10E The shape of the shield pattern BMLa capable of suppressing the eddy current EDC from forming a large loop is described.

[0203] refer to Fig. 10A , the shielding pattern BMLa may have a plurality of slits SLT defined therein. The plurality of slits SLT may extend in the second direction DR2 and may be arranged to be spaced apart from each other in the first direction DR1. The plurality of slits SLT may be connected to the outside of the shielding pattern BMLa. The plurality of slits SLT are not limited to extending in a straight line.

[0204] The shielding pattern BMLa may include a first segment PAR1 extending in the second direction DR2 and arranged in the first direction DR1 and a second segment PAR2 extending in the first direction DR1 and connected to the first segment PAR1. Among the plurality of first segments PAR1, the first segments PAR1 closest to each other may be separated from each other by a slit SLT. For example, the slit SLT may be located between the plurality of first segments PAR1. The upper ends of the first segments PAR1 may be connected by the second segments PAR2. In an embodiment, each of the slits SLT may be an open-ended slit surrounded by the second segment PAR2 and two adjacent first segments PAR1, and the lower end of each slit SLT is open.

[0205] The eddy current EDC may be formed as a small loop in the plurality of first sections PAR1 and the second section PAR2. Since the plurality of first sections PAR1 are spaced apart from each other and do not form a continuous region, the loop of the eddy current EDC may have a small size. Compared to when the shielding pattern BMLa is implemented with a continuous flat panel in which the slits SLT are not defined, the loop of the eddy current EDC may be separated from each other and may have a small size. Since the loop of the eddy current EDC has a small size, the elimination magnetic field MF2 (refer to Fig. 7A and Figure 7B ) size, and can improve the charging efficiency of the charging electrode PCE.

[0206] refer to Fig. 10B , the shielding pattern BMLa may be divided into a plurality of sections PAR1 to PAR13 by a plurality of slits SLT. The plurality of slits SLT may extend radially relative to the center of the shielding pattern BMLa. The plurality of slits SLT may divide the shielding pattern BMLa into thirteen sections, the thirteen sections including the thirteenth section PAR13 located at the center of the shielding pattern BMLa and the first section PAR1 to the twelfth section PAR12 surrounding the thirteenth section PAR13. Each of the plurality of slits SLT may be an end-opening slit surrounded by the thirteenth section PAR13 and two adjacent sections of the first section PAR1 to the twelfth section PAR12, and each slit SLT is opened farther from the thirteenth section PAR13. The eddy current EDC may be formed as a small loop in the first section PAR1 to the thirteenth section PAR13, and therefore, the plurality of slits SLT may prevent the eddy current EDC from forming a large loop in the shielding pattern BMLa.

[0207] refer to Fig. 10C, the shielding pattern BMLa may have a plurality of slits SLT defined therein. The plurality of slits SLT may include a first slit SLT1 extending in the first direction DR1 and a second slit SLT2 extending in the second direction DR2. The first slits SLT1 may be formed in a plurality of rows arranged in the first direction DR1. The first slits SLT1 of the plurality of rows may be arranged in the second direction DR2. The second slits SLT2 may be disposed between the first slits SLT1 of the plurality of rows in the second direction DR2. The second slits SLT2 may be disposed between the first slits SLT1 in the first direction DR1. The shielding pattern BMLa may be divided into a first section PAR1 to a fifteenth section PAR15 by the first slits SLT1 and the second slits SLT2. In an embodiment, each of the first slits SLT1 and the second slits SLT2 may be surrounded by the shielding pattern BMLa. The first slits SLT1 and the second slits SLT2 arranged in the first direction DR1 and the second direction DR2 may divide the shielding pattern BMLa into a first section PAR1 to a fifteenth section PAR15. The eddy current EDC may be formed as a small loop in the first to fifteenth sections PAR1 to PAR15. The plurality of slits SLT may prevent the eddy current EDC from being formed as a large loop in the shield pattern BMLa.

[0208] refer to Fig. 10D , the shielding pattern BMLa may have a slit SLT defined therein. The slit SLT may include a plurality of first slit portions SLT1_1 extending in the first direction DR1 and a plurality of second slit portions SLT2_1 extending in the second direction DR2. The plurality of first slit portions SLT1_1 may be connected to the plurality of second slit portions SLT2_1. Each of the second slit portions SLT2_1 may connect two first slit portions SLT1_1 that are closest to each other among the first slit portions SLT1_1. The second slit portions SLT2_1 may be alternately disposed on the right and left sides of the shielding pattern BMLa.

[0209] The shielding pattern BMLa may be divided into first to fourth sections PAR1 to PAR4 by the first to second slit portions SLT1_1 and SLT2_1. Eddy current EDC may be formed as a small loop in the first to fourth sections PAR1 to PAR4. The slits SLT may prevent the eddy current EDC from being formed as a large loop.

[0210] refer to Fig. 10E, the shielding pattern BMLa may have a plurality of slits SLT defined therein. The plurality of slits SLT may include a first slit SLT1 and a second slit SLT2 extending in the first direction DR1. The first slit SLT1 may extend from the left surface of the shielding pattern BMLa toward the central portion of the shielding pattern BMLa. The central portion may extend in the second direction DR2. The first slit SLT1 may be arranged in the second direction DR2. The second slit SLT2 may extend from the right surface of the shielding pattern BMLa toward the central portion of the shielding pattern BMLa. The second slit SLT2 may be arranged in the second direction DR2. Each of the first slits SLT1 and a corresponding one of the second slits SLT2 may be disposed in the same position in the second direction DR2. A pair of first slits SLT1 and second slits SLT2 at the same position in the second direction DR2 may be disposed on the left and right sides of the central portion of the shielding pattern BMLa.

[0211] The shielding pattern BMLa may be divided into the first section PAR1 to the ninth section PAR9 by the first slit SLT1 and the second slit SLT2. In an embodiment, each of the first slit SLT1 and the second slit SLT2 may be an end-opening slit surrounded by the central portion of the first section PAR1 to the ninth section PAR9 and two adjacent sections, and each slit SLT is opened at a farther end from the central portion of the shielding pattern BMLa. The eddy current EDC may be formed as a small loop in the first section PAR1 to the ninth section PAR9. A plurality of slits SLT may prevent the eddy current EDC from forming a large loop.

[0212] FIG. 11A to FIG. 11C is a plan view of the shielding pattern BMLa and the charging electrode PCE according to an embodiment of the present disclosure.

[0213] refer to FIG. 11A to FIG. 11C , the charging electrode PCE may have various shapes. When viewed from above the plane, the shielding pattern BMLa may cover the charging electrode PCE. The shielding pattern BMLa may have a shape corresponding to the charging electrode PCE. When viewed from above the plane, the shielding pattern BMLa may be arranged to cover the top of the charging electrode PCE. Therefore, the shielding pattern BMLa may prevent the parasitic capacitance and magnetic field generated by the charging electrode PCE from being degraded and included in the driving element layer 120 (reference Fig. 7A and Figure 7B ) in the semiconductor pattern, conductive pattern and signal line. FIG. 11A to FIG. 11C In the figure, for convenience, the width of the charging electrode PCE is not considered, and the charging electrode PCE is represented by a solid line.

[0214] refer to Fig.11A, the charging electrode PCE may include a first local electrode PCE-U extending in the second direction DR2 and having a bar shape and a second local electrode PCE-L extending in the first direction DR1 and having a bar shape. Fig.11A The shape of the charging electrode PCE shown can be compared with the reference Figure 8 The shapes of the charging electrodes PCE described are identical.

[0215] A plurality of slits SLT extending in the second direction DR2 and arranged to be spaced apart from each other in the first direction DR1 may be defined in the shielding pattern BMLa. The shielding pattern BMLa may include a first segment PAR1 extending in the second direction DR2 and arranged in the first direction DR1 and a second segment PAR2 extending in the first direction DR1 and connected to the first segment PAR1. The shielding pattern BMLa may have a shape corresponding to the charging electrode PCE. When viewed from above a plane, the first segment PAR1 may cover the first local electrode PCE-U. When viewed from above a plane, the second segment PAR2 may cover the second local electrode PCE-L. When viewed from above a plane, the plurality of slits SLT may not expose the charging electrode PCE. For example, when viewed from above a plane, the charging electrode PCE may be disposed in a space between two adjacent slits of the plurality of slits SLT.

[0216] refer to Fig. 11B , the charging electrode PCE may be a multi-coil. The charging electrode PCE may include first to fifth charging electrodes PCE1 to PCE5. When viewed from above a plane, each of the first to fifth charging electrodes PCE1 to PCE5 may have a coil shape wound at least once. Each of the first to fifth charging electrodes PCE1 to PCE5 may have a coil shape that is long in the second direction DR2. The first to fifth charging electrodes PCE1 to PCE5 may be arranged to be spaced apart from each other in the first direction DR1.

[0217] The shielding pattern BMLa may have a shape corresponding to the first to fifth charging electrodes PCE1 to PCE5. When viewed from above a plane, the shielding pattern BMLa may cover the first to fifth charging electrodes PCE1 to PCE5. The plurality of slits SLT defined in the shielding pattern BMLa may not expose the first to fifth charging electrodes PCE1 to PCE5. For example, the first to fifth charging electrodes PCE1 to PCE5 may be disposed in a space between two adjacent slits of the plurality of slits SLT. When viewed from above a plane, the plurality of slits SLT may be disposed within a coil shape of the first to fifth charging electrodes PCE1 to PCE5. The plurality of slits SLT may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0218] refer to Fig. 11C , the charging electrode PCE may be a single coil. The charging electrode PCE may be a large coil. The shielding pattern BMLa may have a shape corresponding to the charging electrode PCE. However, a plurality of slits SLT may be arranged in the first direction DR1 to divide the shielding pattern BMLa into smaller areas. When viewed from above a plane, the shielding pattern BMLa may cover the charging electrode PCE.

[0219] Fig.12 is a cross-sectional view of a portion of a display module DM according to an embodiment of the present disclosure. Fig. 7A The same components as those described above will be given the same reference numerals, and descriptions thereof will be omitted.

[0220] refer to Fig.12 , when viewed from above a plane, the shielding pattern BMLa may cover the first transistor TFT-1 to the third transistor TFT-3. The shielding pattern BMLa may be disposed below the first transistor TFT-1 to the third transistor TFT-3. The shielding pattern BMLa may be disposed to cover the lower surface of the first transistor TFT-1 to the third transistor TFT-3. The shielding pattern BMLa may prevent the charging electrode PCE from affecting the first transistor TFT-1 to the third transistor TFT-3. For example, the shielding pattern BMLa may prevent the parasitic capacitance and the magnetic field generated by the charging electrode PCE from deteriorating the characteristics of the first transistor TFT-1 to the third transistor TFT-3.

[0221] FIG. 13A to FIG. 13E is a plan view of a transistor TFT and a shielding pattern BMLa according to an embodiment of the present disclosure. FIG. 13A to FIG. 13E , a shielding pattern BMLa and nine transistors TFT are shown.

[0222] refer to FIG. 13A to FIG. 13E , the shielding pattern BMLa may be divided into a plurality of sections by the slits SLT. When viewed from above the plane, the slits SLT may not overlap with the transistor TFT. The shielding pattern BMLa may include a plurality of unit patterns UN covering the transistor TFT when viewed from above the plane and connection patterns CO1 and CO2 connecting the plurality of unit patterns UN to each other. For example, each of the plurality of unit patterns UN may cover a corresponding entire transistor in the transistor TFT. The plurality of unit patterns UN may be a plurality of sections of the shielding pattern BMLa, respectively. The plane area of ​​the plurality of unit patterns UN may be greater than the plane area of ​​the transistor TFT.

[0223] refer to Fig.13A, the shielding pattern BMLa may include a plurality of unit patterns UN and a first connection pattern CO1 and a second connection pattern CO2. The outer surface of the unit pattern UN may be spaced apart from the outer surface of the transistor TFT by a first distance TH1. Therefore, the shielding pattern BMLa may be prevented from failing to cover the transistor TFT due to an error between layers in a process of forming the shielding pattern BMLa and a process of forming the transistor TFT.

[0224] The plurality of unit patterns UN may be connected by the first connection pattern CO1 and the second connection pattern CO2. The plurality of first connection patterns CO1 may extend in the second direction DR2 and may connect the unit patterns UN arranged in the second direction DR2. The second connection pattern CO2 may connect ends of the plurality of first connection patterns CO1. The second connection pattern CO2 may extend in the first direction DR1. When viewed from above a plane, the shielding pattern BMLa may be open in a direction opposite to the second direction DR2.

[0225] The second connection pattern CO2 may overlap the non-display area 100-NDA located on the upper side of the display panel 100. The width TH2 of the first connection pattern CO1 and the second connection pattern CO2 may be a minimum line width to be formed by a photolithography device (such as a stepper) that forms the shape of the shielding pattern BMLa in a photolithography process. Therefore, the second connection pattern CO2 may be prevented from occupying a space of the display area 100-DA in which a plurality of lines are disposed.

[0226] refer to Fig. 13B , a plurality of first connection patterns CO1 may extend in the first direction DR1 and may connect the unit patterns UN arranged in the first direction DR1. A second connection pattern CO2 may connect ends of the plurality of first connection patterns CO1. The second connection pattern CO2 may extend in the second direction DR2. The second connection pattern CO2 may overlap the non-display area 100-NDA adjacent to the side surface of the display panel 100.

[0227] refer to Fig. 13C , a plurality of first connection patterns CO1 may extend in the first direction DR1 and may connect the unit patterns UN arranged in the first direction DR1. The second connection patterns CO2 may extend in the second direction DR2 and may connect the unit patterns UN arranged in the second direction DR2. The second connection patterns CO2 may overlap the display area 100-DA. The second connection patterns CO2 may be disposed adjacent to one side of the display area 100-DA. The shielding pattern BMLa may be open in the first direction DR1.

[0228] refer to Fig.13D, a plurality of first connection patterns CO1 may extend in the second direction DR2 and may connect the unit patterns UN arranged in the second direction DR2. The second connection patterns CO2 may extend in the first direction DR1 and may connect the unit patterns UN arranged in the first direction DR1. The second connection patterns CO2 may overlap the display area 100-DA. The second connection patterns CO2 may be disposed adjacent to the upper side of the display area 100-DA. The shielding pattern BMLa may be opened in a direction opposite to the second direction DR2.

[0229] refer to Fig.13E , a plurality of first connection patterns CO1 may extend in the second direction DR2 and may connect the unit patterns UN arranged in the second direction DR2. A plurality of second connection patterns CO2 may extend in the first direction DR1 and may connect the unit patterns UN arranged in the first direction DR1. One unit pattern UN may be connected to a unit pattern UN adjacent to the second direction DR2 through the first connection pattern CO1. One unit pattern UN may be connected to a unit pattern UN adjacent to the first direction DR1 through the second connection pattern CO2. The slit SLT may be provided between adjacent transistors TFT. Two unit patterns UN closest to each other among the plurality of unit patterns UN may be connected to each other through the first connection pattern CO1 or the second connection pattern CO2.

[0230] Fig.14A and Fig. 14B is a cross-sectional view of a portion of a display module DM according to an embodiment of the present disclosure. Hereinafter, the same components as those described above will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0231] refer to Fig.14A and Fig. 14B , the display module DM may further include an insulating layer INS and a second shielding pattern BMLb. The insulating layer INS may be disposed on the base layer 110 and may cover the shielding pattern (or first shielding pattern) BMLa. The insulating layer INS may be disposed between the first shielding pattern BMLa and the second shielding pattern BMLb. The insulating layer INS may include an insulating material and may prevent electrical connection between the first shielding pattern BMLa and the second shielding pattern BMLb.

[0232] The second shielding pattern BMLb may be disposed on the insulating layer INS and may be aligned with the display area 100-DA (refer to Figure 5) overlap. The relationship of Formula 1 regarding the first thickness T1 of the first shielding pattern BMLa may be applied to the second thickness T2 of the second shielding pattern BMLb. For example, the second thickness T2 of the second shielding pattern BMLb may satisfy the relationship of Formula 1 as described above to ensure the charging efficiency of the charging electrode PCE.

[0233] refer to Fig.14A , when viewed from above the plane, the first shielding pattern BMLa may cover the charging electrode PCE, and when viewed from above the plane, the second shielding pattern BMLb may cover the transistor TFT. Since the first shielding pattern BMLa and the second shielding pattern BMLb cover the charging electrode PCE and the transistor TFT as described above when viewed from above the plane, the charging electrode PCE may be prevented from deteriorating the characteristics of the transistor TFT.

[0234] refer to Fig. 14B , the first shielding pattern BMLa may cover the transistor TFT when viewed from above the plane, and the second shielding pattern BMLb may cover the charging electrode PCE when viewed from above the plane.

[0235] Fig.15 is a plan view of an input sensor 200 according to an embodiment of the present disclosure.

[0236] refer to Fig.15 , the input sensor 200 may sense the first input using a capacitive method, and may sense the second input using an electromagnetic induction method. The first input may be as shown in FIG. Figure 1A The input performed by the user's body FG as described above, and the second input may be as described in reference Figure 1A The input performed by the stylus pen STP is described. For example, the first input may be an input capable of causing a capacitance change, and the second input may be an input providing a magnetic field signal.

[0237] The input sensor 200 may sense the first input and the second input by time division driving. The input sensor 200 may include sensing electrodes for sensing the first input and the second input. The period in which the input sensor 200 operates in the first mode to sense the first input may be defined as a first operation period, and the period in which the input sensor 200 operates in the second mode to sense the second input may be defined as a second operation period. The input sensor 200 may switch between the first mode and the second mode by a user's selection. In an embodiment, one of the first mode and the second mode may be activated, or the input sensor 200 may switch between the first mode and the second mode by activation of a specific application. The input sensor 200 may remain in the first mode when sensing the first input while the input sensor 200 operates alternately in the first mode and the second mode, or the input sensor 200 may remain in the second mode when sensing the second input while the input sensor 200 operates alternately in the first mode and the second mode.

[0238] The sensing electrodes of the input sensor 200 may include a first group of electrodes SE for sensing a first input and a second group of electrodes PSE for sensing a second input. Although six first electrodes PSE1 and eight second electrodes PSE2 belonging to the second group are shown as an example, the input sensor 200 may include more first electrodes PSE1 and more second electrodes PSE2 belonging to the second group. Meanwhile, the shapes of the first group of electrodes SE and the second group of electrodes PSE are not limited to Fig.15 , and may be changed into various shapes for detecting the first input and the second input by the input sensor 200.

[0239] The first group of electrodes SE may include first electrodes SE1 arranged in the first direction DR1 and extending in the second direction DR2 and second electrodes SE2 crossing the first electrodes SE1. The first electrodes SE1 and the second electrodes SE2 of the first group may be capacitively coupled.

[0240] The driving circuit of the input sensor 200 provides a driving signal to one of the first electrode SE1 and the second electrode SE2 of the first group, and the sensing circuit of the input sensor 200 measures a change in capacitance of a mutual capacitor formed between the first electrode SE1 and the second electrode SE2 of the first group through the other of the first electrode SE1 and the second electrode SE2 of the first group. After performing the above operation during the first segment of the first operation cycle, the above operation may be reversely performed during the second segment of the first operation cycle. The first segment and the second segment may be repeated as a group.

[0241] The second group of electrodes PSE may include first electrodes PSE1 arranged in the first direction DR1 and extending in the second direction DR2 and second electrodes PSE2 crossing the first electrodes PSE1. The first electrodes PSE1 and the second electrodes PSE2 of the second group may sense the touch pen STP (reference Figure 1A The driving circuit of the input sensor 200 provides a driving signal to at least one of the first electrode PSE1 and the second electrode PSE2 of the second group, and the sensing circuit of the input sensor 200 senses the electromagnetic induction current formed in the first electrode PSE1 and the second electrode PSE2 of the second group.

[0242] The input sensor 200 may include a first group of signal lines and a second group of signal lines. The first group of signal lines may include a first signal line SL1 connected to an end of a first electrode SE1 of the first group and a second signal line SL2 connected to an end of a second electrode SE2 of the first group, and the second group of signal lines may include a first signal line PSL1 connected to a first electrode PSE1 of the second group and a second signal line PSL2 connected to an end of a second electrode PSE2 of the second group.

[0243] The first electrode SE1 and the second electrode SE2 of the first group and the first electrode PSE1 and the second electrode PSE2 of the second group may be disposed in the display area DA. The first signal line SL1 and the second signal line SL2 of the first group and the first signal line PSL1 and the second signal line PSL2 of the second group may be disposed in the non-display area NDA. The electrodes SE1, SE2, PSE1 and PSE2 and the signal lines SL1, SL2, PSL1 and PSL2 may be disposed on the same layer, or may be disposed on different layers.

[0244] The input sensor 200 may include a second pad PD2 and a third pad PD3. The second pad PD2 and the third pad PD3 may be disposed in an area spaced apart from each other along the first direction DR1. Each of the first signal line SL1 and the second signal line SL2 of the first group and the first signal line PSL1 and the second signal line PSL2 of the second group may be connected to at least one corresponding pad among the second pad PD2 and the third pad PD3. When viewed from above a plane, the second pad PD2 and the third pad PD3 may be adjacent to a lower end of the input sensor 200. When viewed from above a plane, Figure 5 The illustrated first pad PD1 may be disposed between the second pad PD2 and the third pad PD3 .

[0245] The input sensor 200 may be divided into a left area and a right area with respect to the center of the input sensor 200 in the first direction DR1. The second pad PD2 is disposed in the left area, and the third pad PD3 is disposed in the right area. The first signal line SL1 of the first group connected to the first electrode SE1 disposed in the left area may be connected to the second pad PD2. The first signal line SL1 of the first group connected to the first electrode SE1 disposed in the right area may be connected to the third pad PD3.

[0246] The input sensor 200 may be divided into an upper area and a lower area in the second direction DR2 relative to the center of the input sensor 200. Some of the second signal lines SL2 of the first group may be connected to the left end of the second electrode SE2 of the first group disposed in the lower area. Some of the second signal lines SL2 of the first group may be connected to the second pad PD2. Other second signal lines SL2 of the first group may be connected to the right end of the second electrode SE2 of the first group disposed in the upper area. Other second signal lines SL2 of the first group may be connected to the third pad PD3.

[0247] Each of the first electrodes SE1 of the first group may include a first extension portion SE1-1 and a second extension portion SE1-2 extending in the second direction DR2 and spaced apart from each other in the first direction DR1. The first extension portion SE1-1 and the second extension portion SE1-2 may have shapes symmetrical to each other (e.g., horizontally symmetrical to each other) with respect to the second direction DR2. The first electrode PSE1 of the second group may be disposed between the first extension portion SE1-1 and the second extension portion SE1-2.

[0248] Each of the first electrodes SE1 of the first group may further include a first middle portion SE1-3. Fig.15 , the first middle portion SE1-3 disposed in the lower area is shown as an example. The first middle portion SE1-3 may not be disposed in the upper area. The first middle portion SE1-3 may extend in the first direction DR1. The first middle portion SE1-3 may be disposed between one end of the first extension portion SE1-1 and one end of the second extension portion SE1-2. The first signal line SL1 of the first group may be connected to the first middle portion SE1-3.

[0249] Each of the second electrodes SE2 of the first group may include a third extension portion SE2-1 and a fourth extension portion SE2-2 extending in the first direction DR1 and spaced apart from each other in the second direction DR2. The third extension portion SE2-1 and the fourth extension portion SE2-2 may have shapes symmetrical to each other (e.g., vertically symmetrical to each other) with respect to the first direction DR1. The second electrode PSE2 of the second group may be disposed between the third extension portion SE2-1 and the fourth extension portion SE2-2.

[0250] Each of the second electrodes SE2 of the first group may further include a second middle portion SE2-3. The second middle portion SE2-3 of the second electrode SE2 of the first group disposed in the upper region may be disposed on the right side and may not be disposed on the left side. The second middle portion SE2-3 of the second electrode SE2 of the first group disposed in the lower region may be disposed on the left side.

[0251] The second middle portion SE2-3 may extend in the second direction DR2. The second middle portion SE2-3 may be disposed between one end of the third extension portion SE2-1 and one end of the fourth extension portion SE2-2. The second signal line SL2 of the first group may be connected to the second middle portion SE2-3.

[0252] The first electrodes PSE1 of the second group may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The first electrodes PSE1 of the second group may be disposed on the same layer as the first electrodes SE1 of the first group. The first electrodes PSE1 of the second group may be disposed between the first extension portion SE1-1 and the second extension portion SE1-2 of the first electrodes SE1 of the first group.

[0253] In the upper region, ends of the first electrode PSE1 of the second group may be connected together through the first signal line PSL1 of the second group. One end of the first signal line PSL1 of the second group may be connected to the second pad PD2, and the opposite end of the first signal line PSL1 may be connected to the third pad PD3. The first signal line PSL1 of the second group may include: a first portion PSL1-1 extending in the first direction DR1 and connected to the end of the first electrode PSE1 of the second group disposed in the upper region; a second portion PSL1-2 bent from the first portion PSL1-1 and connected to the second pad PD2; and a third portion PSL1-3 bent from the first portion PSL1-1 and connected to the third pad PD3.

[0254] The second electrodes PSE2 of the second group may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The second electrodes PSE2 of the second group may be disposed on the same layer as the second electrodes SE2 of the first group. The second electrodes PSE2 of the second group may be disposed between the third extension portion SE2-1 and the fourth extension portion SE2-2 of the second electrodes SE2 of the first group.

[0255] The left end of the second electrode PSE2 of the second group disposed in the upper region may be connected to one of the second signal lines PSL2 of the second group. The right end of the second electrode PSE2 of the second group disposed in the lower region may be connected to another of the second signal lines PSL2 of the second group. However, the connection relationship between the second electrode PSE2 of the second group and the second signal line PSL2 of the second group is not limited to the above description. For example, in an embodiment of the present disclosure, all of the left ends or right ends of the second electrode PSE2 of the second group may be connected to the same second signal line PSL2 of the second group.

[0256] Fig.16 is an enlarged plan view of a portion of the input sensor 200 according to an embodiment of the present disclosure. Fig.16 yes Fig.15 An enlarged plan view of the intersection area AA1. Fig.17 and Fig.18 is a cross-sectional view of a portion of an input sensor 200 according to an embodiment of the present disclosure. Fig.17 is corresponding to Fig.16 2 is a cross-sectional view of the input sensor 200 taken along line II-II′. Fig.18 is corresponding to Fig.16 2 is a cross-sectional view of the input sensor 200 taken along line III-III'. Fig.19 is an enlarged plan view of a portion of the input sensor 200 according to an embodiment of the present disclosure. Fig.19 It is shown Fig.16 Magnified plan views of some of the electrodes shown in .

[0257] refer to Fig.16 and Fig.17 , each of the first extension portion SE1-1 and the second extension portion SE1-2 of the first electrode SE1 of the first group may include: a first sensing portion SP1 arranged in the second direction DR2; and a first middle portion EP1 (or a cross portion), each of which connects two sensing portions adjacent to each other among the first sensing portions SP1. The first sensing portion SP1 may have a curved shape. For example, the first sensing portion SP1 may have a shape that is curved to the left or right in the first direction DR1 to maintain a certain distance from the first electrode PSE1 of the second group. The first sensing portion SP1 may have a greater width than the first middle portion EP1.

[0258] The first intermediate portion EP1 is disposed on a different layer from the first sensing portion SP1. The first intermediate portion EP1 disposed below the second insulating layer 200-IL2 may correspond to a bridge. A bridge such as the first intermediate portion EP1 may be disposed in an area where the first conductive pattern and the second conductive pattern intersect. The bridge may constitute a portion of the first conductive pattern. The remaining portion of the first conductive pattern and the second conductive pattern may be disposed on a different layer from the bridge.

[0259] The first middle portion EP1 as a bridge may be provided to prevent short circuits between the first extension portion SE1-1 and the second extension portion SE1-2, the first group second electrode SE2, and the second group second electrode PSE2. The first middle portion EP1 may connect two adjacent first sensing portions SP1 through a first contact hole T-CH1 passing through the second insulating layer 200-IL2.

[0260] Each of the third extension portion SE2-1 and the fourth extension portion SE2-2 of the second electrode SE2 of the first group may include: a second sensing portion SP2 arranged in the first direction DR1; and a second intermediate portion EP2, each of which is disposed between two second sensing portions adjacent to each other among the second sensing portions SP2. The second sensing portion SP2 may have a curved shape. For example, the second sensing portion SP2 may have a shape that is curved upward or downward in the second direction DR2 to maintain a certain distance from the second electrode PSE2 of the second group.

[0261] The second middle portion EP2 is disposed on the same layer (eg, the second insulating layer 200 - IL2 ) as the second sensing part SP2 . The second middle portion EP2 may form one body with the second sensing part SP2 .

[0262] The first sensing portion SP1 and the second sensing portion SP2 may be spaced apart from each other without overlapping each other. The first sensing portion SP1 and the second sensing portion SP2 may be alternately arranged in the first crossing direction CDR1 and the second crossing direction CDR2. The first sensing portion SP1 and the second sensing portion SP2 may form a mutual capacitor. For example, each of the first sensing portions SP1 and the corresponding one of the second sensing portions SP2 may serve as an opposing electrode of a corresponding mutual capacitor.

[0263] refer to Fig.16 and Fig.18, the first electrode PSE1 of the second group may include: a third sensing part PSP1 arranged in the second direction DR2; and a third intermediate part PEP1, each of which connects two sensing parts adjacent to each other among the third sensing parts PSP1. The third sensing part PSP1 may have a shape protruding leftward and rightward in the first direction DR1. The third sensing part PSP1 may have a shape similar to a rhombus shape.

[0264] The third intermediate part PEP1 is disposed on a different layer from the third sensing part PSP1. The third intermediate part PEP1 disposed under the second insulating layer 200-IL2 corresponds to a bridge. The third intermediate part PEP1 as a bridge is disposed to prevent a short circuit between the third sensing part PSP1, the second electrode SE2 of the first group, and the second electrode PSE2 of the second group. The third intermediate part PEP1 connects two adjacent third sensing parts PSP1 through a second contact hole T-CH2 passing through the second insulating layer 200-IL2.

[0265] The second electrode PSE2 of the second group may include: a fourth sensing part PSP2 arranged in the first direction DR1; and a fourth intermediate part PEP2, each of which is disposed between two sensing parts adjacent to each other among the fourth sensing parts PSP2. The fourth sensing part PSP2 may have a shape protruding upward and downward in the second direction DR2. The fourth intermediate part PEP2 is disposed on the same layer (e.g., the second insulating layer 200-IL2) as the fourth sensing part PSP2.

[0266] The fourth intermediate portion PEP2 may form one body with the fourth sensing portion PSP2.

[0267] The position of the bridge member can be changed, and the portion including the bridge member can be changed. Figures 15 to 18 Unlike the described embodiment, the bridge may be included in the first group of second electrodes SE2 and the second group of second electrodes PSE2.

[0268] Some of the first signal lines SL1 and the second signal lines SL2 of the first group and the first signal lines PSL1 and the second signal lines PSL2 of the second group may be arranged on the same layer as the third intermediate portion PEP1, and the others may be arranged on the same layer as the third sensing portion PSP1. This arrangement is to prevent short circuits with the signal lines described above. In an embodiment of the present disclosure, most of the signal lines described above may be arranged on the same layer. However, a bridge may be arranged in an area where the signal lines cross each other.

[0269] refer to Figures 15 to 18The first electrode SE and the second electrode PSE described above may have a thickness selected from the range of 0.1 μm to 1 μm. When the first electrode SE and the second electrode PSE have a thickness less than 0.1 μm, wiring resistance may be increased, and thus the input sensing performance of the input sensor 200 may be reduced. When the first electrode SE and the second electrode PSE have a thickness greater than 1 μm, the thickness of the input sensor 200 may be excessively increased, causing the electronic device ED (reference Figure 1A ) may increase in total thickness, and thus folding characteristics may be deteriorated.

[0270] The first electrode SE and the second electrode PSE may have a wiring resistance of 100Ω or less. The first electrode SE and the second electrode PSE may have a low resistance of 100Ω or less. Figure 1A ) The charging electrodes PCE for charging are independently arranged as in the above reference Figures 6 to 7B The plurality of resin layers included in the base layer 110 of the display panel 100 described above may not be required in the input sensor 200 for controlling the stylus pen STP (refer to Figure 1A ) The arrangement space of the electrodes and wires for charging can increase the number of channels of the first group of electrodes SE and the second group of electrodes PSE. Therefore, the sensing electrodes including the first group of electrodes SE and the second group of electrodes PSE can have a low resistance of 100Ω or less, and the driving voltage for driving the sensing electrodes can be reduced to about 3.3V or less.

[0271] Fig.19 Shows Fig.16 An enlarged view of the first sensing portion SP1 and the third sensing portion PSP1 is shown. The first sensing portion SP1 is shown to represent the first group of electrodes SE, and the third sensing portion PSP1 is shown to represent the second group of electrodes PSE.

[0272] refer to Fig.19 , the first sensing part SP1 and the third sensing part PSP1 may have a mesh shape. For example, each of the first sensing part SP1 and the third sensing part PSP1 may include a second conductive wire BP2 extending in the first cross direction CDR1 and a first conductive wire BP1 extending in the second cross direction CDR2. The first conductive wire BP1 and the second conductive wire BP2 may be formed by the same process and may form one body. The mesh sheet formed by the first conductive wire BP1 and the second conductive wire BP2 may be patterned to form Fig.15 Shown are a first group of first and second electrodes SE1 and SE2 and a second group of first and second electrodes PSE1 and PSE2.

[0273] The opening T-OP having a rhombus shape may be defined by the first conductive wire BP1 and the second conductive wire BP2. The opening T-OP may correspond to Figure 6 For example, the first conductive line BP1 and the second conductive line BP2 are connected to the emission area LA. Figure 6 The non-emitting areas NLA are shown overlapping.

[0274] Fig. 20 is a plan view showing electrodes included in the input sensor 200 according to an embodiment of the present disclosure during a first sensing period. Fig. 20 is shown during the operating cycle Fig.15 A plan view of the first set of electrodes SE.

[0275] During the first sensing cycle, the operation of the input sensor 200 does not involve Fig.15 That is, the input sensor 200 does not provide a driving signal to the second set of electrodes PSE, and does not sense a signal from the second set of electrodes PSE. To simplify the illustration, Fig. 20 Not shown Fig.15 The second set of electrodes PSE.

[0276] During the first operation cycle, the driving circuit of the input sensor provides a driving signal to the first electrode SE1 or the second electrode SE2 of the first group. For example, the driving circuit of the input sensor may scan the first electrode SE1 or the second electrode SE2 of the first group. For example, the driving circuit of the input sensor sequentially provides the driving signal to the first electrode SE1 of the first group through the first signal line SL1 of the first group. The activation periods of the driving signals applied to the first electrodes SE1 of the first group may be different from each other. The driving signal may include a plurality of pulse waves or a plurality of sine waves within the activation period. The driving circuit of the input sensor may be embedded in a separate driver IC of the input sensor, or may be embedded in a driver IC DIC mounted on the display panel 100 (refer to Figure 2 )middle.

[0277] A current path is formed from an electrode receiving a driving signal among the first electrodes SE1 of the first group to the second electrodes SE2 of the first group. The current path passes through a mutual capacitor formed between the first electrodes SE1 and the second electrodes SE2 of the first group. A change in the capacitance of the mutual capacitor is detected by the second electrodes SE2 of the first group. The sensing circuit of the input sensor measures the current passing through the second electrodes SE2 of the first group, and calculates the capacitance change based on the measured current. For example, the current measured through the electrode among the second electrodes SE2 of the first group where an input by the user's body FG occurs is different from the current measured through the other electrodes. The sensing circuit of the input sensor may be embedded in a separate driver IC of the input sensor, or may be embedded in a driver IC DIC mounted on the display panel 100 (refer to Figure 2 )middle.

[0278] Fig.21 is a plan view showing electrodes included in the input sensor 200 according to an embodiment of the present disclosure during a second sensing period. Fig.21 , a first electrode SE1 of a first group and a first electrode PSE1 of a second group are shown to generate an induced current by a magnetic field signal output from a stylus pen STP. Fig.21 Induction current is generated in a first group of second electrodes SE2 and a second group of second electrodes PSE2 as shown.

[0279] refer to Fig.15 and Fig.21 During the second sensing period, the sensing circuit of the input sensor may apply a ground voltage to the first signal line PSL1 of the second group and the second signal line PSL2 of the second group. Fig.21 , the second pad PD2 connected to the first signal line PSL1 of the second group may be grounded, and the second pad PD2 connected to the second signal line PSL2 of the second group disposed in the left area may be grounded. The resonant circuit of the stylus pen STP generates a magnetic field when discharged. By the magnetic field emitted from the stylus pen STP, an induced current may be generated in the input sensor 200, which is inductively coupled to the resonant circuit of the stylus pen STP.

[0280] A first capacitor ICP1 may be defined between the first electrode SE1 of the first group and the first electrode PSE1 of the second group, and a second capacitor ICP2 may be defined between the second electrode SE2 of the first group and the second electrode PSE2 of the second group. When the first signal line PSL1 of the second group is grounded, the first induced current IC1 may flow from the first electrode SE1 of the first group to the first electrode PSE1 of the second group through the first capacitor ICP1. When the second signal line PSL2 of the second group is grounded, the second induced current IC2 may flow from the second electrode SE2 of the first group to the second electrode PSE2 of the second group through the second capacitor ICP2. The sensing circuit of the input sensor may sense the first induced current IC1 passing through the first signal line SL1 of the first group and the second pad PD2 connected thereto, and may sense the second induced current IC2 passing through the second signal line SL2 of the first group and the third pad PD3 connected thereto, thereby recognizing the input made by the stylus STP.

[0281] According to an embodiment of the present disclosure, a sensing electrode for sensing an input of a stylus pen and a charging electrode for charging the stylus pen can be spaced apart from each other with pixels between them. Therefore, the number of channels of the sensing electrode included in the input sensor can be increased, and thus the sensing performance of the sensing electrode can be improved.

[0282] According to an embodiment of the present disclosure, the shielding pattern may have a certain thickness or less. Therefore, it is possible to prevent the magnetic field generated by the shielding pattern from canceling the magnetic field of the charging electrode and reducing the charging efficiency.

[0283] According to an embodiment of the present disclosure, when driving the charging electrode, the shielding pattern can reduce interference with the pixel driving element.

[0284] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: A display panel comprising a display area and a non-display area around the display area; as well as an input sensor disposed on the display panel, the input sensor comprising a sensing electrode configured to sense an electromagnetic induction current, Wherein, the display panel comprises: A base layer including a plurality of resin layers; a plurality of pixels disposed on the base layer and overlapping the display area; a charging electrode disposed under at least one resin layer among the plurality of resin layers and overlapping the display area; and a first shielding pattern disposed on the base layer and overlapping the display area, the first shielding pattern having a first thickness and having at least one slit dividing the first shielding pattern into a plurality of sections, and Wherein, the first thickness corresponds to a thickness that satisfies the following relationship: Wherein, T1 represents the first thickness, A is pi, B is the magnetic permeability of the first shielding pattern, C is the frequency of the current flowing through the first shielding pattern, and D is the resistivity of the first shielding pattern.

2. The display device according to claim 1, in, The first shield pattern overlaps the charging electrode when viewed in a plan view.

3. The display device according to claim 1, in, Each of the plurality of pixels includes a light emitting element and at least one transistor connected to the light emitting element, and Wherein, when viewed in a plan view, the first shielding pattern overlaps with the transistor.

4. The display device according to claim 3, in, The first shielding pattern comprises: a plurality of unit patterns, including a first unit pattern covering the transistor; and A plurality of connection patterns, each of the plurality of connection patterns connecting two adjacent unit patterns among the plurality of unit patterns.

5. The display device according to claim 4, in, When viewed in the plan view, the entire transistor is covered by the first unit pattern.

6. The display device according to claim 1, in, The charging electrode is disposed in a space between two adjacent slits among the at least one slit when viewed in a plan view.

7. The display device according to claim 1, in, The at least one slit comprises a plurality of slits, and The plurality of slits extend in a first direction and are spaced apart from each other in a second direction intersecting the first direction.

8. The display device according to claim 1, in, The at least one slit comprises a plurality of slits, and Wherein, the plurality of slits extend radially relative to a center of the first shielding pattern.

9. The display device according to claim 1, in, The at least one slit has a single slit, wherein the single slit includes a plurality of first slit portions extending in a first direction and a plurality of second slit portions extending in a second direction intersecting the first direction, and Each of the plurality of second slit portions connects two adjacent first slit portions of the plurality of first slit portions.

10. The display device according to claim 1, in, The plurality of resin layers include: a first resin layer; and a second resin layer, disposed on the first resin layer, wherein the charging electrode is disposed on the first resin layer and covered by the second resin layer, and Wherein, the first shielding pattern is arranged on the second resin layer.

11. The display device according to claim 10, wherein: The display panel further includes: an insulating layer covering the first shielding pattern; and The second shielding pattern is disposed on the insulating layer and overlaps the display area.

12. The display device according to claim 11, in, The second thickness of the second shielding pattern corresponds to a thickness that satisfies the relationship of the following formula: Wherein, T2 represents the second thickness.

13. The display device according to claim 11, in, When viewed from above a plane, one of the first shielding pattern and the second shielding pattern covers transistors of the plurality of pixels, and Wherein, when viewed from above the plane, the other of the first shielding pattern and the second shielding pattern covers the charging electrode.

14. The display device according to claim 1, in, The sensing electrode comprises: The first electrode of the first group extends in a first direction; The second electrode of the first group extends in a second direction intersecting the first direction and is capacitively coupled to the first electrode of the first group; A second group of first electrodes extending in the first direction and sensing the electromagnetic induced current; The second electrode of the second group extends in the second direction and senses the electromagnetic induction current; The first signal line of the first group is connected to one end of the first electrode of the first group; The second signal line of the first group is connected to one end of the second electrode of the first group; The first signal line of the second group is connected to one end of the first electrode of the second group; and The second signal line of the second group is connected to one end of the second electrode of the second group.

15. The display device according to claim 1, in, The first shielding pattern includes at least one of rhodium, tungsten, and molybdenum.

16. A display device comprising: A display panel comprising a display area and a non-display area around the display area; as well as an input sensor, disposed on the display panel, comprising a sensing electrode for sensing electromagnetic induction current, Wherein, the display panel comprises: a plurality of pixels overlapping the display area, each of the pixels comprising a light emitting element and at least one transistor connected to the light emitting element; a charging electrode spaced apart from the sensing electrode with the plurality of pixels therebetween and overlapping the display area, wherein the charging electrode is below a first pixel of the plurality of pixels; and a shielding pattern disposed above the charging electrode and overlapping the display area, the shielding pattern being divided into a plurality of sections by at least one slit, and the A shielding pattern is disposed between the charging electrode and the first pixel, and Wherein, the plurality of segments are configured to form a current path for generating a magnetic field.

17. The display device according to claim 16, in, The first thickness of the shielding pattern satisfies the following relationship: Wherein, T1 is the first thickness, A is the circumference, B is the magnetic permeability of the shielding pattern, C is the frequency of the current flowing through the shielding pattern, and D is the resistivity of the shielding pattern.

18. The display device according to claim 16, in, When viewed in a plan view, the shield pattern covers the charging electrode.

19. The display device according to claim 16, in, When viewed in a plan view, the shield pattern covers the transistor.

20. Electronic devices, including: case; An electronic module is disposed in the housing; A display device, arranged to overlap with the electronic module; as well as A stylus pen including a resonant circuit, Wherein, the display device comprises: A display panel comprising a display area and a non-display area around the display area; and an input sensor disposed on the display panel and configured to sense a resonance signal transmitted from the stylus pen, Wherein, the display panel comprises: a base layer, comprising a plurality of resin layers; a plurality of pixels disposed on the base layer and overlapping the display area; a charging electrode disposed under at least one of the plurality of resin layers and charging the stylus pen; and a first shielding pattern disposed on the base layer and overlapping the display area, the first shielding pattern having a first thickness, and Wherein, the first thickness corresponds to a thickness that satisfies the following relationship: Wherein, T1 represents the first thickness, A is pi, B is the magnetic permeability of the first shielding pattern, C is the frequency of the current flowing through the first shielding pattern, and D is the resistivity of the first shielding pattern.

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