Application specific integrated circuit (ASIC) power control

Abstract

A logical power network disposed in an application specific integrated circuit (ASIC). The ASIC includes a central processor. The ASIC also includes at least one intellectual property (IP) core operably connected to the central processor and in which a set of electrical components is disposed. The ASIC also includes a network-on-chip (NOC) operably connected to the central processor and the at least one IP core. The ASIC also includes a logical power network operably connected to the central processor, the at least one IP core, and the set of electrical components and the NOC therein. The logical power network is adapted to individually and independently control power of the at least one IP core and a set of electrical components disposed in the at least one IP core.

Description

Technical Field

[0001] The present disclosure generally relates to application specific integrated circuits (ASICs). More specifically, the present disclosure relates to ASIC power control. Specifically, the present disclosure relates to an ASIC power control having a logic power network that logically controls dynamic power of at least one intellectual property (IP) core in the ASIC and electrical components disposed in the at least one IP core. Background Art

[0002] Application-specific integrated circuits (hereinafter referred to as ASICs) are customized devices and / or components that are configured for specific purposes and optimized for specific tasks. Unlike general-purpose integrated circuits, ASICs are implemented for specific applications in various industries, including the automotive industry, aerospace industry, mobile device industry, medical industry, home automation industry, and other similar industries. In addition, ASICs can also be set up in complex versions that include multiple functions (such as microprocessors, peripheral functions, interface functions, and other similar functions). These complex ASICs can also include intellectual property (IP) cores pre-designed by third-party developers to perform pre-designed specific functions. For these components, such complex ASICs must include a power management system that delivers power to each component and network set up on these complex ASICs. However, such power management systems for these ASICs are very complex and difficult to implement because the power of each component on these ASICs needs to be controlled individually while reducing the power consumption in the ASICs.

[0003] In order to counter these power management systems, the designers of these ASICs may use power gate devices to control the power entering a single component (such as an IP core). However, due to the large number of devices and components set on these complex ASICs, it is quite time-consuming and complicated to install these power gate devices. Typically, the designers of these complex ASICs must cut off and / or rearrange the power nets of these complex ASICs to allow the power gate to control the power entering each individual component. In one instance, each IP core of the complex ASIC is separated and isolated on a single power island on the ASIC, so that each IP core is individually controlled by a power gate. In this case, the designers of these ASICs must also include power isolation buffers between each IP core and / or each electrical component on the ASIC to prevent electrical interference between adjacent and / or nearby components on the ASIC. In addition, when modeling power in simulation applications, it is quite difficult to test and verify these connections on the ASIC. In addition, complex ASICs also consider preventing power leakage driven by certain components set in the ASIC. Specifically, random access memory components (RAM) set in the IP core are usually the main cause of power leakage in complex ASICs. Therefore, these power gates must also be integrated with these RAMs to prevent power leakage in the ASIC, which ultimately leads to longer build times and more complex power systems for these ASICs. Summary of the invention

[0004] The presently disclosed ASIC power control system provides the ASIC designer with the ability to logically control components without having to rearrange and / or reconfigure the power control system. The presently disclosed ASIC power control system includes a logic power network that is capable of logically controlling the dynamic power of an IP core in the ASIC through a first logic power gate or clock gate. The presently disclosed ASIC power control system also includes a logic power network that is capable of logically controlling the power of an electrical component disposed in each IP core through a second logic power gate or component power gate. Thus, the ASIC power control system disclosed herein addresses some of the deficiencies of previously known techniques and uses of ASIC power control systems.

[0005] In one form, an exemplary embodiment of the present disclosure may provide an application specific integrated circuit (ASIC). The ASIC includes a central processing unit. The ASIC also includes at least one intellectual property (IP) core operably connected to the central processing unit, and the at least one IP core has an electrical component group disposed therein. The ASIC also includes a network on chip (NOC) operably connected to the central processing unit and the at least one IP core. The ASIC also includes a logic power network operably connected to the central processing unit, the at least one IP core, the electrical component group therein, and the NOC. The logic power network is suitable for individually and independently controlling the power of the at least one IP core and the electrical component group disposed in the at least one IP core.

[0006] This exemplary embodiment or another exemplary embodiment may also provide: wherein the logic power network further includes: an IP clock gate operably connected to the at least one IP core; wherein the IP clock gate is configured to control the dynamic power of the at least one IP core. This exemplary embodiment or another exemplary embodiment may also provide: wherein the logic power network further includes: a component power gate operably connected to the electrical component group; wherein the component power gate is configured to control the power of each electrical component in the electrical component group. This exemplary embodiment or another exemplary embodiment may also provide: wherein the logic power network further includes: a first side logic channel operably connected to the central processor, the at least one IP core, the NOC and the IP clock gate; wherein the IP clock gate is adapted to control the dynamic power of the at least one IP core between an on state and an off state when receiving at least one input from the central processor through the first side logic channel. This exemplary embodiment or another exemplary embodiment may also provide: wherein the logic power network further comprises: a second side logic channel operably connected to the central processor, the at least one IP core and the component power gate; wherein the component power gate is adapted to control the power of the electrical component group of the at least one IP core between an on state and an off state when receiving at least another input from the central processor through the second side logic channel or in response to receiving at least another input from the central processor through the second side logic channel. This exemplary embodiment or another exemplary embodiment may also provide a first command output from the central processor to the NOC and the IP clock gate; wherein the IP clock gate activates the at least one IP core between an on state and an off state. This exemplary embodiment or another exemplary embodiment may also provide a second command output from the central processor to the component power gate; wherein the component power gate activates the electrical component group of the at least one IP core between an on state and an off state. This exemplary embodiment or another exemplary embodiment may also provide: wherein the electrical component group is a random access memory (RAM) group. This exemplary embodiment or another exemplary embodiment may also provide that: wherein the component power gate is configured to operate with a fin field effect transistor.

[0007] In another aspect, an exemplary embodiment of the present disclosure may provide a logic power network disposed in an application specific integrated circuit (ASIC). The logic power network includes an IP clock gate operably connected to at least one IP core of the ASIC. The logic power network also includes a component power gate operably connected to an electrical component group of the at least one IP core. The IP clock gate is configured to control the dynamic power of the at least one IP core. The component power gate is configured to control the power of each electrical component in the electrical component group.

[0008] The exemplary embodiment or another exemplary embodiment may also provide a first side logic channel, the first side logic channel can operably connect the IP clock gate with the central processor of the ASIC, the at least one IP core and the network on chip (NOC) of the ASIC; wherein the IP clock gate is adapted to control the dynamic power of the at least one IP core between an on state and an off state when receiving at least one input from the central processor through the first side logic channel or in response to receiving at least one input from the central processor through the first side logic channel. The exemplary embodiment or another exemplary embodiment may also provide a second side logic channel, the second side logic channel can operably connect the component power gate with the central processor and the at least one IP core; wherein the component power gate is adapted to control the power of the electrical component group of the at least one IP core between an on state and an off state when receiving at least another input from the central processor through the second side logic channel or in response to receiving at least another input from the central processor through the second side logic channel. This exemplary embodiment or another exemplary embodiment may also provide a first command output from the central processor to the NOC and the IP clock gate; wherein the IP clock gate is adapted to activate the at least one IP core between an on state and an off state. This exemplary embodiment or another exemplary embodiment may also provide a second command output from the central processor to the component power gate; wherein the component power gate activates the electrical component group of the at least one IP core between an on state and an off state.

[0009] In another aspect, an exemplary embodiment of the present disclosure may provide a method for controlling the power of an application-specific integrated circuit (ASIC). The method includes the following steps: outputting a first command through a central processor of the ASIC; receiving the first command at an intellectual property (IP) clock gate of the logic power network through a first-side logic channel of a logic power network; receiving the first command at a component power gate of the logic power network through a second-side logic channel of the logic power network; controlling the dynamic power of at least one IP core through the IP clock gate; and disabling the operation of an electrical component group set in the at least one IP core from an active state to a dormant state through the component power gate.

[0010] This exemplary embodiment or another exemplary embodiment may also provide the following steps: notifying the network on chip (NOC) of the ASIC through the IP clock gate on the first side logic channel that the dynamic power of the at least one IP core has changed. This exemplary embodiment or another exemplary embodiment may also provide: the step of disabling the operation of the electrical component group set in the at least one IP core through the component power gate includes: the electrical component group is in a dormant state. This exemplary embodiment or another exemplary embodiment may also be provided with the following steps: recording unauthorized access behavior to the at least one IP core through the error unit of the ASIC. This exemplary embodiment or another exemplary embodiment may also provide the following steps: outputting a second command through the central processor of the ASIC; receiving the second command at the IP clock gate of the logic power network through the first side logic channel of the logic power network; controlling the dynamic power of the at least one IP core through the IP clock gate; and notifying the NOC through the IP clock gate on the first side logic channel that the dynamic power of the at least one IP core is ready for use. This exemplary embodiment or another exemplary embodiment may also provide the following steps: outputting a second command through the central processor of the ASIC; receiving the second command at the component power gate of the logic power network through the second side logic channel of the logic power network; and enabling the operation of the electrical component group set in the at least one IP core through the component power gate, wherein the electrical component group is in an activated state before disabling operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments of the present disclosure are set forth in the following description, are illustrated in the accompanying drawings, and are particularly and distinctly pointed out and set forth in the appended claims.

[0012] Figure 1 is a schematic diagram of a prior art intellectual property (IP) core power system in which a group of electrical components is disposed.

[0013] Figure 2 is a schematic diagram of an IP core having a logic power network and an electrical component group disposed therein according to one aspect of the present disclosure.

[0014] Figure 3 is a schematic diagram of an application specific integrated circuit (ASIC) having a logic power network and an IP core group according to one aspect of the present disclosure.

[0015] Figure 4 is a flow chart of a method for controlling ASIC power.

[0016] Like reference numerals represent like parts throughout the drawings. DETAILED DESCRIPTION

[0017] Figure 1 A prior art application specific integrated circuit (hereinafter referred to as "ASIC") is shown, generally indicated at 1. As shown herein, the ASIC 1 includes at least one semiconductor intellectual property (IP) core or IP core 2, which is a reusable component of logic functions that can set a specific function in the prior art ASIC 1 during operation. In the illustrated embodiment, a single IP core 2 is described and shown herein. In other exemplary embodiments, any suitable number of IP cores can be set in the ASIC for a particular application.

[0018] Still refer to Figure 1 , the IP core 2 of the prior art ASIC 1 includes at least one power terminal 3 for providing power to the IP core 2 during operation. In the illustrated embodiment, the IP core 2 includes a first power terminal 3A and a second power terminal 3B for providing power to the IP core 2 during operation; the use and purpose of each power terminal 3A, 3B will be described in more detail below.

[0019] Still refer to Figure 1 , the IP core 2 of the prior art ASIC 1 includes an electrical component group 4 disposed inside the IP core 2. The electrical component group 4 of the IP core 2 includes electrical components for performing at least one application-specific function required by the IP core 2 in the prior art ASIC 1. In the illustrated embodiment, the IP core 2 is provided with a first, second, third and fourth electrical components 4A, 4B, 4C, 4D, wherein each of the first, second, third and fourth electrical components 4A, 4B, 4C, 4D is a random access memory (RAM) component. In other exemplary embodiments, any appropriate number of electrical components and any appropriate electrical components may be used in the IP core to implement at least one application-specific function in the prior art ASIC. In addition, in a specific application configuration of the prior art ASIC 1, each electrical component in the electrical component group 4A, 4B, 4C, 4D is disposed on a power island that is separate and independent from another power island.

[0020] Still see Figure 1, the IP core 2 of the prior art ASIC 1 includes a hard-wired power gate network 6, which controls the power of the IP core 2 and the electrical components 4 disposed therein. The power gate network 6 typically includes a power gate switch 6A, which is operably connected to the IP core 2 as a whole, thereby controlling the power of the IP core 2 between an on state and an off state. In other words, the power gate switch 6A controls all power at the IP core 2. The power gate network 6 typically also includes a power isolation buffer 6B, which is operably connected and / or bridged to each electrical component in the electrical component group 4. This connection between the electrical component group 4 and the power isolation buffer 6B requires the designer of the prior art ASIC 1 to configure the power network of the prior art ASIC 1, wherein the power of the electrical component group 4 is separated and independent from another electrical component group 4 of another IP core 2 disposed in the prior art ASIC 1.

[0021] Typically, the power gate switch 6A is configured to be separate from the IP core 2 and independent of each other, which results in failure to meet the unified power format (hereinafter referred to as "UPF") process. Such problems occur in the prior art ASIC 1 because the power gate switch 6A needs to be hard-wired with each electrical component in the electrical component group 4 according to the application-specific configuration of the electrical component 4. Specifically, multiple electrical connections are electrically connected to the electrical component group 4, so that the power of the electrical component group 4 is controlled through the power gate switch 6A, and the power of each electrical component in the electrical component group 4 is isolated from another electrical component group of another IP core provided in the prior art ASIC 1 through the power isolation buffer 6B. Therefore, due to the physical design and arrangement of the electrical component group 4 provided in the IP core 2, multiple electrical connections between the power gate network 6 and the electrical component group 4 become difficult and time-consuming.

[0022] Once the prior art ASIC 1 power system is completed, the designers of these prior art ASIC 1 power systems must run verification programs and / or applications to determine whether the reconfigured power connections set the appropriate power for each IP core and / or electrical component connected in the prior art ASIC 1 power system. Typically, due to the new power system configuration and design in the prior art ASIC 1, when these power gate switches 6A are connected to the IP core 2, the designer must create new simulation programs. Therefore, the creation of these new simulation programs will result in longer build time and test time.

[0023] Figure 2An ASIC 10 is shown in accordance with one aspect of the present disclosure. The ASIC 10 includes at least one semiconductor IP core or IP core 12, which is a reusable component of logic functions that can be used to provide specific application functions in the ASIC 10 during operation. In the illustrated embodiment, a single IP core 12 is described and illustrated herein. In other exemplary embodiments, any suitable number of IP cores may be provided in the ASIC for a particular application.

[0024] Still refer to Figure 2 , the IP core 12 of the ASIC 10 includes at least one power terminal 13 for providing power to the IP core 12 during operation. In the illustrated embodiment, the IP core 12 includes a first power terminal 13A and a second power terminal 13B for providing power to the IP core 12 during operation; the use and purpose of each terminal 13A, 13B will be described in more detail below.

[0025] Still refer to Figure 2 , the IP core 12 of the ASIC 10 includes an electrical component group 14 disposed inside the IP core 12. The electrical component group 14 of the IP core 12 includes electrical components for performing at least one application-specific function required by the IP core 12 in the ASIC 10. In the illustrated embodiment, the IP core 12 is provided with first, second, third and fourth electrical components 14A, 14B, 14C, 14D, wherein each of the first, second, third and fourth electrical components 14A, 14B, 14C, 14D is a random access memory (RAM) element. In other exemplary embodiments, any suitable number of electrical components and any suitable electrical components may be used in the IP core to implement at least one application-specific function in the ASIC. In addition, in the specific application configuration of the ASIC 1, each electrical component in the electrical component group is separate and independent of each other.

[0026] As described herein, each electrical component in the electrical component group 14 includes a preconfigured power system that is independent of the surrounding and / or peripheral electrical components disposed therein. Therefore, each electrical component in the electrical component group 14 includes a power gate switch, a power isolation buffer, and other appropriate power control components, so that the electrical component can switch between an open state and a closed state. For example, the first, second, third, and fourth electrical components 14A, 14B, 14C, 14D are RAMs that include power gate switches, power isolation buffers, and other appropriate power control components, so that the RAMs can switch between different operating modes and / or settings (e.g., sleep mode, hibernation mode, etc.) or switch between an open state and a closed state. In addition, the IP core can use fin field effect (FinFet) transistor technology to reduce the overall power leakage of other electrical components disposed in the RAM 14A, 14B, 14C, 14D, and the IP core 2. Although this power technology is available, these RAMs 14A, 14B, 14C, 14D still leak power.

[0027] Still see Figure 2 , ASIC 1 includes a logic power network 16 that is operably coupled to the power network (not shown) of IP core 2 and ASIC 1. The logic power network 16 controls the power of IP core 12 and the electrical component group 14 disposed therein, respectively, thereby reducing power dissipation and reducing power leakage. As described in more detail below, compared to the prior art ASIC 1, the logic power network 16 is configured to remove power at the IP core 12 power level and the electrical component group 14 power level without complex physical hard wiring. In other words, the logic power network 16 is configured to logically control the power of the IP core 12 power level and the electrical component group 14 power level by pre-configuring the motherboard application on ASIC 10, which will be described in more detail below.

[0028] The logic power network 16 includes a first logic power gate or IP clock gate 16A (hereinafter referred to as "clock gate"), which is logically connected to the IP core 12 for controlling dynamic power entering the IP core 12. Specifically, the clock gate 16A is logically connected to the IP core 12 through a first side logic channel 16B. During operation, the clock gate 16A is adapted to control and activate the dynamic power and / or clock signal of the IP core 12 set from the power network of the ASIC 10. Therefore, the clock gate 16A is configured to activate the dynamic power of the IP core 12 between an on state and an off state according to a command from the central processor of the ASIC 10, which will be described in more detail below.

[0029] Including the clock gate 16A in the IP core 12 of the ASIC 10 is considered advantageous at least because, in contrast to the prior art ASIC 1 described above, the clock gate 16A completely controls the dynamic power of the IP core 12 without requiring reconfiguration or rearrangement of the power grid of the ASIC 10. In other words, the clock gate 16A is configured to logically control the dynamic power of the IP core 12 through a preconfigured motherboard application and / or component provided in the ASIC 10. Thus, the power grid of the ASIC 10 remains unchanged, and the dynamic power of the IP core 12 is logically controlled by switching the dynamic control between an on state and an off state.

[0030] Still see Figure 2 , the logic power network 16 also includes a second logic power gate or component power gate 16C, which is operably connected to the electrical component group 14 of the IP core 12 through the second side logic channel 16D. Specifically, the component power gate 16C is operably connected to the second power terminal 13B of the IP core 12 through the second side logic channel 16D. The component power gate 16C is logically connected to each electrical component in the electrical component group 14 provided in the IP core 12 through a program and / or application preconfigured and integrated into the electrical component group 14. After these connections, the component power gate 16C can communicate with each electrical component in the electrical component group 14 through logical control, thereby activating one or all electrical components in the electrical component group 14. In addition, the component power gate 16C is a standardized bus that enables the central processor or other similar components of the ASIC 10 to communicate with the electrical components in the electrical component group 14 to activate between an on state and a off state, which will be described in more detail below.

[0031] As described herein, the component power gate 16C is capable of communicating with the first, second, third, and fourth RAMs 14A, 14B, 14C, 14D during operation. Based on the preconfigured power systems within these RAMs 14A, 14B, 14C, 14D, the component power gate 16C is configured to control these power systems so as to activate these RAMs 14A, 14B, 14C, 14D individually and / or collectively between power modes and / or between an on state and a closed state. This communication between the component power gate 16C and the first, second, third, and fourth RAMs 14A, 14B, 14C, 14D is considered to be advantageous, at least because the component power gate 16C is capable of preventing leakage driven by the RAMs 14A, 14B, 14C, 14D during power-off operation.

[0032] The component power gate 16C is considered advantageous at least because the component power gate 16C is program agnostic, because the component power gate 16C can be used with various programs and / or applications provided by the electrical component group 14 in the IP core 12. In other words, the component power gate 16C is suitable for sending abstract and / or agnostic signals to various electrical component groups in various IP cores in various ASIC power systems. Therefore, the component power gate 16C is modular and can be used with various ASIC power systems without modifying the pre-configured ASIC power system. With this modularity, designers of these ASIC power systems can reuse and repurpose the electrical components in the IP core for other applications because the component power gate 16C logically controls the electrical components.

[0033] refer to Figure 3 , the ASIC 10 also includes a central processor or processor 18. The central processor 18 can be any suitable central processor 18 for the desired application required and created for the ASIC 10. The central processor 18 is operably connected to the logic power network 16. Specifically, the central processor 18 is operably connected to the clock gate 16A through the first side logic channel 16B, and the central processor 18 is operably connected to the component power gate 16C through the second side logic channel 16D. As described in more detail below, the central processor 18 is configured to send commands and / or signals to one or both of the clock gate 16A and the component power gate 16C to activate the dynamic power of at least one IP core 12 and activate the power of at least one electrical component of the electrical component group 14 within the at least one IP core 12.

[0034] Still refer to Figure 3 ASIC 10 also includes a network on chip or a network on chip (NOC) device. NOC 20 can be any NOC suitable for the desired application required and created by ASIC 10. Figure 3As shown, the NOC 20 is operably connected to the logic power network 16 and the central processor 18 individually and through the first side logic channel 16B. Specifically, the NOC 20 is operably connected to the clock gate 16A of the logic power network 16 and the central processor 18 through the first side logic channel 16B and the individual connection. The NOC 20 is also operably connected to at least one IP core 12 through an electrical connection 21. In the illustrated embodiment, the NOC 20 is operably connected to the first IP core 12A through a first electrical connection 21A, to the second IP core 12B through a second electrical connection 21B, and to the third IP core 12C in the ASIC 10 through a third electrical connection 21C. In other exemplary embodiments, any suitable number of IP cores can be operably connected to the NOC depending on the desired application and function of the ASIC. The NOC 20 is also independent of the component power gate 16C of the logic power network 16, wherein the second side logic channel 16D is not connected to the NOC 20. The NOC 20 is also operatively connected to the central processor 18 via an electrical connection 22 that is independent of the logic power network 16 .

[0035] Now that the components and networks of ASIC 10 have been described, a method of using ASIC 10 will be described in more detail.

[0036] In a first use, the central processor 18 is capable of switching the dynamic power of at least one IP core 12 from an on state to an off state through a logic power network provided in the ASIC 10. During this use, the central processor 18 sends a first command to the clock gate 16A through the first side logic channel 16B, thereby switching the dynamic power of at least one IP core 12 from an on state to an off state. In this example, the first command sent from the central processor 18 to the clock gate 16A commands the clock gate 16A to switch the dynamic power of the first IP core 12A from an on state to an off state. After receiving the first command, the clock gate 16A is enabled to disable the dynamic power of the first IP core 12 by deactivating the dynamic power of the first IP core 12 from an on state to an off state. As described above, the clock gate 16A of the logic power network 16 is configured to logically control the dynamic power of each IP core 12A, 12B, 12C provided in the ASIC 10.

[0037] In other exemplary embodiments, the clock gate 16A can logically control a specific IP core 12 or all IP cores 12 by disabling and / or deactivating dynamic power according to at least one command given by the central processor 18 .

[0038] Once the first command is sent from the central processor 18 to the clock gate 16A, the central processor 18 notifies the NOC 20 through a first notification: the dynamic power of the first IP core 12 is in a closed state before, at the same time, or after the clock gate 16A logically performs the operation. Once the NOC 20 receives the notification, the NOC 20 will logically record the notification, that is, the first IP core 12A is in a closed state. When a user or other device attempts to access the first IP core 12A in a closed state, this record of the first IP core 12A can be used to ensure security. If such an unauthorized operation occurs, the unauthorized operation will be recorded in the motherboard error system of the ASIC 10, thereby recording such unauthorized or invalid access to the first IP core 12.

[0039] In addition, the central processor 18 may also send a first command to the logic power network 16, so that at least one electrical component of the electrical component group 14 of at least one IP core 12 is in a closed state. Specifically, the central processor 18 may send a first command to the component power gate 16C through the second side logic channel 16D, so that at least one electrical component of the electrical component group 14 of at least one IP core 12 is in a closed state. In this example, the central processor 18 sends a first command to the component power gate 16C, so that at least one electrical component of the electrical component group 14 of the first IP core 12A is in a closed state. Once the command is received, the component power gate 16C turns off at least one electrical component or all electrical components of the electrical component group 14. According to the command, the central processor 18 may send any appropriate number of commands to the component power gate 16C, so that any electrical component of the electrical component group of at least another IP core is in a closed state.

[0040] In other exemplary embodiments, the command sent by the central processor can be any appropriate command for controlling the electrical component group set in the IP core of the ASIC. In the illustrated embodiment, the central processor 18 is suitable for sending a command to the component power gate 16C through the second side logic channel 16D, thereby setting at least one RAM of the RAM group 14 of the first IP core 12 to a specific state preconfigured to a specific RAM instead of a closed state. In one example, the central processor 18 is suitable for sending a command to the component power gate 16C through the second side logic channel 16D, thereby setting at least one RAM in the RAM group 14 of the first IP core 12 to a sleep mode or sleep state preconfigured to a specific RAM instead of a closed state. In another example, the central processor 18 is suitable for sending a command to the component power gate 16C through the second side logic channel 16D, thereby setting at least one RAM of the RAM group 14 of the first IP core 12 to a sleep mode and / or a frozen sleep state preconfigured to a specific RAM instead of a closed state.

[0041] Once at least one IP core 12 is set to the off state by the clock gate 16A and / or the component power gate 16C, the ASIC 10 can command at least one IP core 12 to be in the on state for various operational reasons. Therefore, the following usage method details the logic power network 16 to set the dynamic power for at least one IP core 12 and set the electrical component 14 of at least one IP core 12 from the off state to the on state.

[0042] After this operation, the central processor 18 may send a second command to the logic power network 16, thereby setting at least one electrical component of the electrical component group 14 of at least one IP core 12 from the off state to the on state. Specifically, the central processor 18 may send a first command to the component power gate 16C through the second side logic channel 16D, thereby making at least one electrical component of the electrical component group 14 of at least one IP core 12 in the on state. In this example, the central processor 18 sends a first command to the component power gate 16C, thereby setting at least one electrical component of the electrical component group 14 of the first IP core 12A from the off state to the on state. Upon receiving the command, the component power gate 16C sets at least one electrical component or all electrical components of the electrical component group 14 from the off state to the on state. Based on the command, the central processor 18 may send any appropriate number of commands to the component power gate 16C, thereby setting any electrical component of the electrical component group of at least another IP core from the off state to the on state.

[0043] In other exemplary embodiments, the command sent by the central processor can be any suitable command for controlling the electrical component group set in the IP core of the ASIC. In the illustrated embodiment, the central processor 18 is suitable for sending a command to the component power gate 16C through the second side logic channel 16D, thereby setting at least one RAM of the RAM group 14 of the first IP core 12 to a specific state preconfigured to a specific RAM instead of a closed state. In one example, the central processor 18 is suitable for sending a command to the component power gate 16C through the second side logic channel 16D, thereby setting at least one RAM of the RAM group 14 of the first IP core 12 from a sleep mode and / or sleep state preconfigured to a specific RAM to an open state or an activated state. In another example, the central processor 18 is suitable for sending a command to the component power gate 16C through the second side logic channel 16D, thereby setting at least one RAM of the RAM group 14 of the first IP core 12 from a sleep mode and / or sleep state preconfigured to a specific RAM to an open state or an activated state.

[0044] Then, the central processor 18 is able to switch the dynamic power of at least one IP core 12 from the off state to the on state through the logic power network set in the ASIC 10. During this use, the central processor 18 sends a second command to the clock gate 16A through the first side logic channel 16B, thereby switching the dynamic power of at least one IP core 12 from the off state to the on state. In this example, the second command sent from the central processor 18 to the clock 16A commands the clock gate 16A to switch the dynamic power of the first IP core 12A from the off state to the on state. After receiving the second command, the clock gate 16A enables the dynamic power of the first IP core 12 by activating the dynamic power of the first IP core 12 from the off state to the on state. As described above, the clock gate 16A of the logic power network 16 is configured to logically control the dynamic power of each IP core 12A, 12B, 12C set in the ASIC 10.

[0045] In other exemplary embodiments, the clock gate 16A can logically control a specific IP core 12 or all IP cores 12 by enabling and / or activating dynamic power according to at least one command given by the central processor 18 .

[0046] Once the second command is sent from the central processor 18 to the clock gate 16A, the central processor 18 notifies the NOC 20 through a second notification that the dynamic power of the first IP core 12 is in the on state after the clock gate 16A logically performs the operation. In this embodiment, after the clock gate 16A sets the first IP core 12 to the on state, the second notification sent from the central processor 18 to the NOC 20 can be delayed, thereby allowing the first IP core 12A to be available for operation. In other words, the second notification sent from the central processor 18 to the NOC 20 can be delayed, thereby allowing the first IP core 12 to start and be in an operational state. In addition, after the component power gate 16C sets at least one or all electrical components of the electrical component group 14 of the first IP core 12 from the off state to the on state, the second notification sent by the central processor 18 to the NOC 20 may be delayed. This delay allows at least one or all electrical components of the electrical component group 14 of the first IP core 12 to start and be in an operational state. Once the first IP core 12A is powered up and ready for use, the NOC 20 will be notified by one of the clock gate 16A and the CPU 18 .

[0047] In other exemplary embodiments, the logic power network 16 and the central processor 18 may continuously set one or all IP cores 12 to an on state or an off state depending on the operation of the ASIC 10 .

[0048] Figure 4A method 100 of controlling power of an application specific integrated circuit (ASIC) is shown. An initial step 102 of the method 100 includes outputting a first command via a central processor of the ASIC. Another step 104 of the method 100 includes receiving the first command at an intellectual property (IP) clock gate of the logic power network via a first side logic channel of the logic power network. Another step 106 of the method 100 includes receiving the first command at a component power gate of the logic power network via a second side logic channel of the logic power network. Another step 108 of the method 100 includes controlling dynamic power of at least one IP core via the IP clock gate. Another step 110 of the method 100 includes disabling operation of an electrical component group disposed in at least one IP core from an active state to a sleep state via the component power gate.

[0049] In other exemplary embodiments, method 100 may include additional and / or optional steps. Optional steps may include: notifying a network on chip (NOC) of the ASIC through an IP clock gate on a first-side logic channel that the dynamic power of at least one IP core has changed. Optional steps may include, wherein the step of disabling the operation of the electrical component group set in the at least one IP core through the component power gate includes: the electrical component group is in a dormant state. Optional steps may include: recording unauthorized access behavior to the at least one IP core through an error unit of the ASIC. Optional steps may include: outputting a second command through a central processor of the ASIC; receiving the second command at the IP clock gate of the logic power network through the first-side logic channel of the logic power network; controlling the dynamic power of the at least one IP core through the IP clock gate; and notifying the NOC through the IP clock gate on the first-side logic channel that the dynamic power of the at least one IP core is ready for use. Optional steps may include: outputting a second command through a central processor of the ASIC; receiving the second command at the component power gate of the logic power network through the second-side logic channel of the logic power network; and enabling the operation of the electrical component group set in the at least one IP core through the component power gate, wherein the electrical component group is in an active state before disabling the operation.

[0050] As described herein, aspects of the present disclosure may include one or more electrical, pneumatic, hydraulic or other similar secondary components and / or systems. Therefore, the present disclosure is contemplated to include any necessary operating components thereof. For example, electrical components will be understood to include any appropriate and necessary wiring, fuses, etc. required for their normal operation. Similarly, any pneumatic system provided may include any secondary or peripheral components, such as air hoses, compressors, valves, instruments, etc. It should also be understood that any connection between the various components not explicitly described herein may be made by any appropriate means, including mechanical fasteners or more permanent attachment methods, such as welding, etc. Alternatively, where feasible and / or desirable, the various components of the present disclosure may be formed as a single unit.

[0051] Various inventive concepts may be embodied as one or more methods, where examples have been provided. The actions performed as part of a method may be ordered in any suitable manner. Thus, embodiments may be constructed in which the actions are performed in a different order than shown, which may include performing some actions simultaneously, even though shown as sequential actions in an illustrative embodiment.

[0052] Although various inventive embodiments are described and illustrated herein, a person of ordinary skill in the art will readily conceive of various other means and / or structures for performing functions and / or obtaining results and / or one or more advantages described herein, and each of these changes and / or modifications is considered to be within the scope of the inventive embodiments described herein. More generally, a person of ordinary skill in the art will readily understand that all parameters, dimensions, materials, and configurations described herein are intended to be examples, and that actual parameters, dimensions, materials, and / or configurations will depend on the specific application in which the invention is taught. A person of ordinary skill in the art will recognize or be able to determine many equivalents of the specific inventive embodiments described herein using only routine experiments. Therefore, it should be understood that the aforementioned embodiments are presented only by way of example, and within the scope of the attached claims and their equivalents, the inventive embodiments may be implemented in a manner different from that specifically described and required. The inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods (if such features, systems, articles, materials, kits, and / or methods are not mutually contradictory) is included within the scope of the invention disclosed herein.

[0053] The above embodiments can be implemented in a variety of ways. For example, the embodiments of the technology disclosed herein can be implemented using hardware, software, or a combination thereof. When implemented in software, the software code or instructions can be executed on any suitable processor or set of processors, whether set in a single computer or distributed in multiple computers. In addition, the instructions or software codes can be stored in at least one non-temporary computer-readable storage medium.

[0054] In addition, a computer or smartphone for executing software codes or instructions through its processor may have one or more input and output devices. Among other uses, these devices can also be used to present a user interface. Examples of output devices that can be used to set a user interface include a printer or display screen for visual presentation output and a speaker or other sound generating device for auditory presentation output. Examples of input devices that can be used for a user interface include a keyboard and a pointing device, such as a mouse, a touch pad, and a digitized tablet. As another example, a computer can receive input information through voice recognition or other audible formats.

[0055] Such computers or smartphones may be interconnected via one or more networks of any suitable form, including local or wide area networks (e.g., enterprise networks) and intelligent networks (IN) or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol, and may include wireless networks, wired networks, or fiber optic networks.

[0056] The various methods or processes outlined herein may be encoded as software / instructions that can be executed on one or more processors using various operating systems or platforms. In addition, such software may be written using a variety of suitable programming languages ​​and / or programming or scripting tools, and may also be compiled into executable machine language code or intermediate code that is executed on a framework or virtual machine.

[0057] In this form, various inventive concepts may be embodied as a computer-readable storage medium (or multiple computer-readable storage media) (e.g., computer memory, one or more floppy disks, disks, optical disks, tapes, flash memory, USB flash drives, SD cards, circuit configurations in field programmable gate arrays or other semiconductor devices, or other non-transitory media or tangible computer storage media), encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments disclosed above. The computer-readable medium may be removable so that the program stored thereon can be loaded onto one or more different computers or other processors, thereby implementing the various forms of the present disclosure as described above.

[0058] The term "program" or "software" or "instruction" is used in a general sense herein to refer to any type of computer code or computer executable instruction set that can be used to program a computer or other processor to implement various aspects of the embodiments described above. In addition, it should be understood that, according to one aspect, one or more computer programs that execute the method of the present disclosure do not have to reside on a single computer or processor, but can be distributed in a modular manner between multiple different computers or processors to implement various aspects of the present disclosure.

[0059] Computer executable instructions can take many forms, such as program modules that are executed by one or more computers or other devices. Typically, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. Typically, the functions of program modules can be combined or distributed as needed in various implementations.

[0060] In addition, the data structure can be stored in a computer-readable medium in any suitable form. For ease of illustration, the data structure can be shown as having fields that are related by location in the data structure. This relationship can also be achieved by allocating storage for the fields, which has locations in the computer-readable medium that convey the relationship between the fields. However, any suitable mechanism can be used to establish the relationship between the information in the data structure fields, including through the use of pointers, tags or other mechanisms to establish relationships between data elements.

[0061] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0062] As used herein, "logic" includes, but is not limited to, hardware, firmware, software, and / or combinations thereof, for performing a function or action, and / or causing a function or action from another logic, method, and / or system. For example, based on the desired application or requirements, logic may include a software-controlled microprocessor, discrete logic such as a processor (e.g., a microprocessor), an application-specific integrated circuit (ASIC), a programmed logic device, a storage device containing instructions, an electrical device with a memory, and the like. Logic may include one or more gates, a combination of gates, or other circuit components. Logic may also be fully embodied as software. When describing multiple logics, multiple logics may be merged into one physical logic. Similarly, when describing a single logic, the single logic may be distributed between multiple physical logics.

[0063] In addition, the logic of the various methods proposed in this article for implementing the system can be directed to the improvement of existing computer-centric or Internet-centric technologies, which may not have previous analog versions. The logic can set specific functions directly related to the structure to solve some of the problems identified in this article. The logic can also set more advantages to solve these problems by setting the exemplary inventive concept as a specific logical structure and consistent functions of the method and system. In addition, the logic can also set specific computer implementation rules to improve the existing technology process. The logic set in this article is not just collecting data, analyzing information and displaying results. In addition, part or all of the present disclosure may rely on the underlying equations derived from the specific arrangement of the devices or components described in this article. Therefore, parts of the present disclosure are related to the specific arrangement of the components and are not directed to abstract concepts. In addition, the teachings proposed by the present disclosure and the attached claims involve more than just performing activities previously known, well-known, conventional and traditional in the industry. In some methods or processes of the present disclosure, some forms of natural phenomena may be combined, and the process or method steps are new and useful additional features.

[0064] Unless otherwise expressly stated, the articles "a" and "an" used in this specification and claims should be understood as "at least one". The phrase "and / or" (if any) used in this specification and claims should be understood as "either or both" connected elements, that is, elements that are connected in some cases and separated in other cases. Multiple elements listed with "and / or" should be interpreted in the same way, that is, "one or more" connected elements. In addition to the elements explicitly identified in the "and / or" clause, other elements may optionally be present, whether they are related or unrelated to the explicitly identified elements. Therefore, as a non-limiting example, when used in conjunction with open language such as "including", the reference to "A and / or B" may refer to only A (optionally including elements other than B) in one embodiment; only B (optionally including elements other than A) in another embodiment; both A and B (optionally including other elements) in another embodiment; and so on. As used in the specification and claims, "or" should be understood to have the same meaning as the above-mentioned "and / or". For example, when separating items in a list, "or" or "and / or" should be interpreted as inclusive, that is, including at least one of a plurality or a group of elements, but also including a plurality, and optionally, including other items not listed. Only when terms are clearly indicated to the contrary, such as "only one" or "exactly one", or when used in the claims, "consisting of...", does it mean to include exactly one element of a plurality or a group of elements. In general, the term "or" as used herein should be interpreted as indicating exclusive substitution (i.e., "one or the other but not both") only when it is preceded by an exclusive term (e.g., "any one", "one of", "only one", or "exactly one"). "Mainly consisting of...", when used in the claims, should have the usual meaning in the field of patent law.

[0065] As used herein in the specification and claims, the phrase "at least one" when referring to a list of one or more elements should be understood to refer to at least one element selected from any one or more elements in the list of elements, but does not necessarily include at least one of each element specifically listed in the list of elements, nor does it exclude any combination of elements in the list of elements. This definition also allows that in addition to the elements specifically identified in the list of elements referred to by the phrase "at least one", elements may optionally be present, whether related or unrelated to the specifically identified elements. Thus, as a non-limiting example, "at least one of A and B" (or equivalently, "at least one of A or B", or equivalently, "at least one of A and / or B") may refer to at least one, optionally including more than one A, without B (and optionally including elements other than B) in one embodiment; to at least one, optionally including more than one B, without A (and optionally including elements other than A) in another embodiment; to at least one, optionally including more than one A, and at least one, optionally including more than one B (and optionally including other elements) in yet another embodiment; and so on.

[0066] As used in this specification and in the claims, the term "enable" or a phrase or claim element beginning with the term "enable" should be understood to mean causing something to occur or causing something to happen. For example, enabling the occurrence of an event may be caused by the actions of a first party even if the second party actually performs the event or causes the event to occur to the second party. In other words, enabling refers to one party setting up the tools, objects, or resources to another party to cause the event to occur. Therefore, in this example, the claim element "enables the occurrence of an event" means that the first party is setting up the tools or resources to the second party that the second party needs to perform the event, but the affirmative single action is that the first party is responsible for setting up the tools or resources to cause the described event to occur.

[0067] When a feature or element is referred to herein as being "located on" another feature or element, it may be directly located on another feature or element, or there may also be intermediate features and / or elements. On the contrary, when a feature or element is referred to as being "directly located on" another feature or element, there are no intermediate features or elements. It should also be understood that when a feature or element is referred to as being "connected," "attached" or "engaged" to another feature or element, it may be directly connected, attached or engaged to another feature or element, or there may be intermediate features or elements. On the contrary, when a feature or element is referred to as being "directly connected," "directly attached" or "directly engaged" to another feature or element, there are no intermediate features or elements. Although described or shown for one embodiment, the features and elements described or shown in this way may be applied to other embodiments. It should also be understood by those skilled in the art that the structure or feature mentioned to be "adjacent" to another feature may have a portion overlapping with an adjacent feature or being located under an adjacent feature.

[0068] For ease of description, spatial relative terms such as "below", "below", "below", "above", "upper", "above", "rear", "front" may be used herein to describe the relationship between one element or feature and another element or feature, as shown in the figure. It should be understood that, in addition to the directions shown in the figure, spatial relative terms are also intended to cover different directions of the device in use or operation. For example, if the device in the figure is inverted, the element described as "located" "below" or "lower" of other elements or features will be located "above" other elements or features. Therefore, the exemplary term "below" can cover the direction above and below. The device can be oriented in other ways (rotated 90 degrees or other directions), and the spatial relative descriptors used herein can be interpreted accordingly. Similarly, unless otherwise explicitly stated, the terms "upward", "downward", "vertical", "horizontal", "lateral", "lateral", "longitudinal", etc. are used herein only for the purpose of explanation.

[0069] Although the terms "first" and "second" may be used herein to describe various features / elements, these features / elements should not be limited by these terms unless the context indicates otherwise. These terms can be used to distinguish one feature / element from another feature / element. Thus, a first feature / element discussed herein may be referred to as a second feature / element, and similarly, a second feature / element discussed herein may be referred to as a first feature / element without departing from the teachings of the present invention.

[0070] An embodiment is an implementation or example of the present disclosure. References in the specification to "an embodiment," "one embodiment," "some embodiments," "a specific embodiment," "exemplary embodiment," or "other embodiments" etc. mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least some embodiments of the present invention, but not necessarily all embodiments. Various appearances of "an embodiment," "one embodiment," "some embodiments," "a specific embodiment," "exemplary embodiment," or "other embodiments" etc. do not necessarily refer to the same embodiment.

[0071] If the specification states that a component, feature, structure or characteristic "may", "might" or "could" be included, that specific component, feature, structure or characteristic is not necessarily included. If the specification or claims mention "a" or "an" element, it does not mean that there is only one of the element. If the specification or claims mention "an additional" element, it does not exclude the presence of multiple additional elements.

[0072] As used in this specification and claims, including in the embodiments, unless otherwise expressly stated, all numbers can be read as being preceded by the word "about" or "approximately", even if the term does not explicitly appear. The phrase "about" or "approximately" can be used to describe magnitude and / or position, thereby indicating that the value and / or position is within a reasonable expected value and / or position range. For example, a numerical value may have a value of + / -0.1% of the value (or value range), + / -1% of the value (or value range), + / -2% of the value (or value range), + / -5% of the value (or value range), + / -10% of the value (or value range), etc. Any numerical range described herein is intended to include all subranges contained therein.

[0073] In addition, the method of implementing the present disclosure can be performed in a different order than described herein. Therefore, unless explicitly stated, the order of the method should not be understood as a limitation. It can be recognized that certain steps of the method can achieve similar results by performing them in different orders.

[0074] In the claims and the foregoing description, all transitional phrases, such as "comprises," "comprising," "carrying," "having," "containing," "involving," "holding," "consisting of," etc., shall be construed as open-ended, i.e., meaning including but not limited to. Only the transitional phrases "consisting of" and "consisting essentially of" shall be closed or semi-closed transitional phrases, respectively, as described in the U.S. Patent Office Manual of Patent Examining Procedure.

[0075] In the above description, certain terms are used for brevity, clarity and ease of understanding. No unnecessary limitations should be implied thereby, except as required by the prior art, as these terms are used for descriptive purposes and are intended to be broadly interpreted.

[0076] Moreover, the descriptions and illustrations of the various embodiments of the disclosure are examples, and the disclosure is not limited to the exact details shown or described.

Claims

1. An application specific integrated circuit (ASIC), comprising: CPU; at least one intellectual property (IP) core operatively connected to the central processor, the at least one IP core having a set of electrical components disposed therein; a network on chip (NOC) operably connected to the central processor and the at least one IP core; and A logic power network operatively connected to the central processor, the at least one IP core and the electrical component group therein, and the NOC; The logic power network is suitable for individually and independently controlling the power of the at least one IP core and the electrical component group arranged in the at least one IP core.

2. The ASIC according to claim 1, wherein: The logic power network includes: an IP clock gate operatively connected to the at least one IP core; The IP clock gate is configured to control the dynamic power of the at least one IP core.

3. The ASIC according to claim 2, wherein: The logic power network also includes: a component power gate operatively connected to the electrical component group; The component power gate is configured to control the power of each electrical component of the electrical component group.

4. The ASIC according to claim 3, wherein: The logic power network also includes: A first side logic channel operatively connected to the central processor, the at least one IP core, the NOC and the IP clock gate; The IP clock gate is adapted to control the dynamic power of the at least one IP core between an on state and an off state when receiving at least one input from the central processor through the first side logic channel.

5. The ASIC of claim 4, wherein: The logic power network also includes: A second side logic channel operatively connected to the central processor, the at least one IP core and the component power gate; Wherein, the component power gate is suitable for controlling the power of the electrical component group of the at least one IP core between an on state and an off state when receiving at least another input from the central processor through the second side logic channel or in response to receiving at least another input from the central processor through the second side logic channel.

6. The ASIC of claim 5, further comprising: A first command outputted from the central processor to the NOC and the IP clock gate; The IP clock gate activates the at least one IP core between an on state and a off state.

7. The ASIC of claim 6, further comprising: a second command outputted from the central processor to the component power gate; The component power gate activates the electrical component group of the at least one IP core between an on state and an off state.

8. The ASIC of claim 1, wherein: The group of electrical components is a random access memory (RAM) group.

9. The ASIC of claim 3, wherein: The component power gate is configured to operate with a FinFET.

10. A logic power network arranged in an application specific integrated circuit (ASIC), comprising: an IP clock gate operatively connected to at least one IP core of the ASIC; as well as component power gates operatively connected to the set of electrical components of the at least one IP core; wherein the IP clock gate is configured to control the dynamic power of the at least one IP core; and The component power gate is configured to control the power of each electrical component of the electrical component group.

11. The logic power network of claim 10, further comprising: a first side logic channel operatively connecting the IP clock gate with a central processor of the ASIC, the at least one IP core, and a network on chip (NOC) of the ASIC; The IP clock gate is adapted to control the dynamic power of the at least one IP core between an on state and an off state when receiving at least one input from the central processor through the first side logic channel or in response to receiving at least one input from the central processor through the first side logic channel.

12. The logic power network of claim 11 , further comprising: a second side logic channel operatively connecting the component power gate with the central processor and the at least one IP core; Wherein, the component power gate is suitable for controlling the power of the electrical component group of the at least one IP core between an on state and an off state when receiving at least another input from the central processor through the second side logic channel or in response to receiving at least another input from the central processor through the second side logic channel.

13. The logic power network of claim 12, further comprising: A first command outputted from the central processor to the NOC and the IP clock gate; The IP clock gate is suitable for activating the at least one IP core between an on state and a off state.

14. The logic power network of claim 13, further comprising: a second command outputted from the central processor to the component power gate; The component power gate activates the electrical component group of the at least one IP core between an on state and an off state.

15. A method of controlling power of an application specific integrated circuit (ASIC), comprising the steps of: Outputting a first command through a central processor of the ASIC; receiving the first command at an intellectual property (IP) clock gate of the logic power network through a first side logic channel of the logic power network; receiving the first command at a component power gate of the logic power network through a second side logic channel of the logic power network; controlling the dynamic power of at least one IP core through the IP clock gate; and The operation of the electrical component group provided in the at least one IP core is disabled from an active state to a dormant state through the component power gate.

16. The method according to claim 15, further comprising: A network on chip (NOC) of the ASIC is notified through an IP clock gate on the first-side logic channel that the dynamic power of the at least one IP core has changed.

17. The method according to claim 15, wherein: The step of disabling the operation of the electrical component group disposed in the at least one IP core through the component power gate includes: the electrical component group is in a sleep state.

18. The method of claim 15, further comprising: Unauthorized access to the at least one IP core is recorded by the error unit of the ASIC.

19. The method of claim 16, further comprising: outputting a second command through the central processor of the ASIC; receiving the second command at the IP clock gate of the logic power network through the first side logic channel of the logic power network; controlling the dynamic power of the at least one IP core through the IP clock gate; and The NOC is notified through the IP clock gate on the first-side logic channel that the dynamic power of the at least one IP core is ready to be used.

20. The method of claim 16, further comprising: outputting a second command through the central processor of the ASIC; receiving the second command at the component power gate of the logic power network through the second side logic channel of the logic power network; and The operation of the electrical component group disposed in the at least one IP core is enabled through the component power gate, wherein the electrical component group is in an activated state before the operation is disabled.

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