Semiconductor structure with direct liquid cooling
By welding and fixing the sealing ring or sealing cover to the mold body in the automotive inverter system, combined with the turbulence structure, the problem of insufficient sealing of the direct liquid cooling module is solved, achieving efficient cooling effect and chip temperature uniformity, and improving system performance and lifespan.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2022-10-04
- Publication Date
- 2026-05-19
AI Technical Summary
In existing automotive inverter systems, the direct liquid cooling module suffers from insufficient sealing, resulting in poor cooling performance and impacting system performance and lifespan.
The sealing ring or sealing cap is fixed to the mold body by laser welding or ultrasonic welding, combined with the turbulent structure to ensure effective sealing of the coolant and heat dissipation area and efficient heat transfer.
This achieves optimal sealing reliability for the direct liquid cooling module, shortens the thermal path, ensures all chips operate under similar junction temperatures and cooling conditions, and improves system performance and reliability.
Smart Images
Figure CN119547206B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of sealing technology for direct liquid cooling of electronic modules, such as cool-formed power modules for automotive and industrial equipment. More particularly, this application relates to a semiconductor structure cooled by a coolant. This application also relates to a sealing element for sealing a power module to prevent coolant flow. Background Technology
[0002] In automotive and industrial applications, particularly in automotive inverter systems, efficient cooling is crucial for improving performance and extending lifespan. Such cooling systems involve thermal paths from the chip surface to the cooling medium (coolant, such as water or a water-glycol mixture). The more efficient these thermal paths are, the higher the power the system can handle within a given active chip area. Basic simulations of cooling power modules show that "direct liquid cooling" technology outperforms other technologies. This concept assumes that the cooling medium is in direct contact with the packaged heat dissipation area, thus requiring a highly efficient, sealed cooling medium.
[0003] Recent results indicate that the molding process is insufficient to seal the cooling medium in the package due to inadequate mold temperature reaching the power module region. A "cold" mold leads to insufficient adhesion, resulting in inadequate sealing.
[0004] Therefore, a sealing concept is needed to achieve optimal sealing reliability for direct liquid cooling modules. Summary of the Invention
[0005] The apparatus and method according to this application can provide a solution for semiconductor structures cooled by a coolant without the aforementioned disadvantages.
[0006] Therefore, a solution for a highly efficient sealed direct liquid cooling module is provided.
[0007] The above and other objectives are achieved through the features of the independent claim. Other implementations will be apparent from the dependent claims, the description, and the drawings.
[0008] This application provides two different embodiments for sealing:
[0009] 1) The first embodiment relates to a sealing ring, also known as a sealing ring, for example, such as Figure 1 and Figure 3 As described in [the text].
[0010] 2) The second embodiment is based on, for example Figure 2 and Figure 4 The sealing cap described herein.
[0011] The proposed solution in this application may involve one or more of the following:
[0012] - The sealing area is repositioned to the top of the second mold body by means of a suitable sealing element, which can be used in two different embodiments: in embodiment 1 as a sealing ring, also known as a sealing ring; and in embodiment 2 as a sealing cap, for example, the sealing cap can be made of aluminum.
[0013] - The sealing element (i.e., sealing ring or sealing cap) is installed and sealed to the surface of the module cooler by laser welding or ultrasonic welding (made of aluminum in Example 1 and copper in Example 2).
[0014] - Because the second mold body initially has stickiness issues (which, as mentioned above, can lead to a cold mold), an additional laser processing step is required to remelt the overlapping mold body below, so that the rough surface of the sealing element and the thermoplastic of the second mold body are reliably interconnected.
[0015] - The turbulent structure is directly fixed to the surface of the module cooler using laser welding or ultrasonic welding. The first version used zigzag elements, and the second version used aluminum strip adhesive.
[0016] -The sealing cap of Example 2 may have a pre-attached turbulent structure.
[0017] - The turbulent structure can be formed asymmetrically for junction temperature matching.
[0018] - The cooling fins for turbulent liquid flow can be positioned according to the orientation of the chips in the power module to achieve an ideal short thermal path and ensure that the temperature deviation between each chip is minimized.
[0019] - Compared to indirect cooling methods, the critical thermal path from the chip (heat source) to the cooling medium (such as water or ethylene glycol) can be shortened.
[0020] - Due to the overlapping concept proposed in this application, the scheme described below improves the sealing and interconnection quality between the module cooler area and the second mold body.
[0021] - The sealing ring (Example 1) does not require an additional interlayer, which may affect the thermal path or integrity of the module.
[0022] - Due to the sealing scheme described in this application, it is no longer necessary to roughen the cooler to obtain better adhesion.
[0023] - The turbulent structure can be easily attached to the module cooler area by direct bonding or welding.
[0024] - For the sealing cap according to Embodiment 2, an asymmetric turbulent structure can be employed. This asymmetric turbulent structure allows all chips within the system to operate at nearly the same junction temperature level, which is highly beneficial for improving system performance.
[0025] - The turbulent structure can be easily clamped onto the module surface.
[0026] This application also relates to a turbulent structure, particularly a non-uniform turbulent structure. This turbulent structure can be sandwiched between the cooler region of the module and the cover plate (top and bottom) to balance the chip temperature, for example, within a certain range of approximately 5°C, 10°C, or 15°C throughout the semiconductor structure. This temperature balance facilitates uniform flow of the cooling medium through the power module, thereby improving performance and reliability. In this concept, a non-uniform turbulent insert can be attached to the cooler region, for example, sandwiched between the cooler region and the cover plate (top and bottom). The non-uniform turbulent insert ensures such contact and diffusion performance that the chip temperature can be maintained within a certain temperature range, for example, within 5°C, 10°C, or 15°C even under full load.
[0027] According to a first aspect, this application relates to a semiconductor structure with coolant cooling, the semiconductor structure comprising: a power module for power conversion, the power module including a first module side and a second module side opposite to the first module side, wherein a first mold body is disposed between the first module side and the second module side; the first module side includes an upper metal layer; a second mold body at least partially encapsulating the power module, wherein a portion of the upper metal layer forming an upper heat dissipation area of the power module is not covered by the second mold body; in a transition region between the upper heat dissipation area and the second mold body, an upper metal sealing element covers the upper heat dissipation area and the second mold body to seal the power module and prevent coolant from flowing through the upper heat dissipation area.
[0028] This semiconductor structure provides a seal that enables optimal sealing reliability for direct liquid cooling modules, whether they are single-sided or double-sided cooling modules.
[0029] While a semiconductor structure with power modules has been described above, this is not limited to a semiconductor structure consisting of a single power module. It should be understood that the semiconductor structure may include one or more such power modules.
[0030] In an exemplary implementation of the semiconductor structure, the upper metal sealing element forms a weld joint with the upper heat dissipation region.
[0031] The advantage of doing this is that heat can be optimally transferred from the power module to the upper heat dissipation area through the welded joint.
[0032] In an exemplary implementation of the semiconductor structure, the upper metal sealing element forms a rough surface connection with the second mold body in the transition region between the upper heat dissipation region and the second mold body.
[0033] The rough surface structure provides the technical effect that the upper metal sealing element includes a drilled structure of soft material that can be engaged with the second mold body, for example, a drilled structure made of thermoplastic. Therefore, the rough surface structure of the upper metal sealing element has sharp edges that engage with the second mold body, thus providing a tight or sealed connection through mechanical adhesion (e.g., in the manner of Velcro fasteners).
[0034] In an exemplary implementation of the semiconductor structure, the second mold body includes a remelted mold material in the transition region between the upper heat dissipation region and the second mold body, the remelted mold material having a rough surface.
[0035] The advantage of this is that the rough surface structure of the remelted second mold body can be efficiently clamped into the rough surface structure of the upper metal sealing element to provide optimal sealing.
[0036] In an exemplary implementation of the semiconductor structure, the second module side includes a lower metal layer; wherein a portion of the lower metal layer forming the lower heat dissipation region of the power module is not covered by the second mold body; the semiconductor structure further includes: in the transition region between the lower heat dissipation region and the second mold body, a lower metal sealing element covers the lower heat dissipation region and the second mold body to seal the power module and prevent coolant from flowing through the lower heat dissipation region.
[0037] This semiconductor structure provides a seal that enables optimal sealing reliability not only for single-sided cooling modules but also for double-sided cooling modules.
[0038] In an exemplary implementation of the semiconductor structure, the semiconductor structure includes: a turbulence element mounted above the upper metal layer and / or below the lower metal layer for generating turbulence in a coolant flowing through the upper heat dissipation region and / or below the lower heat dissipation region.
[0039] By using such a turbulence element, the power module can be cooled efficiently. The turbulence generated by the turbulence element on the cooling medium ensures that all semiconductor chips in the power module have similar junction temperatures and similar cooling conditions.
[0040] In an exemplary implementation of the semiconductor structure, the upper metal sealing element forms a sealing ring, and the sealing ring forms an annular structure or a frame structure along the transition region between the upper heat dissipation region and the second mold body.
[0041] The advantage of this is that the sealing ring provides optimal sealing in the transition area between the upper heat dissipation area and the second mold body.
[0042] In an exemplary implementation of the semiconductor structure, the turbulence element is mounted on the upper metal layer and does not contact the upper metal sealing element.
[0043] The advantage of this is that heat can be transferred directly from the upper metal layer to the outside of the semiconductor structure. Independent heat transfer can be achieved through the seal.
[0044] In an exemplary implementation of the semiconductor structure, the upper metal sealing element forms a sealing cap that covers the upper heat dissipation area of the power module.
[0045] The advantage of this is that the sealing cap can simultaneously achieve both sealing and heat transfer functions.
[0046] In an exemplary implementation of the semiconductor structure, the turbulence element is mounted on the upper metal sealing element.
[0047] The advantage of doing this is that it allows for both efficient cooling and sealing.
[0048] In an exemplary implementation of the semiconductor structure, the turbulence element includes a plurality of turbulence sheets disposed symmetrically or asymmetrically on the upper metal layer and / or the lower metal layer.
[0049] The advantage of these turbulent sheets is that they create the largest heat dissipation and turbulent surface.
[0050] In an exemplary implementation of the semiconductor structure, the semiconductor structure includes: a plurality of chips embedded in the power module, wherein each chip is placed at a pre-specified location relative to the upper metal layer and / or the lower metal layer, the pre-specified location being pre-specified by a package layout; and at least one turbulence sheet of the turbulence element is placed at the pre-specified location on the upper metal layer and / or the lower metal layer.
[0051] The advantage of this is that the design of the semiconductor structure can optimize heat transfer for each of the multiple chips.
[0052] Each power module of the semiconductor structure can have the same number of chips or a different number of chips. In one example, each power module can have 6 chips or 12 chips. In other examples, a power module can have 2 chips, 3 chips, 4 chips, 5 chips, or even only 1 chip. It should be understood that other numbers of chips are also possible, such as 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, and more.
[0053] In an exemplary implementation of the semiconductor structure, the turbulence element is welded to the upper metal layer, and the turbulence element and the upper metal layer form a first welding pattern; or the turbulence element is welded to the upper metal sealing element, and the turbulence element and the upper metal sealing element form a first welding pattern, and the upper metal sealing element and the upper metal layer form a second welding pattern.
[0054] The advantage of doing so is that the first welding pattern and / or the second welding pattern can be designed to achieve optimal heat transfer based on the known location of the chip embedded in the power module.
[0055] In an exemplary implementation of the semiconductor structure, the first welding pattern and / or the second welding pattern are aligned with the arrangement of the turbulent sheet of the turbulent element.
[0056] The advantage of doing this is that the turbulent sheet can be placed on the power module to achieve optimal heat transfer.
[0057] In an exemplary implementation of the semiconductor structure, the first welding pattern and / or the second welding pattern are aligned with the pre-specified positions of the plurality of chips embedded in the power module.
[0058] The advantage of this approach is that the solder pattern can be designed to achieve optimal heat transfer. It should be noted that heat is generated by the chip; optimal heat dissipation can be achieved when the solder pattern is aligned with the chip's position.
[0059] In an exemplary implementation of the semiconductor structure, the first welding pattern and / or the second welding pattern includes a plurality of solder joints, the density of which is based on the temperature of the plurality of chips embedded in the power module.
[0060] The advantage of doing this is that more heat can be transferred to areas of the chip with higher temperatures.
[0061] In an exemplary implementation of the semiconductor structure, the plurality of solder joints are arranged in a plurality of solder lines, the distance between any two solder lines being based on the temperature of the respective chips among the plurality of chips placed below the two solder lines.
[0062] The advantage of doing this is that heat dissipation can be controlled by design, utilizing the distance between the welding lines.
[0063] The temperature of the multiple chips embedded in a power module is typically not uniform. Chips with higher temperatures tend to have more solder joints, while chips with lower temperatures have fewer solder joints.
[0064] The welding pattern can be adjusted based on the independent thermal characteristics of the individual chip.
[0065] Unlike chips operating at low temperatures, the turbulence structure and the welding structure can be arranged more densely or at a higher density on chips operating at high temperatures.
[0066] In one example, the turbulent structure is uniform, while the welded structure is non-uniform, depending on the chip temperature. In another example, the welded structure is uniform, while the turbulent structure is non-uniform, depending on the chip temperature.
[0067] In an exemplary implementation of the semiconductor structure, the temperature of the plurality of chips embedded in the power module is within a temperature range of 5°C, 10°C, or 15°C relative to a reference temperature.
[0068] It should be understood that other temperature ranges may also be applied, such as 1°C, 2°C, 3°C, 4°C, 6°C, 7°C, 8°C, 9°C, 11°C, 12°C, 13°C, 14°C, 16°C, 17°C, 18°C, 19°C, 20°C, or values between these two or above 20°C.
[0069] The advantage of this is that, based on the design of the welded structure, uniform heat transfer can be achieved in the heat distribution area.
[0070] In an exemplary implementation of the semiconductor structure, the upper metal layer or the upper metal sealing element forms a metal-to-metal contact with the turbulent sheet of the turbulent element, and the metal-to-metal contact forms the first weld pattern and / or the second weld pattern.
[0071] The metal-to-metal contact can be a cold shut, such as aluminum to aluminum, or an intermetallic connection.
[0072] The advantage of this is that such metal-to-metal contact allows for highly efficient heat transfer.
[0073] In an exemplary implementation of the semiconductor structure, the turbulence element is clamped, snapped, soldered, or connected to the upper metal layer and / or the lower metal layer.
[0074] The advantage of doing this is that it allows for more flexible design and more efficient heat transfer.
[0075] According to a second aspect, this application relates to a method for manufacturing a semiconductor structure with coolant cooling, the method comprising: providing a power module for power conversion, the power module including a first module side and a second module side opposite to the first module side, wherein a first mold body is disposed between the first module side and the second module side; the first module side including an upper metal layer; a second mold body at least partially encapsulating the power module, wherein a portion of the upper metal layer forming an upper heat dissipation region of the power module is not covered by the second mold body; and in a transition region between the upper heat dissipation region and the second mold body, covering the upper heat dissipation region and the second mold body by an upper metal sealing element to seal the power module and prevent coolant from flowing through the upper heat dissipation region.
[0076] The method can also be used to provide a semiconductor structure with dual-sided cooling. Then, as described above, a lower metal sealing element is included to cover the lower heat dissipation region and the second mold body in the transition region between the lower heat dissipation region and the second mold body to seal the power module and prevent coolant from flowing through the lower heat dissipation region during process steps.
[0077] This method provides a seal that enables optimal sealing reliability for direct liquid cooling modules, whether they are single-sided or double-sided cooling modules.
[0078] In an exemplary implementation of the method, the method includes welding the upper metal sealing element to the upper heat dissipation area via a laser welding or ultrasonic welding process.
[0079] The advantage of doing this is that seals can be easily produced using known production tools.
[0080] In an exemplary implementation of the method, the method includes attaching the upper metal sealing element to the second mold body via a remelting process step of the second mold body.
[0081] The advantage of this is that remelting the second mold body can provide a rough surface structure within the second mold body, which can be efficiently clamped into the rough surface structure of the upper metal sealing element to provide a reliable seal.
[0082] In an exemplary implementation of the method, the method includes: mounting the turbulence element onto the upper metal layer or the upper metal sealing element by means of a laser welding or ultrasonic welding process step, for generating turbulence in the coolant flowing through the upper heat dissipation region.
[0083] By using such a turbulence element, the power module can be cooled efficiently. The turbulence generated by the turbulence element on the cooling medium ensures that all semiconductor chips in the power module have similar junction temperatures and similar cooling conditions. Attached Figure Description
[0084] Other embodiments of this application will be described in conjunction with the following drawings, wherein:
[0085] Figure 1 A schematic 3D view of an exemplary semiconductor structure 100a with a sealing ring according to a first embodiment is shown;
[0086] Figure 2 A schematic 3D view of an exemplary semiconductor structure 100b with a sealing cap according to a second embodiment is shown;
[0087] Figure 3 A schematic cross-section of an exemplary semiconductor structure 100a with a sealing ring according to a first embodiment is shown;
[0088] Figure 4 A schematic cross-sectional view of an exemplary semiconductor structure 100b with a sealing cap according to a second embodiment is shown;
[0089] Figure 5 A top view of a semiconductor structure 100a, 100b having three power modules 110 and mounted turbulence elements is shown as an example.
[0090] Figure 6 Two top views 610 and 620 of the power module 110 are shown, on which irregularly spaced turbulence elements are mounted;
[0091] Figure 7 Two top views of the power module 110 are shown, on which turbulence elements with irregularly spaced thin plates are mounted;
[0092] Figure 8 A schematic diagram of a method 800 for producing a semiconductor structure according to this application is shown. Detailed Implementation
[0093] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification, illustrating specific aspects by way of illustration that may be practiced in this application. It should be understood that other aspects may be utilized, and structural or logical changes may be made without departing from the scope of this application. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of this application is defined by the appended claims.
[0094] It should be understood that the annotations relating to the described method also apply to the device or system corresponding to performing the method, and vice versa. For example, if a specific method step is described, the corresponding device may include units for performing the described method step, even if such units are not explicitly described or shown in the drawings. Furthermore, it should be understood that features of the various exemplary aspects described in this application can be combined with each other unless otherwise explicitly stated.
[0095] The semiconductor structures, devices, and systems described in this application can be implemented in automotive, industrial, or consumer electronics applications, such as for driving loads and converting power. However, the semiconductor structures, devices, and systems described in this application can also be implemented in wireless communication schemes (e.g., communication schemes based on 5G or Wi-Fi), for example, for the Internet of Things (IoT). The described semiconductor structures, devices, and systems may include integrated circuits and / or power semiconductors and can be manufactured according to various technologies. For example, the semiconductor structures, devices, and systems can be used in power and / or logic integrated circuits, analog integrated circuits, mixed-signal integrated circuits, etc.
[0096] This application describes single-side cooling (SSC) and double-side cooling (DSC) packages. The single-side cooling (SSC) package is covered by an insulating mold. Therefore, the heat dissipation path of the package is primarily its bottom (e.g., drain or collector) side cooling plate. The double-side cooling (DSC) package, in addition to the bottom side cooling plate, also has a top (e.g., source or emitter) side cooling plate. These cooling plates help reduce thermal resistance. Because heat is dissipated simultaneously from both the top and bottom surfaces, the double-side cooling package can efficiently utilize the heat sink. The double-side cooling package is designed for efficient cooling to achieve the highest energy levels that such a system can switch to.
[0097] This application describes power modules having semiconductor chips. For example, these power modules may include MOSFET transistors or IGBTs. For example, the power modules may be manufactured based on silicon nitride or gallium nitride semiconductor technology or silicon semiconductor technology.
[0098] This application describes sealing rings and sealing caps. A sealing ring is a sealing element that covers two separate areas or materials that come into contact with each other. The sealing ring produces a sealing effect, sealing the two areas or materials together. The sealing ring only covers the transition area where the two areas or materials come into contact, while the rest of the two areas or materials are not covered. For example, a sealing ring can be formed as a sealing ring or a sealing frame. Examples of sealing rings are as follows... Figure 1 and Figure 3 As shown.
[0099] A sealing cap, similar to a sealing ring, is a sealing element that covers two separate, contacting areas or materials. A sealing cap also produces a sealing effect, sealing the two areas or materials together. However, unlike a sealing ring, a sealing cap not only covers the transition area where the two areas contact each other, but also covers the entire first area or the entire area of the first material, meaning the entire first area or material is covered by the sealing cap. For example, a sealing cap can be formed as a closed rectangle, a closed square, or any other closed geometry. Examples of sealing caps are shown below. Figure 2 and Figure 4 As shown.
[0100] Figure 1 A schematic 3D view of an exemplary semiconductor structure 100a with a sealing ring according to a first embodiment is shown. The semiconductor structure 100a is configured to be cooled by a coolant (e.g., water). Cooling can be performed from one side or both sides.
[0101] like Figure 1 As shown, the semiconductor structure 100a includes one or more power modules 110, a second mold body 120, and an upper metal sealing element 130a. Figure 1 Three such power modules are illustrated in the example. It should be understood that any other number of power modules can be applied to the semiconductor structure 100a.
[0102] Power module 110 can be used for power conversion. Power module 110 includes a first module side 111a and a second module side 111b opposite to the first module side 111a, such as... Figure 1 The zoomed-in view is shown in the bottom right corner.
[0103] The first mold body 113 of the power module 110 is disposed between the first module side 111a and the second module side 111b.
[0104] The first module side 111a includes an upper metal layer 114a, such as Figure 1 The zoomed-in view is shown in the bottom right corner.
[0105] Unlike the first mold body 113, which serves as the mold body for the corresponding power module 110, the second mold body 120 is the mold body for the entire semiconductor structure 100a.
[0106] The second mold body 120 at least partially encapsulates the power module 110, wherein a portion of the upper metal layer 114a forming the upper heat dissipation region 115a of the power module 110 is not covered by the second mold body 120, such as Figure 1 As shown.
[0107] The upper metal sealing element 130a covers the upper heat dissipation area 115a and the second mold body 120 in the transition area 131a between the upper heat dissipation area 115a and the second mold body 120 to seal the power module 110 and prevent coolant from flowing through the upper heat dissipation area 115a. Figure 1 The zoomed-in view in the lower right corner shows the transition region 131a in more detail.
[0108] The upper metal sealing element 130a can form a welded joint with the upper heat dissipation area 115a.
[0109] The upper metal sealing element 130a can form a rough surface connection with the second mold body 120 in the transition area 131a between the upper heat dissipation area 115a and the second mold body 120.
[0110] The second mold body 120 may include remelted mold material in the transition region 131a between the upper heat dissipation region 115a and the second mold body 120. This remelted mold material may have a rough surface or surface structure.
[0111] Semiconductor structure 100a can be used for unilateral cooling and / or bilateral cooling. While the features of semiconductor structure 100a required for unilateral cooling, i.e., features related to upper heat dissipation, have been described in the preceding sections, the following description relates to additional features required for bilateral cooling, particularly additional features related to lower heat dissipation.
[0112] The second module side 111b may include a lower metal layer 114b, such as Figure 1 The zoomed-in view in the lower right corner shows a more detailed view.
[0113] A portion of the lower metal layer 114b of the lower heat dissipation area 115b of the power module 110 is not covered by the second mold body 120.
[0114] The semiconductor structure 100a may further include a lower metal sealing element 130b, which covers the lower heat dissipation region 115b and the second mold body 120 in a transition region 131b between the lower heat dissipation region 115b and the second mold body 120 to seal the power module 110 and prevent coolant from flowing through the lower heat dissipation region 115b. Figure 1The zoomed-in view in the lower right corner shows the transition region 131b in more detail.
[0115] like Figure 1 As shown, the semiconductor structure 100a may include a turbulence element 140 mounted above the upper metal layer 114a and / or below the lower metal layer 114b for generating turbulence in the coolant flowing through the upper heat dissipation region 115a and / or below the lower heat dissipation region 115b.
[0116] exist Figure 1 In the first embodiment shown, the upper metal sealing element 130a forms a sealing ring. For example, the sealing ring can be formed into an annular structure or a frame structure along the transition region 131a between the upper heat dissipation region 115a and the second mold body 120, such as... Figure 1 As shown.
[0117] The turbulence element 140 can be mounted on the upper metal layer 114a without contacting the upper metal sealing element 130a, such as Figure 1 As shown.
[0118] Turbulence element 140 may include multiple turbulence sheets 340a, such as Figure 3 As shown in more detail. These turbulent sheets 340a may be disposed symmetrically or asymmetrically on the upper metal layer 114a and / or the lower metal layer 114b.
[0119] The advantage of turbulent sheets is that they form the largest heat dissipation and turbulent surface.
[0120] In this schematic diagram, three power modules 110 are shown as an example. However, the semiconductor structure 100 may include any number of power modules, such as 1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.
[0121] Figure 2 A schematic 3D view of an exemplary semiconductor structure 100b with a sealing cap according to a second embodiment is shown.
[0122] The construction of semiconductor structure 100b is similar to Figure 1 The semiconductor structure 100a is shown. The only difference is that they use different sealing elements, namely... Figure 2 The sealing cap inside.
[0123] The upper metal sealing element 130a forms a sealing cover, which covers the upper heat dissipation area 115a of the power module 110.
[0124] The sealing cap 130a corresponding to the upper metal sealing element 130a covers the upper heat dissipation area 115a and the second mold body 120 in the transition area 131a between the upper heat dissipation area 115a and the second mold body 120 to seal the power module 110 and prevent coolant from flowing through the upper heat dissipation area 115a. Figure 2 The zoomed-in view in the lower right corner shows the transition region 131a in more detail.
[0125] However, the sealing cover 130a not only covers the transition area 131a, but also the entire upper heat dissipation area 115a, just like a cover covering the area 115a.
[0126] It should be noted that Figure 2 The turbulence element 140 shown is not covered by the sealing cap 130a. The turbulence element 140 can be mounted on the upper metal sealing element 130a.
[0127] The sealing cap 130a can be formed into a closed rectangle with rounded corners, such as... Figure 2 As shown.
[0128] The same structure can be implemented on the lower heat dissipation area 115b, i.e., the sealing cover 130b that covers not only the transition area 131b but also the entire lower heat dissipation area 115b. Another turbulence element 140 can be mounted on the lower metal sealing element 130b, i.e., on the lower sealing cover 130b.
[0129] Figure 3 A schematic cross-sectional view of an exemplary semiconductor structure 100a with a sealing ring according to a first embodiment is shown. The structure of the semiconductor structure 100a is the same as that referenced above. Figure 1 The descriptions are the same. However, Figure 3 A cross-section is shown, in which further details can be seen, particularly regarding the placement of the power module 110, the embedded chip 310, and the turbulence element 140.
[0130] Turbulence element 140 may include multiple turbulence sheets 340a, such as Figure 3 The details are shown below. These turbulent sheets 340a can be disposed symmetrically or asymmetrically on the upper metal layer 114a and / or the lower metal layer 114b.
[0131] Each power module 110 of the semiconductor structure 100a may include a plurality of chips 310 embedded in the power module 110.
[0132] The spacer 313 can be used to equalize the gap between the top substrates 114a, 114c, 114e forming the upper metal layer 114a and the bottom substrates 114b, 114d, 114f forming the lower metal layer 114b.
[0133] The top substrates 114a, 114c, 114e may include an isolation layer 114c (e.g., ceramic) located between the inner conductive layer 114e (e.g., copper) and the outer layer 114a (e.g., copper or aluminum oxide or copper coated with aluminum oxide).
[0134] In the same manner, the bottom substrates 114b, 114d, 114f may include an isolation layer 114d (e.g., ceramic) located between the inner conductive layer 114f (e.g., copper) and the outer layer 114b (e.g., copper or aluminum oxide or copper coated with aluminum oxide).
[0135] Chip 310 and spacer 313 can be placed between bottom substrates 114b, 114d, 114f and top substrates 114a, 114c, 114e. Specifically, chip 310 can be placed between a first interconnect layer 311 placed on the inner conductive layer 114f of the bottom substrate and a second interconnect layer 312 placed on the bottom side of spacer 313. Spacer 313 can be placed between the second interconnect layer 312 and a third interconnect layer 314 placed on the top substrate, particularly under the inner conductive layer 114e of the top substrate.
[0136] from Figure 3 It can be seen that the lead frame 301 can be attached to the bottom substrates 114b, 114d, 114f or to the top substrates 114a, 114c, 114e. Figure 3 (Not shown in the image).
[0137] Each chip 310 can be placed at a pre-specified location relative to the upper metal layer 114a and / or the lower metal layer 114b. For example, the pre-specified location can be pre-specified through package layout.
[0138] One or more turbulence sheets 340a of the turbulence element 140 can be placed at pre-specified locations on the upper metal layer 114a and / or the lower metal layer 114b.
[0139] Each power module 110 of the semiconductor structure can have the same number of chips or a different number of chips. In one example, each power module 110 can have 6 chips or 12 chips. In other examples, power module 110 can have 2 chips, 3 chips, 4 chips, 5 chips, or even only 1 chip. It should be understood that other numbers of chips are also possible, such as 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, and more.
[0140] The turbulence element 140 can be soldered onto the upper metal layer 114a and / or the lower metal layer 114b.
[0141] from Figure 3It can be seen that the turbulence element 140 can form a first weld pattern 350a with the upper metal layer 114a and / or form another first weld pattern 350b with the lower metal layer 114b. The two weld patterns 350a and 350b can be the same or different.
[0142] The first weld pattern 350a and / or another first weld pattern 350b can be aligned with the arrangement of the turbulence sheets 340a, 340b of the turbulence element 140. For example, the first weld patterns 350a, 350b are located at the positions where the upper metal layer 114a and / or the lower metal layer 114b contact the corresponding metal layers 114a, 114b, and are attached to weld points to form a welded connection between the turbulence element 140 and the corresponding metal layers 114a, 114b.
[0143] First solder pattern 350a and another first solder pattern 350b can be aligned with pre-designated locations of multiple chips 310 embedded in the power module 110. This means that the locations where chips are embedded in the semiconductor structure require better cooling than the locations between embedded chips. At these locations where chips are embedded, the fins can be more densely distributed, resulting in more solder joints.
[0144] The first solder pattern 350a and another first solder pattern 350b may include multiple solder joints. The density of these solder joints may be based on the temperature of the multiple chips 310 embedded in the power module 110.
[0145] For example, multiple solder joints can be set up as follows: Figure 6 The multiple bonding lines 601 shown. The distance between any two bonding lines can be based on the temperature of the corresponding chips in the multiple chips 310.
[0146] For example, the temperature of the multiple chips 310 embedded in the power module 110 can be within a temperature range of 5°C, 10°C, or 15°C relative to a reference temperature.
[0147] It should be understood that other temperature ranges may also be applied, such as 1°C, 2°C, 3°C, 4°C, 6°C, 7°C, 8°C, 9°C, 11°C, 12°C, 13°C, 14°C, 16°C, 17°C, 18°C, 19°C, 20°C, or values between these two or above 20°C.
[0148] The upper metal layer 114a can form a metal-to-metal contact with the turbulence sheet 340a of the turbulence element 140. This metal-to-metal contact forms a first weld pattern 350a.
[0149] In the same manner, the lower metal layer 114b can form a metal-to-metal contact with the turbulence sheet 340b of the turbulence element 140. This metal-to-metal contact forms another first weld pattern 350b.
[0150] Metal-to-metal contact can be a cold shut, such as aluminum to aluminum, or an intermetallic connection.
[0151] The turbulence element 140 can be clamped, snapped, welded, or connected to the upper metal layer 114a and / or the lower metal layer 114b.
[0152] Figure 4 A schematic cross-section of an exemplary semiconductor structure 100b with a sealing cap according to a second embodiment is shown.
[0153] The structure of semiconductor structure 100b is the same as the one mentioned above. Figure 3 The description is the same. However, in the second embodiment with a sealing cap, the entire upper metal layer 114a is covered by the upper metal sealing element 130a. Similarly, the entire lower metal layer 114b is covered by the lower metal sealing element 130b.
[0154] In this second embodiment, the turbulence element 140 is welded to the upper metal sealing element 130a, the turbulence element 140 and the upper metal sealing element 130a form a first welding pattern 350a, and the upper metal sealing element 130a and the upper metal layer 114a form a second welding pattern 351a.
[0155] On the bottom side, similar features can be seen, namely, the turbulence element 140 is welded to the lower metal sealing element 130b, the turbulence element 140 and the lower metal sealing element 130b form another first weld pattern 350b, and the lower metal sealing element 130b and the lower metal layer 114b form another second weld pattern 351b.
[0156] The first welding pattern 350a and / or the second welding pattern 351a can be aligned with the arrangement of the turbulence sheet 340a of the turbulence element 140.
[0157] For the bottom side, another first weld pattern 350b and / or another second weld pattern 351b can be aligned with the arrangement of the turbulence sheet 340b of the turbulence element 140.
[0158] The first welding pattern 350a and / or the second welding pattern 351a can be aligned with the pre-specified positions of the plurality of chips 310 embedded in the power module 110.
[0159] For the bottom side, another first welding pattern 350b and / or another second welding pattern 351b can be aligned with pre-specified positions of a plurality of chips 310 embedded in the power module 110.
[0160] The first welding pattern 350a and / or the second welding pattern 351a may include multiple solder joints. The density of these solder joints may be based on the temperature of the multiple chips 310 embedded in the power module 110, for example, as described above. Figure 3 The same relationship applies to another first weld pattern 350b and another second weld pattern 351b.
[0161] The upper metal sealing element 130a can form a metal-to-metal contact with the turbulence sheet 340a of the turbulence element 140. This metal-to-metal contact can form a first weld pattern and / or a second weld pattern.
[0162] On the bottom side, the lower metal sealing element 130b can form a metal-to-metal contact with the turbulence sheet 340b of the turbulence element 140. This metal-to-metal contact can form another first weld pattern and / or another second weld pattern (on the bottom side).
[0163] Metal-to-metal contact can be a cold shut, such as aluminum to aluminum, or an intermetallic connection.
[0164] The turbulence element 140 can be clamped, snapped, welded, or connected to the upper metal sealing element 130a and / or the lower metal sealing element 130b.
[0165] Figure 5 A top view of semiconductor structures 100a and 100b with three power modules 110 and mounted turbulence elements is shown as an example. The turbulence elements may correspond to the combination described above. Figures 1 to 4 The turbulence element 140 is described above. Semiconductor structures 100a and 100b can correspond to the combinations described above. Figures 1 to 4 The semiconductor structure described above.
[0166] exist Figure 5 The image shows the location of chip 310 within power module 110. These locations may have a design-specific distribution. Cooling fins for turbulent liquid flow can be distributed in optimized locations based on chip orientation.
[0167] Figure 6 Two top views 610 and 620 of the power module 110 are shown, on which irregularly spaced turbulence elements are mounted.
[0168] As described above Figure 3 and Figure 4 The multiple solder joints can be arranged in multiple solder lines 601. The distance between any two solder lines can be based on the temperature of the corresponding chips in the multiple chips 310 placed below (or above) the two solder lines 601.
[0169] In the top view 610 on the left, regions 611 and 612 with different weld line densities are shown. For example, unlike the second region 612, the first region 611 may have fewer weld lines 601, i.e., the distribution distance between them is larger.
[0170] In this configuration, the chip temperature of the chip below the first region 611 can be lower than the chip temperature of the chip below the second region 612.
[0171] In the top view 620 on the right, a region 621 with a high solder line density is shown. The chip below this region 621 can be designed to have higher temperatures.
[0172] The temperature of the multiple chips embedded in a power module is typically not uniform. Chips with higher temperatures tend to have more solder joints, while chips with lower temperatures have fewer solder joints.
[0173] The soldering pattern can be adjusted based on the independent thermal characteristics of each chip.
[0174] Unlike chips operating at low temperatures, turbulent structures and soldered structures can be arranged more densely or at higher densities on chips operating at high temperatures.
[0175] In one example, the turbulent structure is uniform, while the welded structure is non-uniform, depending on the chip temperature. In another example, the welded structure is uniform, while the turbulent structure is non-uniform, depending on the chip temperature.
[0176] For example, the temperature of the multiple chips 310 embedded in the power module 110 can be within a temperature range of 5°C, 10°C, or 15°C relative to a reference temperature.
[0177] It should be understood that other temperature ranges may also be applied, such as 1°C, 2°C, 3°C, 4°C, 6°C, 7°C, 8°C, 9°C, 11°C, 12°C, 13°C, 14°C, 16°C, 17°C, 18°C, 19°C, 20°C, or values between these two or above 20°C.
[0178] Figure 7 Two top views of the power module 110 are shown, on which turbulence elements with irregularly spaced slabs are mounted.
[0179] For example, in the top view on the left, a power module 110 is shown, in which the turbulence element 140 includes two portions 710 having different regions with fins 340a and 340b distributed with different densities. In the first region 711, the fin density is lower than in the second region 712 and the third region 713, while in the third region 713, the fin density is the highest.
[0180] Similarly, the top view on the right shows a power module 110 with a turbulence element 140 comprising two sections 710 and 720 having different regions with fins 340a and 340b distributed at different densities. In the first region 711, the fin density is lower than in the second region 712 and the third region 713, while in the third region 713, the fin density is highest. The two sections 710 and 720 may have different numbers of fin rows. For example, section 710 has five rows of fins, while section 720 has four rows of fins.
[0181] Figure 8 A schematic diagram of a method 800 for producing a semiconductor structure with coolant cooling according to this application is shown.
[0182] Method 800 includes: providing 801 a power module 110 for power conversion, the power module 110 including a first module side 111a and a second module side 111b opposite to the first module side 111a, for example, as described above. Figures 1 to 4 The first mold body 113 is disposed between the first module side 111a and the second module side 111b; the first module side 111a includes an upper metal layer 114a.
[0183] Method 800 includes: encapsulating 802 power module 110 at least partially through a second mold body 120, wherein a portion of the upper metal layer 114a forming the upper heat dissipation region 115a of the power module 110 is not covered by the second mold body 120.
[0184] Method 800 includes: covering the upper heat dissipation region 115a and the second mold body 120 in a transition region 131a between the upper heat dissipation region 115a and the second mold body 120 with an upper metal sealing element 130a to seal the power module 110 and prevent coolant from flowing through the upper heat dissipation region 115a, for example, as described above. Figures 1 to 4 As stated above.
[0185] The method can also be used to provide a semiconductor structure with dual-sided cooling. Then, as described above, a process step including a lower metal sealing element 130b covering the lower heat dissipation region 115b and the second mold body 120 in a transition region 131b between the lower heat dissipation region 115b and the second mold body 120 to seal the power module 110 and prevent coolant from flowing through the lower heat dissipation region 115b.
[0186] Method 800 may include welding the upper metal sealing element 130a to the upper heat dissipation area 115a by means of a laser welding or ultrasonic welding process.
[0187] Method 800 may include attaching the upper metal sealing element 130a to the second mold body 120 via a remelting process step of the second mold body 120.
[0188] Method 800 may include mounting the turbulence element 140 onto the upper metal layer 114a or the upper metal sealing element 130a by means of a laser welding or ultrasonic welding process step, for generating turbulence in the coolant flowing through the upper heat dissipation region 115a.
[0189] Although a particular feature or aspect of this application may have been disclosed with respect to only one of several implementations, such features or aspects may be combined as desired and advantageously for any given or particular application with one or more other features or aspects of other implementations. Furthermore, to a certain extent, the terms “comprising,” “having,” “having,” or other variations of these words are used in the detailed description or claims; such terms, like the term “including,” are similar and both imply inclusion. Similarly, the terms “exemplary” and “for example” are used only as examples and not as best or optimal. The terms “coupled” and “connected,” as well as their derivatives, may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, whether they are in direct physical contact or electrical contact, or whether they are not in direct contact with each other.
[0190] While specific aspects have been described and illustrated herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may be used to replace the specific aspects shown and described without departing from the scope of this application. This application is intended to cover any modifications or alterations to the specific aspects discussed herein.
[0191] Although the elements in the following claims are listed in a particular order using corresponding labels, these elements are not necessarily limited to being implemented in said particular order unless the formulation of the claims otherwise implies a particular order for implementing some or all of these elements.
[0192] Based on the above guidance, many alternatives, modifications, and variations will be apparent to those skilled in the art. Of course, those skilled in the art will readily recognize that numerous other applications of this application exist besides those described herein. Although this application has been described with reference to one or more specific embodiments, those skilled in the art will recognize that many changes can be made to this application without departing from its scope. Therefore, it should be understood that this application may be practiced in ways other than those specifically described herein, as long as it remains within the scope of the appended claims and their equivalents.
Claims
1. A semiconductor structure, characterized in that, include: A power module (110) for power conversion, the power module (110) includes a first module side (111a) and a second module side (111b) opposite to the first module side (111a), wherein a first mold body (113) is disposed between the first module side (111a) and the second module side (111b); The first module side (111a) includes an upper metal layer (114a). A second mold body (120) at least partially encapsulates the power module (110), wherein a portion of the upper metal layer (114a) forming the upper heat dissipation region (115a) of the power module (110) is not covered by the second mold body (120); An upper metal sealing element (130a) covers the upper heat dissipation area (115a) and the second mold body (120) in a transition area (131a) between the upper heat dissipation area (115a) and the second mold body (120) to seal the power module (110) and prevent coolant from flowing through the upper heat dissipation area (115a). The upper metal sealing element (130a) forms a sealing ring, and the sealing ring forms an annular structure or a frame structure along the transition area (131a) between the upper heat dissipation area (115a) and the second mold body (120). A turbulence element (140), mounted on the upper metal layer (114a) and not in contact with the upper metal sealing element (130a), is used to generate turbulence in the coolant flowing below the upper heat dissipation area (115a).
2. The semiconductor structure according to claim 1, characterized in that, The upper metal sealing element (130a) and the upper heat dissipation area (115a) form a welded joint.
3. The semiconductor structure according to claim 1 or 2, characterized in that, The upper metal sealing element (130a) forms a rough surface connection with the second mold body (120) in the transition region (131a) between the upper heat dissipation region (115a) and the second mold body (120).
4. The semiconductor structure according to claim 3, characterized in that, The second mold body (120) includes remelted mold material in the transition region (131a) between the upper heat dissipation region (115a) and the second mold body (120), the remelted mold material having a rough surface.
5. The semiconductor structure according to claim 1 or 2, characterized in that, The second module side (111b) includes a lower metal layer (114b); a portion of the lower metal layer (114b) forming the lower heat dissipation area (115b) of the power module (110) is not covered by the second mold body (120); The semiconductor structure also includes: A lower metal sealing element (130b) covers the lower heat dissipation area (115b) and the second mold body (120) in a transition area (131b) between the lower heat dissipation area (115b) and the second mold body (120) to seal the power module (110) and prevent coolant from flowing through the lower heat dissipation area (115b).
6. The semiconductor structure according to claim 5, characterized in that, The turbulence element (140) is mounted above the upper metal layer (114a) and / or below the lower metal layer (114b) to generate turbulence in the coolant flowing through the upper heat dissipation region (115a) and / or below the lower heat dissipation region (115b).
7. The semiconductor structure according to claim 6, characterized in that, The turbulence element (140) includes a plurality of turbulence sheets (340a) disposed symmetrically or asymmetrically on the upper metal layer (114a) and / or the lower metal layer (114b).
8. The semiconductor structure according to claim 7, characterized in that, include: Multiple chips are embedded in the power module (110), wherein each chip is placed at a pre-specified location relative to the upper metal layer (114a) and / or the lower metal layer (114b), the pre-specified location being pre-specified by the package layout; At least one turbulence sheet (340a) of the turbulence element (140) is placed at the pre-designated position of the upper metal layer (114a) and / or the lower metal layer (114b).
9. The semiconductor structure according to claim 8, characterized in that, The turbulence element (140) is welded to the upper metal layer (114a), and the turbulence element (140) and the upper metal layer (114a) form a first welding pattern (350a); or The turbulence element (140) is welded to the upper metal sealing element (130a), the turbulence element (140) and the upper metal sealing element (130a) form a first welding pattern (350a), and the upper metal sealing element (130a) and the upper metal layer (114a) form a second welding pattern (351a).
10. The semiconductor structure according to claim 9, characterized in that, The first welding pattern (350a) and / or the second welding pattern (351a) are aligned with the arrangement of the turbulence sheet (340a) of the turbulence element (140).
11. The semiconductor structure according to claim 9, characterized in that, The first welding pattern (350a) and / or the second welding pattern (351a) are aligned with the pre-designated positions of the plurality of chips (310) embedded in the power module (110).
12. The semiconductor structure according to claim 9, characterized in that, The first welding pattern (350a) and / or the second welding pattern (351a) include a plurality of solder joints, the density of which is based on the temperature of the plurality of chips (310) embedded in the power module (110).
13. The semiconductor structure according to claim 12, characterized in that, The plurality of solder joints are arranged in a plurality of solder lines (601), and the distance between any two solder lines (601) is based on the temperature of the respective chips in the plurality of chips (310) placed below the two solder lines (601).
14. The semiconductor structure according to claim 8, characterized in that, The temperature of the plurality of chips (310) embedded in the power module (110) is within a temperature range of 5°C, 10°C or 15°C relative to a reference temperature.
15. The semiconductor structure according to claim 9, characterized in that, The upper metal layer (114a) or the upper metal sealing element (130a) forms a metal-to-metal contact with the turbulent sheet (340a) of the turbulent element (140), and the metal-to-metal contact forms the first welding pattern and / or the second welding pattern.
16. The semiconductor structure according to claim 6, characterized in that, The turbulence element (140) is clamped, snapped, welded, or connected to the upper metal layer (114a) and / or the lower metal layer (114b).
17. A method for producing a semiconductor structure, characterized in that, The method includes: A power module (110) for power conversion is provided, the power module (110) including a first module side (111a) and a second module side (111b) opposite to the first module side (111a), wherein a first mold body (113) is disposed between the first module side (111a) and the second module side (111b); The first module side (111a) includes an upper metal layer (114a). The power module (110) is encapsulated at least partially by the second mold body (120), wherein a portion of the upper metal layer (114a) forming the upper heat dissipation region (115a) of the power module (110) is not covered by the second mold body (120); In the transition region (131a) between the upper heat dissipation area (115a) and the second mold body (120), the upper heat dissipation area (115a) and the second mold body (120) are covered by an upper metal sealing element (130a) to seal the power module (110) and prevent coolant from flowing through the upper heat dissipation area (115a). The upper metal sealing element (130a) forms a sealing ring, and the sealing ring forms an annular structure or a frame structure along the transition region (131a) between the upper heat dissipation area (115a) and the second mold body (120). The turbulence element (140) is mounted on the upper metal layer (114a) by means of laser welding or ultrasonic welding, wherein the turbulence element (140) does not contact the upper metal sealing element (130a) and is used to generate turbulence in the coolant flowing below the upper heat dissipation area (115a).
18. The method according to claim 17, characterized in that, include: The upper metal sealing element (130a) is welded to the upper heat dissipation area (115a) by laser welding or ultrasonic welding process.
19. The method according to claim 17 or 18, characterized in that, include: The upper metal sealing element (130a) is attached to the second mold body (120) by means of a remelting process of the second mold body (120).