Structure and method for powering metal wire

Abstract

A semiconductor device component includes: a contact pad (12) provided on a surface of a semiconductor substrate (10); a seed metal layer (14) disposed on the contact pad; and an interconnect disposed on the seed metal layer. The seed metal layer has a width greater than a width of the interconnect, wherein a foot portion (14F) of the seed metal layer extends beyond the width of the interconnect. The semiconductor device component also includes an etch resistant protection structure (18) disposed on a surface of the interconnect and a surface of the foot portion of the seed metal layer extending beyond the width of the interconnect.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a continuation of and claims priority to U.S. application serial number 18 / 313,425 filed on May 8, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present description relates generally to semiconductor components and, more particularly, to metallization systems in semiconductor components. Background Art

[0004] The metallization layers (e.g., redistribution layers (RDL)) on an integrated circuit chip include electrical conductors (wires) that connect transistors and other components on the chip. Aluminum and copper are two common metals commonly used for integrated circuit metallization. As circuit dimensions decrease below the 0.25 μm level, copper begins to replace aluminum as the primary metallization medium. Summary of the invention

[0005] In general terms, a semiconductor device component includes: a contact pad disposed on a surface of a semiconductor substrate; a seed metal layer disposed on the contact pad; and an interconnect disposed on the seed metal layer. The seed metal layer has a width greater than a width of the interconnect, wherein a foot portion of the seed metal layer extends beyond the width of the interconnect. The semiconductor device component also includes an etch-resistant protection structure disposed on a surface of the interconnect and on a surface of the foot portion of the seed metal layer extending beyond the width of the interconnect.

[0006] In general terms, a semiconductor device component includes: a contact pad disposed on a semiconductor substrate surface; a metal line made of copper; and a seed metal layer interposed between the contact pad and the metal line. The seed metal layer has a width greater than a width of the metal line, wherein a foot portion of the seed metal layer extends from under the metal line to a side of the metal line. The semiconductor device component also includes an anti-copper etching protection structure disposed on a top and side of the metal line and a top and edge of the foot portion of the seed metal layer.

[0007] In general terms, a method includes: providing a contact pad on a surface of a semiconductor substrate; providing a metal line made of copper on the contact pad; and inserting a seed metal layer between the contact pad and the metal line. The seed metal layer has a width greater than a width of the metal line, wherein a foot portion of the seed metal layer extends from under the metal line to a side of the metal line. The method also includes providing an anti-etching protection structure on the metal line and the foot portion of the seed metal layer extending beyond the width of the metal line.

[0008] The details of one or more implementations are set forth in the accompanying drawings and the description that follows. Other features will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example semiconductor device component in accordance with principles of the present disclosure is shown in cross-sectional view in which a protection structure made of copper etch-resistant metal is formed on a copper interconnect to protect the copper interconnect from corrosion.

[0010] Figure 2A shows the first manufacturing stage Figure 1 semiconductor device components.

[0011] Figure 2B Shown in the second manufacturing stage Figure 1 semiconductor device components.

[0012] Figure 2C Shown is the third manufacturing stage Figure 1 semiconductor device components.

[0013] Figure 2D Shown is a fourth manufacturing stage Figure 1 semiconductor device components.

[0014] Figure 2E Shown is the fifth manufacturing stage Figure 1 semiconductor device components.

[0015] FIG. 2A to FIG. 2J Shows the various stages of manufacturing Figure 1 Semiconductor device components (e.g., Figure 1 semiconductor device components).

[0016] Figure 2H shows the eighth stage of the manufacturing process Figure 1 A semiconductor device component wherein a portion of a seed metal layer (eg, a seed metal layer) on a semiconductor substrate that is not masked by a spacer (or a copper interconnect) is removed.

[0017] Fig.2IFIG. 1 shows a schematic diagram of a silicon substrate at a ninth stage of the manufacturing process after removing portions of a seed metal layer (eg, a seed metal layer) on a silicon substrate that are not masked by spacers (or copper interconnects). Figure 1 semiconductor device components.

[0018] Figure 2J FIG. 1 shows a schematic diagram of a manufacturing process at the tenth stage after forming a foot portion (seed metal layer foot). Figure 1 semiconductor device components.

[0019] Figure 3A and Figure 3B Shows the different stages of manufacturing Figure 1 Additional views of semiconductor device components.

[0020] Figure 4 An example method is shown for fabricating a copper-based metallization layer (eg, a redistribution layer) of a semiconductor device component, which may include a semiconductor device fabricated in a semiconductor substrate.

[0021] Figure 5 Another example method for fabricating a copper-based metallization layer (eg, a redistribution layer) of a semiconductor device component is shown.

[0022] In the drawings that are not necessarily drawn to scale, similar reference symbols and / or alphanumeric identifiers may indicate similar and / or similar parts (elements, structures, etc.) in different views. The drawings illustrate various specific implementations discussed in the present disclosure by way of example and not limitation. Reference symbols and / or alphanumeric identifiers shown in one drawing may not be repeated for the same and / or similar elements in the related views in other drawings. Reference symbols and / or alphanumeric identifiers repeated in multiple figures may not be specifically discussed with respect to each of the figures in these figures, but are provided for the convenience of cross-references between related views. In addition, not all similar elements in the drawings are specifically referenced with reference symbols and / or alphanumeric identifiers when multiple instances of the element are shown. DETAILED DESCRIPTION

[0023] In semiconductor technology, copper interconnects are interconnects (wires, metal wires) made of copper. Copper interconnects can be used, for example, for silicon or other semiconductor integrated circuits (ICs) (semiconductor device components, such as large-scale integrated circuits (LSI) chips) to reduce propagation delays and power consumption. Because copper is a better conductor than aluminum (Al). ICs using copper (Cu) as their interconnects can have interconnects of narrower size and have less resistance to current passing through them. These properties of copper interconnects can produce ICs (semiconductor device components) with better performance. For example, copper interconnects can be used to go to IC chips (e.g., LSI power chips) or power interconnects from IC chips.

[0024] Although silicon is the most common semiconductor element used for power semiconductor devices, and although copper is a popular choice for conductor traces on printed circuit boards (PCBs) and ceramic substrates due to its conductivity, diffusion of copper into surrounding materials may degrade the electrical properties of the surrounding materials (e.g., diffused copper atoms form deep energy level traps in silicon and thus adversely affect the behavior of silicon transistors). Therefore, a barrier metal must be provided between the copper interconnect and the power semiconductor device to chemically isolate the copper conductor from the underlying silicon and to limit the diffusion of copper into the power semiconductor device.

[0025] Because copper cannot be plasma etched, in some example implementations, copper interconnects may be formed by a metal patterning process called additive patterning, which is similar to conventional metal embedding techniques, also known as damascene processes. In this process, the underlying silicon oxide insulating layer is patterned with open trenches or vias where the copper conductors should be. A thick copper coating is deposited on the insulating layer that significantly overfills the trenches and vias, and chemical mechanical planarization (CMP) is used to remove the copper that extends above the top of the insulating layer. Copper recessed within the trenches or vias in the insulating layer is not removed, but becomes a patterned conductor.

[0026] In some other example implementations, copper interconnects may be formed by plating copper on a patterned seed metal layer. Metal deposition in a damascene structure may include three steps: a copper barrier layer, a copper seed metal layer, and a bulk copper layer. For example, the first two layers may be made by sputtering, and the last layer may involve copper electroplating (ECP). The copper barrier layer may be, for example, a tantalum / tantalum-tungsten (Ta / TaW), a titanium / titanium-tungsten (Ti / TiW), or a copper-titanium (Cu / Ti) barrier layer that prevents copper from diffusing into the dielectric. The copper seed metal layer aids in the growth of the electroplated bulk copper film. Copper electroplating fills the vias and trenches with copper. After the copper electroplating is completed, chemical mechanical polishing (CMP) is used to remove excess copper deposited on the field areas of the semiconductor device components.

[0027] As advanced semiconductor device features shrink with each technology node, interconnect structures made of copper become more important due to copper's higher conductivity and resistance to electromigration. New metals are being introduced as barrier materials for advanced technology nodes. These types of materials allow copper to fill the narrowest structures and act as a seed enhancement layer. However, it is difficult to solve the compatibility issue of interconnect metals for copper chemical mechanical polishing (CMP) processes. Metal voids (formed due to electromigration) and copper corrosion (due to etching by chemical reactants such as acids and bases) remain issues that need to be controlled. The wet chemical environment in the CMP process can cause copper corrosion to become one of the main problems for copper interconnects.

[0028] Therefore, it would be advantageous to have a method of protecting copper interconnects on semiconductor device components from corrosion during and after fabrication.

[0029] The disclosure herein describes a method and structure for a metallization system that protects copper interconnects on semiconductor device components from electromigration and corrosion.

[0030] In an example implementation of the method, the seed metal layer and the exposed surfaces of the copper interconnect (formed on the seed metal layer) susceptible to etchant attack are encapsulated in (or coated with) a protective material structure resistant to copper etchants (eg, acid, base).

[0031] In an example implementation, a semiconductor device component (e.g., a power device component) is manufactured on a semiconductor substrate (e.g., a silicon substrate). A contact pad of a terminal (e.g., an input or output) of a semiconductor device in the semiconductor device component may be a conductive pad (e.g., an aluminum layer) formed on a surface of the silicon substrate. A dielectric passivation layer (e.g., silicon dioxide or silicon nitride) is formed on a portion of the aluminum layer and on the silicon substrate. A seed metal layer is disposed on the dielectric passivation layer and a portion of the conductive pad (i.e., the aluminum layer) that is not protected by the dielectric passivation layer. The seed metal layer may be patterned to define an area for forming a copper interconnect.

[0032] A copper interconnect (e.g., a metal line) having a top surface and a side surface is formed on a patterned portion of a seed metal layer using, for example, an electroplating technique. After the copper interconnect is formed, the excess seed metal layer portion (e.g., the seed metal layer portion on the dielectric passivation layer) may be removed, for example, by etching. The surface portion and edge position of the remaining patterned seed metal layer may extend from under the copper interconnect to the side of the copper interconnect and be exposed to the environment. The disadvantage of this method is that when the excess seed metal layer portion (e.g., on a portion of the dielectric passivation layer) is etched away, the seed metal layer portion under the copper interconnect may be overetched or undercut, thereby forming an undercut region under the copper interconnect. Acids, bases, or other contaminants may be trapped in the undercut region, which may cause corrosion of the copper interconnect and degrade the reliability of the semiconductor component.

[0033] In an example implementation, a protective structure made of an etch-resistant material (i.e., a material resistant to copper etchants) is disposed on the exposed top and side surfaces of the copper interconnect and on the exposed side surfaces and edges of the patterned seed metal layer below the copper interconnect. In an example implementation, the protective structure made of a copper etch-resistant metal may be formed as an electroless nickel-gold (Ni / Au) protective structure. The Ni / Au protective structure may include a nickel layer formed on the copper interconnect and a gold layer formed on the nickel layer. In an example implementation, the protective structure extends along the side edges of the copper interconnect and also covers the side edges (i.e., surface portions and edges) of the portion of the seed metal layer that may extend beyond the copper interconnect.

[0034] Figure 1 An example semiconductor device component 100 in accordance with principles of the present disclosure is shown in cross-sectional view in which a protection structure 18 made of an etch-resistant metal is formed on a copper interconnect 15 to protect the copper interconnect from corrosion.

[0035] The protection structure may be made of, for example, an electroless Ni / Au bilayer deposited on the exposed top and side surfaces of the copper interconnects and on the exposed side surfaces and edges of the patterned portions of the seed metal layer on which the copper interconnects are formed.

[0036] like Figure 1 As shown, the semiconductor device component 100 may include a semiconductor device (e.g., a power device) (not shown) formed in a semiconductor substrate (e.g., a silicon substrate 10). An aluminum contact pad 12 is disposed in an oxide layer 11 on a surface S of the silicon substrate 10. The aluminum contact pad 12 may be connected to a terminal of a semiconductor device (not shown) formed in the silicon substrate 10. A passivation material layer 13 (e.g., silicon dioxide or silicon nitride) may be disposed on the oxide layer 12 and the aluminum contact pad 12. A seed metal layer 14 may be disposed on the passivation material layer 13 and the aluminum contact pad 12. In addition, a copper interconnect 15 may be formed on the seed metal layer 14 in contact with the aluminum contact pad 12. The copper interconnect 15 (e.g., a metal line) may, for example, have a rectangular cross-section, wherein a width W (e.g., in the x-direction) and a height H (e.g., in the y-direction) are provided above a top surface 14S of the seed metal layer 14. In an example implementation, the copper interconnect 15 may be a power metal line. An example power metal line may have dimensions of a width W and a height H of several microns each. In an example implementation, the width W may be in the range of 5 μm to 30 μm (eg, 20 μm), and the height H may be in the range of 5 μm to 20 μm (eg, 10 μm).

[0037] During the manufacture of semiconductor device component 100, seed metal layer 14 may be patterned and etched so that the remaining portion of seed metal layer below copper interconnect 15 has a width WS that is the same as or greater than the width W of copper interconnect 15. Figure 1 In the example shown, the remaining portion of the seed metal layer (after etching) has another portion (e.g., seed metal layer foot 14F) extending beyond the width W of the copper interconnect 15. The portion of the seed metal layer 14 extending beyond the width W of the copper interconnect 15 (e.g., seed metal layer foot 14F) may, for example, have a top surface 14S having a width w in the x-direction and an edge 14E (e.g., a vertical edge) having a height h in the y-direction.

[0038] In order to protect the copper in the copper interconnect 15 from corrosion, a protective structure 18 is provided on the top surface and the side surface of the copper interconnect 15. The protective structure 18 also extends further downward along the side of the copper interconnect 15 in the -y direction (e.g., until the passivation layer 13) to encapsulate (or coat) the portion of the seed metal layer 14 extending beyond the width W of the copper interconnect 15 (e.g., the seed metal layer foot 14F). The protective structure 18 may coat all surfaces of the seed metal layer foot 14F, including the edge 14E (having a height h in the -y direction). The protective structure 18 may seal all portions of the seed metal layer foot 14F extending beyond the width W of the copper interconnect 15, and protect the seed metal layer foot 14F from the etchant.

[0039] In an example implementation, the protective structure 18 may include a double layer of nickel (e.g., layer 16) and gold (e.g., layer 17). The double layer of nickel and gold may be formed by electroless deposition of nickel followed by electroless deposition of gold. In some example implementations, the protective structure 18 may include a nickel layer (e.g., layer 16) and a layer (e.g., layer 17) of another chemically inert metal or alloy (e.g., palladium or tin-silver alloy) that is chemically resistant to copper etchants.

[0040] The protection structure 18 can seal the seed metal layer footer 14F and block the side or undercut etching (ie, etching along the x-direction) of the seed metal layer footer 14F by, for example, a wet etchant that may exist outside the seed metal layer footer 14F in a subsequent CMP process.

[0041] FIG. 2A to FIG. 2J Shows the various stages of manufacturing Figure 1 A semiconductor device component (eg, semiconductor device component 100 ) is provided.

[0042] Figure 2A A semiconductor device component 100 is shown in a first manufacturing stage. In this first stage, a conductive contact pad is formed on a top surface S of a semiconductor substrate (e.g., a silicon substrate 10). A conductive contact pad (e.g., an aluminum contact pad 12) may be formed in an oxide layer 11 (e.g., a surface oxide) on the top surface S of the silicon substrate. The conductive pad (e.g., an aluminum contact pad 12) may be connected to a terminal of a semiconductor device (not shown) formed in the silicon substrate 10.

[0043] In addition, a passivation layer (e.g., passivation layer 13) may be provided on the oxide layer 11 (e.g., surface oxide) on the top surface S of the semiconductor substrate. The passivation layer 13 may, for example, include silicon oxide, silicon nitride, or other dielectric materials, etc. The passivation layer 13 may be photolithographically patterned and etched to expose the top surface SS of the conductive contact pad (e.g., aluminum contact pad 12) through the opening in the passivation layer 13.

[0044] Figure 2B The semiconductor device component 100 is shown in a second manufacturing stage. In this second stage, a seed metal layer (e.g., seed metal layer 14) may be disposed on the passivation layer 13 and on the top surface SS of the conductive pad (e.g., aluminum contact pad 12). The seed metal layer (e.g., seed metal layer 14) may include a barrier material (e.g., tantalum (Ta), tantalum-tungsten (TW), titanium (Ti), titanium-tungsten (TiW), etc.) and include a metal seed material layer such as a copper layer. The seed metal layer 14 (including, for example, TiW and copper) may be deposited on the silicon substrate 10, for example, by sputtering. In some example implementations, the seed metal layer 14 may include a layer having about to about The thickness of the Ti or TiW layer and the to about The thickness of the copper layer.

[0045] Figure 2C The semiconductor device component 100 is shown in a third manufacturing stage. In this third stage, a photolithographically patterned resist layer 19 may be provided on a semiconductor substrate (e.g., silicon substrate 10) on top of a seed metal layer (e.g., seed metal layer 14). The photolithographically patterned resist layer 19 may include openings 19O aligned with conductive contact pads (e.g., aluminum contact pads 12) provided on a top surface S of the semiconductor substrate. The openings 19O may correspond to an interconnect layout of a redistribution layer (RDL) of the semiconductor device component 100, the interconnects of which are formed in a further stage of manufacturing.

[0046] Figure 2D The semiconductor device component 100 is shown in a fourth manufacturing stage. In this fourth stage, copper metal may be disposed in the opening 19O in the photolithographically patterned resist layer 19 to form a copper interconnect (e.g., copper interconnect 15) of the semiconductor device component 100. In an example implementation, the copper disposed in the opening 19O may have a thickness or height H (e.g., in the y direction) of about 5 μm to 20 μm (e.g., 10 μm). In an example implementation, the copper disposed in the opening 19O may be electroplated on the seed metal layer 14 in the opening.

[0047] Figure 2EThe semiconductor device component 100 is shown in a fifth manufacturing stage. In this fifth stage, the resist layer (eg, photolithographically patterned resist layer 19) is removed, leaving copper interconnects 15 disposed on a seed metal layer (eg, seed metal layer 14) on the top surface S of the semiconductor substrate.

[0048] Further manufacturing stages may involve masking and etching the seed metal layer (e.g., seed metal layer 14) to remove the seed metal layer from a majority of the top surface S of the silicon substrate 10 on the sides of the copper interconnect 15, while leaving a portion of the seed metal layer that extends beyond the width W of the copper interconnect 15 (e.g., seed metal layer foot 14F) ( Figure 1 ). Such masking and etching of the seed metal layer (eg, seed metal layer 14 ) may involve a photoresist mask or a tetraethoxysilane (TEOS) mask to create spacers adjacent to (or along) the vertical sides of the copper interconnect 15 .

[0049] Figure 2F and Figure 2G An example use of a TEOS spacer (eg, spacer 17S) for patterned removal (etching) of a seed metal layer (eg, seed metal layer 14) on a semiconductor device component 100 is shown. Figure 2F As shown, in the sixth manufacturing stage, a conformal layer of TEOS (e.g., TEOS layer 17) with a thickness t may be deposited on the silicon substrate 10 (e.g., by chemical vapor deposition (CVD)). In an exemplary implementation, the thickness t of the TEOS layer 17 may be, for example, in the range of 2 μm to 7 μm (e.g., 5 μm). The TEOS layer 17 may conformally extend over the top and sides of the copper interconnect 15 and the seed metal layer (e.g., seed metal layer 14) on the silicon substrate 10.

[0050] like Figure 2G As shown, at the seventh manufacturing stage, the conformal TEOS layer 17 may be directionally etched back (e.g., by anisotropic dry etching) through the thickness t (in the negative y direction) to remove the TEOS material disposed on top of the copper interconnect 15 and on top of the seed metal layer 14. The anisotropic dry etching may leave behind the TEOS (or resist material) to form a spacer 17S adjacent to or along the side of the copper interconnect 15.

[0051] In some other example implementations, instead of using a CVD TEOS material, the spacer 17S may be formed of a photoresist material that is spin-coated or spray-coated on the silicon substrate 10 .

[0052] Figure 2HThe semiconductor device component 100 is shown at the eighth stage of the manufacturing process, wherein the portion of the seed metal layer (e.g., seed metal layer 14) on the semiconductor substrate 10 that is not masked by the spacer 17S (or the copper interconnect 15) is removed. The removal of the seed metal layer may include etching all components of the seed metal layer (e.g., copper and a barrier material such as Ti or TiW).

[0053] Fig.2I The semiconductor device component 100 is shown at a ninth stage of the manufacturing process. In this ninth stage, the spacer 17S (TEOS or resist) is removed, leaving a portion of the seed metal layer located below the copper interconnect 15 in place, the portion having a width WS that is wider than the width W of the copper interconnect 15. The portion of the seed metal layer that extends beyond the width W of the copper interconnect 15 may include a foot portion (seed metal layer foot 14F) having a vertical edge 14E and a surface 14S that extends to the side of the copper interconnect 15.

[0054] Figure 2J The semiconductor device component 100 is shown at the tenth stage of the manufacturing process after forming the footer portion (seed metal layer footer 14F). At this stage, a protective structure (e.g., protective structure 18) is disposed on the top and sides of the copper interconnect 15. The protective structure 18 further encapsulates the footer portion of the seed metal layer (seed metal layer footer 14F) extending below the copper interconnect beyond the width of the copper interconnect 15.

[0055] The protective structure 18 may include a copper etch resistant material (e.g., Ni, palladium (Pd), gold, tin-silver (Sn-Ag) alloy, etc.). In an example implementation, the protective structure may include a double layer of nickel (e.g., layer 16) and gold (e.g., layer 17). In an example implementation, the nickel layer (e.g., layer 16) may have a thickness, for example, in the range of 1 μm to 4 μm (e.g., 2 μm). The gold layer (e.g., layer 17) may have a thickness, for example, of 1 μm or less (e.g., 0.25 μm to 0.5 μm).

[0056] The protective structure 18 may surround or encapsulate the seed metal layer foot 14F (including the edge 14E and the surface 14S). The protective structure 18 may seal the edge 14E and the surface 14S of the seed metal layer foot 14F to prevent the etchant (e.g., wet acid etchant) from attacking the seed metal layer foot 14F, and thereby avoid undercutting of the seed metal layer. This blocking of the potential undercutting of the seed metal layer may prevent the etchant from further reaching and corroding the copper interconnect 15.

[0057] In an example implementation, Figure 3AAs shown, at a further stage of the manufacturing process, an epoxy resin layer (e.g., resin 31) may be disposed on the semiconductor device component 100 to encapsulate the redistribution layer components (e.g., copper interconnects 15) formed on the top surface of the silicon substrate 10. In addition, in some example implementations, as Figure 3B As shown, at the next stage of the manufacturing process, the semiconductor device component 100 may be back-grinded to reduce the thickness of the silicon substrate 10 (eg, to a thickness Ts).

[0058] Figure 4 An example method 400 is shown for fabricating a copper-based metallization layer (eg, a redistribution layer) of a semiconductor device component, which may include a semiconductor device fabricated in a semiconductor substrate.

[0059] Method 400 includes forming a contact pad (410) in an opening in a passivation layer disposed on a surface of a semiconductor substrate. The contact pad may be made of a conductive material (e.g., aluminum, copper, aluminum-copper alloy, etc.) and may be connected to a semiconductor device formed in the semiconductor substrate. The contact pad may be exposed through an opening in a passivation layer disposed on the surface of the semiconductor substrate. The passivation layer may be made of silicon oxide, silicon nitride, or other dielectric materials.

[0060] The method 400 also includes disposing a seed metal layer on the surface of the semiconductor substrate to cover the contact pad and the passivation layer (420). The seed metal layer may include copper and a barrier layer material (e.g., Ti, TiW, Ta, TaW, etc.). In some example implementations, disposing the seed metal layer may include sputtering a TiCu or TiWCu film on the surface of the semiconductor substrate.

[0061] The method 400 may also include patterning openings in a resist layer on the surface of the semiconductor substrate (i.e., on the seed metal layer) (430). The patterned resist layer may have a number of openings corresponding to the layout of the interconnects of the copper-based metallization layer. For example, an opening having a width W in the resist layer may be aligned with a contact pad on the surface of the semiconductor substrate.

[0062] The method 400 may also include depositing copper material in the openings in the resist layer (e.g., by electroplating) (440). In an example implementation, the copper may be deposited in the openings aligned with the contact pads on the surface of the semiconductor substrate. The copper deposited in the openings of the resist layer will contact the seed metal layer covering the contact pads and form a copper interconnect of the semiconductor device component. The copper interconnect deposited in the openings may have a height H and a width W.

[0063] The method 400 may also include removing the resist layer (450) and forming a masking spacer (460) along the side of the copper interconnect. In an example implementation, forming the masking spacer along the side of the copper interconnect may include coating the semiconductor substrate (including the top and side of the copper interconnect and the top surface of the seed metal layer) with a conformal layer of masking material. In an example implementation, the masking material may be a CVD TEOS material or a spin-coated or sprayed resist material. Forming the masking spacer along the side of the copper interconnect may also include anisotropic etching back of the conformal layer of masking material to remove the masking material on the top of the copper interconnect and on the top surface of the seed metal layer. The anisotropic etching back may form the masking spacer adjacent to (attached to) the (vertical) side of the copper interconnect.

[0064] The method 400 also includes removing a portion of the seed metal layer located on the surface of the semiconductor substrate semiconductor device (470). Removing the portion of the seed metal layer may involve etching the portion of the seed metal layer that is not masked by the masking spacer (or copper interconnect). The etching may involve an etchant based on the composition of the seed metal layer (e.g., Cu, Ti, TiW, Ta, or TaW, etc.). As a result of etching outside the masking spacer, the remaining (unetched) portion of the seed metal layer (beneath the masking spacer and the copper interconnect) may extend beyond the width W ( Figure 2H and Fig.2I ). The portion of the seed metal layer 14 extending beyond the width W of the copper interconnect 15 (e.g., the seed metal layer foot 14F) may, for example, have a top surface 14S having a width w in the x-direction and an edge 14E (e.g., a vertical edge) having a height h in the y-direction ( Figure 2H and Fig.2I In an exemplary implementation, the width w of the seed metal layer foot portion 14F in the x-direction may be in the range of 0 μm to 10 μm (eg, 5 μm).

[0065] The method 400 also includes removing the masking spacer (480) (made of TEOS or a resist material) and providing a protective structure (490) over the copper interconnect and over the portion of the seed metal layer that extends beyond the width W of the copper interconnect. The protective structure may include a material that is generally resistant to wet etching by an acid or base (e.g., Ni, Au, Pd, Sn-Ag alloy, etc.). In an example implementation, the protective structure may include a Ni layer and an Au layer. The Ni layer and the Au layer may be deposited on all copper-containing surfaces (e.g., the top and side surfaces of the copper interconnect and the top and edges of the portion of the seed metal layer that extends beyond the width W of the copper interconnect) by electroless plating. The protective structure is provided to seal all copper-containing surfaces of the copper interconnect and the seed metal layer to prevent the ingress of etchants.

[0066] In some example implementations, method 400 may further include disposing an epoxy or resin (e.g., polyimide, polybenzoxazole (PBO) polymer, phenolic, etc.) on the semiconductor device component to encapsulate the redistribution layer component (e.g., copper interconnect) formed on the top surface of the silicon substrate ( Figure 3A ). In addition, in some example implementations, method 400 may further include back grinding the semiconductor device component to reduce the thickness of the silicon substrate (eg, to a thickness Ts) ( Figure 3B ).

[0067] Figure 5 Another example method 500 for fabricating a copper-based metallization layer (eg, a redistribution layer) of a semiconductor device component, which may include a semiconductor device fabricated in a semiconductor substrate, is shown.

[0068] The method 500 includes: providing a contact pad (510) on a surface of a semiconductor substrate; providing a metal line (520) made of copper on the contact pad; and inserting a seed metal layer (530) between the contact pad and the metal line. The seed metal layer has a width greater than a width of the metal line, wherein a foot portion of the seed metal layer extends from under the metal line to a side of the metal line.

[0069] The method 500 also includes providing an etch-resistant protection structure over the metal line and the foot portion of the seed metal layer extending beyond a width of the metal line ( 540 ).

[0070] In method 500, inserting a seed metal layer between a contact pad and a metal line includes: setting a precursor seed metal layer on the surface of a semiconductor substrate, including above the contact pad; setting a metal line made of copper on the precursor seed metal layer above the contact pad; forming a masking spacer along a side of the metal line to mask a portion of the precursor seed metal layer set on the surface of the semiconductor substrate; and etching an unmasked portion of the precursor seed metal layer to form a seed metal layer inserted between the contact pad and the metal line, wherein a foot portion of the seed metal layer extends from under the metal line to the side of the metal line.

[0071] Item 1. A semiconductor device component, comprising: a contact pad, which is disposed on a surface of a semiconductor substrate; a seed metal layer, which is disposed on the contact pad; an interconnect, which is disposed on the seed metal layer, the seed metal layer having a width greater than a width of the interconnect, wherein a foot portion of the seed metal layer extends beyond the width of the interconnect; and an anti-etching protection structure, which is disposed on the surface of the interconnect and on the surface of the foot portion of the seed metal layer extending beyond the width of the interconnect.

[0072] Clause 2. A semiconductor device component as recited in any of the clauses herein, wherein the interconnect is made of copper and the contact pad comprises aluminum or an aluminum-copper alloy.

[0073] Clause 3. A semiconductor device component according to any of the clauses herein, wherein the seed metal layer comprises a barrier metal layer made of at least one of titanium (Ti), titanium-tungsten (TiW), tantalum (Ta), and tantalum-tungsten (TaW).

[0074] Clause 4. A semiconductor device component as recited in any of the clauses herein, wherein the seed metal layer comprises a copper layer.

[0075] Clause 5. A semiconductor device component according to any one of the clauses herein, wherein the seed metal layer comprises a to about The thickness of the Ti or TiW layer and the to about The thickness of the copper layer.

[0076] Clause 6. The semiconductor device component of any of the clauses herein, wherein the interconnect comprises a copper material electroplated on the seed metal layer.

[0077] Clause 7. The semiconductor device component of any of the clauses herein, wherein the seed metal layer comprises a material sputtered onto the contact pad.

[0078] Clause 8. A semiconductor device component according to any of the clauses herein, wherein the etch-resistant protection structure disposed on a surface of the interconnect and a surface of the foot portion of the seed metal layer extending beyond the width of the interconnect comprises a material resistant to copper etchants.

[0079] Item 9. A semiconductor device component according to any of the items described herein, wherein the etch-resistant protection structure disposed on the surface of the interconnect and on the surface of the foot portion of the seed metal layer extending beyond the width of the interconnect comprises at least one of nickel, palladium, gold and a tin-silver alloy.

[0080] Clause 10. A semiconductor device component according to any of the clauses herein, wherein the etch-resistant protection structure disposed on a surface of the interconnect and a surface of the foot portion of the seed metal layer extending beyond the width of the interconnect comprises a nickel layer and a gold layer.

[0081] Clause 11. A semiconductor device component according to any of the clauses of the present invention, wherein the anti-etching protection structure disposed on the surface of the interconnect and on the surface of the foot portion of the seed metal layer extending beyond the width of the interconnect seals the edge and surface of the foot portion of the seed metal layer extending beyond the width of the interconnect.

[0082] Item 12. A semiconductor device component, comprising: a contact pad disposed on a surface of a semiconductor substrate; a metal line made of copper; a seed metal layer interposed between the contact pad and the metal line, the seed metal layer having a width greater than a width of the metal line, wherein a foot portion of the seed metal layer extends from under the metal line to a side of the metal line; and an anti-copper etching protection structure disposed on the top and side of the metal line and the top and edge of the foot portion of the seed metal layer.

[0083] Clause 13. A semiconductor device component as recited in any of the clauses herein, wherein the seed metal layer comprises copper and at least one of tantalum (Ta), tantalum-tungsten (TW), titanium (Ti), titanium-tungsten (TiW).

[0084] Clause 14. The semiconductor device component of any of the clauses herein, wherein the anti-copper etch protection structure comprises at least one of nickel, gold, palladium, and a tin-silver alloy.

[0085] Item 15. A method, comprising: setting a contact pad on a surface of a semiconductor substrate; setting a metal line made of copper on the contact pad; inserting a seed metal layer between the contact pad and the metal line, the seed metal layer having a width greater than a width of the metal line, wherein a foot portion of the seed metal layer extends from under the metal line to a side of the metal line; and setting an anti-etching protection structure over the metal line and the foot portion of the seed metal layer extending beyond the width of the metal line.

[0086] Clause 16. A method according to any one of the clauses of the present invention, wherein inserting the seed metal layer between the contact pad and the metal line includes: setting a precursor seed metal layer on the surface of the semiconductor substrate, including above the contact pad; setting the metal line made of copper on the precursor seed metal layer above the contact pad; forming masking spacers along the sides of the metal line to mask the portion of the precursor seed metal layer set on the surface of the semiconductor substrate; and etching the unmasked portion of the precursor seed metal layer to form the seed metal layer inserted between the contact pad and the metal line, wherein the foot portion of the seed metal layer extends from under the metal line to the side of the metal line.

[0087] Clause 17. The method of any of the clauses herein, wherein a width W of the metal line is in a range of 5 μm to 30 μm, and a height H of the metal line is in a range of 5 μm to 20 μm.

[0088] Clause 18. The method of any of the clauses herein, wherein providing an etch resistant protection structure comprises providing a nickel layer and a layer of one of gold, palladium, or a tin-silver alloy over the metal line and the foot portion of the seed metal layer.

[0089] Clause 19. A method according to any of the clauses herein, wherein providing the nickel layer and the layer of one of the gold, palladium or tin-silver alloy comprises electroless deposition of the nickel layer and electroless deposition of a layer of one of the gold, palladium or tin-silver alloy.

[0090] Clause 20. A method according to any of the clauses herein, wherein the seed metal layer comprises copper and at least one of tantalum (Ta), tantalum-tungsten (TW), titanium (Ti), titanium-tungsten (TiW) sputter-deposited on the semiconductor substrate.

[0091] Clause 21. A method according to any one of the clauses herein, wherein the seed metal layer comprises to The thickness of the Ti or TiW layer is within the range of to A copper layer with a thickness within the range of. As used in this specification and claims, the singular may include the plural unless the context clearly indicates a specific situation. In addition to the orientation shown in the drawings, spatial relative terms (e.g., on..., above..., above..., below..., below..., below..., below..., etc.) are intended to cover different orientations of the device in use or operation. In some specific implementations, the relative terms above... and below... may include vertically above... and vertically below..., respectively. In some specific implementations, the term adjacent may include lateral adjacent or horizontal adjacent.

[0092] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0093] Although certain features of the described implementations have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the implementations. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described.

Claims

1. A semiconductor device component, comprising: A contact pad (12), the contact pad being arranged on a surface of the semiconductor substrate (10); A seed metal layer (14), the seed metal layer being disposed on the contact pad; an interconnect (15) disposed on the seed metal layer, the seed metal layer having a width greater than a width of the interconnect, wherein a foot portion (14F) of the seed metal layer extends beyond the width of the interconnect; and An anti-etching protection structure (18) is provided on a surface of the interconnection and on a surface of the foot portion of the seed metal layer extending beyond the width of the interconnection. 2 . The semiconductor device component of claim 1 , wherein the interconnect is made of copper, and the contact pad comprises aluminum or an aluminum-copper alloy. 3 . The semiconductor device component according to claim 1 , wherein the seed metal layer comprises a barrier metal layer made of at least one of titanium Ti, titanium-tungsten TiW, tantalum Ta, and tantalum-tungsten TaW. The semiconductor device component of claim 3 , wherein the seed metal layer comprises a copper layer.

5. The semiconductor device component according to claim 4, wherein the seed metal layer comprises a to about The thickness of the Ti or TiW layer and the to about The thickness of the copper layer. 6 . The semiconductor device component of claim 1 , wherein the interconnect comprises a copper material electroplated on the seed metal layer. 7 . The semiconductor device component of claim 1 , wherein the seed metal layer comprises a material sputtered on the contact pad. 8 . The semiconductor device component of claim 1 , wherein the etch-resistant protection structure disposed on a surface of the interconnect and a surface of the foot portion of the seed metal layer extending beyond the width of the interconnect comprises a material resistant to copper etchants.

9. The semiconductor device component according to claim 1, wherein the etch-resistant protection structure disposed on the surface of the interconnect and the surface of the foot portion of the seed metal layer extending beyond the width of the interconnect comprises at least one of nickel, palladium, gold and tin-silver alloy. 10 . The semiconductor device component according to claim 1 , wherein the anti-etching protection structure provided on a surface of the interconnection and a surface of the foot portion of the seed metal layer extending beyond the width of the interconnection comprises a nickel layer and a gold layer.

11. A semiconductor device component according to claim 1, wherein the anti-etching protection structure arranged on the surface of the interconnection and the surface of the foot portion of the seed metal layer extending beyond the width of the interconnection seals the edge and surface of the foot portion of the seed metal layer extending beyond the width of the interconnection.

12. A semiconductor device component, comprising: A contact pad (12), the contact pad being arranged on a surface of the semiconductor substrate (10); A metal wire (15), wherein the metal wire is made of copper; a seed metal layer (14) interposed between the contact pad and the metal line, the seed metal layer having a width greater than a width of the metal line, wherein a foot portion (14F) of the seed metal layer extends from under the metal line to a side of the metal line; and A copper etch-resistant protection structure (18) is provided on the top and the side of the metal line and the top and the edge of the foot portion of the seed metal layer. 13 . The semiconductor device component according to claim 12 , wherein the seed metal layer comprises copper and at least one of tantalum Ta, tantalum-tungsten TW, titanium Ti, and titanium-tungsten TiW.

14. The semiconductor device component of claim 12, wherein the anti-copper etching protection structure comprises at least one of nickel, gold, palladium, and tin-silver alloy.

15. A method comprising: Providing a contact pad (12) on the surface of the semiconductor substrate (10); Arranging a metal wire (15) made of copper on the contact pad; interposing a seed metal layer (14) between the contact pad and the metal line, the seed metal layer having a width greater than a width of the metal line, wherein a foot portion (14F) of the seed metal layer extends from under the metal line to a side of the metal line; as well as An anti-etching protection structure (18) is disposed over the metal line and the foot portion of the seed metal layer extending beyond the width of the metal line.

16. The method according to claim 15, wherein inserting the seed metal layer between the contact pad and the metal line comprises: disposing a precursor seed metal layer on the surface of the semiconductor substrate, including above the contact pad; disposing the metal line made of copper on the precursor seed metal layer above the contact pad; forming a masking spacer along a side of the metal line to mask a portion of the precursor seed metal layer disposed on the surface of the semiconductor substrate; as well as An unmasked portion of the precursor seed metal layer is etched to form the seed metal layer interposed between the contact pad and the metal line, wherein the foot portion of the seed metal layer extends from under the metal line to the side of the metal line. 17 . The method according to claim 15 , wherein a width W of the metal line is in a range of 5 μm to 30 μm, and a height H of the metal line is in a range of 5 μm to 20 μm.

18. The method of claim 15, wherein providing an etch-resistant protection structure comprises providing a nickel layer and a layer of one of gold, palladium, or tin-silver alloy over the metal line and the foot portion of the seed metal layer.

19. The method of claim 18, wherein providing the nickel layer and the layer of one of gold, palladium, or tin-silver alloy comprises electroless deposition of the nickel layer and electroless deposition of the layer of one of gold, palladium, or tin-silver alloy. 20 . The method of claim 15 , wherein the seed metal layer comprises copper and at least one of tantalum Ta, tantalum-tungsten TW, titanium Ti, and titanium-tungsten TiW sputter-deposited on the semiconductor substrate.

21. The method according to claim 15, wherein the seed metal layer comprises to The thickness of the Ti or TiW layer is within the range of to The thickness of the copper layer is within the range.

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