Semiconductor pressure sensor

Abstract

A semiconductor pressure sensor for measuring an external pressure applied on the sensor, the semiconductor pressure sensor comprising: a film as part of a semiconductor substrate for deformation due to the external pressure; a first set of adjacent resistors including a sense resistor pair and a compensation resistor pair; and a second set of adjacent resistors including a sense resistor pair and a compensation resistor pair, where the sense resistor pair is located on or adjacent to the film edge, and where the compensation resistor pair is located at least partially outside of the film or on a zero stress region of the film, and where the resistors in each resistor pair are orthogonal, and wherein the resistors are connected in a Wheatstone bridge configuration.

Description

Technical Field

[0001] The present invention relates to the field of pressure sensors. More specifically, the present invention relates to a pressure sensor comprising a piezoresistor mounted on a membrane. Background Art

[0002] In general, pressure sensors provide an output signal with the aid of piezoresistors, which are configured together in a certain configuration, usually as a Wheatstone bridge. The piezoresistors are placed on the edges of the membrane in the lateral and longitudinal directions relative to the membrane stress, which is proportional to the applied pressure. When a pressure difference is applied to the membrane, the membrane will bend and a stress will be generated on the edges of the membrane. This stress will change the resistance of the piezoresistors, and therefore the output voltage will change depending on the stress. In summary: the pressure difference between the top and bottom sides of the membrane will produce an output voltage on the Wheatstone bridge, which output voltage is indicative of the applied pressure difference.

[0003] Problems arise when the piezoresistors change due to sources other than the pressure differential, such as external stress or temperature gradients. Changes in the piezoresistors due to sources other than the pressure differential can affect the sensor output and give undesired signals.

[0004] When the piezoresistors are placed in a Wheatstone bridge configuration, they are robust to sources that affect certain combinations of the piezoresistors. When the differential output of the Wheatstone bridge does not change, there are no undesired signals (ignoring some minor effects like self-heating of the piezoresistors and common-mode voltage effects on the amplifier).

[0005] FIG. 1 shows a prior art layout of piezoresistors R1 , R2 , R3 and R4 on a membrane. Figure 2 An electronic circuit is shown in which piezoresistors R1, R2, R3 and R4 are arranged in a Wheatstone bridge topology. Supply voltage V 电桥 (V bridge ) is applied to the node between R1 and R3, and ground is connected to the node between R2 and R4. The output voltage is the node between R1 and R2 (voltage V inm ) and the node between R3 and R4 (V inp ) are measured between

[0006] A first example showing the robustness of the Wheatstone bridge is when all resistors R1, R2, R3, R4 are changed by the same percentage. In this case, the output V inm and V inp This example shows how common mode effects such as temperature on a piezoresistor can be compensated.

[0007] The second example is when all resistors in one branch of a Wheatstone bridge are changed by the same percentage. In this case, the output V inm and V inp However, this is less than ideal, since the currents through the different branches of the Wheatstone bridge are different, which may be the cause of some imbalance (e.g., different self-heating of the resistors may give them different sensitivities).

[0008] A third example is when 2 piezoresistors connected to the same supply voltage change by the same percentage. This will change the single-ended output in exactly the same way, leaving the differential output unchanged. However, this is also not ideal, as the common mode output does change and can have an effect on the amplifier's amplification.

[0009] In a fourth example, there are two pairs of piezoresistors. Each pair changes by the same percentage, but the pairs change by different percentages. The piezoresistors (R1, R3) can change by the same first percentage, and the piezoresistors (R2, R4) can change by the same second percentage. In another case, the piezoresistors (R1, R2) can change by the same first percentage, and (R3, R4) can change by the same second percentage. The differential output does not change, and thus the Wheatstone bridge configuration is also robust to such changes, such as stress or temperature gradients on the membrane with the Wheatstone bridge.

[0010] When the resistance of the piezoresistors changes due to a different source than the stress that changes the differential output of the Wheatstone bridge, an undesired signal is generated. For example, it is possible that the stress source produces an irregular stress gradient on the chip as indicated by the arrow in Figure 1. The arrow represents the stress gradient. For example, the stress source can be presented at the beginning of the arrow, so that a high stress is obtained at the beginning of the arrow and a low stress is obtained at the end of the arrow. For example, this may be due to packaging stress or due to metal stress on one side of the die. Therefore, the piezoresistors will not be subjected to the same stress, and the output signal will have an error. In this example, the piezoresistors R2 are subjected to much greater stress from the stress source than the other 3 resistors, and this will change the output of the Wheatstone bridge.

[0011] Another external influence could be a temperature gradient or a local hot spot that heats up one resistor in the bridge more than the others. This can also produce an erroneous Wheatstone bridge output signal.

[0012] Basically, a symmetric Wheatstone bridge configuration laid over a particular region or area of ​​the membrane compensates for linear stress gradients and linear temperature gradients over that area, but does not compensate for non-linear stress or temperature gradients.

[0013] Conventional piezoresistance strain sensors are only able to partially compensate for external stress or temperature influences. Conventional piezoresistance strain sensors typically do not compensate for stress or temperature when the gradient is non-linear or when the stress or temperature changes are very local.

[0014] Therefore, there is a need for a semiconductor pressure sensor that can compensate for irregularly changing disturbances. Summary of the invention

[0015] An object of embodiments of the present invention is to provide a good semiconductor pressure sensor.

[0016] The above objects are achieved by the method and device according to the present invention.

[0017] Embodiments of the present invention relate to a semiconductor pressure sensor for measuring an external pressure applied to the sensor.

[0018] The semiconductor pressure sensor includes a membrane as part of a semiconductor substrate for being deformed due to external pressure.

[0019] In addition, the semiconductor pressure sensor includes: a first group of adjacent resistors and a second group of adjacent resistors, the first group of adjacent resistors includes a sensing resistor pair (a first resistor pair R1a, R2a) and a compensation resistor pair (a third resistor pair R1b, R2b), and the second group of adjacent resistors includes a sensing resistor pair (a second resistor pair R3a, R4a) and a compensation resistor pair (a fourth resistor pair R3b, R4b).

[0020] The sensing resistor pair is located on or adjacent to the membrane edge and the compensation resistor pair is located at least partially outside the membrane or on a zero stress region of the membrane, and the resistors in each resistor pair are orthogonal and connected in a Wheatstone bridge configuration.

[0021] In a Wheatstone bridge configuration, a first resistor (R1a) of the first resistor pair and a first resistor (R1b) of the third resistor pair are connected in series at a first bias node (V 电桥 ) and the first output node (V inm ); the second resistor (R2a) in the first resistor pair and the second resistor (R2b) in the third resistor pair are connected in series at the first output node (V inm ) and the second bias node (GND); the first resistor (R3a) in the second resistor pair and the first resistor (R3b) in the fourth resistor pair are connected in series at the first bias node (V 电桥 ) and the second output node (V inp ); the second resistor (R4a) in the second resistor pair and the second resistor (R4b) in the fourth resistor pair are connected in series at the second output node (Vinp ) and the second bias node (GND).

[0022] In an embodiment of the present invention, the first resistor (R1a) in the first resistor pair and the first resistor (R1b) in the third resistor pair are orthogonal, and the first resistor (R3a) in the second resistor pair and the first resistor (R3b) in the fourth resistor pair are orthogonal, and the second resistor (R2a) in the first resistor pair and the second resistor (R2b) in the third resistor pair are orthogonal, and the second resistor (R4a) in the second resistor pair and the second resistor (R4b) in the fourth resistor pair are orthogonal.

[0023] In an embodiment of the invention, the membrane has a square or rectangular shape.

[0024] In an embodiment of the invention, a first group of adjacent resistors is arranged at a first side of the membrane and a second group of adjacent resistors is arranged at a second side of the membrane.

[0025] In an embodiment of the present invention, the first side is adjacent to the second side.

[0026] In an embodiment of the present invention, the first side is opposite to the second side.

[0027] In an embodiment of the invention, the membrane has a circular or oval shape.

[0028] In an embodiment of the present invention, the first group and the second group have an angular interval of 90°.

[0029] In an embodiment of the invention, the voltage difference between the first output node and the second output node is used as a measure of the pressure on the membrane.

[0030] Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not just as explicitly set out in the claims.

[0031] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 shows a prior art layout of a piezoresistors on a membrane.

[0033] Figure 2 An electronic circuit is shown in which the piezoresistors of FIG. 1 are arranged in a Wheatstone bridge topology.

[0034] Figure 3 A layout of piezoresistors of a semiconductor pressure sensor comprising two sets of adjacent piezoresistors on a square membrane is shown.

[0035] Figure 4 A layout of piezoresistors of a semiconductor pressure sensor comprising two sets of adjacent piezoresistors on a circular membrane is shown.

[0036] Figure 5 A layout of piezoresistors of a semiconductor pressure sensor comprising two sets of adjacent piezoresistors on a square membrane is shown, wherein the compensation resistors are positioned in the zero stress region of the membrane.

[0037] Figure 6 A possible Wheatstone bridge configuration of piezoresistors arranged in a layout according to an embodiment of the invention is shown.

[0038] Figure 7 The influence of stress gradient and the influence of load stress concentration on the semiconductor pressure sensor according to the embodiment of the present invention are shown.

[0039] Any reference signs in the claims should not be construed as limiting the scope.

[0040] The same reference numbers in different drawings refer to the same or similar elements. DETAILED DESCRIPTION

[0041] The present invention will be described with respect to specific embodiments and with reference to certain drawings, but the invention is not limited thereto but only by the claims. The drawings described are only schematic and non-limiting. In the drawings, for illustrative purposes, the size of some of the elements may be exaggerated and not drawn to scale. The dimensions and relative dimensions do not correspond to actual reductions in the practice of the invention.

[0042] The terms first, second, etc. in the specification and in the claims are used to distinguish between similar elements and not necessarily to describe a sequence in time, space, level, or in any other manner. It should be understood that the terms so used are interchangeable under appropriate circumstances, and that the embodiments of the invention described herein are capable of operation in a sequence different from that described or illustrated herein.

[0043] Furthermore, the terms top, bottom, etc. in the description and claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in orientations other than those described or illustrated herein.

[0044] It should be noted that the term "comprising" used in the claims should not be interpreted as being limited to the means listed thereafter; it does not exclude other elements or steps. Thus, the term should be interpreted as specifying the presence of the stated features, integers, steps or components as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that for the present invention, the only relevant components of the device are A and B.

[0045] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment, but may. Furthermore, in one or more embodiments, as would be apparent to one of ordinary skill in the art from this disclosure, the particular features, structures, or characteristics may be combined in any suitable manner.

[0046] Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than those expressly recited in each claim. On the contrary, as reflected in the appended claims, the inventive aspects lie in fewer features than all of the features of a single preceding disclosed embodiment. Thus, the claims appended to the Detailed Description are hereby expressly incorporated into the Detailed Description, with each claim itself representing a separate embodiment of the invention.

[0047] In addition, although some embodiments described herein include some features included in other embodiments but do not include other features included in these other embodiments, the combination of features of different embodiments is intended to fall within the scope of the present invention and form different embodiments as will be understood by those skilled in the art. For example, in the appended claims, any of the embodiments claimed for protection may be used in any combination.

[0048] In the description provided herein, numerous specific details are set forth. However, it should be understood that embodiments of the present invention may be implemented without these specific details. In other examples, well-known methods, structures, and techniques are not shown in detail to avoid confusion in understanding this description.

[0049] When referring to a zero stress region of the membrane in the embodiments of the present invention, what is referred to is a region where the stress does not change significantly with the pressure difference between the top and bottom sides of the membrane. Compared with the piezoresistors at the sides of the membrane, the piezoresistors at least partially positioned in the zero stress region are insensitive or less sensitive to the pressure difference.

[0050] In an embodiment of the present invention, the piezoresistors form groups of adjacent piezoresistors. Adjacent piezoresistors may, for example, be present in a portion between two lines passing through the center of the membrane and having a 90° angle between them. In such embodiments, adjacent piezoresistors are present in a quarter of the membrane. In some embodiments, the angle may be less than 90°, or even less than 80°, or even less than 70°, or even less than 60°, or even less than 50°, or even less than 40°, or even less than 30°.

[0051] The semiconductor pressure sensor 100 according to the embodiment of the present invention is provided in a substrate 105 .

[0052] The semiconductor pressure sensor 100 comprises a membrane 110. In an embodiment of the invention, the membrane 110 is obtained by making a cavity in a substrate. The membrane 110 is supported by a rim 120 at the edge of the membrane 110. The substrate may be, for example, a silicon substrate.

[0053] The semiconductor pressure sensor 100 according to an embodiment of the present invention includes a plurality of groups of adjacent resistors. Each group includes two resistor pairs. A resistor pair is positioned so that it is sensitive to the pressure applied to the sensor, and an adjacent resistor pair is positioned so that it is significantly less sensitive to the applied pressure. This is achieved by positioning the significantly less sensitive resistor at least partially outside the membrane or at least partially on the zero stress zone of the membrane, and positioning the piezoresistors at least partially on the membrane. In an embodiment of the present invention, these groups are positioned on separate areas. In each area, the piezoresistors are oriented to be sensitive to stress caused by pressure. In an embodiment of the present invention, the piezoresistors are oriented so that the stress in the direction of the piezoresistors is higher than the stress in other directions. The direction of the piezoresistors may be different for different groups.

[0054] In an embodiment of the present invention, the resistors in the resistor pairs are piezoresistors. If the sensor comprises a membrane with different sides and an angle between the sides, the resistors can be located on different membrane sides. If the sensor comprises a membrane with a continuous membrane edge (no angle), each group of adjacent piezoresistors can be separated by a distance that is greater than the distance between the piezoresistors within the group. These groups may exist on adjacent sides of the membrane, but this is not strictly required. For example, they may also exist on opposite sides of the membrane. They may also exist on the same side of the membrane. Figure 3 The figure shows an exemplary embodiment of the present invention, in which there are two groups of adjacent piezoresistors. The figure shows a schematic diagram of a pressure sensor. In this example, the membrane is square, and a first group of piezoresistors (R1a, R2a, R1b, R2b) is present on a first side of the membrane, and a second group of piezoresistors (R3a, R4a, R3b, R4b) is present on a second side of the membrane adjacent to the first side. Other membrane shapes (such as rectangular, circular or elliptical) are also possible. However, the present invention is not limited thereto.

[0055] An example of a semiconductor pressure sensor including a circular membrane according to an embodiment of the present invention is represented by Figure 4 In the case of a circular or elliptical membrane, the groups (first group: R1a, R2a, R1b, R2b; second group: R3a, R4a, R3b, R4b) can have an angular spacing of 90° on the circle or ellipse, for example. Figure 4 This is illustrated for a circular membrane in . It shows a first group of piezoresistors R1a and R2a and a first group of resistors R1b and R2b, which are outside the membrane and are therefore insensitive to the pressure on the membrane. The second group includes piezoresistors R3a and R4a and pressure-insensitive resistors R3b and R4b. In this example, the angular separation between the two groups is 90°. This is the angle between a first line passing through the center of the circle and the center of the first group and a second line passing through the center of the circle and the center of the second group.

[0056] Thus, in an embodiment of the present invention, the first group of adjacent piezoresistors includes a first resistor pair R1a, R2a and a third resistor pair R1b, R2b, and the second group of adjacent piezoresistors includes a second resistor pair R3a, R4a and a fourth resistor pair R3b, R4b. The first group of adjacent piezoresistors and the second group of adjacent piezoresistors are located in different stress regions.

[0057] The first resistor pair R1a, R2a is located on or adjacent to the edge of the membrane, at a location on the membrane where stress is caused by a pressure difference over the membrane, and the second resistor pair R3a, R4a is separated from the first resistor pair and is located on or adjacent to the edge of the membrane, at a location on the membrane where stress is caused by a pressure difference over the membrane. The first resistor pair and the second resistor pair are sensing resistors. The first resistor pair and the second resistor pair are therefore sensitive to stress caused by pressure on the membrane.

[0058] The third resistor pair and the fourth resistor pair are placed at positions where the stress caused by the voltage difference is low or negligible compared to the stress caused at the positions of the first resistor pair and the third resistor pair. Therefore, the third resistor pair R1b, R2b and the fourth resistor pair R3b, R4b can be at least partially located outside the membrane or at least partially located on the zero stress area of ​​the membrane. The third resistor pair and the fourth resistor pair are compensation resistors.

[0059] The third resistor pair and the fourth resistor pair can, for example, be positioned so that the piezoresistors of these pairs are 50% less sensitive to applied pressure, or even 70% less, or even 90% less, or even 95% less, than the piezoresistors of the first resistor pair and the second resistor pair near the edge of the membrane.

[0060] The piezoresistors of the first resistor pair R1a, R2a and the second resistor pair R3a, R4a of the piezoresistors may be located substantially on the membrane. For example, at least 50%, or even at least 60%, or even at least 70%, or even at least 80%, 90% of the surface area of ​​the piezoresistors may be located on the membrane. Part of it may be located on the edge of the membrane, since this edge may be subject to relatively high stress when a pressure difference is applied to the membrane.

[0061] In an embodiment of the present invention, when the piezoresistors in the third resistor pair and the fourth resistor pair are substantially positioned outside the membrane, for example, at least 90% of the surface area of ​​the piezoresistors may be located outside the membrane. In an embodiment of the present invention, when the piezoresistors in the third resistor pair and the fourth resistor pair are outside the edge of the membrane, they may be located near the edge of the membrane so as to better match the piezoresistors in the first resistor pair and the second resistor pair, respectively, but they may be located further away from the edge of the membrane than the piezoresistors in the first resistor pair and the second resistor pair.

[0062] Figure 3 The middle figure shows an example with compensation resistors on the outside of the membrane. The "a" resistor is the sensing resistor and the "b" resistor is the compensation resistor. Figure 5 The middle figure shows an example with a compensation resistor on the zero stress area 115 of the film 110 .

[0063] In an embodiment of the invention, the resistors in each resistor pair are orthogonal. In an embodiment of the invention, the resistors are connected in a Wheatstone bridge configuration designed so that changes in the signals of the resistors caused by disturbances (such as, for example, by stress gradients or temperature gradients on the sensor) are significantly reduced or even completely eliminated.

[0064] In an embodiment of the present invention, the resistors may be connected in the following Wheatstone bridge configuration:

[0065] The first resistor R1a of the first resistor pair and the first resistor R1b of the third resistor pair are connected in series at a first bias node V 电桥 With the first output node V inm between;

[0066] The second resistor R2a in the first resistor pair and the second resistor R2b in the third resistor pair are connected in series at the first output node V inm and a second bias node GND;

[0067] The first resistor R3a of the second resistor pair and the first resistor R3b of the fourth resistor pair are connected in series at the first bias node V 电桥 The second output node V inp between;

[0068] The second resistor R4a in the second resistor pair and the second resistor R4b in the fourth resistor pair are connected in series at the second output node V inp and the second bias node GND.

[0069] In view of the series connection of the measuring and compensating resistors, a particularly advantageous configuration is obtained, since it enables efficient routing, and this is true even when the number of metals in the MEMS design is limited to one. Furthermore, such a particular Wheatstone bridge configuration has the advantage that the number of bonding pads can be limited.

[0070] In an embodiment of the present invention, the piezoresistors may be positioned in a point-symmetrical layout:

[0071] The first resistor R1a of the first resistor pair is orthogonal to the first resistor R1b of the third resistor pair, and

[0072] The second resistor R2a of the first resistor pair is orthogonal to the second resistor R2b of the third resistor pair, and

[0073] The first resistor (R3a) of the second resistor pair is orthogonal to the first resistor (R3b) of the fourth resistor pair, and

[0074] The second resistor R4a of the second resistor pair is orthogonal to the second resistor R4b of the fourth resistor pair.

[0075] When the substrate has a (100) oriented silicon surface, for a p-type substrate, the varistor is preferably along <110> direction, and for n-type substrates, the varistor is preferably placed in <100> The reference resistor should be placed in the same orientation as the varistor family (e.g. <110> ) to be able to compensate for package stress.

[0076] In embodiments of the invention where the membrane has a square or rectangular shape, a first set of adjacent resistors may be arranged at a first side of the membrane and a second set of adjacent resistors may be arranged at a second side of the membrane.The first side may be immediately adjacent to the second side. Figure 3 An example of this is illustrated in . Alternatively, the first side may be opposite to the second side.

[0077] like Figure 6 The Wheatstone configuration shown in FIG. Figure 3 , Figure 4 and Figure 5 The semiconductor pressure sensor layout is shown in . By placing a compensation resistor in series with the varistor, they are connected in a single Wheatstone configuration.

[0078] In an embodiment of the present invention, the first output node V inm The second output node V inp The voltage difference between V 输出 (V out ) is used as a measure of the pressure on the membrane. The voltage difference can be detected at the analog input interface. The signal can be converted to digital using an analog-to-digital converter. Calibration of the sensor can be done digitally using the ADC value for the voltage difference and the calibration constant in a polynomial equation.

[0079] for Figure 6 For the Wheatstone bridge configuration, the following equation holds:

[0080]

[0081] To calculate the sensitivity, it is assumed that all compensation resistors are set to R and no package stress is applied. In this case, the following equation can be obtained:

[0082] R 1a =R 4a =R l and

[0083] R 2a =R 3a =R t ,and

[0084] R 1b =R 2b =R 4b =R 3b =R

[0085] Assume that the original resistor size is the same. In addition, assume that the piezoresistance coefficient is also the same α 1 =α 4 =β 2 =β3 =γ:

[0086]

[0087] Replace R with R+γPR 1 , and replace R with R-γPR t , where P is the pressure on the membrane, the equation becomes:

[0088]

[0089]

[0090] Piezoresistors will also change with temperature, and therefore will also change when there is a temperature gradient across the semiconductor pressure sensor.

[0091] When a stress is applied to the piezoresistor in the same direction as the current flow, this will cause the change in resistance to be different than when the stress is applied perpendicular to the current flow in the piezoresistor.

[0092] The effect of stress on the sensor Figure 7 If there is a stress gradient with high stress on the left and low stress on the right, the stress on R1 and R2 is higher than the stress on R3 and R4 (see Figure 7 The stress on R1a is the same as the stress on R1b, and the stress on R2a is the same as the stress on R2b. The effect of stress on the piezoelectric coefficient of the piezoresistors depends on the orientation of the piezoresistors. For p-type resistors, the coefficients are almost the same value, but for orthogonal piezoresistors, the opposite is true.

[0093] Since the resistors R1a and R1b and the resistors R2a and R2b have different orientations, the stress is significantly compensated and the output voltage V inm and V inp The same is true for R3a and R3b and R4a and R4b.

[0094] for Figure 7 The same reasoning can be made for the right side figure of , which shows local stress concentration. For stress, each resistor is compensated individually. For example, if the first piezoresistors R1a and the second piezoresistors R1b are subjected to the same stress, the stress is significantly compensated locally. Similarly, if the third piezoresistors R2a and the fourth piezoresistors R2b are subjected to the same stress, the stress is also significantly compensated locally, and the output voltage will remain substantially constant.

[0095] Temperature compensation is achieved by providing adjacent resistors within each group. Temperature has a similar effect on the resistors R1a and R1b in the first group. They will both increase or decrease due to temperature changes. Therefore, having only resistors R1a and R1b will not compensate for the temperature effects on the resistors due to temperature changes. Therefore, resistors R2a and R2b are positioned close to resistors R1a and R1b so that they are subject to substantially the same temperature. By doing this, the temperature effects on the resistors can be compensated so that the measured pressure is substantially independent of temperature gradients or hot spots.

Claims

1. A semiconductor pressure sensor for measuring an external pressure applied to the sensor, the semiconductor pressure sensor comprising: a film, as a part of the semiconductor substrate, adapted to be deformed by the external pressure, the film having a film edge and a film thickness; a first group of adjacent resistors and a second group of adjacent resistors, the first group of adjacent resistors including a first resistor pair (R1a, R2a) and a third resistor pair (R1b, R2b), the second group of adjacent resistors including a second resistor pair (R3a, R4a) and a fourth resistor pair (R3b, R4b); wherein the first resistor pair (R1a, R2a) is located on or adjacent to the membrane edge, and wherein the second resistor pair (R3a, R4a) is separate from the first resistor pair and is located on or adjacent to the membrane edge; and wherein the third resistor pair (R1b, R2b) is at least partially located outside the membrane or at least partially located on a zero stress area of ​​the membrane, and the fourth resistor pair (R3b, R4b) is at least partially located outside the membrane or at least partially located on a zero stress area of ​​the membrane; wherein the resistors in each resistor pair are orthogonal; And wherein the first resistor (R1a) of the first resistor pair and the first resistor (R1b) of the third resistor pair are connected in series at a first bias node (V 电桥 ) and the first output node (V inm )between; The second resistor (R2a) of the first resistor pair and the second resistor (R2b) of the third resistor pair are connected in series at the first output node (V inm ) and a second bias node (GND); The first resistor (R3a) of the second resistor pair and the first resistor (R3b) of the fourth resistor pair are connected in series at the first bias node (V 电桥 ) and the second output node (V inp )between; The second resistor (R4a) of the second resistor pair and the second resistor (R4b) of the fourth resistor pair are connected in series at the second output node (V inp ) and the second bias node (GND).

2. The semiconductor pressure sensor according to claim 1, wherein: The first resistor (R1a) of the first resistor pair and the first resistor (R1b) of the third resistor pair are orthogonal, and wherein the first resistor (R3a) of the second resistor pair and the first resistor (R3b) of the fourth resistor pair are orthogonal, and wherein the second resistor (R2a) of the first resistor pair and the second resistor (R2b) of the third resistor pair are orthogonal, and wherein the second resistor (R4a) of the second resistor pair and the second resistor (R4b) of the fourth resistor pair are orthogonal.

3. The semiconductor pressure sensor according to claim 1, wherein: The membrane has a square or rectangular shape.

4. The semiconductor pressure sensor according to claim 3, wherein: The first group of adjacent resistors is arranged at a first side of the membrane, and wherein the second group of adjacent resistors is arranged at a second side of the membrane.

5. The semiconductor pressure sensor according to claim 4, wherein: The first side is immediately adjacent to the second side.

6. The semiconductor pressure sensor according to claim 4, wherein: The first side is opposite to the second side.

7. The semiconductor pressure sensor according to claim 1, wherein: The membrane has a circular or oval shape.

8. The semiconductor pressure sensor according to claim 7, wherein: The first group and the second group have an angular interval of 90°.

9. The semiconductor pressure sensor according to claim 1, wherein: The voltage difference between the first output node and the second output node is used as a measure of the pressure on the membrane.

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