Clock signal generation method, generation device, electronic device and readable medium

Abstract

This disclosure belongs to the field of signal processing technology, specifically disclosing a clock signal generation method, apparatus, device, and medium. The method includes: determining frequency parameters of a frequency adjustment unit based on the frequency correlation between a first clock signal frequency of an original clock source and a second clock signal frequency of a target clock signal to be generated, the first clock signal frequency, and a third clock signal frequency of a preset clock source, so that the frequency adjustment unit generates a target clock signal according to the frequency parameters; counting the target clock signal and the source clock signal of the original clock source respectively; determining whether the original clock source is in an abnormal state based on a first count value of the source clock signal and a second count value of the target clock signal; and updating the frequency parameters if the original clock source is not in an abnormal state, so that the frequency adjustment unit generates subsequent target clock signals according to the updated frequency parameters. This method can improve the stability of the generated clock signal.

Description

Technical Field

[0001] This disclosure relates to the field of signal processing technology, specifically to a clock signal generation method, generation device, electronic device, and readable medium. Background Technology

[0002] In applications such as video matrices, it is necessary to generate an output clock with a frequency correspondence to the source clock. For example, the clock frequency of the output clock is a multiple of the clock frequency of the source clock.

[0003] However, in traditional clock signal generation methods, in order to generate an output clock that corresponds to the source clock in frequency, the source clock can only be used as a reference clock for frequency adjustment. Once the source clock becomes disordered, the output clock will be abnormal, affecting practical applications. Summary of the Invention

[0004] To address this issue, this disclosure provides a clock signal generation method, generation device, electronic device, and readable medium to solve the problem of abnormal output clock caused by source clock disorder in the prior art.

[0005] To achieve the above objectives, the first aspect of this disclosure provides a clock signal generation method, the method comprising:

[0006] Determine the frequency correlation between the first clock signal frequency of the original clock source and the second clock signal frequency of the target clock signal to be generated;

[0007] Based on the frequency correlation, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, the frequency parameters of the frequency adjustment unit are determined so that the frequency adjustment unit generates a target clock signal according to the frequency parameters and the third clock signal frequency of the preset clock source.

[0008] The generated target clock signal and the source clock signal of the original clock source are counted respectively to obtain a first count value of the source clock signal and a second count value of the target clock signal;

[0009] Based on the first count value and the second count value, determine whether the original clock source is in an abnormal state;

[0010] When the original clock source is in a normal state, the frequency parameters are updated according to the first count value and the second count value, so that the frequency adjustment unit generates the subsequent target clock signal according to the updated frequency parameters.

[0011] In one optional implementation, the target clock signal and the source clock signal are counted according to a preset counter. The counting of the generated target clock signal and the source clock signal of the original clock source respectively includes:

[0012] Determine the target counting threshold from the counting range of the preset counter;

[0013] The source clock signal of the original clock source is counted to obtain a first count value of the source clock signal;

[0014] When the first count value reaches the target count threshold, the target clock signal is counted to obtain a second count value of the target clock signal.

[0015] In one optional implementation, determining whether the original clock source is in an abnormal state based on the first count value and the second count value includes:

[0016] Based on the target counting threshold and the first threshold interval, a preset upper boundary abnormal threshold and a preset lower boundary abnormal threshold are determined;

[0017] Calculate the count difference between the first count value and the second count value;

[0018] If the count difference is greater than the preset upper boundary abnormal threshold or the count difference is less than the preset lower boundary abnormal threshold, the original clock source is determined to be in an abnormal state.

[0019] In one optional implementation, updating the frequency parameter based on the first count value and the second count value includes:

[0020] Based on the target counting threshold and the second threshold interval, determine the target upper boundary threshold and the target lower boundary threshold;

[0021] If the difference between the first count value and the second count value is greater than the target upper boundary threshold or the difference between the count values ​​is less than the target lower boundary threshold, the frequency parameter is updated based on the difference between the count values.

[0022] In one optional implementation, updating the frequency parameter based on the count difference includes:

[0023] Based on the comparison results between the count difference and the target upper boundary threshold and the target lower boundary threshold, the target frequency parameter adjustment method is determined from at least two preset frequency parameter adjustment methods;

[0024] Based on the count difference, determine the parameter adjustment range corresponding to the target frequency parameter adjustment method;

[0025] Update the parameter values ​​in the frequency parameters that correspond to the parameter adjustment region.

[0026] In one alternative implementation, before counting the generated target clock signal and the source clock signal of the original clock source, the method further includes:

[0027] Based on the frequency correlation, determine the frequency adjustment parameters corresponding to the original clock source;

[0028] The frequency of the first clock signal of the original clock source is adjusted according to the frequency adjustment parameters corresponding to the original clock source to obtain the frequency-adjusted source clock signal.

[0029] In one alternative implementation, the method further includes:

[0030] If no clock edge of the source clock signal is detected within a preset time, the original clock source is determined to be in an abnormal state.

[0031] If it is determined that the original clock source is in an abnormal state, the frequency parameter is set to a preset frequency parameter so that the frequency adjustment unit generates a subsequent target clock signal according to the preset frequency parameter.

[0032] A second aspect of this disclosure provides a clock signal generation apparatus, the apparatus comprising:

[0033] The determination module is used to determine the frequency correlation between the frequency of the first clock signal of the original clock source and the frequency of the second clock signal of the target clock signal to be generated.

[0034] The generation module is used to determine the frequency parameters of the frequency adjustment unit based on the frequency correlation, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, so that the frequency adjustment unit generates a target clock signal based on the frequency parameters and the third clock signal frequency of the preset clock source.

[0035] The counting module is used to count the generated target clock signal and the source clock signal of the original clock source respectively, to obtain a first count value of the source clock signal and a second count value of the target clock signal;

[0036] The judgment module is used to determine whether the original clock source is in an abnormal state based on the first count value and the second count value;

[0037] An update module is used to update the frequency parameters based on the first count value and the second count value when the original clock source is in a non-abnormal state, so that the frequency adjustment unit generates a subsequent target clock signal based on the updated frequency parameters.

[0038] A third aspect of this disclosure provides an electronic device, comprising:

[0039] One or more processors;

[0040] A storage device having stored one or more programs thereon, which, when executed by one or more processors, cause the one or more processors to implement the clock signal generation method described above.

[0041] One or more I / O interfaces are connected between the processor and the memory and configured to enable information interaction between the processor and the memory.

[0042] The fourth aspect of this disclosure provides a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the clock signal generation method described above.

[0043] This disclosure has the following advantages:

[0044] In this embodiment, firstly, the frequency correlation between the first clock signal frequency of the original clock source and the second clock signal frequency of the target clock signal to be generated is determined; then, based on the frequency correlation, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, the frequency parameters of the frequency adjustment unit are determined, so that the frequency adjustment unit generates the target clock signal according to the frequency parameters and the third clock signal frequency of the preset clock source; secondly, the generated target clock signal and the source clock signal of the original clock source are counted respectively to obtain a first count value of the source clock signal and a second count value of the target clock signal; finally, based on the first count value and the second count value, it is determined whether the original clock source is in an abnormal state; thus, if the original clock source is in a normal state, the frequency parameters are updated according to the first count value and the second count value, so that the frequency adjustment unit generates the subsequent target clock signal according to the updated frequency parameters.

[0045] Therefore, the present invention generates a target clock signal by means of a frequency adjustment unit based on frequency parameters and a preset clock source, rather than the original clock source. Furthermore, the present invention updates the frequency parameters based on the first count value of the source clock signal of the original clock source and the second count value of the target clock signal only when the original clock source is in a normal state. On the one hand, this ensures that a target clock signal with a frequency correlation with the source clock signal of the original clock source can be generated when the original clock source is in a normal state. On the other hand, even when the original clock source is in an abnormal state, a stable target clock signal can be generated based on the frequency parameters and the preset clock source, thus avoiding clock loss. Attached Figure Description

[0046] The accompanying drawings are provided to further understand the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof.

[0047] Figure 1 A flowchart of a clock signal generation method provided in this disclosure embodiment;

[0048] Figure 2 This is a schematic diagram illustrating the adjustment of frequency parameters in an embodiment of this disclosure;

[0049] Figure 3 A flowchart of a clock signal generation method provided in this disclosure embodiment;

[0050] Figure 4 A schematic diagram illustrating a clock signal generation method provided in an embodiment of this disclosure;

[0051] Figure 5 A block diagram of a clock signal generation apparatus provided in an embodiment of this disclosure;

[0052] Figure 6 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0053] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0054] As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the related enumerated entries.

[0055] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used in this disclosure, the singular forms “a” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0056] When the terms “comprising” and / or “made of” are used in this disclosure, they specify the presence of the said feature, integral, step, operation, element and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0057] The embodiments described herein can be described with reference to plan views and / or cross-sectional views, using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0058] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so specified in this disclosure.

[0059] In clock signal applications, such as video matrix scenarios, it is necessary to ensure that the clock frequencies of the source clock and the output clock satisfy a frequency correspondence. For example, the clock frequency of the output clock should be a fixed multiple of the clock frequency of the source clock.

[0060] However, in traditional clock signal generation methods, only the frequency of the source clock can be adjusted to generate the output clock. Once the source clock becomes disordered, the output clock will also become abnormal.

[0061] In view of this, the present disclosure provides a clock signal generation method, generation apparatus, electronic device, and readable medium. The method generates a target clock signal by means of a frequency adjustment unit based on frequency parameters and a preset clock source, rather than the original clock source. Furthermore, the frequency parameters are updated based on the first count value of the source clock signal of the original clock source and the second count value of the target clock signal only when the original clock source is in a normal state. This ensures that a target clock signal with a frequency correlation with the source clock signal of the original clock source can be generated when the original clock source is in a normal state. On the other hand, even when the original clock source is in an abnormal state, a stable target clock signal can be generated based on the frequency parameters and the preset clock source, thus avoiding clock loss.

[0062] In a first aspect, embodiments of this disclosure provide a clock signal generation method.

[0063] Figure 1 A flowchart of a clock signal generation method provided in this disclosure embodiment is shown below. Figure 1 The method includes:

[0064] Step S110: Determine the frequency correlation between the first clock signal frequency of the original clock source and the second clock signal frequency of the target clock signal to be generated.

[0065] The original clock source is the signal source that generates the source clock signal, i.e., the source clock. The first clock signal frequency of the original clock source refers to the number of times the original clock source generates the source clock signal per unit time.

[0066] The target clock signal is the clock signal to be generated. The frequency of the second clock signal of the target clock signal is the number of times the target clock signal is generated per unit time.

[0067] It should be noted that the frequency correlation between the second clock signal frequency and the first clock signal frequency is used to characterize the preset numerical relationship between the second clock signal frequency and the first clock signal frequency.

[0068] For example, the ratio of the second clock signal frequency to the first clock signal frequency is a preset multiplier value, or the second clock signal frequency is equal to the first clock signal frequency; this disclosure does not limit this.

[0069] It should also be noted that the frequency correlation needs to be adaptively determined according to the actual application scenario, and this disclosure does not impose any restrictions on this.

[0070] For example, in a video matrix scenario, it is necessary to convert the clock signal frequency of the clock source to achieve consistent frame rates across different display devices.

[0071] Therefore, for two display devices A and B, it is assumed that the clock signal of display device A is the source clock signal generated by the original clock source, and its clock signal frequency is the first clock signal frequency.

[0072] To ensure that display device A and display device B have the same frame rate, a target clock signal needs to be generated for display device B. The frequency correlation between the second clock signal frequency and the first clock signal frequency of the target clock signal can be determined in the following way:

[0073]

[0074] The input horizontal pixel count and input vertical pixel count are the number of pixels displayed by display device A in the horizontal and vertical directions, respectively, and the output horizontal pixel count and output vertical pixel count are the number of pixels displayed by display device B in the horizontal and vertical directions, respectively. Thus, through the above frequency correlation, the frame rates of display device A and display device B are kept consistent.

[0075] Step S120: Determine the frequency parameters of the frequency adjustment unit based on the frequency correlation, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, so that the frequency adjustment unit generates the target clock signal according to the frequency parameters and the third clock signal frequency of the preset clock source.

[0076] The preset clock source is the reference clock required by the frequency adjustment unit when generating the target clock signal.

[0077] It should be noted that since the original clock source, such as the chip input clock, has poor stability, it is easy for the original clock source to fail. Therefore, in order to improve the stability of the preset clock source, a stable clock, such as a crystal oscillator clock, can be selected as the preset clock source.

[0078] The third clock signal frequency of the preset clock source is used to characterize the number of times the preset clock source generates a clock signal per unit time.

[0079] The frequency parameter of the frequency adjustment unit is used to characterize the correlation between the frequency of the third clock signal of the preset clock source and the frequency of the second clock signal of the target clock signal to be generated.

[0080] That is, assuming the frequency of the third clock signal of the preset clock source is f1, then the frequency of the second clock signal of the target clock signal to be generated by the frequency adjustment unit is n*f1. Here, n is the frequency parameter of the frequency adjustment unit, and n is greater than 0.

[0081] Correspondingly, the input to the frequency adjustment unit is the clock signal generated by the preset clock source, and the output of the frequency adjustment unit is the target clock signal.

[0082] It should be noted that the frequency parameters can be determined based on the frequency of the first clock signal, the frequency of the third clock signal, and the frequency correlation.

[0083] For example, assuming the frequency correlation is the ratio between the frequency of the second clock signal and the frequency of the first clock signal, the frequency parameter can be obtained by multiplying the frequency correlation by the frequency ratio between the frequency of the first clock signal and the frequency of the third clock signal.

[0084] Therefore, after determining the frequency parameters of the frequency adjustment unit, by continuously inputting the clock signal generated by the preset clock source to the frequency adjustment unit, the frequency adjustment unit can adjust the frequency of the third clock signal of the preset clock source according to the frequency parameters, and continuously generate the corresponding target clock signal.

[0085] It should also be noted that the frequency adjustment unit is a circuit device used to adjust the frequency of the input signal, and the corresponding frequency adjustment unit can be selected adaptively according to the frequency adjustment needs.

[0086] For example, when it is necessary to amplify the clock signal frequency of the input signal, a frequency multiplier can be selected as the frequency adjustment unit; when it is necessary to reduce the clock signal frequency of the input signal, a frequency divider can be selected as the frequency adjustment unit. This disclosure does not limit this.

[0087] Step S130: Count the generated target clock signal and the source clock signal of the original clock source respectively to obtain the first count value of the source clock signal and the second count value of the target clock signal.

[0088] Among them, a preset counter can be used to count the target clock signal and the source clock signal.

[0089] Specifically, when the clock edge of the target clock signal is detected, the preset counter increments the second count value of the target clock signal by 1.

[0090] The preset counter increments the first count value of the source clock signal by 1 when the clock edge of the source clock signal is detected.

[0091] In one alternative implementation, to avoid frequent updates to the frequency parameters, the target clock signal can be delayed by setting a target count threshold.

[0092] Accordingly, the generated target clock signal and the source clock signal of the original clock source are counted respectively, including: determining a target counting threshold from the counting range of a preset counter; counting the source clock signal of the original clock source to obtain a first count value of the source clock signal; and counting the target clock signal when the first count value reaches the target counting threshold to obtain a second count value of the target clock signal.

[0093] The counting range of the preset counter is determined by the number of bits in the preset counter.

[0094] By selecting a target counting threshold, it is easy to determine the preset numerical relationship between the first count value and the second count value. Assuming that the frequency of the second clock signal of the generated target clock signal and the frequency of the first clock signal of the original clock source remain stable, then the count difference between the first count value and the second count value should be the target counting threshold.

[0095] It should be noted that when determining the target counting threshold from the counting range of the preset counter, an adaptive selection can be made according to actual needs, and the embodiments disclosed herein do not impose any restrictions on this.

[0096] For example, the middle value of the counting range can be selected as the target counting threshold. The target clock signal will only be counted when the first count value reaches the middle value of the counting range. Thus, the frequency parameter will not be updated before the first count value reaches the middle value of the counting range, effectively avoiding frequent updates to the frequency parameter.

[0097] It should also be noted that since the preset counter prioritizes counting the source clock signal, when the first count value reaches the counting range of the preset counter, the first count value and the second count value need to be reset, that is, recounted, to avoid the counting disorder phenomenon where the source clock signal has been recounted while the target clock signal continues to count.

[0098] Step S140: Determine whether the original clock source is in an abnormal state based on the first count value and the second count value.

[0099] Among them, the original clock source being in an abnormal state refers to phenomena such as clock disorder, clock failure, or clock loss in the original clock source.

[0100] Since the preset clock source in this embodiment is a stable clock, when the original clock source is in a non-abnormal state, the numerical relationship between the first count value and the second count value should be within the preset numerical range.

[0101] Therefore, by calculating the numerical relationship between the first count value and the second count value, and comparing this numerical relationship with a preset numerical range, it can be determined whether the original clock source is in an abnormal state.

[0102] For example, if the numerical relationship between the first count value and the second count value is a difference relationship, the preset numerical range can be determined by the upper boundary abnormal threshold and the lower boundary abnormal threshold corresponding to the difference relationship.

[0103] If the numerical relationship between the first count value and the second count value is a ratio, then the preset numerical range can be determined by the upper boundary abnormal threshold and the lower boundary abnormal threshold corresponding to the ratio relationship.

[0104] Step S150: When the original clock source is in a non-abnormal state, update the frequency parameters according to the first count value and the second count value, so that the frequency adjustment unit generates the subsequent target clock signal according to the updated frequency parameters.

[0105] In the case that the original clock source is in a non-abnormal state, by comparing the first count value with the second count value, it can be determined whether the clock signal frequency of the target clock signal generated by the frequency adjustment unit has a frequency correlation relationship with the clock signal frequency of the original clock source based on the numerical relationship between the first count value and the second count value.

[0106] Therefore, based on the first count value and the second count value, the frequency parameters of the frequency adjustment unit are updated, so that the frequency adjustment unit can adjust the frequency of the third clock signal of the preset clock source according to the updated frequency parameters to generate the subsequent target clock signal, thereby achieving the effect that the target clock signal follows the source clock signal.

[0107] It should also be noted that when the first or second count value reaches the count range of the preset counter, or after updating the frequency parameters, the generated target clock signal and the source clock signal need to be recounted. Therefore, the above steps S130 to S150 can be executed multiple times in a loop to continuously detect whether the original clock source is in an abnormal state and to continuously update the frequency parameters, so that the frequency adjustment unit can continuously fine-tune the generation of subsequent target clock signals according to the updated frequency parameters.

[0108] In this embodiment, the frequency adjustment unit generates a target clock signal based on frequency parameters and a preset clock source, rather than the original clock source. The frequency parameters are updated only when the original clock source is in a normal state, based on the first count value of the source clock signal of the original clock source and the second count value of the target clock signal. This ensures that a target clock signal with a frequency correlation with the source clock signal of the original clock source can be generated when the original clock source is in a normal state. On the other hand, even when the original clock source is in an abnormal state, a stable target clock signal can be generated based on the frequency parameters and the preset clock source, avoiding clock loss.

[0109] Furthermore, those skilled in the art can make various modifications and variations to the methods disclosed herein:

[0110] In one alternative implementation, in order to accurately determine whether the original clock source is in an abnormal state, an abnormal threshold can be determined based on the target counting threshold and the threshold interval. Thus, by comparing the difference between the first count value and the second count value with the abnormal threshold, it can be determined whether the original clock source is in an abnormal state.

[0111] Accordingly, based on the first count value and the second count value, it is determined whether the original clock source is in an abnormal state, including: determining a preset upper boundary abnormal threshold and a preset lower boundary abnormal threshold based on the target count threshold and the first threshold interval; calculating the count difference between the first count value and the second count value; and determining that the original clock source is in an abnormal state if the count difference is greater than the preset upper boundary abnormal threshold or less than the preset lower boundary abnormal threshold.

[0112] The target counting threshold is a counting threshold selected from the counting range of the preset counter. The specific explanation is as described above and will not be repeated here.

[0113] The preset upper boundary abnormality threshold is the upper boundary value used to determine that the original clock source is in an abnormal state. If the difference between the first count value and the second count value is greater than the preset upper boundary abnormality threshold, the original clock source is determined to be in an abnormal state.

[0114] The preset lower boundary anomaly threshold is a lower boundary value used to determine if the original clock source is in an abnormal state. If the difference between the first count value and the second count value is less than the preset lower boundary anomaly threshold, the original clock source is determined to be in an abnormal state.

[0115] In other words, the preset upper boundary abnormal threshold must be greater than the preset lower boundary abnormal threshold.

[0116] It should be noted that, in order to ensure that the preset upper boundary abnormal threshold and the preset lower boundary abnormal threshold are within a reasonable range, the preset upper boundary abnormal threshold and the preset lower boundary abnormal threshold need to be determined based on the target count threshold and the first threshold interval.

[0117] Specifically, when the original clock source is in a non-abnormal state, the difference between the first count value and the second count value must be the same as the target count threshold, or only slightly deviate from the target count threshold.

[0118] Therefore, by determining the first threshold interval, the target counting threshold can be increased or decreased by the first threshold interval to obtain the preset upper boundary abnormal threshold and the preset lower boundary abnormal threshold.

[0119] The first threshold interval can be adaptively set according to the actual application needs. For example, by reducing the value of the first threshold interval, the preset upper boundary abnormal threshold is reduced and the preset lower boundary abnormal threshold is increased, so as to expand the threshold range in which the counting difference is located when the original clock source is in an abnormal state.

[0120] In one alternative implementation, to improve the efficiency of frequency parameter adjustment, a second threshold interval can be set to determine the target upper boundary threshold and the target lower boundary threshold based on the target count threshold and the second threshold interval. Then, based on the target upper boundary threshold and the target lower boundary threshold, it can be determined whether to update the frequency parameter.

[0121] The second threshold interval is used to characterize the allowable deviation between the count difference and the target count threshold.

[0122] The target upper boundary threshold is used to determine the upper boundary value of the frequency parameter that needs to be updated. If the count difference between the first count value and the second count value is greater than the target upper boundary threshold, it indicates that the deviation between the count difference and the target count threshold is large, and the frequency parameter needs to be updated.

[0123] The target lower boundary threshold is used to determine the lower boundary value of the frequency parameter that needs to be updated. If the count difference between the first count value and the second count value is less than the target lower boundary threshold, it also indicates that the deviation between the count difference and the target count threshold is large, and the frequency parameter needs to be updated.

[0124] It should be noted that the target upper boundary threshold and the target lower boundary threshold can be obtained by increasing or decreasing the target counting threshold by the second threshold interval.

[0125] Furthermore, the second threshold interval can be adaptively set according to actual application needs. For example, by increasing the value of the second threshold interval, the upper boundary threshold of the target can be increased and the lower boundary threshold of the target can be decreased, so as to reduce the threshold range in which the count difference is located when determining the frequency parameter that needs to be updated.

[0126] It should also be noted that the second threshold interval must be smaller than the first threshold interval mentioned above; that is, the preset upper boundary anomaly threshold must be greater than the target upper boundary threshold, and the preset lower boundary anomaly threshold must be less than the target lower boundary threshold. For ease of understanding, Figure 2 A schematic diagram of frequency parameter adjustment in an embodiment of this disclosure is shown, with reference to... Figure 2 .

[0127] Where m is the target counting threshold, Threshold1 is the target upper boundary threshold, Threshold2 is the target lower boundary threshold, Threshold3 is the preset upper boundary abnormal threshold, Threshold4 is the preset lower boundary abnormal threshold, diff is the counting difference between the first count value and the second count value, and T is the clock period of the preset clock source.

[0128] from Figure 2 It can be seen that when the count difference diff is within the threshold range between the preset upper boundary abnormal threshold Threshold3 and the preset lower boundary abnormal threshold Threshold4, the frequency adjustment unit is determined to be in a non-abnormal state.

[0129] Furthermore, when the count difference diff is within the threshold range between the target upper boundary threshold Threshold1 and the target lower boundary threshold Threshold2, the frequency parameter will not be updated. When the count difference diff is greater than the target upper boundary threshold Threshold1, the frequency parameter will be increased to increase the clock signal frequency of the generated target clock signal. When the count difference diff is less than the target lower boundary threshold Threshold2, the frequency parameter will be decreased to reduce the clock signal frequency of the generated target clock signal.

[0130] In one alternative implementation, to improve the flexibility and accuracy of frequency parameter adjustment, the frequency parameter adjustment method and the corresponding parameter adjustment area can be determined based on the count difference. Then, the frequency parameter can be updated by updating the parameter value corresponding to the parameter adjustment area in the frequency parameter.

[0131] Accordingly, based on the count difference, the frequency parameters are updated, including: determining the target frequency parameter adjustment method from at least two preset frequency parameter adjustment methods based on the comparison results of the count difference with the target upper boundary threshold and the target lower boundary threshold; determining the parameter adjustment area corresponding to the target frequency parameter adjustment method based on the count difference; and updating the parameter values ​​in the frequency parameters corresponding to the parameter adjustment area.

[0132] The comparison results between the count difference and the target upper boundary threshold and the target lower boundary threshold are used to characterize the magnitude of the count difference deviation.

[0133] Among them, the frequency parameter adjustment method is used to characterize the fineness of the frequency parameter adjustment. For example, it is used to characterize the first frequency parameter adjustment method for fine-tuning the frequency parameter, the second frequency parameter adjustment method for moderately adjusting the frequency parameter, and the third frequency parameter adjustment method for larger adjustments.

[0134] Furthermore, based on the comparison results between the count difference and the target upper boundary threshold and the target lower boundary threshold, the target frequency parameter adjustment method can be determined.

[0135] For example, when the count difference deviation is small, a first frequency parameter adjustment method can be selected as the target frequency parameter adjustment method. When the count difference deviation is large, a third frequency parameter adjustment method can be selected as the target frequency parameter adjustment method.

[0136] The parameter adjustment region is used to characterize the adjustment position of the frequency parameter. Specifically, the parameter adjustment region can be an integer region, a decimal region, or a region with a preset number of bits.

[0137] It should be noted that different frequency parameter adjustment methods correspond to different parameter adjustment areas. For example, under the first frequency parameter adjustment method, the corresponding parameter adjustment area can be a decimal area or a first preset number of digits area. Under the second frequency parameter adjustment method, the corresponding parameter adjustment area can be a second preset number of digits area. Under the third frequency parameter adjustment method, the corresponding parameter adjustment area can be an integer area or a third preset number of digits area.

[0138] It should also be noted that, under different frequency parameter adjustment methods, a preset number of bits can be adaptively selected, and a corresponding preset number of bits range can be set.

[0139] Furthermore, based on the count difference, the parameter adjustment range corresponding to the target frequency parameter adjustment method can be determined.

[0140] For example, when the count difference deviation is small (such as the difference between the count difference and the target upper boundary threshold or the target lower boundary threshold being in the first difference interval), the decimal region is selected as the parameter adjustment region, or the first preset number of digits region is selected, such as the region after one decimal point, as the parameter adjustment region.

[0141] For example, when the count difference deviation is moderate (such as the difference between the count difference and the target upper boundary threshold or the target lower boundary threshold being in the second difference interval), a second preset digit region, such as the units digit region, is selected as the parameter adjustment region.

[0142] It should be noted that after determining the parameter adjustment area, the specific adjustment parameter value corresponding to the parameter adjustment area can also be determined based on the count difference. The adjustment parameter value can be positive or negative, and this embodiment does not limit it.

[0143] For example, if the count difference is less than the target lower boundary threshold, the adjustment parameter value can be set to a negative value, and if the count difference deviation is small, the absolute value of the adjustment parameter value can be set to a smaller value.

[0144] Therefore, by updating the parameter values ​​in the frequency parameters corresponding to the parameter adjustment region, the updated frequency parameters can be obtained. For example, if the parameter adjustment region is the decimal region, the parameter value corresponding to the decimal region in the frequency parameters is 0.5, and the adjustment parameter value is -0.1, then the parameter value corresponding to the decimal region in the updated frequency parameters will be 0.4.

[0145] In one alternative implementation, in order to improve the efficiency of judging the abnormal state of the original clock source and the efficiency of updating the frequency parameters, when the frequency correlation between the first clock signal frequency of the original clock source and the second clock signal frequency of the target clock signal to be generated is not equal, the frequency of the first clock signal of the original clock source can be adjusted according to the frequency correlation to obtain the frequency-adjusted source clock signal, so as to count the frequency-adjusted source clock signal.

[0146] Accordingly, before counting the generated target clock signal and the source clock signal of the original clock source respectively, the process also includes: determining the frequency adjustment parameters corresponding to the original clock source according to the frequency correlation; adjusting the frequency of the first clock signal of the original clock source according to the frequency adjustment parameters corresponding to the original clock source to obtain the frequency-adjusted source clock signal.

[0147] The frequency correlation characterizes the numerical relationship between the frequency of the first clock signal of the original clock source and the frequency of the second clock signal of the target clock signal to be generated.

[0148] Specifically, if the frequency of the first clock signal of the original clock source and the frequency of the second clock signal of the target clock signal to be generated are not equal, then the frequency adjustment parameters corresponding to the original clock source are determined according to the frequency correlation.

[0149] The frequency adjustment parameter corresponding to the original clock source represents the adjustment ratio of the clock signal frequency of the original clock source. For example, if the frequency adjustment parameter is m, m>0, and the first clock signal frequency of the original clock source is f2, then the adjusted clock signal frequency of the original clock source is m*f2.

[0150] It should be noted that the frequency of the first clock signal of the original clock source can be adjusted by the preset frequency adjustment unit according to the frequency adjustment parameters corresponding to the original clock source, so as to obtain the source clock signal with adjusted frequency.

[0151] For example, by inputting the source clock signal of the original clock source into a preset frequency adjustment unit, such as a preset frequency multiplier or preset frequency divider, the preset frequency adjustment unit adjusts the frequency of the first clock signal of the original clock source according to the frequency adjustment parameters, and outputs the frequency-adjusted source clock signal, so that the frequency-adjusted source clock signal can be counted to obtain the first count value.

[0152] When the frequency correlation is not equal, if the source clock signal of the original clock source is counted directly, the count difference between the first count value and the second count value needs to be proportionally converted according to the frequency correlation. Based on the count difference after proportional conversion, it can be determined whether the original clock source is in an abnormal state and whether the frequency parameters need to be updated.

[0153] Therefore, according to the frequency correlation relationship, the frequency of the first clock signal of the original clock source is pre-adjusted so that the clock signal frequency of the source clock signal after frequency adjustment can be equal to the second clock signal frequency of the target clock signal to be generated. By counting the source clock signal after frequency adjustment, the frequent proportional conversion of the count difference between the first count value and the second count value is avoided, thereby effectively improving the efficiency of judging the abnormal state of the original clock source and the efficiency of frequency parameter update.

[0154] In one alternative implementation, in order to accurately determine whether the original clock source is in an abnormal state, a preset time can be set. If no clock edge of the source clock signal is detected within the preset time, it means that the original clock source is lost. At this time, by determining that it is in an abnormal state, the frequency adjustment unit can generate a stable target clock signal with preset frequency parameters.

[0155] Accordingly, the clock signal generation method of this disclosure further includes: if no clock edge of the source clock signal is detected within a preset time, determining that the original clock source is in an abnormal state; and if the original clock source is determined to be in an abnormal state, setting the frequency parameter to a preset frequency parameter so that the frequency adjustment unit generates a subsequent target clock signal according to the preset frequency parameter.

[0156] The preset time can be adaptively set according to actual testing needs. This embodiment does not limit this. For example, the preset time can be set to 5s, 10s, etc.

[0157] If no clock edge of the source clock signal is detected within the preset time, it means that the original clock source did not generate a source clock signal within the preset time, and correspondingly, the first count value of the source clock signal will not change.

[0158] Therefore, under these circumstances, it can be determined that the original clock source has experienced clock loss and that the original clock source is in an abnormal state.

[0159] Correspondingly, if the original clock source is in an abnormal state, the first count value of the source clock signal will deviate. If the frequency parameters are still updated based on the first count value and the second count value, the target clock signal generated by the frequency adjustment unit will also become abnormal.

[0160] Therefore, when the original clock source is in an abnormal state, the frequency parameter can be set to a preset frequency parameter so that the frequency adjustment unit can generate the subsequent target clock signal according to the preset frequency parameter.

[0161] The preset frequency parameter can be the initial frequency parameter used by the frequency adjustment unit when it first generates the target clock signal, or it can be the current frequency parameter corresponding to the current state of the frequency adjustment unit. This embodiment does not limit this.

[0162] In other words, when the original clock source is in an abnormal state, the frequency adjustment unit can either use the initial frequency parameters to generate the subsequent target clock signal, or it can maintain the current frequency parameters to generate the subsequent target clock signal, so that the generated subsequent target clock signal is in a stable state.

[0163] To facilitate understanding, an example will be used below to illustrate the implementation of the above embodiments.

[0164] For video matrix products that require consistent input and output frame rates, a frame lock scheme is typically used to ensure that the input clock and output clock have a fixed frequency relationship.

[0165] The above scheme uses the chip input clock as a reference and a frequency multiplier to generate a fixed-rate output clock, thus outputting periodic timing information with a frame rate that always follows the input clock. However, when the input clock is lost, the frequency multiplier will change accordingly, leading to abnormal or lost chip output. To address the issue of abnormal output clock when the source input clock is lost, this example proposes a clock signal generation method. Figure 3 A flowchart of a clock signal generation method provided in this example is shown below. Figure 3 The method includes:

[0166] Step S300: Determine the frequency correlation between the first clock signal frequency of the original clock source and the second clock signal frequency of the target clock signal to be generated.

[0167] In the video matrix scenario, since frame rate = pixel clock frequency / (number of horizontal pixels * number of vertical pixels), in order to achieve consistent frame rates between the two display devices, the frequency correlation between the first clock signal frequency of device A and the second clock signal frequency of device B must satisfy: second clock signal frequency / first clock signal frequency = number of horizontal pixels of device B * number of vertical pixels of device B / (number of horizontal pixels of device A * number of vertical pixels of device A).

[0168] Therefore, by detecting the clock signal frequency, horizontal pixel count, and vertical pixel count of device A, and the known horizontal pixel count and vertical pixel count of device B, the frequency correlation can be determined.

[0169] Step S301: Determine the frequency parameters of the frequency adjustment unit based on the frequency correlation, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, so that the frequency adjustment unit generates the target clock signal according to the frequency parameters and the third clock signal frequency of the preset clock source.

[0170] In the traditional clock signal generation method, the original clock source is directly used as the reference clock for the frequency adjustment unit, thereby generating the target clock signal by utilizing the aforementioned frequency correlation relationship.

[0171] Finally, based on the number of horizontal and vertical pixels of device B and the target clock signal, the output timing sequence is generated, which can obtain the output timing sequence that is consistent with the frame rate of device A and always follows the timing sequence of device A.

[0172] However, under the above clock signal generation method, if the input clock is disordered or lost, it will cause the generated target clock signal to be abnormal, which in turn will cause the device to display abnormally or be interrupted.

[0173] Therefore, in the clock signal generation method of this example, a preset clock source, rather than the original clock source, is used as the reference clock for the frequency adjustment unit.

[0174] Therefore, based on the determined frequency correlation, the first clock signal frequency of the original clock source, the third clock signal frequency of the preset clock source, and the frequency parameters of the set frequency adjustment unit, these frequency parameters are the initial frequency parameters.

[0175] Step S302: Determine the frequency adjustment parameters corresponding to the original clock source based on the frequency correlation relationship.

[0176] Step S303: Adjust the frequency of the first clock signal of the original clock source according to the frequency adjustment parameters corresponding to the original clock source to obtain the frequency-adjusted source clock signal.

[0177] In cases where the frequency correlation is not equal, the frequency of the first clock signal of the original clock source can be adjusted according to the frequency correlation, so that the frequency of the source clock signal after frequency adjustment is 1:1 with the frequency of the second clock signal of the target clock signal to be generated.

[0178] Step S304: Determine the target counting threshold from the counting range of the preset counter.

[0179] The preset counter is used to count the target clock signal and the source clock signal. The counting range of the preset counter is determined by the number of bits in the preset counter. For example, if the preset counter is 13 bits, its counting range is 2^13.

[0180] For ease of processing, the target counting threshold can be taken as the midpoint of the counting range.

[0181] Step S305: Count the source clock signal of the original clock source to obtain the first count value of the source clock signal.

[0182] Specifically, a preset counter src_cnt is used to count the source clock signal src_clk starting from 0. Each time a source clock signal is detected, the first count value is incremented by 1.

[0183] Step S306: When the first count value reaches the target count threshold, count the target clock signal to obtain the second count value of the target clock signal.

[0184] Specifically, when the first count value reaches the midpoint of the counting range, a preset counter dst_cnt is used to count the target clock signal dst_clk from 0. For each target clock signal detected, the second count value is incremented by 1.

[0185] Step S307: Determine whether the original clock source is in an abnormal state based on the first count value and the second count value.

[0186] By calculating the difference between the first count value and the second count value, the relationship between the count difference and preset abnormal thresholds (preset upper boundary abnormal threshold and preset lower boundary abnormal threshold) is used to determine whether the original clock source is in an abnormal state.

[0187] Step S308: When the original clock source is in a non-abnormal state, update the frequency parameters according to the first count value and the second count value, so that the frequency adjustment unit generates the subsequent target clock signal according to the updated frequency parameters.

[0188] If the difference between the first count value and the second count value is between the upper boundary threshold and the lower boundary threshold of the target, the frequency parameter is not updated.

[0189] If the count difference is greater than the target upper boundary threshold but less than the preset upper boundary abnormal threshold, the frequency parameter is increased to increase the clock signal frequency of the generated target clock signal, thereby reducing the count difference.

[0190] If the count difference is less than the target lower boundary threshold but greater than the preset lower boundary abnormal threshold, the frequency parameter is reduced to lower the clock signal frequency of the generated target clock signal, thereby increasing the count difference.

[0191] Step S309: When the original clock source is in an abnormal state, the frequency parameter is set to the preset frequency parameter so that the frequency adjustment unit generates the subsequent target clock signal according to the preset frequency parameter.

[0192] If the original clock source is in an abnormal state, this indicates that the count difference is greater than the preset upper boundary abnormal threshold or less than the preset lower boundary abnormal threshold. For example, if the original clock source is lost, the count difference will decrease until it falls below the preset lower boundary abnormal threshold.

[0193] At this point, the frequency parameter can be set to a preset frequency parameter, which can be the initial frequency parameter, so that the frequency adjustment unit, such as the frequency multiplier, operates at the initial frequency parameter and outputs a target clock signal of a fixed frequency.

[0194] Similarly, if the original clock source is detected to be lost (for example, no clock edge of the source clock signal is detected within a preset time), the frequency parameter is also set to the preset frequency parameter, so that the frequency adjustment unit, such as the frequency multiplier, operates at the initial frequency parameter.

[0195] Figure 4 A schematic diagram of the clock signal generation method in this example is shown. (Refer to...) Figure 4The input clock is the original clock source, the crystal oscillator clock is the preset clock source, the frequency multiplier is the frequency adjustment unit used to generate the target clock signal, and the frequency divider is used to adjust the frequency of the first clock signal of the original clock source so that the frequency of the source clock signal src_clk output by the frequency divider is 1:1 with the frequency of the target clock signal dst_clk output by the frequency multiplier.

[0196] Therefore, by counting the source clock signal src_clk and the target clock signal dst_clk, a first count value and a second count value are obtained, and the frequency parameters of the frequency multiplier are updated according to the first count value and the second count value.

[0197] Specifically, when updating frequency parameters, the parameter adjustment range can be determined, such as updating only the integer or decimal range of the frequency parameters, to improve the flexibility of frequency parameter adjustment.

[0198] In this embodiment, by selecting a preset clock source (e.g., a crystal oscillator clock) as the reference clock, the frequency parameters are updated only when the original clock source is in a normal state, using the second count value of the source clock signal of the original clock source and the first count value of the generated target clock signal. This allows the frequency adjustment unit to continuously fine-tune the generated target clock signal according to the updated frequency parameters, so that the target clock signal follows the source clock signal within a certain range. When the original clock source is in an abnormal state, the frequency parameters are set to preset frequency parameters, so that the frequency adjustment unit can generate a target clock signal of a fixed frequency according to the preset frequency parameters, thus avoiding clock loss.

[0199] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0200] Secondly, embodiments of this disclosure provide a clock signal generation apparatus. Figure 5 A block diagram of a clock signal generation apparatus provided in an embodiment of this disclosure, referring to... Figure 5 The device includes:

[0201] The determining module 51 is used to determine the frequency correlation between the first clock signal frequency of the original clock source and the second clock signal frequency of the target clock signal to be generated;

[0202] The generation module 52 is used to determine the frequency parameters of the frequency adjustment unit according to the frequency correlation relationship, the first clock signal frequency of the original clock source and the third clock signal frequency of the preset clock source, so that the frequency adjustment unit generates a target clock signal according to the frequency parameters and the third clock signal frequency of the preset clock source.

[0203] The counting module 53 is used to count the generated target clock signal and the source clock signal of the original clock source respectively, to obtain a first count value of the source clock signal and a second count value of the target clock signal;

[0204] The judgment module 54 is used to determine whether the original clock source is in an abnormal state based on the first count value and the second count value;

[0205] The update module 55 is used to update the frequency parameters according to the first count value and the second count value when the original clock source is in a non-abnormal state, so that the frequency adjustment unit generates the subsequent target clock signal according to the updated frequency parameters.

[0206] In one optional implementation, the target clock signal and the source clock signal are counted according to a preset counter. Then, the counting module 53 counts the generated target clock signal and the source clock signal of the original clock source, respectively, including: determining a target counting threshold from the counting range of the preset counter; counting the source clock signal of the original clock source to obtain a first count value of the source clock signal; and counting the target clock signal when the first count value reaches the target counting threshold to obtain a second count value of the target clock signal.

[0207] In one optional implementation, the determination module 54 determines whether the original clock source is in an abnormal state based on the first count value and the second count value, including: determining a preset upper boundary abnormal threshold and a preset lower boundary abnormal threshold based on the target count threshold and the first threshold interval; calculating the count difference between the first count value and the second count value; and determining that the original clock source is in an abnormal state if the count difference is greater than the preset upper boundary abnormal threshold or the count difference is less than the preset lower boundary abnormal threshold.

[0208] In one optional implementation, the update module 55 updates the frequency parameter based on the first count value and the second count value, including: determining a target upper boundary threshold and a target lower boundary threshold based on the target count threshold and the second threshold interval; and updating the frequency parameter based on the count difference when the count difference between the first count value and the second count value is greater than the target upper boundary threshold or the count difference is less than the target lower boundary threshold.

[0209] In one optional implementation, updating the frequency parameter based on the count difference includes: determining a target frequency parameter adjustment method from at least two preset frequency parameter adjustment methods based on a comparison result between the count difference and the target upper boundary threshold and the target lower boundary threshold; determining a parameter adjustment region corresponding to the target frequency parameter adjustment method based on the count difference; and updating the parameter value in the frequency parameter corresponding to the parameter adjustment region.

[0210] In one optional implementation, before the counting module 53 counts the generated target clock signal and the source clock signal of the original clock source respectively, the device is further configured to: determine the frequency adjustment parameter corresponding to the original clock source according to the frequency correlation; adjust the frequency of the first clock signal of the original clock source according to the frequency adjustment parameter corresponding to the original clock source to obtain the frequency-adjusted source clock signal.

[0211] In an optional implementation, the device is further configured to: determine that the original clock source is in an abnormal state if no clock edge of the source clock signal is detected within a preset time; and, if the original clock source is determined to be in an abnormal state, set the frequency parameter to a preset frequency parameter so that the frequency adjustment unit generates a subsequent target clock signal according to the preset frequency parameter.

[0212] The apparatus provided in this disclosure can have functions or include modules that can be used to perform the methods described in the first aspect of the method embodiments above. The specific implementation and technical effects can be referred to the description of the method embodiments above. For the sake of brevity, they will not be repeated here.

[0213] It should be noted that all modules involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this disclosure; however, this does not mean that other units are absent from this embodiment.

[0214] Reference Figure 6 This disclosure provides an electronic device, which includes:

[0215] One or more processors 601;

[0216] The memory 602 stores one or more programs that, when executed by one or more processors, cause the one or more processors to implement any of the above clock signal generation methods.

[0217] One or more I / O interfaces 603 are connected between the processor and the memory and configured to enable information exchange between the processor and the memory.

[0218] The processor 601 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 602 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read / write interface) 603 is connected between the processor 601 and the memory 602, enabling information exchange between the processor 601 and the memory 602, including but not limited to a data bus (Bus).

[0219] In some embodiments, the processor 601, memory 602, and I / O interface 603 are interconnected via a bus, and thus connected to other components of the computing device.

[0220] This embodiment also provides a computer-readable medium having a computer program stored thereon. When the program is executed by a processor, it implements the clock signal generation method provided in this embodiment. To avoid repetition, the specific steps of the clock signal generation method will not be repeated here.

[0221] Those skilled in the art will understand that all or some of the steps, systems, or apparatuses in the methods, systems, and apparatuses described above can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0222] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0223] Those skilled in the art will understand that although some embodiments described herein include certain features that are included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of this embodiment and form different embodiments.

[0224] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A method for generating a clock signal, characterized in that, The method comprises: Determine the frequency correlation between the first clock signal frequency of the original clock source and the second clock signal frequency of the target clock signal to be generated; Based on the frequency correlation, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, the frequency parameters of the frequency adjustment unit are determined so that the frequency adjustment unit generates a target clock signal according to the frequency parameters and the third clock signal frequency of the preset clock source. The generated target clock signal and the source clock signal of the original clock source are counted respectively to obtain a first count value of the source clock signal and a second count value of the target clock signal; Based on the first count value and the second count value, determine whether the original clock source is in an abnormal state; When the original clock source is in a normal state, the frequency parameters are updated according to the first count value and the second count value, so that the frequency adjustment unit generates the subsequent target clock signal according to the updated frequency parameters.

2. The clock signal generation method according to claim 1, characterized in that, The target clock signal and the source clock signal are counted according to a preset counter. The counting of the generated target clock signal and the source clock signal of the original clock source respectively includes: Determine the target counting threshold from the counting range of the preset counter; The source clock signal of the original clock source is counted to obtain a first count value of the source clock signal; When the first count value reaches the target count threshold, the target clock signal is counted to obtain a second count value of the target clock signal.

3. The clock signal generation method according to claim 2, characterized in that, The step of determining whether the original clock source is in an abnormal state based on the first count value and the second count value includes: Based on the target counting threshold and the first threshold interval, a preset upper boundary abnormal threshold and a preset lower boundary abnormal threshold are determined; Calculate the count difference between the first count value and the second count value; If the count difference is greater than the preset upper boundary abnormal threshold or the count difference is less than the preset lower boundary abnormal threshold, the original clock source is determined to be in an abnormal state.

4. The clock signal generation method according to claim 2, characterized in that, The step of updating the frequency parameter based on the first count value and the second count value includes: Based on the target counting threshold and the second threshold interval, determine the target upper boundary threshold and the target lower boundary threshold; If the difference between the first count value and the second count value is greater than the target upper boundary threshold or the difference between the count values ​​is less than the target lower boundary threshold, the frequency parameter is updated based on the difference between the count values.

5. The clock signal generation method according to claim 4, characterized in that, The step of updating the frequency parameter based on the count difference includes: Based on the comparison results between the count difference and the target upper boundary threshold and the target lower boundary threshold, the target frequency parameter adjustment method is determined from at least two preset frequency parameter adjustment methods; Based on the count difference, determine the parameter adjustment range corresponding to the target frequency parameter adjustment method; Update the parameter values ​​in the frequency parameters that correspond to the parameter adjustment region.

6. The clock signal generation method according to any one of claims 1-5, characterized in that, Before counting the generated target clock signal and the source clock signal of the original clock source, respectively, the method further includes: Based on the frequency correlation, determine the frequency adjustment parameters corresponding to the original clock source; The frequency of the first clock signal of the original clock source is adjusted according to the frequency adjustment parameters corresponding to the original clock source to obtain the frequency-adjusted source clock signal.

7. The clock signal generation method according to any one of claims 1-5, characterized in that, The method further includes: If no clock edge of the source clock signal is detected within a preset time, the original clock source is determined to be in an abnormal state. If it is determined that the original clock source is in an abnormal state, the frequency parameter is set to a preset frequency parameter so that the frequency adjustment unit generates a subsequent target clock signal according to the preset frequency parameter.

8. A clock signal generating device, characterized in that, The device comprises: The determination module is used to determine the frequency correlation between the frequency of the first clock signal of the original clock source and the frequency of the second clock signal of the target clock signal to be generated. The generation module is used to determine the frequency parameters of the frequency adjustment unit based on the frequency correlation, the first clock signal frequency of the original clock source, and the third clock signal frequency of the preset clock source, so that the frequency adjustment unit generates a target clock signal based on the frequency parameters and the third clock signal frequency of the preset clock source. The counting module is used to count the generated target clock signal and the source clock signal of the original clock source respectively, to obtain a first count value of the source clock signal and a second count value of the target clock signal; The judgment module is used to determine whether the original clock source is in an abnormal state based on the first count value and the second count value; An update module is used to update the frequency parameters based on the first count value and the second count value when the original clock source is in a non-abnormal state, so that the frequency adjustment unit generates a subsequent target clock signal based on the updated frequency parameters.

9. An electronic device, characterized in that, include: one or more processors; A storage device having stored one or more programs thereon, which, when executed by the one or more processors, cause the one or more processors to implement the method according to any one of claims 1-7; One or more I / O interfaces are connected between the processor and the memory and configured to enable information interaction between the processor and the memory.

10. A computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements the method according to any one of claims 1-7.

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