System and method, device and medium for synchronizing high-speed clock based on low-speed clock
By adjusting the internal clock cycle through the arbiter and processor of the external clock source and receiving device, the misalignment problem caused by clock frequency deviation in ATE test equipment is solved, achieving low-complexity cross-board clock synchronization and ensuring the normal operation of the equipment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHUHAI CORE IND MEASUREMENT & CONTROL CO LTD
- Filing Date
- 2024-10-31
- Publication Date
- 2026-05-12
AI Technical Summary
In multi-board ATE testing equipment, the clock source on different boards has frequency offset, which leads to control and data misalignment and affects the normal operation of the equipment. Existing clock synchronization solutions are complex and difficult to design.
An external clock source is used to synchronize with multiple receiving devices through a synchronization arbiter, offset processing module, and synchronization processor. By adjusting the processing cycle of the internal clock, it is synchronized with the external clock, thus reducing hardware complexity.
It achieves cross-board clock synchronization without restricting the relationship between internal and external clocks, reducing hardware complexity and cost, and ensuring clock synchronization accuracy during long-term operation.
Smart Images
Figure CN119556766B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of clock synchronization technology for ATE test equipment, and particularly to a system, method, apparatus, and medium for synchronizing a high-speed clock with a low-speed clock. Background Technology
[0002] In ATE test equipment with multiple boards, different boards use different clock sources, and even if the clock sources are at the same frequency, there will be a certain frequency offset. Due to the presence of frequency offset, after long-term use, the clocks on different boards will become misaligned, causing control and data misalignment between boards, resulting in control asynchrony and data asynchrony, which affects the normal operation of the ATE test equipment.
[0003] Some related technologies have proposed schemes that use external clocks to synchronize the internal clock of a circuit board. For example, one external clock can synchronize one internal clock, or multiple external clock sources can be synchronized to an internal clock domain. However, this requires that the external clock and the internal clock be in phase, and that the frequency of the internal clock be an integer multiple of the external clock. Therefore, the clock synchronization of these technologies places high demands on both the external clock and the internal clock, leading to increased hardware complexity and design difficulty. Summary of the Invention
[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a system, method, device, and medium for synchronizing a high-speed clock with a low-speed clock, which can realize the synchronization of multiple internal clocks by one external clock without any limiting relationship between internal and external clocks, thereby reducing hardware complexity.
[0005] In a first aspect, embodiments of the present invention provide a system for synchronizing a high-speed clock based on a low-speed clock, comprising:
[0006] An external clock source, which is used to output an external clock;
[0007] Multiple receiving devices are provided, each including an external clock rising edge acquisition unit, an internal clock counter, a synchronization arbiter, an offset processing module, a synchronization processor, and a post-processor. The external clock rising edge acquisition unit is connected to an external clock source. The external clock rising edge acquisition unit and the internal clock counter are connected to the input of the synchronization arbiter. The output of the synchronization arbiter is connected to the input of the offset processing module. The output of the offset processing module is connected to the synchronization processor. The synchronization processor is connected to the post-processor.
[0008] The external clock rising edge collector responds to the rising edge of the external clock by outputting a rising edge acquisition signal to the synchronous arbiter. The internal clock counter is used to count the trigger edges of the internal clock. When the count value of the trigger edge reaches a preset period count value, a period completion signal is output. The period count value is used to characterize the multiple between the period of the external clock and the period of the internal clock. The period of the external clock is greater than the period of the internal clock.
[0009] The synchronization arbiter is used to trigger the offset processing module to send a synchronization trigger signal to the synchronization processor when the cycle completion signal and the rising edge acquisition signal arrive at different times.
[0010] In response to the synchronization trigger signal, the synchronization processor adjusts the processing cycle of the subsequent processor to be the same as the external clock based on the offset between the internal clock and the external clock.
[0011] According to some embodiments of the present invention, the offset processing module includes a stop processor, the output of which is connected to the input of the synchronization processor, and the input of which is connected to the output of the synchronization arbitrator;
[0012] Wherein, when the rising edge acquisition signal arrives at the synchronization arbitrator later than the cycle completion signal, the synchronization arbitrator is used to trigger the stop processor to output a pause enable signal to the synchronization processor. The synchronization processor responds to the pause enable signal, determines the pause duration based on the arrival time difference between the cycle completion signal and the rising edge acquisition signal, and controls the subsequent processor to pause operation based on the pause duration.
[0013] When the external clock rising edge acquisition device detects the next rising edge acquisition signal, the synchronous processor restarts the next processing cycle of the subsequent processor.
[0014] According to some embodiments of the present invention, the offset processing module further includes an advance processor, the output of which is connected to the input of the synchronization processor, and the input of which is connected to the output of the synchronization arbitrator.
[0015] Wherein, when the rising edge acquisition signal arrives at the synchronization arbitrator earlier than the cycle completion signal, the synchronization arbitrator triggers the advance processor to output an advance enable signal to the synchronization processor. The synchronization processor, in response to the advance enable signal, determines the advance duration based on the arrival time difference, determines the target item for the current cycle based on the advance duration, and controls the subsequent processor to process the target item in advance and start the next processing cycle. According to some embodiments of the present invention, the external clock rising edge acquisition device is connected to the internal clock counter, and the internal clock counter clears the count value of the trigger edge in response to the rising edge acquisition signal.
[0016] Secondly, embodiments of the present invention provide a method for synchronizing a high-speed clock based on a low-speed clock, applied to the system for synchronizing a high-speed clock based on a low-speed clock as described in the first aspect, the method comprising:
[0017] An external clock source sends an external clock to each receiving device. After detecting the rising edge of the external clock by an external clock rising edge collector, it sends a rising edge acquisition signal to the synchronization arbiter.
[0018] The trigger edges of the internal clock are counted by an internal clock counter. When the count value of the trigger edge reaches a preset period count value, a period completion signal is sent to the synchronization arbitrator. The period count value is used to characterize the multiple between the period of the external clock and the period of the internal clock, and the period of the external clock is greater than the period of the internal clock.
[0019] When the rising edge acquisition signal and the cycle completion signal arrive at different times, the synchronization arbiter triggers the offset processing module to send a synchronization trigger signal to the synchronization processor. The synchronization processor adjusts the processing cycle of the subsequent processor to be the same as the external clock based on the offset between the internal clock and the external clock.
[0020] According to some embodiments of the present invention, the offset processing module includes a stop processor and an advance processor, the output terminal of the stop processor and the output terminal of the advance processor are respectively connected to the input terminal of the synchronization processor, and the input terminal of the stop processor and the input terminal of the advance processor are respectively connected to the output terminal of the synchronization arbitrator.
[0021] The synchronization arbitrator trigger offset processing module sends a synchronization trigger signal to the synchronization processor. Based on the offset between the internal clock and the external clock, the synchronization processor adjusts the processing cycle of the subsequent processor to be the same as the external clock, including:
[0022] When the rising edge acquisition signal arrives at the synchronization arbitrator later than the period completion signal, the synchronization arbitrator triggers the stop processor to output a pause enable signal to the synchronization processor;
[0023] The synchronous processor responds to the pause enable signal, determines the pause duration based on the arrival time difference between the cycle completion signal and the rising edge acquisition signal, and controls the subsequent processor to pause operation based on the pause duration;
[0024] When the external clock rising edge acquisition device detects the next rising edge acquisition signal, the synchronous processor restarts the next processing cycle of the subsequent processor.
[0025] According to some embodiments of the present invention, the synchronization arbitrator trigger offset processing module sends a synchronization trigger signal to the synchronization processor, and the synchronization processor adjusts the processing cycle of the subsequent processor to be the same as the external clock based on the offset between the internal clock and the external clock, including:
[0026] When the rising edge acquisition signal arrives at the synchronization arbiter earlier than the period completion signal, the synchronization arbiter triggers the advance processor to output the advance enable signal to the synchronization processor.
[0027] The synchronization processor responds to the advance enable signal and determines the advance duration based on the arrival time difference;
[0028] Based on the advance time, the target item for the current cycle is determined, and the subsequent processor is controlled to process the target item in advance and start the next processing cycle.
[0029] According to some embodiments of the present invention, the external clock rising edge acquisition device is connected to the internal clock counter, and after sending a cycle completion signal to the synchronization arbitrator, the method further includes:
[0030] The internal clock counter stops counting;
[0031] When the rising edge acquisition signal is obtained, the current count value of the trigger edge is cleared and the counting is restarted.
[0032] Thirdly, embodiments of the present invention provide an apparatus for synchronizing a high-speed clock based on a low-speed clock, including at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor, the instructions being executed by the at least one control processor to enable the at least one control processor to execute the system for synchronizing a high-speed clock based on a low-speed clock as described in the second aspect above.
[0033] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer-executable instructions for executing the system based on low-speed clock synchronization with a high-speed clock as described in the first aspect above.
[0034] The system based on synchronizing a low-speed clock with a high-speed clock according to an embodiment of the present invention has at least the following beneficial effects: an external clock source, wherein the external clock source is used to output an external clock; multiple receiving devices, wherein each receiving device includes an external clock rising edge acquisition unit, an internal clock counter, a synchronization arbitrator, an offset processing module, a synchronization processor, and a post-processor; the external clock rising edge acquisition unit is connected to the external clock source; the external clock rising edge acquisition unit and the internal clock counter are connected to the input terminal of the synchronization arbitrator; the output terminal of the synchronization arbitrator is connected to the input terminal of the offset processing module; the output terminal of the offset processing module is connected to the synchronization processor; and the synchronization processor is connected to the post-processor; wherein the external clock rising edge acquisition unit responds to the external clock source. The rising edge of the clock outputs a rising edge acquisition signal to the synchronization arbiter. The internal clock counter counts the trigger edges of the internal clock. When the trigger edge count reaches a preset period count value, a period completion signal is output. The period count value represents the multiple between the period of the external clock and the period of the internal clock, where the period of the external clock is greater than the period of the internal clock. The synchronization arbiter triggers the offset processing module to send a synchronization trigger signal to the synchronization processor when the period completion signal and the rising edge acquisition signal arrive at different times. The synchronization processor, in response to the synchronization trigger signal, adjusts the processing cycle of the subsequent processor to be the same as the external clock based on the offset between the internal clock and the external clock. According to the technical solution of this embodiment, each receiving device outputs a period completion signal based on its own period count value. The synchronization arbiter determines a frequency offset by the difference in arrival times between the period completion signal and the rising edge acquisition signal. Period synchronization is achieved through the synchronization processor, thereby enabling cross-board synchronization of any number of receiving devices with a single external clock, reducing hardware complexity and cost. Attached Figure Description
[0035] Figure 1 This is a clock connection diagram of an external clock and a receiving device provided in one embodiment of the present invention;
[0036] Figure 2 This is a functional module connection diagram of a receiving device provided in another embodiment of the present invention;
[0037] Figure 3 This is a flowchart of a system based on synchronizing a low-speed clock with a high-speed clock, provided in another embodiment of the present invention.
[0038] Figure 4 This is a flowchart of a method for synchronizing a high-speed clock based on a low-speed clock, provided in another embodiment of the present invention;
[0039] Figure 5 This is a structural diagram of a device based on synchronizing a low-speed clock with a high-speed clock, provided in another embodiment of the present invention.
[0040] Explanation of reference numerals in the attached figures:
[0041] 10 External clock source; 20 Receiving device; 21 External clock rising edge acquisition unit; 22 Internal clock counter; 23 Synchronization arbiter; 24 Stop processor; 25 Advance processor; 26 Synchronization processor Detailed Implementation
[0042] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0043] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0044] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.
[0045] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.
[0046] This invention provides a system, method, apparatus, and medium for synchronizing a high-speed clock based on a low-speed clock. The system includes: an external clock source for outputting an external clock; and multiple receiving devices, each including an external clock rising edge acquisition unit, an internal clock counter, a synchronization arbitrator, an offset processing module, a synchronization processor, and a post-processor. The external clock rising edge acquisition unit is connected to the external clock source. The external clock rising edge acquisition unit and the internal clock counter are connected to the input of the synchronization arbitrator. The output of the synchronization arbitrator is connected to the input of the offset processing module. The output of the offset processing module is connected to the synchronization processor. The synchronization processor is connected to the post-processor. The clock rising edge acquisition unit responds to the rising edge of the external clock by outputting a rising edge acquisition signal to the synchronization arbiter. The internal clock counter counts the trigger edges of the internal clock. When the trigger edge count reaches a preset period count value, it outputs a period completion signal. The period count value represents the multiple between the period of the external clock and the period of the internal clock, where the period of the external clock is greater than the period of the internal clock. The synchronization arbiter triggers the offset processing module to send a synchronization trigger signal to the synchronization processor when the period completion signal and the rising edge acquisition signal arrive at different times. The synchronization processor, responding to the synchronization trigger signal, adjusts the processing cycle of the subsequent processor to be the same as the external clock based on the offset between the internal and external clocks. According to the technical solution of this embodiment, each receiving device outputs a period completion signal based on its own period count value. The synchronization arbiter determines a frequency offset by the difference in arrival times between the period completion signal and the rising edge acquisition signal. Period synchronization is achieved through the synchronization processor, thereby enabling cross-board synchronization of any number of receiving devices with a single external clock, reducing hardware complexity and cost.
[0047] First, refer to Figures 1 to 3 The system for synchronizing a low-speed clock with a high-speed clock, provided in this application embodiment, includes:
[0048] External clock source 10 is used to output an external clock.
[0049] Multiple receiving devices 20, each receiving device 20 includes an external clock rising edge acquisition unit 21, an internal clock counter 22, a synchronization arbiter 22, an offset processing module, a synchronization processor 26, and a post-processor. The external clock rising edge acquisition unit 21 is connected to an external clock source 10. The external clock rising edge acquisition unit 21 and the internal clock counter 22 are connected to the input of the synchronization arbiter 22. The output of the synchronization arbiter 22 is connected to the input of the offset processing module. The output of the offset processing module is connected to the synchronization processor 26. The synchronization processor 26 is connected to the post-processor.
[0050] Among them, the external clock rising edge acquisition unit 21 responds to the rising edge of the external clock and outputs the rising edge acquisition signal to the synchronous arbiter 22. The internal clock counter 22 is used to count the trigger edge of the internal clock. When the count value of the trigger edge reaches the preset period count value, the period completion signal is output. The period count value is used to characterize the multiple between the period of the external clock and the period of the internal clock. The period of the external clock is greater than the period of the internal clock.
[0051] Among them, the synchronization arbiter 22 is used to trigger the offset processing module to send a synchronization trigger signal to the synchronization processor 26 when the cycle completion signal and the rising edge acquisition signal arrive at different times.
[0052] In response to the synchronization trigger signal, the synchronous processor 26 adjusts the processing cycle of the subsequent processor to be the same as the external clock based on the offset between the internal clock and the external clock.
[0053] It should be noted that the external clock source 10 and the receiving device 20 in this embodiment have a one-to-many relationship, that is, one external clock source 10 is connected to multiple receiving devices 20, and the external clock generated by the external clock source 10 is simultaneously input to each receiving device 20. Each receiving device 20 independently executes the clock synchronization scheme of this embodiment, which can reduce the number of external clock sources 10 and simplify hardware complexity.
[0054] It should be noted that the external clock rising edge acquisition unit 21 can detect the rising edge by striking two clock cycles. After striking the external clock, it determines whether the level between the two cycles conforms to the rising edge rule. If it does, it generates a rising edge acquisition signal and sends the rising edge acquisition signal to the synchronization arbiter 22.
[0055] It should be noted that the receiving device 20 is equipped with an internal clock source, which provides the internal clock. The internal clock counter 22 is used to count the trigger edges of the internal clock, including rising and falling edges. Each time a trigger edge is detected, a count is performed. After the count is completed according to the period count value, a period completion signal is generated and sent to the synchronization arbitrator 22.
[0056] It should be noted that the external clock in this embodiment is a low-speed clock, and it is only necessary to ensure that the external clock is a clock of equal length. The internal clock is a high-speed clock, that is, the period of the external clock is greater than that of the internal clock. The period count value can be obtained by dividing the period of the external clock by the period of the internal clock, and the period count value is an integer greater than 1. The number of trigger edges of the internal clock between two rising edges should be equal to the period count value.
[0057] Therefore, if the internal and external clocks are synchronized, it can be determined that the rising edge acquisition signal and the cycle completion signal are generated simultaneously, and the synchronization arbiter 22 will receive both signals at the same time. In this embodiment, the simultaneous receipt of the rising edge acquisition signal and the cycle completion signal by the synchronization arbiter 22 is used as the basis for determining the synchronization of the internal and external clocks. When the two signals arrive synchronously, it is determined that the internal and external clocks are synchronized, and the judgment of the next cycle continues. If the two signals do not arrive synchronously, there is a deviation between the internal and external clocks. The offset processing module sends a synchronization trigger signal to the synchronization processor 26, and the synchronization processor 26 controls the subsequent processor to pause or advance processing, so that the subsequent processor can align with the external clock.
[0058] Through the technical solution of this embodiment, each receiving device 20 can set a period count value according to the period multiple of the internal and external clocks. After detecting the rising edge of the external clock, a rising edge acquisition signal is triggered. After the period count is completed based on the trigger edge of the internal clock, a period completion signal is triggered. When the rising edge acquisition signal and the period completion signal are different, they reach the synchronization arbitrator 22. The synchronization arbitrator 22 determines that the internal and external clocks are out of sync and sends a synchronization trigger signal to the synchronization processor 26 through the offset processing module. The synchronization processor 26 suspends or advances the processing of the subsequent processor, so that the processing cycle of the subsequent processor is aligned with the period of the external clock. Thus, the high-speed internal clock is synchronized by the low-speed external clock. Each receiving device 20 can independently run the above steps according to its own internal clock, realizing the synchronization of multiple receiving devices 20 by one external clock, simplifying the hardware equipment, and still achieving the accuracy of clock synchronization under long-term operation.
[0059] Additionally, in one embodiment, reference is made to Figure 2 and Figure 3 The offset processing module includes a stop processor 24, the output of which is connected to the input of a synchronization processor 26, and the input of which is connected to the output of a synchronization arbiter 22.
[0060] When the rising edge acquisition signal arrives at the synchronous arbiter 22 later than the cycle completion signal, the synchronous arbiter 22 is used to trigger the stop processor 24 to output a pause enable signal to the synchronous processor 26. The synchronous processor 26 responds to the pause enable signal, determines the pause duration based on the arrival time difference between the cycle completion signal and the rising edge acquisition signal, and controls the subsequent processor to pause operation based on the pause duration.
[0061] When the external clock rising edge acquisition unit 21 detects the next rising edge acquisition signal, the synchronous processor 26 restarts the next processing cycle of the subsequent processor.
[0062] It should be noted that, as Figure 2 and Figure 3As shown, when the rising edge acquisition signal arrives at the synchronization arbiter 22 later than the cycle completion signal, it is likely due to factors such as frequency offset, cycle jitter, or acquisition differences causing the external clock to run slower than the internal clock, requiring a pause in the subsequent processor for a period of time. In this embodiment, the synchronization arbiter 22, based on the condition that the rising edge acquisition signal arrives later than the cycle completion signal, sends a pause enable signal to the synchronization processor 26 via the stop processor 24. The synchronization processor 26 determines the pause duration based on the arrival time difference between the cycle completion signal and the rising edge acquisition signal, controlling the subsequent processor to pause all processing until the external clock rising edge acquisition device 21 detects the next rising edge of the external clock, at which point the subsequent processor restarts, ensuring that the processing cycle of the subsequent processor is consistent with the external clock cycle, thereby achieving internal and external clock alignment.
[0063] Additionally, in one embodiment, reference is made to Figure 2 and Figure 3 The offset processing module also includes an advance processor 25, the output of which is connected to the input of the synchronization processor 26, and the input of the advance processor 25 is connected to the output of the synchronization arbitrator 22.
[0064] When the rising edge acquisition signal arrives at the synchronization arbitrator 22 earlier than the cycle completion signal, the synchronization arbitrator 22 triggers the advance processor 25 to output an advance enable signal to the synchronization processor 26. The synchronization processor 26 responds to the advance enable signal, determines the advance duration based on the arrival time difference, determines the target item of the current cycle based on the advance duration, controls the subsequent processor to process the target item in advance, and starts the next processing cycle.
[0065] It should be noted that, as Figure 2 and Figure 3 As shown, when the rising edge acquisition signal arrives at the synchronization arbiter 22 earlier than the cycle completion signal, it is likely due to factors such as frequency offset, cycle jitter, and acquisition differences causing the external clock to run faster than the internal clock. In this embodiment, the synchronization arbiter 22, based on the condition that the rising edge acquisition signal arrives earlier than the cycle completion signal, sends an advance enable signal to the synchronization processor 26 through the advance processor 25. The synchronization processor 26 determines the advance duration based on the arrival time difference between the cycle completion signal and the rising edge acquisition signal, identifies all processing items within the advance duration as target items, controls the subsequent processor to advance all target items, and immediately starts the processing of the next cycle, thereby achieving internal and external clock alignment.
[0066] Additionally, in one embodiment, reference is made to Figure 2 and Figure 3 The external clock rising edge acquisition unit 21 is connected to the internal clock counter 22, and the internal clock counter 22 responds to the count value of the rising edge acquisition signal to clear the trigger edge.
[0067] It should be noted that the internal clock counter 22 is reset and recounted in response to the rising edge acquisition signal. When the internal clock is synchronized with the external clock, the count value is equal to the period count value when the rising edge acquisition signal arrives. Therefore, the internal clock can count in a complete cycle.
[0068] It should be noted that if the external clock is earlier than the internal clock, the rising edge acquisition signal will be detected before the internal clock counter 22 completes the counting of the cycle count value. At this time, it will be directly cleared and a new count will be executed. This can be combined with the advance processing operation in the above embodiment to make the internal and external clocks aligned, and ensure that the cycle completion signal and the rising edge acquisition signal arrive at the synchronization arbiter 22 synchronously in the next cycle.
[0069] It should be noted that if the external clock is later than the internal clock, after the internal clock counter 22 completes the counting based on the period count value, it pauses the counting and waits for the rising edge acquisition signal. After the rising edge acquisition signal is obtained, it is cleared and a new counting is performed. This can work with the pause processing operation in the above embodiment to make the internal and external clocks aligned, and ensure that the period completion signal and the rising edge acquisition signal arrive at the synchronization arbiter 22 synchronously in the next period.
[0070] In addition, embodiments of the present invention provide a method for synchronizing a high-speed clock based on a low-speed clock, applicable to... Figures 1 to 3 The system shown in the embodiment is based on synchronizing a low-speed clock with a high-speed clock, with reference to... Figure 4 The method includes, but is not limited to, the following steps:
[0071] S10, the external clock source sends the external clock to each receiving device, and after detecting the rising edge of the external clock by the external clock rising edge collector, it sends the rising edge acquisition signal to the synchronization arbitrator.
[0072] S20: The internal clock trigger edge is counted by the internal clock counter. When the count value of the trigger edge reaches the preset period count value, a period completion signal is sent to the synchronization arbitrator. The period count value is used to characterize the multiple between the period of the external clock and the period of the internal clock. The period of the external clock is greater than the period of the internal clock.
[0073] S30, when the rising edge acquisition signal and the cycle completion signal arrive at different times, the synchronous arbiter triggers the offset processing module to send a synchronous trigger signal to the synchronous processor. Based on the offset between the internal clock and the external clock, the synchronous processor adjusts the processing cycle of the subsequent processor to be the same as the external clock.
[0074] It should be noted that the technical principle of clock synchronization based on the internal functional modules of the receiving device can be found in [reference needed]. Figures 1 to 3 The description of the illustrated embodiments will not be repeated here.
[0075] The technical solution of this embodiment enables each receiving device to set a period count value according to the multiple of the internal and external clock periods. After detecting the rising edge of the external clock, a rising edge acquisition signal is triggered. After the period count is completed based on the trigger edge of the internal clock, a period completion signal is triggered. When the rising edge acquisition signal and the period completion signal are different, they reach the synchronization arbitrator. The synchronization arbitrator determines that the internal and external clocks are out of sync and sends a synchronization trigger signal to the synchronization processor through the offset processing module. The synchronization processor pauses or advances the processing of the subsequent processor, so that the processing cycle of the subsequent processor is aligned with the period of the external clock. Thus, the high-speed internal clock is synchronized by the low-speed external clock. Each receiving device can independently run the above steps according to its own internal clock, realizing the synchronization of multiple receiving devices by one external clock, simplifying the hardware, and still achieving accurate clock synchronization under long-term operation.
[0076] In another embodiment, step S30 may include, but is not limited to, the following steps:
[0077] S311, when the rising edge acquisition signal arrives at the synchronous arbiter later than the period completion signal, the synchronous arbiter triggers the stop processor to output a pause enable signal to the synchronous processor;
[0078] S312, the synchronous processor responds to the pause enable signal, determines the pause duration based on the arrival time difference between the period completion signal and the rising edge acquisition signal, and controls the subsequent processor to pause operation based on the pause duration;
[0079] S313: When the external clock rises, the acquisition unit detects the next rising edge acquisition signal and restarts the next processing cycle of the subsequent processor through the synchronous processor.
[0080] It should be noted that the principle of using a stop processor and a synchronization arbiter to pause the subsequent processor to achieve clock synchronization can be found in the above description. Figure 2 and Figure 3 The description of the illustrated embodiments will not be repeated here.
[0081] In another embodiment, step S30 may include, but is not limited to, the following steps:
[0082] S321, when the rising edge acquisition signal arrives at the synchronous arbiter earlier than the period completion signal, the synchronous arbiter triggers the advance processor to output the advance enable signal to the synchronous processor.
[0083] S322, the synchronous processor responds to the advance enable signal and determines the advance duration based on the arrival time difference;
[0084] S323 determines the target items for the current cycle based on the advance time, controls the subsequent processor to process the target items in advance and start the next processing cycle.
[0085] It should be noted that the principle of using an advance processor and a synchronization arbiter to perform advance processing on subsequent processors to achieve clock synchronization can be referred to the above. Figure 2 and Figure 3 The description of the illustrated embodiments will not be repeated here.
[0086] In another embodiment, the external clock rising edge acquisition unit is connected to the internal clock counter. After step S20 is completed, the following steps are included, but are not limited to:
[0087] S21, the internal clock counter stops counting;
[0088] S22, when a rising edge acquisition signal is obtained, clear the current trigger edge count value and restart the count.
[0089] It should be noted that the principle of stopping and restarting the internal clock counter can be referred to the above. Figure 2 and Figure 3 The description of the illustrated embodiments will not be repeated here.
[0090] like Figure 5 As shown, Figure 5 This is a structural diagram of a device for synchronizing a low-speed clock with a high-speed clock according to an embodiment of the present invention. The present invention also provides a device for synchronizing a low-speed clock with a high-speed clock, comprising:
[0091] The processor 501 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.
[0092] The memory 502 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 502 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 502 and is called and executed by the processor 501 to execute the method of synchronizing a low-speed clock with a high-speed clock according to the embodiments of this application.
[0093] The input / output interface 503 is used to implement information input and output;
[0094] The communication interface 504 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).
[0095] Bus 505 transmits information between various components of the device (e.g., processor 501, memory 502, input / output interface 503, and communication interface 504);
[0096] The processor 501, memory 502, input / output interface 503, and communication interface 504 are connected to each other within the device via bus 505.
[0097] This application also provides an electronic device, including the device described above for synchronizing a high-speed clock with a low-speed clock.
[0098] This application also provides a storage medium, which is a computer-readable storage medium, storing a computer program that, when executed by a processor, implements the above-described method for synchronizing a high-speed clock based on a low-speed clock.
[0099] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0100] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
[0101] The above provides a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.
Claims
1. A system for synchronizing a low-speed clock with a high-speed clock, characterized in that, include: An external clock source, which is used to output an external clock; Multiple receiving devices are provided, each including an external clock rising edge acquisition unit, an internal clock counter, a synchronization arbiter, an offset processing module, a synchronization processor, and a post-processor. The external clock rising edge acquisition unit is connected to an external clock source. The external clock rising edge acquisition unit and the internal clock counter are connected to the input of the synchronization arbiter. The output of the synchronization arbiter is connected to the input of the offset processing module. The output of the offset processing module is connected to the synchronization processor. The synchronization processor is connected to the post-processor. The external clock rising edge collector responds to the rising edge of the external clock by outputting a rising edge acquisition signal to the synchronous arbiter. The internal clock counter is used to count the trigger edges of the internal clock. When the count value of the trigger edge reaches a preset period count value, a period completion signal is output. The period count value is used to characterize the multiple between the period of the external clock and the period of the internal clock. The period of the external clock is greater than the period of the internal clock. The synchronization arbiter is used to trigger the offset processing module to send a synchronization trigger signal to the synchronization processor when the cycle completion signal and the rising edge acquisition signal arrive at different times. The synchronous processor, in response to the synchronous trigger signal, adjusts the processing cycle of the subsequent processor to be the same as the external clock based on the offset between the internal clock and the external clock. The offset processing module includes a stop processor, the output of which is connected to the input of the synchronization processor, and the input of which is connected to the output of the synchronization arbitrator. Wherein, when the rising edge acquisition signal arrives at the synchronization arbitrator later than the cycle completion signal, the synchronization arbitrator is used to trigger the stop processor to output a pause enable signal to the synchronization processor. The synchronization processor responds to the pause enable signal, determines the pause duration based on the arrival time difference between the cycle completion signal and the rising edge acquisition signal, and controls the subsequent processor to pause operation based on the pause duration. When the external clock rising edge acquisition device detects the next rising edge acquisition signal, the synchronous processor restarts the next processing cycle of the subsequent processor. The offset processing module further includes an advance processor, the output of which is connected to the input of the synchronization processor, and the input of which is connected to the output of the synchronization arbitrator. Wherein, when the rising edge acquisition signal arrives at the synchronization arbitrator earlier than the cycle completion signal, the synchronization arbitrator is used to trigger the advance processor to output an advance enable signal to the synchronization processor. The synchronization processor responds to the advance enable signal, determines the advance duration based on the arrival time difference, determines the target item of the current cycle based on the advance duration, controls the subsequent processor to process the target item in advance and start the next processing cycle.
2. The system based on synchronizing a low-speed clock with a high-speed clock according to claim 1, characterized in that, The external clock rising edge acquisition unit is connected to the internal clock counter. The internal clock counter stops counting after outputting the cycle completion signal and restarts counting after clearing the count value of the trigger edge in response to the rising edge acquisition signal.
3. A method for synchronizing a high-speed clock based on a low-speed clock, characterized in that, The method, applied to the system based on synchronizing a low-speed clock with a high-speed clock as described in any one of claims 1 to 2, comprises: An external clock source sends an external clock to each receiving device. After detecting the rising edge of the external clock by an external clock rising edge collector, it sends a rising edge acquisition signal to the synchronization arbiter. The trigger edges of the internal clock are counted by an internal clock counter. When the count value of the trigger edge reaches a preset period count value, a period completion signal is sent to the synchronization arbitrator. The period count value is used to characterize the multiple between the period of the external clock and the period of the internal clock, and the period of the external clock is greater than the period of the internal clock. When the rising edge acquisition signal and the cycle completion signal arrive at different times, the synchronization arbiter triggers the offset processing module to send a synchronization trigger signal to the synchronization processor. The synchronization processor adjusts the processing cycle of the subsequent processor to be the same as the external clock based on the offset between the internal clock and the external clock. The offset processing module includes a stop processor and an advance processor. The output terminals of the stop processor and the advance processor are respectively connected to the input terminals of the synchronization processor, and the input terminals of the stop processor and the advance processor are respectively connected to the output terminals of the synchronization arbitrator. The synchronization arbitrator trigger offset processing module sends a synchronization trigger signal to the synchronization processor. Based on the offset between the internal clock and the external clock, the synchronization processor adjusts the processing cycle of the subsequent processor to be the same as the external clock, including: When the rising edge acquisition signal arrives at the synchronization arbitrator later than the period completion signal, the synchronization arbitrator triggers the stop processor to output a pause enable signal to the synchronization processor; The synchronous processor responds to the pause enable signal, determines the pause duration based on the arrival time difference between the cycle completion signal and the rising edge acquisition signal, and controls the subsequent processor to pause operation based on the pause duration; When the external clock rising edge acquisition device detects the next rising edge acquisition signal, the synchronous processor restarts the next processing cycle of the subsequent processor. The synchronization arbitrator trigger offset processing module sends a synchronization trigger signal to the synchronization processor. Based on the offset between the internal clock and the external clock, the synchronization processor adjusts the processing cycle of the subsequent processor to be the same as the external clock, including: When the rising edge acquisition signal arrives at the synchronization arbiter earlier than the period completion signal, the synchronization arbiter triggers the advance processor to output an advance enable signal to the synchronization processor. The synchronization processor responds to the advance enable signal and determines the advance duration based on the arrival time difference; Based on the advance time, the target item for the current cycle is determined, and the subsequent processor is controlled to process the target item in advance and start the next processing cycle.
4. The method for synchronizing a high-speed clock based on a low-speed clock according to claim 3, characterized in that, The external clock rising edge acquisition unit is connected to the internal clock counter. After sending a cycle completion signal to the synchronization arbitrator, the method further includes: The internal clock counter stops counting; When the rising edge acquisition signal is obtained, the current count value of the trigger edge is cleared and the counting is restarted.
5. A device for synchronizing a high-speed clock based on a low-speed clock, characterized in that, It includes at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor, which, when executed by the at least one control processor, enable the at least one control processor to perform the method of synchronizing a high-speed clock based on a low-speed clock as described in any one of claims 3 to 4.
6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the method of synchronizing a high-speed clock based on a low-speed clock as described in any one of claims 3 to 4.