A Method and System for Saving Power-off Data of a New Energy Commercial Vehicle Domain Controller

Abstract

The present invention relates to a power-off data storage system and method for a new energy commercial vehicle domain controller, including: a storage battery, an N-channel MOS transistor Q1 connected to the storage battery, a single-chip microcomputer, and a driving circuit. The N-channel MOS transistor Q1 is connected to the single-chip microcomputer through a power supply circuit, and the single-chip microcomputer controls the output end of the driving circuit to be connected to the gate of the N-channel MOS transistor; to achieve reverse connection protection, the ON gear signal is connected to an NPN transistor Q2 and a resistor R2 respectively after passing through a resistor R1, and the NPN transistor Q2 is connected to the power supply circuit through a current limiting resistor R3; a PNP transistor Q3 is connected to the power supply circuit, the PNP transistor Q3 is connected to the NPN transistor Q2 through a resistor R4, the PNP transistor Q3 is connected to a series-connected resistor R5 and a resistor R6, the resistor R6 is connected to the ground terminal, and the voltage acquisition IO1 port of the single-chip microcomputer is connected to the resistor R5. By referring to the power supply voltage collected by the single-chip microcomputer IO port and combining the method of a hysteresis comparator, the hysteresis effect can reduce the system sensitivity, increase the anti-interference ability, and ensure the stability of the signal.

Description

Technical Field

[0001] The present application relates to the technical field of new energy commercial vehicles, and particularly to a method and system for storing power-off data of a domain controller of a new energy commercial vehicle. Background Art

[0002] With the development of new energy vehicle electronic products, the demand for various signal data is increasing. Therefore, the amount of data transmitted between various electronic control units of the vehicle is increasing, resulting in the need for a longer time to save data when the vehicle system loses power. It is crucial to ensure the complete storage of data for the domain controller under any abnormal power-off conditions. In the existing disclosed power-off delay circuit, the input voltage is collected through a voltage dividing unit and then converted into a digital switching signal through a switching tube and sent to a single-chip microcomputer for judgment. This method has the following deficiencies:

[0003] 1. After the low-voltage power supply is powered on, if the power supply is sampled continuously to determine whether the system loses power, on the one hand, after the system loses power, the energy stored in the capacitor at the rear stage is released through the loop formed by the sampling resistor network, affecting the time for the system to save data. On the other hand, the system in new energy vehicles has strict requirements for power consumption. Since the loop of the sampling resistor network always exists, it may not meet the system requirements;

[0004] 2. Using the digital quantity fed back by the single-chip microcomputer IO port as the judgment basis for the power supply has relatively low reliability;

[0005] 3. The anti-reverse connection MOS tube uses a P-channel MOS tube, which has a relatively higher cost. The gate of the MOS tube is uncontrollable and it conducts continuously. When the energy at the rear stage is greater than that at the front stage, the energy stored in the capacitor is released to the front-stage power supply through the anti-reverse connection MOS tube, thus shortening the discharge time of the capacitor at the rear stage;

[0006] 4. Using a single-limit comparator circuit as the power-off level judgment scheme has high sensitivity and poor anti-interference ability. If there is a slight jitter in the input signal near the threshold voltage value, it will cause frequent jumps in the output level. Summary of the Invention

[0007] In view of the above problems, the present invention provides a method and system for storing power-off data of a domain controller of a new energy commercial vehicle that realizes anti-reverse connection protection through an N-channel MOS tube, refers to the power supply voltage collected by the single-chip microcomputer IO port, and combines the way of a hysteresis comparator. The hysteresis effect can reduce the system sensitivity, increase the anti-interference ability, and ensure the stability of the signal.

[0008] The present application is realized through the following technical solutions. A power-off data storage system for a domain controller of a new energy commercial vehicle includes:

[0009] A storage battery, an N-channel MOS transistor Q1 connected to the storage battery, a single-chip microcomputer, and a driving circuit. The N-channel MOS transistor Q1 is connected to the single-chip microcomputer through a power supply circuit, and the single-chip microcomputer controls the output end of the driving circuit to be connected to the gate of the N-channel MOS transistor;

[0010] It further includes an NPN transistor Q2, a PNP transistor Q3, and a comparator U1. The ON gear signal is connected to the resistor R2 connected in parallel between the base B and the emitter E of the NPN transistor Q2 after passing through the resistor R1. The collector C of the NPN transistor Q2 is connected to the power supply circuit through a current-limiting resistor R3. The emitter E of the NPN transistor Q2 and the resistor R2 are grounded;

[0011] The emitter E of the PNP transistor Q3 is connected to the power supply circuit. The base B of the PNP transistor Q3 is connected to the collector C of the NPN transistor Q2 through a resistor R4. The collector C of the PNP transistor Q3 is connected to the mutually series-connected resistor R5 and resistor R6. The resistor R6 is connected to the ground terminal, and the voltage acquisition IO1 port of the single-chip microcomputer is connected to the resistor R5;

[0012] The non-inverting input terminal of the comparator U1 is connected to the resistor R5, the inverting input terminal is connected to the current-limiting resistor R8 to the power-down reference voltage Vref terminal, and the output terminal of the comparator U1 is connected to the IO2 interface of the single-chip microcomputer.

[0013] Preferably, a resistor R7 is provided between the positive power supply terminal of the comparator U1 and the resistor R5.

[0014] Preferably, it further includes a capacitor C1. One end of the capacitor C1 is connected to the power supply circuit, and the other end is grounded.

[0015] A data storage method, including:

[0016] When the ON gear signal is at a high level, at this time the NPN transistor Q2 is turned on and the PNP transistor Q3 is turned on. At this time, the input voltage of the storage battery is divided by the mutually series-connected resistor R5 and resistor R6, and the voltage value after being divided by the resistor R6 is collected through the voltage acquisition IO1 port of the single-chip microcomputer. At the same time, the voltage after voltage division is compared with the power-down reference voltage Vref value after passing through the comparator U1. When the voltage value after voltage division is greater than the power-down reference voltage Vref value, the comparator U1 outputs a high-level signal to the single-chip microcomputer I02 port; when the voltage value after voltage division is less than the power-down reference voltage Vref value, the comparator U1 outputs a low-level signal to the single-chip microcomputer I02 port, and the single-chip microcomputer uses the values collected by the IO1 port and the I02 port as the initial conditions for judging the power supply state;

[0017] When the ON - gear signal is at a low level, at this time, neither the NPN transistor Q2 nor the PNP transistor Q3 is turned on. The single - chip microcomputer's I01 port samples the voltage value of the resistor R6, and the comparator U1 outputs a low - level signal to the single - chip microcomputer's I02 port. The single - chip microcomputer uses the values collected by the IO1 port and the I02 port as the initial conditions for judging the power supply state.

[0018] Preferably, after the voltage value collected by the single - chip microcomputer's IO1 port is AD - converted, it is judged whether the collected value is greater than or equal to 8.5V. When it is greater than or equal to 8.5V, the drive circuit outputs normally, and the MOS transistor Q1 conducts normally. When it is less than 8.5V, the gate of the MOS transistor Q1 is turned off, and it is judged whether the system goes into sleep power - down. If it is judged that the system goes into sleep power - down, the power - down data is saved.

[0019] Preferably, for the voltage value output by the comparator U1 collected by the single - chip microcomputer's I02 port, when the value collected by the I02 port is greater than or equal to 9.5V, the drive circuit outputs normally, and the MOS transistor Q1 conducts normally; when the value collected by the I02 port is less than 9.5V, it is continued to judge whether the collected value is greater than or equal to 8.5V. When it is greater than or equal to 8.5V, the drive circuit outputs normally, and the MOS transistor Q1 conducts normally. When it is less than 8.5V, the gate of the MOS transistor Q1 is turned off, and a preliminary judgment is made on whether the system goes into sleep power - down.

[0020] Preferably, the reference voltage Vref value is 9V.

[0021] Preferably, the upper - line voltage threshold and the lower - line voltage threshold of the comparator U1 are 8.5V and 9.5V respectively.

[0022] The beneficial effects of this application are:

[0023] 1. By monitoring the power supply state of the system, and then controlling the on - off state of the reverse - connection - preventing N - channel MOS transistor, the control of the capacitor discharge circuit at the rear stage is realized, and the power - down data saving time of the system is improved;

[0024] 2. For the system power - supply state judgment, referring to the power - supply voltage collected by the single - chip microcomputer's IO port and combined with the hysteresis comparator method, the hysteresis effect can reduce the system sensitivity, increase the anti - interference ability, and ensure the signal stability;

[0025] 3. Through the ON - gear signal, the power - supply voltage sampling of the system is controlled. When the system is in the sleep mode, the sampling circuit is in an open - circuit state, no energy loss occurs, and the standby power consumption of the system is effectively reduced;

[0026] 4. It can reduce the standby power consumption, effectively improve the time for data saving after the system power - down. The dual - acquisition method of analog quantity and digital quantity, combined with the good anti - interference ability of the hysteresis comparator, can improve the reliability of the system for power - down judgment. Brief Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0028] Figure 1 It is a schematic diagram of a power-off data storage system for a new energy commercial vehicle domain controller in an embodiment of the present invention;

[0029] Figure 2 It is a schematic diagram of a method for storing power-off data in an embodiment of the present invention. Detailed Embodiments

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art.

[0031] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known methods, systems, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0032] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0033] The flowcharts shown in the drawings are only illustrative and do not necessarily include all the content and operations / steps, nor are they necessarily executed in the described order. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined. Therefore, the actual execution order may change according to the actual situation.

[0034] As Figure 1 shown, a power-off data storage system for a new energy commercial vehicle domain controller includes:

[0035] A storage battery, an N-channel MOS transistor Q1 connected to the storage battery, a single-chip microcomputer, and a driving circuit. The N-channel MOS transistor Q1 is connected to the single-chip microcomputer through a power supply circuit, and the single-chip microcomputer controls the output end of the driving circuit to be connected to the gate of the N-channel MOS transistor;

[0036] During implementation, the vehicle storage battery and the domain controller are connected by a wire harness. The output voltage of the storage battery in the normal working state is 24V. The power supply voltage output by the storage battery is connected to the board-end connector of the domain controller circuit board through the wire harness, and then connected to the internal MOS transistor Q1 of the circuit board through the connector. Q1 is an N-channel MOS transistor for reverse connection protection. When the positive pole of the power supply is connected to the front end of Q1, the internal body diode of the MOS transistor Q1 is turned on at this time. The output voltage of the storage battery not only charges the energy storage capacitor C1 of the domain controller, but also is converted into the voltage required for the operation of each subsequent part of the circuit through the power supply circuit inside the domain controller, and is supplied to the single-chip microcomputer and other related circuits. The single-chip microcomputer controls the output of the driving circuit, and the output is given to the gate of the MOS transistor Q1. At this time, Q1 can be normally turned on, reducing the energy loss generated on Q1 when the power supply is working normally; when the negative pole of the power supply is connected to the front end of Q1, the MOS transistor Q1 is in a cut-off state at this time, and a closed loop cannot be formed between the input and the output, and the system cannot work normally, realizing the reverse connection protection of the power input of the system;

[0037] In this embodiment, the single-chip microcomputer controls the driving circuit to complete the control of the NMOS gate signal. When the power supply is powered off, the gate drive of the MOS transistor can be turned off. At this time, the MOS transistor is unidirectional conduction, and the energy can only flow from the front stage to the rear stage, preventing the energy of the rear stage from being released.

[0038] It also includes an NPN transistor Q2, a PNP transistor Q3, and a comparator U1. The ON gear signal is connected to the base B of the NPN transistor Q2 and the resistor R2 in parallel through the resistor R1 after passing through the resistor R1. The emitter E of the NPN transistor Q2 is connected to the power supply circuit through a current-limiting resistor R3, and the collector C of the NPN transistor Q2 and the resistor R2 are grounded; when the system is working normally, the ON gear signal is a high-level signal. This high-level signal is divided by the resistor R1 and the resistor R2. The voltage generated on the resistor R2 drops. At this time, the voltage at the base B terminal of the NPN transistor Q2 is greater than the voltage at the emitter E of the NPN transistor Q2. At this time, the NPN transistor Q2 is turned on. At this time, the current-limiting resistor R3 limits the current, and the collector C of the NPN transistor Q2 is grounded.

[0039] Since the emitter E of the PNP transistor Q3 is connected to the power supply circuit, the base B of the PNP transistor Q3 is connected to the emitter E of the NPN transistor Q2 through the resistor R4, the collector C of the PNP transistor Q3 is connected to the resistors R5 and R6 connected in series, the resistor R6 is connected to the ground terminal, and the voltage acquisition IO1 port of the single-chip microcomputer is connected to the resistor R5; therefore, when the NPN transistor Q2 is turned on, the left end of the resistor R4 is in a low-level state at this time, the NPN transistor Q2 is turned on, and the input voltage of the storage battery is divided by the resistors R5 and R6 after passing through the NPN transistor Q2. The voltage value generated after the voltage division by the resistor R6 is input to the voltage acquisition I01 port of the single-chip microcomputer to collect analog data of the input power supply voltage.

[0040] The positive power supply terminal of the comparator U1 is connected to the resistor R5, the negative power supply terminal is connected to the current-limiting resistor R8 and connected to the power-down reference voltage Vref terminal, and the output terminal of the comparator U1 is connected to the IO2 interface of the single-chip microcomputer. Since a resistor R7 is provided between the resistor R5 and the positive power supply terminal of the comparator U1, the voltage value generated after the voltage division of the resistor R6 is not only transmitted to the single-chip microcomputer but also given to the resistor R7. The other end of the resistor R7 is connected to the non-inverting input terminal of the comparator U1, and the inverting input terminal is connected to the power-down reference voltage Vref terminal through the current-limiting resistor R8. If the voltage value generated on R6 is greater than the reference value of the reference voltage Vref terminal, the comparator U1 outputs a high level to the IO2 port of the single-chip microcomputer, and the value collected by the single-chip microcomputer 102 port is used as the reference value for finally judging the power supply state of the system; if the voltage value generated on R6 is less than the reference value of the reference voltage Vref terminal, the comparator U1 outputs a low level to the IO2 port of the single-chip microcomputer, and the single-chip microcomputer refers to the value collected by the IO1 port as the reference value for finally judging the power supply state of the system.

[0041] When the external input ON signal does not exist, the ON signal is at a low level at this time. This signal is divided by the resistors R1 and R2, and the voltage value after the voltage division is still in a low-level state. At this time, the NPN transistor Q2 cannot be normally turned on and is in a cut-off state. The left end of the resistor R4 is connected to the power supply through the current-limiting resistor R3 and is in a high-level state. The PNP transistor Q3 cannot be normally turned on and is in a cut-off state. At this time, the resistors R5 and R6 are connected in series and then connected to the negative power supply, and a complete loop cannot be formed. The voltage value across the resistor R6 is close to 0V and is transmitted to the IO1 port of the single-chip microcomputer to collect and process analog data of the input power supply voltage; the non-inverting input terminal of the hysteresis comparator U1 is also in a power supply state close to 0V, so the voltage value generated on R6 is less than the reference voltage Vref, and the hysteresis comparator U1 outputs a low level to the IO2 port of the single-chip microcomputer. The single-chip microcomputer refers to the value collected by the IO1 port as the reference value for finally judging the power supply state of the system. If it is judged as the sleep power-down state, the output of the drive circuit is turned off, so that the MOS transistor Q1 is cut off, preventing the energy of the energy storage capacitor C1 at the back end of the anti-reverse connection MOS transistor from being consumed by the front-stage power supply.

[0042] In one embodiment, as Figure 2 shown, a method for saving power-off data of a new energy commercial vehicle domain controller is provided. In the normal working state, the voltage range value is 9 - 32V. First, the value of the power-off power reference voltage Vref terminal is set to 9V through hardware. The upper and lower voltage thresholds of the hysteresis of the hysteresis comparator U1 are set to 8.5V and 9.5V respectively through the resistor R7 and the resistor R9.

[0043] When the system is powered on, it is necessary to make a preliminary judgment on whether power-off data needs to be saved. At this time, due to normal operation, when the ON gear signal is at a high level, the NPN transistor Q2 is turned on and the PNP transistor Q3 is turned on. At this time, the input voltage of the battery is divided by the series-connected resistors R5 and R6, and the voltage value after being divided by the resistor R6 is collected through the voltage acquisition IO1 port of the single-chip microcomputer. Before the comparison, the data collected by the single-chip microcomputer I01 port is subjected to AD conversion. When the voltage value after voltage division is greater than the power-off reference voltage Vref value, that is, greater than 8.5V, the drive circuit inputs normally, and the MOS transistor Q1 can be turned on normally. Otherwise, the gate drive of the MOS transistor is turned off;

[0044] At the same time, the voltage after voltage division is compared with the power-off reference voltage Vref value after passing through the comparator U1. Before the comparison, the comparator U1 outputs a high-level signal to the single-chip microcomputer I02 port; during the comparison, if it is greater than or equal to 9.5V, it is in the normal power supply state, the drive circuit outputs normally, and the MOS transistor Q1 can be turned on normally. When it is less than 9.5V, it continues to judge whether it is greater than 8.5V. If it is greater than or equal to 8.5V, the drive circuit outputs normally, and the MOS transistor Q1 can be turned on normally. If it is less than 8.5V, the gate drive of the MOS transistor is turned off;

[0045] When the ON gear signal is at a low level, this signal is divided by the resistors R1 and R2, and the voltage value after voltage division is still at a low level state. At this time, the NPN transistor Q2 cannot be turned on normally and is in a cut-off state. At this time, the left end of the resistor R4 is connected to the power supply through the current-limiting resistor R3 and is at a high level state. The PNP transistor Q3 cannot be turned on normally and is in a cut-off state. At this time, the resistors R5 and R6 are connected in series and then connected to the negative power supply, and a complete loop cannot be formed. The voltage value at both ends of the resistor R6 is close to 0V and is transmitted to the single-chip microcomputer IO1 port to collect and process the analog quantity data of the input power supply voltage; the non-inverting input terminal of the hysteresis comparator U1 is also in a power supply state close to 0V, so the voltage value generated on the R6 is less than the reference voltage Vref, and the hysteresis comparator U1 outputs a low level to the single-chip microcomputer IO2 port. Since the values received by the single-chip microcomputer I01 and the single-chip microcomputer I02 ports are both less than 8.5V, it is judged as the sleep power-off state, and the output of the drive circuit is turned off, so that the MOS transistor Q1 is cut off, preventing the energy of the energy storage capacitor C1 at the back end of the anti-reverse connection MOS transistor from being consumed by the front-stage power supply.

[0046] In this embodiment, the values collected by the microcontroller from the IO1 port and the I02 port are used as the initial conditions for judging the power supply state. If it is judged that the power supply state is in sleep and power-off, the power-off data is saved. Otherwise, the input power supply sampling is continued in a loop. In the sleep and power-off state, since the MOS transistor conducts through the body diode, when the voltage of the subsequent stage is greater than that of the previous stage, the energy stored in the capacitor of the subsequent stage can only be consumed in the subsequent stage, which can increase the time for the system to save power-off data.

[0047] In this embodiment, the sampling circuit is controlled by the ON signal. When the ON signal exists, the input power supply voltage can be sampled and fed back to the corresponding IO port of the microcontroller to complete the data conversion and realize the real-time sampling and calculation of the input voltage signal.

[0048] When the ON signal exists, the input power supply voltage signal is collected by means of resistor voltage division and compared with the comparator reference voltage signal. When the input signal exceeds the reference signal, the output signal of the comparator is high level and the power supply is normal; when the input signal is lower than the reference signal, the output signal of the comparator is low level, and the system makes other relevant logical judgments to determine whether the system follows the sleep and power-off logic. When the input signal is close to the reference signal, the output signal exhibits a hysteresis effect, that is, the output signal will not change immediately and needs to wait until the input signal exceeds or is lower than a certain threshold before it will flip, thus ensuring the stability of the output power-off signal.

[0049] When the signal fed back to the microcontroller indicates that the system power supply is powered off, the microcontroller controls the output of the drive circuit to control the gate drive signal of the reverse connection prevention MOS transistor, so that the MOS transistor changes from the conducting state to the cut-off state, thereby preventing the energy of the capacitor of the subsequent stage from being consumed in the previous stage through the loop formed by this MOS transistor when the voltage of the subsequent stage is greater than that of the previous stage; when the signal fed back to the microcontroller indicates that the system power supply state is normal, the microcontroller controls the output of the drive circuit to control the gate drive signal of the reverse connection prevention MOS transistor, so that the MOS transistor operates in the saturation conduction state, which can reduce the energy consumption of the power supply on the MOS transistor loop.

[0050] Those skilled in the art will readily think of other implementation schemes of this application after considering the specification and the implementation manners disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application, and these variations, uses, or adaptations follow the general principles of this application and include the common general knowledge or conventional technical means in the technical field not disclosed in this application.

[0051] It should be understood that this application is not limited to the exact structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is only limited by the appended claims.

Claims

1. A power-off data storage system for a new energy commercial vehicle domain controller, characterized in that, Comprising: A storage battery, an N-channel MOS transistor Q1 connected to the storage battery, a single-chip microcomputer, and a driving circuit. The N-channel MOS transistor Q1 is connected to the single-chip microcomputer through a power supply circuit, and the single-chip microcomputer controls the output end of the driving circuit to be connected to the gate of the N-channel MOS transistor; It further includes an NPN transistor Q2, a PNP transistor Q3, and a comparator U1. The ON gear signal is connected to a resistor R2 connected in parallel between the base B and the emitter E of the NPN transistor Q2 after passing through a resistor R1. The collector C of the NPN transistor Q2 is connected to the power supply circuit through a current-limiting resistor R3. The emitter E of the NPN transistor Q2 and the resistor R2 are grounded; The emitter E of the PNP transistor Q3 is connected to the power supply circuit. The base B of the PNP transistor Q3 is connected to the collector C of the NPN transistor Q2 through a resistor R4. The collector C of the PNP transistor Q3 is connected to a series-connected resistor R5 and a resistor R6. The resistor R6 is connected to the ground terminal. The voltage acquisition IO1 port of the single-chip microcomputer is connected to the resistor R5; The non-inverting input terminal of the comparator U1 is connected to the resistor R5, and the inverting input terminal is connected to the power-down reference voltage Vref terminal through a current-limiting resistor R8. The output terminal of the comparator U1 is connected to the IO2 interface of the single-chip microcomputer.

2. The power-off data storage system for a new energy commercial vehicle domain controller according to claim 1, wherein A resistor R7 is provided between the positive power supply terminal of the comparator U1 and the resistor R5.

3. The power-off data storage system for a new energy commercial vehicle domain controller according to claim 2, characterized in that It further includes a capacitor C1. One end of the capacitor C1 is connected to the power supply circuit, and the other end is grounded.

4. The data saving method of a power-off data saving system for a new energy commercial vehicle domain controller according to any one of claims 1-3, characterized in that, Comprising: When the ON gear signal is at a high level, at this time, the NPN transistor Q2 and the PNP transistor Q3 are turned on. At this time, the input voltage of the storage battery is divided by the series-connected resistor R5 and resistor R6. The voltage value after being divided by the resistor R6 is collected through the voltage acquisition IO1 port of the single-chip microcomputer. At the same time, the divided voltage is compared with the power-down reference voltage Vref value after passing through the comparator U1. When the divided voltage value is greater than the power-down reference voltage Vref value, the comparator U1 outputs a high-level signal to the single-chip microcomputer I02 port; when the divided voltage value is less than the power-down reference voltage Vref value, the comparator U1 outputs a low-level signal to the single-chip microcomputer I02 port. The single-chip microcomputer uses the values collected by the IO1 port and the I02 port as the initial conditions for judging the power supply state; When the ON gear signal is at a low level, at this time, the NPN transistor Q2 and the PNP transistor Q3 are not turned on. The single-chip microcomputer I01 port collects the voltage value of the resistor R6, and the comparator U1 outputs a low-level signal to the single-chip microcomputer I02 port. The single-chip microcomputer uses the values collected by the IO1 port and the I02 port as the initial conditions for judging the power supply state.

5. A data storage method according to claim 4, characterized in that, After the voltage value collected by the single-chip microcomputer IO1 port is subjected to AD conversion, it is judged whether the collected value is greater than or equal to 8.5V. When it is greater than or equal to 8.5V, the driving circuit outputs normally, and the MOS transistor Q1 conducts normally. When it is less than 8.5V, the gate of the MOS transistor Q1 is turned off, and it is judged whether the system goes into sleep power-down. If it is judged to go into sleep power-down, the power-down data is saved.

6. A data storage method according to claim 4, wherein The voltage value output by the comparator U1 collected by the I / O port I02 of the single-chip microcomputer. When the value collected by the I / O port I02 is greater than or equal to 9.5V, the drive circuit outputs normally and the MOS transistor Q1 conducts normally. When the value collected by the I / O port I02 is less than 9.5V, continue to judge whether the collected value is greater than or equal to 8.5V. When it is greater than or equal to 8.5V, the drive circuit outputs normally and the MOS transistor Q1 conducts normally. When it is less than 8.5V, the gate of the MOS transistor Q1 is turned off to make a preliminary judgment on whether the system goes into sleep and powers down.

7. A data storage method according to claim 4, characterized in that, The reference voltage Vref value is 9V.

8. A data storage method according to claim 4, characterized in that, The upper voltage threshold and the lower voltage threshold of the comparator U1 are 8.5V and 9.5V respectively.

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