Memory performance test optimization method, device and equipment

Abstract

The embodiment of the invention provides a memory performance test optimization method, device and equipment, and the method comprises the steps: calculating and determining a size reference value of a test array based on the storage space capacity of a target storage region, the size of the test array being used for describing the size of a detection region in a memory; determining a change strategy of the test array based on the size reference value, wherein the change strategy is used for generating a new test array size based on the size of the previous test array; compiling a plurality of groups of test arrays generated based on the change strategy in sequence, and performing memory performance test based on compiled data to obtain a test reference result; determining a target size value of the test array based on a first condition and the test reference results, wherein the first condition is used for screening the test reference results; and testing the memory performance by using the test array meeting the target size value to obtain a test result for describing the memory performance.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of memory performance testing, and in particular to a memory performance testing optimization method, device and equipment. Background Art

[0002] In memory performance testing, the Stream tool is often used for bandwidth testing. In Stream bandwidth performance testing, the bandwidth test results often fail to reach the standard value, so tuning operations are required. In the tuning operations, hardware issues such as CPU model, memory insertion method, memory specifications, and BIOS option settings need to be considered. In addition to the above hardware issues, in the test, through the analysis of the stream source code, it can be seen that its bandwidth performance test results are also related to the DSTREAM_ARRAY_S I ZE parameter in the compilation test. The DSTREAM_ARRAY_S I ZE parameter is mainly used to adjust the size of the test array. Summary of the invention

[0003] In order to solve the above technical problems, the embodiment of the present application provides a memory performance test optimization method, including:

[0004] Determine a reference value of the size of a test array based on the storage space capacity of the target storage area, wherein the size of the test array is used to describe the size of the detection area in the memory;

[0005] Determining a change strategy for the test array based on the size reference value, the change strategy being used to generate a new test array size based on a previous test array size;

[0006] Compiling multiple groups of test arrays generated based on the change strategy in sequence, and performing memory performance tests based on the compiled data to obtain test reference results;

[0007] determining a target size value of the test array based on a first condition and the test reference result, the first condition being used to screen the test reference result;

[0008] A memory performance test is performed on a test array that meets the target size value to obtain a test result for describing the memory performance.

[0009] In one embodiment, the step of calculating and determining the size reference value of the test array based on the storage space capacity of the target storage area includes:

[0010] The minimum reference value of the test array size is determined by calculation based on the storage space capacity of the target storage area.

[0011] In one embodiment, the size reference value is proportional to the size of the target storage area.

[0012] In one embodiment, determining a change strategy of the test array based on the size reference value includes:

[0013] A starting size and a step length of a test array are determined based on the size reference value, wherein the starting size has a first proportional value relative to the size reference value, and the step length has a second proportional value relative to the size reference value.

[0014] In one embodiment, determining the target size value of the test array based on the first condition and the test reference result includes:

[0015] When the number of the test reference results meets a threshold, comparing and analyzing the fluctuation amounts among the plurality of the test reference results;

[0016] When the fluctuation amount satisfies the first condition, the test array size corresponding to the target test reference result ranked in the middle among the plurality of test reference results is determined as the target size value.

[0017] In one embodiment, the method further comprises at least one of the following steps:

[0018] Determine the test duration range for a single test based on historical experience data;

[0019] Determine an upper limit value of the size of the test array based on the test duration range;

[0020] The target size value is validated based on the upper size limit value.

[0021] In one embodiment, the sequentially compiling multiple test arrays generated based on the variation strategy includes:

[0022] Compiling is started with a test array that meets the size reference value, and then compiling multiple groups of test arrays generated based on the change strategy in sequence.

[0023] In one embodiment, the memory performance test is performed on the test array that meets the target size value to obtain a test result for describing the actual performance of the memory, including:

[0024] Perform multiple memory performance tests on a test array that meets the target size value to obtain multiple candidate test results;

[0025] Calculating and determining the mean of the plurality of candidate test results;

[0026] The test result is determined based on the mean.

[0027] Another embodiment of the present application also provides a memory performance test optimization device, including:

[0028] A first calculation module, used for calculating and determining a reference value of a size of a test array according to a storage space capacity of a target storage area, wherein the size of the test array is used to describe a size of a detection area in a memory;

[0029] A first determination module, used to determine a change strategy of the test array according to the size reference value, wherein the change strategy is used to generate a new test array size based on a previous test array size;

[0030] A compiling module, used to compile multiple test arrays generated based on the change strategy in sequence, and perform memory performance testing based on the compiled data to obtain a test reference result;

[0031] A second determination module, configured to determine a target size value of the test array according to a first condition and the test reference result, wherein the first condition is used to screen the test reference result;

[0032] The test module is used to perform a memory performance test on a test array that meets the target size value to obtain a test result for describing the memory performance.

[0033] Another embodiment of the present application further provides an electronic device, comprising

[0034] one or more processors;

[0035] a memory configured to store one or more programs;

[0036] When the one or more programs are executed by the one or more processors, the one or more processors implement the memory performance test optimization method as described in any one of the above texts.

[0037] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings.

[0038] The technical solution of the present application is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1A flowchart of a memory performance test optimization method in an embodiment of the present application.

[0041] Figure 2 It is a flowchart of a memory performance test optimization method in another embodiment of the present application.

[0042] Figure 3 Schematic diagram of the application process of the memory performance test optimization method in the embodiment of the present application.

[0043] Figure 4 This is a structural block diagram of the memory performance test optimization device in an embodiment of the present application. DETAILED DESCRIPTION

[0044] Below, specific embodiments of the present application are described in detail with reference to the accompanying drawings, but are not intended to limit the present application.

[0045] It should be understood that various modifications may be made to the embodiments disclosed herein. Therefore, the following description should not be considered as limiting, but merely as an example of an embodiment. Other modifications within the scope of the present disclosure will occur to those skilled in the art.

[0046] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0047] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0048] It should also be understood that, although the present application has been described with reference to some specific examples, those skilled in the art will be able to realize many other equivalent forms of the present application that have the features described in the claims and are therefore within the scope of protection defined thereby.

[0049] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0050] Specific embodiments of the present disclosure are described hereinafter with reference to the accompanying drawings; however, it should be understood that the disclosed embodiments are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant details. Therefore, the specific structural and functional details disclosed herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in a variety of ways with substantially any suitable detailed structure.

[0051] This specification may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0052] Below, embodiments of the present application are described in detail with reference to the accompanying drawings.

[0053] At present, when using memory performance testing tools to perform performance testing on the memory of electronic devices, such as bandwidth testing, the test results often fail to meet the standards. Through analysis and research, the reasons for this situation are determined to include hardware-level reasons and software-level reasons. For hardware-level reasons, they can be improved by tuning the hardware configuration of the device, but for software-level reasons, there is still no good solution.

[0054] In order to solve the impact of the software layer on memory performance testing, this application proposes a memory performance testing optimization method, which is used to improve the impact of the software layer on the test results and optimize the memory performance test by adjusting the size of the test array. Figure 1 As shown, the memory performance test optimization method proposed in this embodiment includes:

[0055] S1: calculating and determining a reference value of a size of a test array based on the storage space capacity of a target storage area, wherein the size of the test array is used to describe the size of a detection area in a memory;

[0056] S2: determining a change strategy for the test array based on the size reference value, the change strategy being used to generate a new test array size based on a previous test array size;

[0057] S3: sequentially compile multiple test arrays generated based on the change strategy, and perform memory performance testing based on the compiled data to obtain a test reference result;

[0058] S4: determining a target size value of the test array based on a first condition and the test reference result, wherein the first condition is used to screen the test reference result;

[0059] S5: Perform a memory performance test on a test array that meets the target size value to obtain a test result for describing the memory performance.

[0060] The test array can be considered as the size of the area in the memory used for testing when the test tool tests the memory performance, that is, the size of the detection area. If the detection area is small or large, it will cause the efficiency of the memory in reading and writing data to be adversely affected, and then have a negative impact on the test results of the memory performance, causing the test results of the memory performance to fail to meet the standards. Moreover, when the detection area is too large, it will also delay the test and waste resources. Therefore, it can be seen that quickly finding and determining the best test array so that the test tool tests the memory based on the best test array can not only accurately obtain memory performance data, improve the test compliance rate, and avoid the test being interfered with by the software level, but also significantly improve the test efficiency.

[0061] Exemplarily, the optimization method in this embodiment is applied to a test system, and the test tool may belong to the test system or be independent of the test system, or the optimization method is applied to a test program, which is deployed in the electronic device where the memory is located, or may be connected to the electronic device based on an external hard disk, or may be other deployment forms, which are not unique. In this embodiment, the execution party is taken as an example of the test system. When determining that the memory is to be tested, the system first determines the target storage area, which may be a preset storage area, such as a storage area preset by the test tool based on previous test experience, or an area preset by the memory for test reference, or an area specified by the user based on experience or related calculations, etc., which are not unique. After the system determines the target storage area, it will query and determine the storage space capacity of the target storage area, and then calculate and determine the size reference value of the test array based on the storage space capacity. The size reference value of the test array may be the size of the minimum test array, or may be an intermediate value in the size range of the test array. Based on the size reference value of the test array, the system may increase or decrease it, etc., to expand multiple candidate values ​​of the test array size. That is, based on the size reference value of the test array, the system can determine the corresponding change strategy, so that the size reference value of the test array can be processed based on the change strategy, and multiple new test arrays with different size values ​​can be generated. When the system obtains multiple different test arrays generated, it will compile multiple groups of test arrays generated based on the change strategy in sequence, and perform memory performance test based on the compiled data to obtain test reference results. After obtaining multiple test reference results, the system will determine the first condition for screening the test reference results, and then screen all the test reference results based on the first condition to determine the target size value of the test array, that is, the optimal size value of the test array. At this time, the test tool can perform memory performance test on the test array that meets the target size value, and obtain a test result that can accurately describe the actual performance of the memory. The test result can be considered to be the most real test result that can best reflect the actual performance of the memory, and the embodiment of the performance is directly related to the optimal size value of the test array, or has a direct corresponding relationship, so by determining the optimal size value of the test array, not only can the actual performance of the memory be tested, but also the test time can be minimized on the basis of testing the actual performance of the memory, thereby improving the test efficiency and reducing the waste of resources.

[0062] In one embodiment, the step of calculating and determining the size reference value of the test array based on the storage space capacity of the target storage area includes:

[0063] S6: Calculate and determine a minimum reference value of the test array size based on the storage space capacity of the target storage area.

[0064] Exemplarily, the target storage area in this embodiment may be, for example, but not limited to, the L3 cache area of ​​the processor (CPU). The L3 cache area is an area that has a close interactive relationship with the memory. When the test array is small, for example, smaller than the size of the L3 cache area, or the same size as the L3 cache area, the corresponding data is directly stored in the L3 cache area and does not enter the memory. Only when the size of the test array is larger than the L3 cache area, the corresponding data will be stored in the memory. Therefore, in this embodiment, the L3 cache area is determined as the template storage area, and the minimum reference value of the test array size is calculated based on its storage space capacity.

[0065] Furthermore, in this embodiment, the minimum reference value of the test array is proportional to the storage space capacity of the target storage area, and the size reference value of the test array is also proportional to the storage space capacity of the target storage area, that is, the size reference value of the test array is proportional to the storage space capacity of the target storage area, and the proportional relationship can be, for example, an integer multiple relationship such as 1, 2, 3, or a non-integer multiple relationship such as 1.2, 1.6, and is not unique. For example, the minimum reference value can be directly the size value of the storage space capacity of the L3 cache area, or it can be a size value of 2 times the storage space capacity of the L3 cache area, or it can be a size value of 3.5 times the storage space capacity of the L3 cache area, etc. In this embodiment, the minimum reference value is taken as an example of a size value of 4 times the storage space capacity of the L3 cache area.

[0066] In order to quickly and accurately determine the optimal size value of the test array, the system in this embodiment will expand based on the minimum reference value after determining the minimum reference value, and derive multiple different size reference values, so as to process and screen the multiple different size reference values ​​to obtain the optimal size reference value. Among them, when it comes to how to expand and derive multiple different size reference values, the method adopted by the system is to generate a change strategy, so as to expand and derive multiple different size reference values ​​based on the change strategy. Specifically, determining the change strategy of the test array based on the size reference value includes:

[0067] S7: Determine a starting size and a step length of a test array based on the size reference value, wherein the starting size has a first proportional value relative to the size reference value, and the step length has a second proportional value relative to the size reference value.

[0068] In this embodiment, when determining the change strategy, the size reference value as the starting value is first determined, and then the minimum change amount of the size reference value is determined. After that, the size reference value of the test array is changed based on the minimum change amount with the starting value as the starting point. The minimum change amount is equivalent to the step size, and the change of the size value of the test array next time is based on the size value of the previous time. In actual application, a first proportional value can be set, and then the starting size is determined based on the size reference value and the first proportional value. At the same time, a second proportional value is set, and then the step size is determined based on the size reference value and the second proportional value. The specific settings of the first proportional value and the second proportional value are not fixed. For example, in this embodiment, the first proportional value is set in the form of 0.5 and the second proportional value is set in the form of 0.5, that is, the first proportional value is the same as the second proportional value. Of course, it can also be set to different values. In addition, the proportional value is not limited to 0.5. The above is only an exemplary description, and the specific settings of the proportional value are not unique.

[0069] After obtaining the change strategy, the size reference value is processed based on the change strategy. After obtaining multiple new size reference values, the system can compile the newly generated size reference values ​​in sequence and generate multiple groups of test arrays accordingly, including:

[0070] S8: Compiling starts with a test array that meets the size reference value, and then sequentially compiles multiple groups of test arrays generated based on the change strategy.

[0071] For example, firstly, the test array corresponding to the size reference value is used as the starting test array for compilation, and then the test arrays corresponding to the new size reference values ​​with gradually increasing size values ​​are compiled in sequence, so as to obtain multiple groups of test array compilation results starting with the size indicated by the size reference value and with gradually increasing size values. After that, the system can perform performance tests on the memory based on the multiple groups of compilation results respectively to obtain multiple test reference results.

[0072] Further, such as Figure 2 As shown, determining the target size value of the test array based on the first condition and the test reference result includes:

[0073] S9: when the number of the test reference results meets a threshold, comparing and analyzing the fluctuation amounts among the plurality of the test reference results;

[0074] S10: When the fluctuation amount satisfies a first condition, determining a test array size corresponding to a target test reference result ranked in the middle among the plurality of test reference results as the target size value.

[0075] The test reference results in this embodiment have a quantity value requirement. Only when the number of test reference results meets the requirement can the steady-state test results be determined. The steady-state test results characterize that as the size of the test array changes, the change of the test results tends to a stable state. For the test results in a steady state, the corresponding test array can be considered to be the best test array. Specifically, when it is determined that the number of test reference results meets the threshold, the fluctuation amount between the multiple test reference results, that is, the change amount of the test reference results, is compared and analyzed. And the change amount is compared with the first condition, and the first condition indicates the standard range of the change amount. If the fluctuation amount meets the first condition and is within the standard range, it can be determined that the test reference result tends to a steady state. At this time, the system will determine the target reference result located in the middle of the multiple test reference results that meet the time series, and determine the test array size corresponding to the target reference result as the target size value of the test array, that is, the optimal size value.

[0076] In another embodiment, in order to improve the test efficiency and ensure the test accuracy, the method further includes at least one of the following steps:

[0077] S11: Determine the test duration range of a single test based on historical experience data;

[0078] S12: Determine the upper limit value of the size of the test array based on the test duration range;

[0079] S13: Verify the target size value based on the size upper limit value.

[0080] For example, the system can analyze and determine the test duration range that meets the above conditions based on previous test experience data, under the premise of ensuring test accuracy, with the purpose of reducing test time and improving test efficiency. The test duration range is the duration range of a single test, and the duration of a single test is directly related to the size of the test array. Based on this, the system will constrain the size upper limit of the test array according to the determined test duration range, that is, determine the size upper limit of the test array. Then, the size value of the test array is further constrained by the upper limit value, and it is verified whether the determined target size value exceeds the upper limit. If so, it indicates that the target size value is unqualified and needs to be tested again, and compared to obtain a new target size value. If the target size value is below the upper limit value, it indicates that the target size value is qualified. At this time, the corresponding test array can be determined based on the target size value, and the memory detection area can be determined in combination with the test array. Finally, the test tool completes the memory performance test based on the detection area.

[0081] Furthermore, the memory performance test is performed on the test array that meets the target size value to obtain a test result for describing the actual performance of the memory, including:

[0082] S14: performing multiple memory performance tests on a test array that meets the target size value to obtain multiple candidate test results;

[0083] S15: Calculate and determine the mean of the plurality of candidate test results;

[0084] S16: Determine the test result based on the mean value.

[0085] For example, in order to increase the test accuracy and make the test results more able to reflect the actual performance level of the memory, in this embodiment, when the test array with the target size is used in combination with the test tool to perform the performance test of the memory, multiple tests will be performed to obtain multiple candidate test results. Then the mean of the multiple candidate test results is calculated, and the final test result is determined based on the mean. The test result is not accidental, but corresponds to the performance state of the memory when it is running stably, so it has high accuracy, strong authenticity, and high reference value.

[0086] In practical application, combined with Figure 3 As shown, the size value of the CPU's L3 cache (L3 cache space) is obtained, for example, the size value of the L3 cache space is queried using lscpu; then the minimum size reference value of the test array is calculated accordingly. Then, starting from the minimum size reference value, with a certain size as the step length, for example, with half of the L3 cache space size as the starting point, and with half of the L3 cache space size as the step length, multiple new test array size reference values ​​are calculated based on the minimum size reference value. After that, all size reference values ​​are compiled in order, and then tested in turn to obtain a test reference result that can express the performance trend of the memory as the test array size changes, and then the performance trends expressed by multiple test reference results and the test time are combined to obtain the steady-state array size, that is, the target size reference value of the test array. For example, after arranging the test reference results in order from small to large test arrays, select a test array size of 4 times the size of the L3 cache space as the starting point, and compare the test reference results at this point with the five groups of test reference results before and after this point in the sequence. If the comparison result indicates that the fluctuation of the test result at this point relative to the multiple groups of test reference results before and after this point is less than 2% of its own value, then it can be considered that the test array size corresponding to the test reference result is the optimal test array size, and the corresponding compilation parameters are the optimal compilation parameters. At this point, the system can combine the test tool to perform a memory performance bandwidth test based on the determined target size value of the test array. The bandwidth test is usually performed 30 times (the number of tests is not unique), and then the total average is taken as the final performance test result.

[0087] like Figure 4 As shown, another embodiment of the present application also provides a memory performance test optimization device, including:

[0088] A first calculation module, used for calculating and determining a reference value of a size of a test array according to a storage space capacity of a target storage area, wherein the size of the test array is used to describe a size of a detection area in a memory;

[0089] A first determination module, used to determine a change strategy of the test array according to the size reference value, wherein the change strategy is used to generate a new test array size based on a previous test array size;

[0090] A compiling module, used to compile multiple test arrays generated based on the change strategy in sequence, and perform memory performance testing based on the compiled data to obtain a test reference result;

[0091] A second determination module, configured to determine a target size value of the test array according to a first condition and the test reference result, wherein the first condition is used to screen the test reference result;

[0092] The test module is used to perform a memory performance test on a test array that meets the target size value to obtain a test result for describing the memory performance.

[0093] In one embodiment, the step of calculating and determining the size reference value of the test array based on the storage space capacity of the target storage area includes:

[0094] The minimum reference value of the test array size is determined by calculation based on the storage space capacity of the target storage area.

[0095] In one embodiment, the size reference value is proportional to the size of the target storage area.

[0096] In one embodiment, determining a change strategy of the test array based on the size reference value includes:

[0097] A starting size and a step length of a test array are determined based on the size reference value, wherein the starting size has a first proportional value relative to the size reference value, and the step length has a second proportional value relative to the size reference value.

[0098] In one embodiment, determining the target size value of the test array based on the first condition and the test reference result includes:

[0099] When the number of the test reference results meets a threshold, comparing and analyzing the fluctuation amounts among the plurality of the test reference results;

[0100] When the fluctuation amount satisfies the first condition, the test array size corresponding to the target test reference result ranked in the middle among the plurality of test reference results is determined as the target size value.

[0101] In one embodiment, the method further comprises at least one of the following steps:

[0102] Determine the test duration range for a single test based on historical experience data;

[0103] Determine an upper limit value of the size of the test array based on the test duration range;

[0104] The target size value is validated based on the upper size limit value.

[0105] In one embodiment, the sequentially compiling multiple test arrays generated based on the variation strategy includes:

[0106] Compiling is started with a test array that meets the size reference value, and then compiling multiple groups of test arrays generated based on the change strategy in sequence.

[0107] In one embodiment, the memory performance test is performed on the test array that meets the target size value to obtain a test result for describing the actual performance of the memory, including:

[0108] Perform multiple memory performance tests on a test array that meets the target size value to obtain multiple candidate test results;

[0109] Calculating and determining the mean of the plurality of candidate test results;

[0110] The test result is determined based on the mean.

[0111] Another embodiment of the present application further provides an electronic device, comprising:

[0112] one or more processors;

[0113] a memory configured to store one or more programs;

[0114] When the one or more programs are executed by the one or more processors, the one or more processors implement the memory performance test optimization method as described in any one of the above texts.

[0115] Furthermore, an embodiment of the present application also provides a storage medium on which a computer program is stored, and when the program is executed by a processor, the memory performance test optimization method described above is implemented. It should be understood that each scheme in this embodiment has the corresponding technical effect in the above method embodiment, which will not be repeated here.

[0116] Furthermore, an embodiment of the present application also provides a computer program product, which is tangibly stored on a computer-readable medium and includes computer-readable instructions, which, when executed, cause at least one processor to perform a memory performance test optimization method such as that in the embodiments described above.

[0117] It should be noted that the computer storage medium of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, system or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access storage medium (RAM), a read-only storage medium (ROM), an erasable programmable read-only storage medium (EPROM or flash memory), an optical fiber, a portable compact disk read-only storage medium (CD-ROM), an optical storage medium, a magnetic storage medium, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can send, propagate or transmit a program configured to be used by or in conjunction with an instruction execution system, system or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, antenna, optical cable, RF, etc., or any suitable combination of the above.

[0118] In addition, it should be understood by those skilled in the art that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) that contain computer-usable program code.

[0119] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A system that specifies the functions of a box or boxes.

[0120] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction system, which is implemented in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0121] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of protection of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

Claims

1. A memory performance test optimization method, characterized in that: include: Determine a reference value of the size of a test array based on the storage space capacity of the target storage area, wherein the size of the test array is used to describe the size of the detection area in the memory; Determining a change strategy for the test array based on the size reference value, the change strategy being used to generate a new test array size based on a previous test array size; Compiling multiple groups of test arrays generated based on the change strategy in sequence, and performing memory performance tests based on the compiled data to obtain test reference results; determining a target size value of the test array based on a first condition and the test reference result, the first condition being used to screen the test reference result; A memory performance test is performed on a test array that meets the target size value to obtain a test result for describing the memory performance.

2. The memory performance test optimization method according to claim 1, characterized in that: The step of calculating and determining a size reference value of the test array based on the storage space capacity of the target storage area includes: The minimum reference value of the test array size is determined by calculation based on the storage space capacity of the target storage area.

3. The memory performance test optimization method according to claim 1, characterized in that: There is a proportional relationship between the size reference value of the test array and the storage space capacity of the target storage area.

4. The memory performance test optimization method according to claim 1, characterized in that: The step of determining a change strategy of the test array based on the size reference value includes: A starting size and a step length of a test array are determined based on the size reference value, wherein the starting size has a first proportional value relative to the size reference value, and the step length has a second proportional value relative to the size reference value.

5. The memory performance test optimization method according to claim 1, characterized in that: The step of determining the target size value of the test array based on the first condition and the test reference result includes: When the number of the test reference results meets a threshold, comparing and analyzing the fluctuation amounts among the plurality of the test reference results; When the fluctuation amount satisfies the first condition, the test array size corresponding to the target test reference result ranked in the middle among the plurality of test reference results is determined as the target size value.

6. The memory performance test optimization method according to claim 5, characterized in that: The method further comprises: Determine the test duration range for a single test based on historical experience data; Determine an upper limit value of the size of the test array based on the test duration range; The target size value is validated based on the upper size limit value.

7. The memory performance test optimization method according to claim 1, characterized in that: The sequentially compiling multiple test arrays generated based on the variation strategy includes: Compiling is started with a test array that meets the size reference value, and then compiling multiple groups of test arrays generated based on the change strategy in sequence.

8. The memory performance test optimization method according to claim 1, characterized in that: The memory performance test is performed on the test array that meets the target size value to obtain a test result for describing the actual performance of the memory, including: Perform multiple memory performance tests on a test array that meets the target size value to obtain multiple candidate test results; Calculating and determining the mean of the plurality of candidate test results; The test result is determined based on the mean.

9. A memory performance test optimization device, characterized in that: include: A first calculation module, used for calculating and determining a reference value of a size of a test array according to a storage space capacity of a target storage area, wherein the size of the test array is used to describe a size of a detection area in a memory; A first determination module, configured to determine a change strategy for a test array according to the size reference value, wherein the change strategy is configured to generate a new test array size based on a previous test array size; A compiling module, used to compile multiple test arrays generated based on the change strategy in sequence, and perform memory performance testing based on the compiled data to obtain a test reference result; A second determination module, configured to determine a target size value of the test array according to a first condition and the test reference result, wherein the first condition is used to screen the test reference result; The test module is used to perform a memory performance test on a test array that meets the target size value to obtain a test result for describing the memory performance.

10. An electronic device comprising: one or more processors; a memory configured to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the memory performance test optimization method as described in any one of claims 1-8.

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