Test pattern determination method for chip testing, controller, device, and medium

Abstract

The present application discloses a test pattern determination method and controller, device, and medium for chip testing, and relates to the field of chip testing technology. The method includes: performing read and write tests on the chip to be tested based on different types of test functions in sequence to obtain a first test result; when the first test result is 1, it is determined that the first read and write test processing fails, and a fault is detected. In response to the generated first error signal, a first target test algorithm determined from multiple candidate test algorithms according to a first enable signal is run, and a first preset pattern file is called according to a first fault type flag; a plurality of candidate test patterns based on the first preset pattern file are sequentially subjected to read and write tests on the chip to be tested to obtain a plurality of corresponding second test results; the candidate test pattern that detects the fault is determined as the first target test pattern according to the second test result, so as to perform defective product screening tests on batches of the same type of chips to be tested. The reliability and efficiency of selecting the target test pattern can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a test pattern determination method, controller, device, and medium for chip testing. Background Art

[0002] Integrated circuit (IC) testing is one of the key means to ensure the performance and quality of integrated circuits. It is mainly achieved through a dedicated integrated circuit test system and other auxiliary equipment. The test system is controlled by computer software, and each hardware module runs in a suitable state according to the instructions. During the chip testing process, the computer sends test instructions and related information. The test process is: write the test pattern into the chip to be tested, read back the data, compare the read-back data with the pre-set expectations, and make a pass or fail judgment.

[0003] Before DDR (Double Data Rate) memory chips are shipped out of the factory, a series of different types of tests need to be performed on the DDR memory chips to detect whether the DDR memory chips have faults or instability, so as to screen out defective products in a batch of DDR memory chips. Different test patterns are usually used to test whether different functions of DDR memory chips are good. Some DDR memory chips are prone to errors under a certain test pattern; using this test pattern to screen out defective products for a batch of DDR memory chips is conducive to improving the efficiency of screening out defective products for a batch of DDR memory chips. However, some test patterns cannot detect faults in DDR memory chips well during the detection of DDR memory chips. At present, the test pattern for screening defective products is set based on the experience of the tester. However, there are many test patterns. If the test pattern is set based on the experience of the tester, different testers may set different test patterns, resulting in inconsistent test results and low reliability. Moreover, if the tester is inexperienced, it may take a lot of time to repeat trial and error to select the appropriate test pattern, and the efficiency and reliability are low. It can be seen that the reliability and efficiency of manually setting the test pattern are low. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a test pattern determination method for chip testing, a controller, a device, and a medium; the method can automatically determine the target test pattern for defective product screening test of batches of the same type of chips to be tested, thereby improving the reliability and efficiency of selecting the target test pattern.

[0005] In a first aspect, an embodiment of the present application provides a method for determining a test pattern for chip testing, the method comprising:

[0006] Based on the different types of test functions of the preset standard test file, the chip to be tested is subjected to a first read-write test process to obtain a first test result;

[0007] When the first test result is 1, it is determined that the first read-write test process fails, a fault is detected, the test is interrupted and the first interrupt position is marked, and a first error signal is generated; the first error signal includes: a first enable signal and a first fault type flag;

[0008] In response to the first error signal, determining a first target test algorithm from a plurality of candidate test algorithms according to the first enable signal; the number of the candidate test algorithms is the same as the number of types of the test function;

[0009] Running the first target test algorithm and calling a first preset code pattern file according to the first fault type flag;

[0010] Based on the multiple candidate test patterns of the first preset pattern file, the second read-write test process is performed on the chip to be tested, and multiple second test results are obtained accordingly;

[0011] According to the second test result, the candidate test pattern in which a fault is detected is determined as a first target test pattern; the first target test pattern is used to perform defective product screening test on batches of the same type of chips to be tested.

[0012] In a second aspect, an embodiment of the present application provides a controller comprising at least one processor and a memory for communicating with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a test code determination method for chip testing as described in any one of the embodiments of the first aspect.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, comprising a controller as described in the embodiment of the second aspect.

[0014] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute a test code determination method for chip testing as described in any one of the embodiments of the first aspect.

[0015] The embodiment of the present application includes: in the process of determining the target test pattern for performing defective product screening test on batches of the same type of chips to be tested, first, based on different types of test functions of a preset standard test file, a first read-write test process is performed on the chip to be tested to obtain a first test result; secondly, when the first test result is 1, it is determined that the first read-write test process fails, a fault is detected, the test is interrupted and the first interrupt position is marked, and a first error signal is generated; the first error signal includes: a first enable signal and a first fault type flag; then, in response to the first error signal, a first target test algorithm is determined from a plurality of candidate test algorithms according to the first enable signal; the candidate test The number of algorithms is the same as the number of types of test functions; then, the first target test algorithm is run, and the first preset pattern file is called according to the first fault type flag; then, based on the multiple candidate test patterns of the first preset pattern file, the second read and write test processing is performed on the chip to be tested, and multiple second test results are obtained accordingly; the second test results provide a reliable reference for determining the first target test pattern; finally, according to the second test results, the candidate test pattern that detects the fault is determined as the first target test pattern; the first target test pattern is used to perform defective screening tests on batches of the same type of chips to be tested; thereby improving the reliability and efficiency of selecting the target test pattern. That is to say, the embodiment of the present application can automatically determine the target test pattern used for performing defective screening tests on batches of the same type of chips to be tested, thereby improving the reliability and efficiency of selecting the target test pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A test system capable of executing a test pattern determination method for chip testing provided by an embodiment of the present application;

[0017] Figure 2 It is a schematic diagram of the steps of a method for determining a test pattern for chip testing provided by an embodiment of the present application;

[0018] Figure 3 This is a specific schematic diagram of generating a first error signal provided by an embodiment of the present application;

[0019] Figure 4 This is a specific schematic diagram of determining a first target test pattern provided by an embodiment of the present application;

[0020] Figure 5 It is a schematic diagram of the hardware structure of a controller provided in one embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0022] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0024] First, some terms used in this application are explained:

[0025] DDR chips usually refer to "Double Data Rate" memory chips, which is a memory technology that allows data to be transferred on both the rising and falling edges of the clock cycle, thereby increasing the data transfer rate. DDR memory technology is the successor to SDRAM (Synchronous Dynamic Random Access Memory), which can provide double the data transfer rate at the same clock frequency.

[0026] The present application discloses a test pattern determination method, controller, electronic device and computer-readable storage medium for chip testing, and relates to the field of chip testing technology. The method includes: performing read and write tests on the chip to be tested based on different types of test functions in sequence to obtain a first test result; when the first test result is 1, it is determined that the first read and write test processing fails, and a fault is detected. In response to the generated first error signal, a first target test algorithm determined from multiple candidate test algorithms according to a first enable signal is run, and a first preset pattern file is called according to a first fault type flag; a plurality of candidate test patterns based on the first preset pattern file are sequentially subjected to read and write tests on the chip to be tested to obtain a plurality of corresponding second test results; the candidate test pattern that detects the fault is determined as the first target test pattern according to the second test result, so as to perform defective product screening tests on batches of the same type of chips to be tested. The reliability and efficiency of selecting the target test pattern can be improved.

[0027] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0028] like Figure 1As shown, the test system capable of executing the test pattern determination method for chip testing includes: a host computer, a test environment temperature chamber, and a chip to be tested; wherein the chip to be tested is placed in the test environment temperature chamber, and the host computer is electrically connected to the test environment temperature chamber and the chip to be tested, respectively. The host computer is used to control the test environment temperature that can be provided by the test environment temperature chamber, and provide the required test environment temperature in the process of defective product screening of the chip to be tested; the host computer is used to execute the test pattern determination method for chip testing provided in the embodiment of the present application, and can automatically determine the target test pattern for defective product screening test of batches of the same type of chips to be tested, thereby improving the reliability and efficiency of selecting the target test pattern.

[0029] Those skilled in the art will appreciate that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0030] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0031] Those skilled in the art will appreciate that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0032] Based on the above system structure, various embodiments of the test pattern determination method for chip testing of the present application are proposed below.

[0033] First, as Figure 2 As shown, the test pattern determination method for chip testing also includes but is not limited to steps S110 to S160.

[0034] Step S110: performing a first read-write test process on the chip to be tested based on different types of test functions of a preset standard test file in sequence to obtain a first test result.

[0035] Step S120: When the first test result is 1, it is determined that the first read / write test process fails, a fault is detected, the test is interrupted and the first interrupt position is marked, and a first error signal is generated; the first error signal includes: a first enable signal and a first fault type flag.

[0036] Step S130: In response to the first error signal, determine a first target test algorithm from a plurality of candidate test algorithms according to the first enable signal; the number of the candidate test algorithms is the same as the number of types of test functions.

[0037] Step S140: running a first target test algorithm, and calling a first preset code pattern file according to a first fault type flag.

[0038] Step S150: performing a second read-write test process on the chip to be tested based on the multiple candidate test patterns of the first preset pattern file in sequence, and obtaining multiple second test results accordingly.

[0039] Step S160: According to the second test result, the candidate test pattern detected as the first target test pattern is determined as the first target test pattern; the first target test pattern is used to perform defective product screening test on batches of the same type of chips to be tested.

[0040] Specifically, the preset standard test file refers to a file including multiple different types of test functions in the memtest program file, wherein different types of test functions include but are not limited to: test_stuck_address, test_random_value, test_xor_comparison, test_sub_comparison, test_mul_comparison, test_div_comparison, test_or_comparison, test_and_comparison, test_seqinc_comparison, test_solidbits_comparison, test_checkerboard_comparison, test_blockseq_comparison, test_walkbits0_comparison, test_walkbits1_comparison, test_bitspread_comparison, test_bitflip_comparison, test_8bit_wide_random, test_16bit_wide_random, March algorithm, etc.

[0041] Among them, the test_stuck_address test will alternately invert the address value and put it into the corresponding storage location, then read it out for comparison, and repeat it many times. It is mainly used to test whether the address bus is stuck (Stuck-At Faults). test_random_value is a data-sensitive test case, equivalent to test_random_comparison, which is used to detect whether the data in the memory is correct. test_xor_comparison: Compared with test_random_value, this test has an additional XOR operation, which is used for data-sensitive / instruction function verification, and can also verify Stuck-At Faults (SAF). test_sub_comparison, compared with test_random_value, this test function has an additional subtraction operation, which is used for data-sensitive / instruction function verification, and can also verify SAF. test_mul_comparison, compared with test_random_value, this test function has an additional multiplication operation, which is used for data-sensitive / instruction function verification, and can also verify SAF. test_div_comparison, compared with test_random_value, this test has an additional division operation, which is used for data-sensitive / instruction function verification, and can also verify SAF. test_or_comparison is merged into test_random_comparison, and is used for data sensitivity / instruction function verification, and can also verify SAF. test_and_comparison is merged into test_random_comparison, and is used for data sensitivity / instruction function verification, and can also verify SAF. test_seqinc_comparison is a subset of test_blockseq_comparison, which simulates customer stress test scenarios. test_solidbits_comparison writes two buffers after fixing all 1s, then reads out for comparison, and then writes all 0s for read-out comparison; this is the Zero-One algorithm. test_checkerboard_comparison is used to set several sets of Data Background, write them in sequence, and then read out for comparison. test_blockseq_comparison is used to write a count-sized block at a time, and the written value is to fill 32 bits with byte-level numbers, then take them out for comparison, and then repeat 256 times; it is also a stress test case, but the number of times has increased. test_walkbits0_comparison is used to test walking zeroes, that is, move 0 in 32 bits, generate a data pattern and then execute.test_walkbits1_comparison is used to test walking ones, that is, to move 1 inside 32bit, generate datapattern and then execute. test_bitspread_comparison is used to move inside 32bit, not just one 0 or 1 at a time, but two 1s, with two empty bits between the two 1s. test_bitflip_comparison is used to continuously move a bit=1 inside 32bit to generate a data pattern and then execute each pattern. test_8bit_wide_random is used to perform 8-bit wide random value tests. test_16bit_wide_random is used to perform 16-bit wide random value tests. March algorithm refers to a series of algorithms used for memory testing, which detect faults in memory by moving up and down in the memory address while writing values ​​to known memory locations and then reading them. There are many variants of March algorithm, such as MarchA, MarchY, MarchC, March X, etc., each with its specific test steps and covered fault types. It can be understood that the test functions cover a variety of memory test scenarios, from simple random value tests to complex arithmetic operations and pattern generation, to ensure the reliability and correctness of the memory of the tested DDR chip.

[0042] It can be understood that there are multiple different types of test functions included in the preset standard test file of the present application, which can be 10, 15, and so on. Therefore, the embodiment of the present application does not impose specific restrictions on the number of different types of test functions configured in the preset standard test file.

[0043] Specifically, although the test functions of each test function are different, they all involve the read and write test processing of the chip to be tested. Each test function in memtest is configured with a corresponding standard pattern, and different standard patterns are used for testing based on different test functions.

[0044] Specifically, the first read-write test processing specifically includes: a write operation of writing a standard code pattern as write data into the memory space of the chip to be tested; reading the data written by the write operation from the memory space of the chip to be tested to obtain readback data; comparing and verifying the consistency of the write data and the readback data. When the write data and the readback data are consistent, the test is judged to be correct and a first test result of 0 is generated; when the write data and the readback data are inconsistent, the test is judged to be incorrect and a first test result of 1 is generated.

[0045] According to some embodiments of the present application, after obtaining the first test result through step S110, the test code type determination method for chip testing also includes: when the first test result is 0, it is judged that the first read-write test processing has passed and no fault is detected; the first test result of this time is recorded, and the next test function is continuously selected in sequence to perform the first read-write test processing.

[0046] According to some embodiments of the present application, after obtaining the first test result through step S110, step S120 is executed: when the first test result is 1, it is determined that the first read-write test process fails, a fault is detected, the test is interrupted and the first interrupt position is marked, and a first error signal is generated; the first interrupt position is used to provide a reference for the subsequent re-performing of the first read-write test process based on the untested test function; the first error signal is used to indicate that the test function detects a fault in the chip to be tested and further determination of the test pattern that can be used to screen defective products is required. The first error signal generated by step S120 provides a reference for the subsequent selection of the target test algorithm.

[0047] Specifically, the first error signal includes: a first enable signal and a first fault type flag. The first enable signal includes: a high level signal with a value of 1 and a low level signal with a value of 0; the first fault type flag is used to indicate the fault type existing in the chip under test obtained through testing.

[0048] Through step S110 to step S160, in the process of determining the target test pattern for performing defective product screening test on batches of the same type of chips to be tested, first, based on different types of test functions of the preset standard test file, the chip to be tested is subjected to a first read-write test process to obtain a first test result; second, when the first test result is 1, it is determined that the first read-write test process fails, a fault is detected, the test is interrupted and the first interrupt position is marked, and a first error signal is generated; the first error signal includes: a first enable signal and a first fault type flag; then, in response to the first error signal, a first target test algorithm is determined from a plurality of candidate test algorithms according to the first enable signal; The number of candidate test algorithms is the same as the number of test function types; then, run the first target test algorithm and call the first preset pattern file according to the first fault type flag; then, based on the multiple candidate test patterns of the first preset pattern file, perform a second read and write test on the chip to be tested, and obtain multiple second test results accordingly; the second test results provide a reliable reference for determining the first target test pattern; finally, according to the second test results, determine the candidate test pattern that detects the fault as the first target test pattern; the first target test pattern is used to perform defective screening tests on batches of the same type of chips to be tested; thereby improving the reliability and efficiency of selecting the target test pattern. That is to say, the embodiment of the present application can automatically determine the target test pattern used for performing defective screening tests on batches of the same type of chips to be tested, thereby improving the reliability and efficiency of selecting the target test pattern.

[0049] According to some embodiments of the present application, step S120 is further described, wherein a first error signal is generated, including but not limited to steps S121 to S125.

[0050] Step S121: When the first test result is 1, determine the first fault type flag of the fault type detected by the first read-write test process; the first fault type flag is used to indicate the fault type existing in the chip under test obtained through the test.

[0051] Step S122: Obtain all recorded first test results.

[0052] Step S123: according to the generation time sequence of each first test result, all the first test results currently recorded are sequentially spliced ​​to obtain spliced ​​data.

[0053] Step S124: when the spliced ​​data is not equal to the preset number of bits, the last bit of the spliced ​​data is padded with 0 to obtain a first enable signal with the same number of bits as the preset number of bits; the first enable signal is binary data; the preset number of bits is equal to the number of test functions in the preset standard test file.

[0054] Step S125: Generate a first error signal according to the first enable signal and the first fault type flag.

[0055] Specifically, the first enable signal is binary data, and the number of bits of the binary data is the same as the total number of current test functions in the preset standard test file. The first enable signal includes: a high level signal with a value of 1 and a low level signal with a value of 0;

[0056] like Figure 3 As shown, an example is given to illustrate the specific process of generating the first error signal.

[0057] Example 1: When there are ten different types of test functions in the preset standard test file, namely test function 1, test function 2, test function 3, ..., test function 10. First, based on test function 1, the first test result obtained by performing the first read-write test on the chip to be tested is 0, then it is judged that the first read-write test is passed and no fault is detected, and the first test result corresponding to test function 1 is recorded as 0; test function 2 is selected in sequence, and the first test result obtained by performing the first read-write test on the chip to be tested based on test function 2 is 0, and the first test result corresponding to test function 2 is recorded as 0; and so on, when test function 5 is detected, the first test result obtained by performing the first read-write test on the chip to be tested based on test function 5 is 1, then it is judged that the first read-write test is not passed, a fault is detected, the test is interrupted and the first interrupt position is marked, and the fault type is judged at the same time, and the first fault type flag is determined based on the fault type. According to all the first test results recorded, all the first test results currently recorded are sequentially spliced ​​to obtain spliced ​​data: 00001 according to the generation time sequence of each first test result; the preset number of bits is 10, when the spliced ​​data is not equal to the preset number of bits, the last bit of the spliced ​​data is padded with 0 to obtain the first enable signal with the same number of bits as the preset number of bits: 0000100000. Finally, the first error signal is generated.

[0058] Specifically, the first fault type flag is unique and indicates a unique fault type. The first fault type flag indicates the fault type existing in the chip under test obtained through testing, and the fault types include but are not limited to: fixed fault, jump fault, coupling fault, adjacent pattern sensitive fault, and address decoding fault.

[0059] Specifically, a fixed fault (also called a stuck fault, SAF) is a fault in which the value in the memory cell is fixed to 0 (abbreviated as SA0, Stuck-At-0) or 1 (abbreviated as SA1, Stuck-At-1) and cannot be changed. A fixed fault can be detected by writing 0 to the cell under test and then reading 0, then writing 1 and then reading 1.

[0060] Specifically, transition faults (also called transition faults, TF): the value in the storage cell cannot jump from 0 to 1 (abbreviated as TF (0->1)), or from 1 to 0 (abbreviated as TF (1->0)). Transition faults can be detected by writing a 1-to-0 transition and then reading 0, and then writing a 0-to-1 transition and reading 1.

[0061] Specifically, coupling faults (CF): the change in the value of one storage unit causes the change in the value of another storage unit. They can be divided into the following types: (1) inversion coupling fault (CFin: inversion): the coupling unit changes state in the opposite direction of the storage unit; (2) idempotent coupling fault (CFid: idempotent): when the value of a storage unit jumps, the value of the coupling unit changes to a specific value (0 or 1); (3) state coupling fault (CFst: state): a specific state of a storage unit causes the coupling unit to jump to a certain state (0 or 1); (4) bridging faults (BF: Bridging Faults): this type of fault is mainly caused by a short circuit or bridge between two or more units, and the fault behavior is usually triggered by a specific value. Bridging coupling faults are further divided into "and bridge faults (ABF)" and "or bridge faults (OBF)", and their behaviors are similar to "and logic" and "or logic" respectively; (5) dynamic coupling faults (CFdyn). Coupling faults can be detected by first performing write and read operations on all storage cells in ascending order, and then performing write and read operations on all storage cells in descending order.

[0062] Specifically, Neighborhood Pattern Sensitive Faults (NPSF): the contents of a memory cell or the ability to change the contents of this cell is affected by the contents of another memory cell.

[0063] Specifically, Address Decoder Faults (ADF or AF): This type of fault mainly occurs in the address decoding logic. The address and the storage unit are one-to-one corresponding. Once the address decoding logic fails, one or more of the following four types of faults will occur: (1) For a given address, there is no corresponding storage unit; (2) For a storage unit, there is no corresponding physical address; (3) For a given address, multiple fixed storage units can be accessed; (4) For a storage unit, it can be accessed through multiple addresses.

[0064] Through steps S121 to S125, a first enable signal is generated according to all the first test results currently recorded to lay a data foundation for subsequently determining a first target test algorithm from multiple candidate test algorithms. At the same time, a unique first fault type flag is generated to determine the fault type detected in the chip to be tested, so that it can be adapted to multiple candidate test code patterns in the first target test algorithm more quickly, thereby improving the efficiency of determining the target test code pattern.

[0065] According to some embodiments of the present application, the first enable signal includes: a high-level signal with a value of 1 and a low-level signal with a value of 0; further illustrating step S130, wherein a first target test algorithm is determined from multiple candidate test algorithms based on the first enable signal, including but not limited to steps S131 to S134.

[0066] Step S131: traverse the first enable signal bit by bit in sequence.

[0067] Step S132: In response to the low level signal of the first enable signal, setting the use state of the corresponding candidate test algorithm to disabled.

[0068] Step S133: In response to the high level signal of the first enable signal, setting the use state of the corresponding candidate test algorithm to enabled.

[0069] Step S134: Determine the enabled candidate test algorithm as the first target test algorithm.

[0070] It is understandable that the number of candidate test algorithms is the same as the number of test functions in the preset standard test file. Each candidate test algorithm is preconfigured corresponding to a test function.

[0071] Through steps S131 to S134, it is not necessary to manually configure the candidate test algorithm including the candidate test pattern on the spot based on experience, which reduces the situation where a large amount of time is required for repeated trial and error to select a suitable test pattern due to insufficient test personnel experience, thereby improving test efficiency and reliability. In addition, the first target test algorithm can be quickly enabled from multiple candidate test algorithms according to the recorded first test result through the first enable signal, thereby improving the efficiency of determining the adapted target test pattern.

[0072] To further explain step S140, it can be understood that when a fault type of the chip under test detected by a test function can be subdivided into multiple sub-fault types, the corresponding candidate test algorithm also configures multiple preset pattern files corresponding to each sub-fault type; when a test function detects a fault type of the chip under test, the corresponding candidate test algorithm also configures a preset pattern file corresponding to one fault type. Therefore, the number of preset pattern files configured in the candidate test algorithm can be 1 or more, which is determined by the number of fault types that can be determined by the corresponding test function. This application does not make specific restrictions here.

[0073] Specifically, the first fault type flag is unique and indicates a unique fault type. Therefore, through step S140, the first target test algorithm is run, and the first preset code pattern file is called according to the first fault type flag; thereby the first preset code pattern file is quickly called from the first target test algorithm.

[0074] Further explaining step S150, after obtaining the first preset pattern file, multiple candidate test patterns are read from the first preset pattern file. Based on the multiple candidate test patterns of the first preset pattern file, a second read-write test is performed on the chip to be tested, and multiple second test results are obtained accordingly. The second test results provide a reliable reference for determining the first target test pattern.

[0075] Specifically, the candidate test code pattern is pre-configured based on the standard function and fault type of the corresponding test function. The second test result is obtained by testing the candidate test code pattern. Based on the second test result, it can be further verified whether the fault type detected by the standard code pattern is correct; and the candidate test code pattern that detects the fault can be determined as the first target test code pattern.

[0076] It can be understood that the first preset code pattern file is pre-configured, and the candidate test code patterns in the first preset code pattern file can be added, deleted, or replaced.

[0077] It is understandable that when a test function can detect multiple fault types existing in a chip, the corresponding candidate test algorithm includes multiple preset code pattern files.

[0078] According to some embodiments of the present application, step S160 is further described, wherein, based on the second test result, the candidate test pattern in which the fault is detected is determined as the first target test pattern, including but not limited to steps S161 to S163.

[0079] Step S161: When the second test result is 0, it is determined that the second read-write test process has passed and no fault is detected.

[0080] Step S162: When the second test result is 1, it is determined that the second read-write test process has not passed and a fault is detected.

[0081] Step S163: Determine the candidate test pattern in which the failure is detected as the first target test pattern.

[0082] Through steps S161 to S163, a first target test code pattern is quickly determined from multiple candidate test code patterns based on the second test result. The first target test code pattern can be used to perform defective product screening tests on batches of the same type of chips to be tested, and screen out defective products with the fault type indicated by the first fault type flag.

[0083] like Figure 4 As shown, taking an example, based on Example 1, the specific process of determining the first target test code type implemented by steps S130 to S160 provided in an embodiment of the present application is further explained.

[0084] Example 2: Obtain 10 candidate test algorithms corresponding to 10 test functions, with corresponding numbers: candidate test algorithm 1, candidate test algorithm 2, candidate test algorithm 3, candidate test algorithm 4, candidate test algorithm 5, candidate test algorithm 6, candidate test algorithm 7, candidate test algorithm 8, candidate test algorithm 9, candidate test algorithm 10; the initial usage status of the ten candidate test algorithms is disabled. Then, based on Example 1, determine that the first enable signal is 0000100000, and obtain the first fault type flag, and set the usage status of the ten candidate test algorithms accordingly according to the first enable signal 0000100000, set the usage status of candidate test algorithm 5 to enabled, and set the usage status of the remaining candidate test algorithms to disabled; that is, determine that candidate test algorithm 5 is the first target test algorithm. After running candidate test algorithm 5, candidate test algorithm 5 can detect two types of faults, then two preset code pattern files are correspondingly configured in candidate test algorithm 5; when the first fault type mark is A, the preset code pattern file A is called accordingly, and when the preset code pattern file A includes 3 candidate test code patterns, the second read-write test processing is performed on the chip to be tested based on candidate test code pattern 1, candidate test code pattern 2, and candidate test code pattern 3 respectively. Among the second test results obtained, the second test result obtained by performing the second read-write test processing on the chip to be tested based on candidate test code pattern 3 is 1, then candidate test code pattern 3 is determined to be the first target test code pattern.

[0085] According to some embodiments of the present application, the test pattern determination method for chip testing further includes but is not limited to steps S210 to S270.

[0086] Step S210: after obtaining the first target test pattern, starting from the first interrupt position marked in the preset standard test file, a first read-write test process is performed on the chip to be tested based on the remaining untested test functions to obtain a first test result.

[0087] Step S220: When the first test result is 1, it is determined that the first read / write test process fails, a fault is detected, the test is interrupted and a second interrupt position is marked, and a second error signal is generated; the second error signal includes: a second enable signal and a second fault type flag.

[0088] Step S230: In response to the second error signal, determine a second target test algorithm from a plurality of candidate test algorithms according to the second enable signal.

[0089] Step S240: running a second target test algorithm, and calling a second preset code pattern file according to a second fault type flag.

[0090] Step S250: performing a second read-write test process on the chip to be tested based on multiple candidate test patterns in the second preset pattern file in sequence, and obtaining multiple second test results accordingly.

[0091] Step S260: According to the second test result, the candidate test pattern detected as a fault is determined as a second target test pattern; the second target test pattern is used to perform defective product screening test on batches of the same type of chips to be tested.

[0092] Step S270: All test functions in the preset standard test file are traversed, and all tests for determining the target test pattern are terminated.

[0093] Specifically, based on step S210 described in Example 1, when the first interrupt position is the position of test function 5 in Example 1, the first read and write test processing is performed in sequence based on the remaining untested test functions sorted after test function 5 (i.e., test function 6, test function 7, test function 8, test function 9, test function 10).

[0094] After step 210, the process also includes: when the second test result is 0, determining that the second read-write test process is passed and no fault is detected; recording the second test result of this time, and continuing to select the next test function in sequence to perform the second read-write test process.

[0095] It can be understood that, based on Example 1, after the first interruption position (test function 5), the second read-write test processing is performed on the chip to be tested based on test function 6, test function 7, test function 8, test function 9, and test function 10 respectively. If the second test results obtained by performing the second read-write test processing on the chip to be tested based on test function 6, test function 7, test function 8, test function 9, and test function 10 are all 0, then only the first target test pattern is ultimately used for defective product screening test on batches of the same type of chips to be tested.

[0096] Specifically, after step S270, the tester can select all or part of the target test code patterns based on all the determined target test code patterns according to actual test requirements, generate corresponding test items, and add them to the defective product screening test task for batches of the same type of chips to be tested.

[0097] Through step S210 to step S270, after obtaining the first target test pattern, continue to test from the first interrupt position to determine the second target test pattern; until all test functions in the preset standard test file are traversed, all tests for determining the target test pattern are terminated; thereby, the target test pattern that can be used for defective screening test of batches of the same type of chips to be tested can be determined more comprehensively. This provides a reliable reference for testers to select test patterns that can be used to screen defective chips to be tested.

[0098] According to some embodiments of the present application, the test pattern determination method for chip testing also includes but is not limited to: in response to the first file update instruction, adding, deleting, or replacing the test function in the preset standard test file to obtain an updated preset standard test file, and correspondingly adding, deleting, or replacing the candidate test algorithm; re-determining the number of test functions; updating the preset number of bits according to the current number of test functions to obtain an updated preset number of bits; the updated preset number of bits is used in the enable signal generation process. In this way, when a new test function appears, or an old test function is deleted or replaced, the preset standard test file and the preset number of bits are updated in a timely manner, thereby providing reliable protection for the subsequent determination of the test pattern that can be used for chip testing.

[0099] Take example 3: Test the function test_stuck_address() to write the corresponding address value to the memory corresponding to the address; write the next address inversely, and compare after all writes are completed. When an error is reported, the address line is judged to have an error first; a unique fault type flag is generated based on the address line error. Then run the candidate test algorithm with the enabled status, call the corresponding preset pattern file based on the fault type flag, run the candidate test pattern in the preset pattern file, perform read and write test processing, and determine the candidate test pattern with the detected fault as the target test pattern.

[0100] It is understandable that some DDR memory chips are prone to errors under some code patterns. When selecting a code pattern that can be used to screen out defective DDR chips, it is necessary to run through all the preset code patterns in memtest, and then manually input and adjust the preset code pattern to finally determine the target code pattern for batch testing of DDR chips. This method is time-consuming and has low testing efficiency. The embodiment of the present application automatically executes the test code pattern determination method for chip testing to form a reliable target test code pattern determination mechanism and a target test code pattern recommendation mechanism, and determines at least one target test code pattern that can be used to screen defective products for a type of DDR chip, thereby improving the reliability and efficiency of selecting the target test code pattern. Moreover, there is no need to rely heavily on manual experience, and even in the face of changes in testers, this solution can still be stably implemented.

[0101] like Figure 5 As shown, the present invention also provides a controller, comprising:

[0102] The processor 501 may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0103] The memory 502 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 502 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 502, and the processor 501 calls and executes the test pattern determination method for chip testing in the embodiment of this application;

[0104] Input / output interface 503, used to implement information input and output;

[0105] Communication interface 504, used to realize communication interaction between the present apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0106] A bus 505 that transmits information between various components of the device (e.g., the processor 501, the memory 502, the input / output interface 503, and the communication interface 504);

[0107] The processor 501 , the memory 502 , the input / output interface 503 and the communication interface 504 are connected to each other in communication within the device via a bus 505 .

[0108] An embodiment of the present application also provides an electronic device, including the controller as described above.

[0109] An embodiment of the present application also provides a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by a processor, the test code type determination method for chip testing is implemented.

[0110] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0111] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0112] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims

1. A method for determining a test pattern for chip testing, characterized in that: Methods include: Based on different types of test functions of a preset standard test file, a first read-write test process is performed on the chip to be tested to obtain a first test result; When the first test result is 1, it is determined that the first read-write test process fails, a fault is detected, the test is interrupted, a first interrupt position is marked, and a first error signal is generated; The first error signal includes: a first enable signal and a first fault type flag; In response to the first error signal, determining a first target test algorithm from a plurality of candidate test algorithms according to the first enable signal; the number of the candidate test algorithms is the same as the number of types of the test function; Running the first target test algorithm and calling a first preset code pattern file according to the first fault type flag; Based on the multiple candidate test patterns of the first preset pattern file, the second read-write test process is performed on the chip to be tested, and multiple second test results are obtained accordingly; According to the second test result, the candidate test pattern in which a fault is detected is determined as a first target test pattern; the first target test pattern is used to perform defective product screening test on batches of the same type of chips to be tested.

2. The method for determining a test pattern for chip testing according to claim 1, characterized in that: After obtaining the first test result, the method further includes: When the first test result is 0, it is determined that the first read-write test is passed and no fault is detected; The first test result of this time is recorded, and the next test function is selected in sequence to perform the first read-write test process.

3. The method for determining a test pattern for chip testing according to claim 2, characterized in that: The generating of the first error signal comprises: When the first test result is 1, determining a first fault type flag of the fault type detected by the first read-write test process; the first fault type flag is used to indicate the fault type existing in the chip under test obtained through the test; Get all first test results recorded; According to the generation time sequence of each of the first test results, all the first test results currently recorded are sequentially spliced ​​to obtain spliced ​​data; When the spliced ​​data is not equal to the preset number of bits, the last bit of the spliced ​​data is padded with 0 to obtain a first enable signal with the same number of bits as the preset number of bits; the first enable signal is binary data; the preset number of bits is equal to the number of test functions in the preset standard test file; The first error signal is generated according to the first enable signal and the first fault type flag.

4. The method for determining a test pattern for chip testing according to claim 1, characterized in that: The first enable signal includes: a high level signal with a value of 1 and a low level signal with a value of 0; The determining a first target test algorithm from a plurality of candidate test algorithms according to the first enable signal includes: Traversing the first enable signal bit by bit in sequence; In response to a low level signal of the first enable signal, setting the use state of the corresponding candidate test algorithm to disabled; In response to a high level signal of the first enable signal, setting the use state of the corresponding candidate test algorithm to enable; The enabled candidate test algorithm is determined as the first target test algorithm.

5. The method for determining a test pattern for chip testing according to claim 1, characterized in that: The step of determining the candidate test pattern in which the fault is detected as the first target test pattern according to the second test result includes: When the second test result is 0, it is determined that the second read-write test is passed and no fault is detected; When the second test result is 1, it is determined that the second read-write test process fails and a fault is detected; The candidate test pattern in which a failure is detected is determined as the first target test pattern.

6. The method for determining a test pattern for chip testing according to claim 3, characterized in that: The method further comprises: After obtaining the first target test pattern, starting from the first interrupt position marked in the preset standard test file, the first read-write test processing is performed on the chip to be tested based on the remaining untested test functions in sequence to obtain a first test result; When the first test result is 1, it is determined that the first read-write test process fails, a fault is detected, the test is interrupted and a second interrupt position is marked, and a second error signal is generated; the second error signal includes: a second enable signal and a second fault type flag; In response to the second error signal, determining a second target test algorithm from a plurality of candidate test algorithms according to the second enable signal; Running the second target test algorithm and calling a second preset code pattern file according to the second fault type flag; Based on the plurality of candidate test patterns in the second preset pattern file, the second read-write test process is performed on the chip to be tested, and a plurality of second test results are obtained accordingly; According to the second test result, the candidate test pattern detected as a fault is determined as a second target test pattern; the second target test pattern is used to perform defective product screening test on batches of the same type of chips to be tested; Until all the test functions in the preset standard test file are traversed, all tests for determining the target test pattern are terminated.

7. The method for determining a test pattern for chip testing according to claim 6, characterized in that: The method further comprises: In response to the first file update instruction, the test function is added, deleted, or replaced in the preset standard test file to obtain an updated preset standard test file, and the candidate test algorithm is added, deleted, or replaced accordingly; Re-determining the number of the test functions; The preset number of bits is updated according to the current number of the test functions to obtain an updated preset number of bits; the updated preset number of bits is used in the enable signal generation process.

8. A controller, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the test code determination method for chip testing as described in any one of claims 1 to 7.

9. An electronic device, characterized in that: Comprising a controller as claimed in claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the test pattern determination method for chip testing according to any one of claims 1 to 7.

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