Voltage regulator and memory device

Abstract

The invention provides a voltage regulator and a memory device. The voltage regulator includes a voltage generator and a bias circuit. The bias circuit dynamically adjusts a bias voltage based on a power saving mode signal of the memory device. The voltage generator adjusts a bias current of the voltage generator based on the bias voltage, wherein the bias current affects a rate of change of the target voltage. A voltage generator generates a target voltage to a driving circuit for driving a memory cell array in a memory device.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, and more particularly to a voltage regulator and a memory device. Background Art

[0002] Dynamic random-access memory (DRAM) devices and / or other electronic circuits require a voltage regulator to generate a stable voltage. For example, in a DRAM device, a voltage generator can generate a negative voltage VNWL required for a word line (WL) of a memory cell array. How to further reduce the power consumption of the voltage regulator in a power saving mode is one of the many technical issues in the field of DRAM technology. Summary of the invention

[0003] The invention provides a voltage regulator and a memory device, which dynamically adjust the bias current based on a power saving mode signal of the memory device, thereby reducing the power consumption of the voltage regulator in the power saving mode.

[0004] In an embodiment according to the present invention, the voltage regulator includes a voltage generator and a bias circuit. The bias circuit is coupled to the voltage generator to provide a bias voltage. The bias circuit dynamically adjusts the bias voltage based on a power saving mode signal of the memory device. The voltage generator is used to generate a target voltage for a driving circuit for driving a memory cell array in the memory device. The voltage generator adjusts a bias current of the voltage generator based on the bias voltage, wherein the bias current affects a slew rate (SR) of the target voltage.

[0005] In an embodiment according to the present invention, the above-mentioned memory device includes a command decoder, a memory cell array, a driving circuit and a voltage regulator. The command decoder is used to selectively generate a power saving mode signal. The driving circuit is used to drive the memory cell array. The voltage regulator is coupled to the command decoder to receive the power saving mode signal. The voltage regulator is coupled to the driving circuit to provide a target voltage. The driving circuit uses the target voltage to turn off at least one wordline (WL) of the memory cell array. The voltage regulator dynamically adjusts the bias current of the voltage regulator based on the power saving mode signal, wherein the bias current affects the rate of change of the target voltage.

[0006] Based on the above, the voltage regulator described in the embodiments of the present invention can dynamically adjust the bias current based on the power saving mode signal of the memory device. For example, when the power saving mode signal indicates that "the memory device enters the power saving mode", the bias circuit can dynamically adjust the bias voltage based on the power saving mode signal to reduce the bias current of the voltage generator from the normal operating current to the power saving mode current. Therefore, the power consumption of the voltage regulator in the power saving mode can be effectively reduced. Conversely, when the power saving mode signal indicates that "the memory device leaves the power saving mode", the bias circuit can dynamically adjust the bias voltage based on the power saving mode signal to adjust the bias current of the voltage generator from the power saving mode current back to the normal operating current. Therefore, in the normal operating mode, the target voltage output by the voltage regulator can be maintained at the rated change rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a circuit block of a memory device according to an embodiment of the present invention;

[0008] Figure 2 is a circuit block diagram of a driving circuit according to an embodiment of the present invention;

[0009] Figure 3 is a circuit block diagram of a voltage regulator according to an embodiment of the present invention;

[0010] Figure 4 is a circuit block diagram of a bias circuit according to an embodiment of the present invention;

[0011] Figure 5 It is a circuit block diagram of a conversion circuit, a variable resistance circuit and a voltage generator according to an embodiment of the present invention.

[0012] Description of Reference Numerals

[0013] 10: Memory controller

[0014] 100: Memory device

[0015] 110: Command decoder

[0016] 120: Voltage regulator

[0017] 130: Driving circuit

[0018] 140: Memory cell array

[0019] 310: Bias circuit

[0020] 311: Conversion circuit

[0021] 312: Variable resistor circuit

[0022] 320: Voltage Generator

[0023] 510: Charge Pump

[0024] Amp1: Amplifier

[0025] Im: main bias current

[0026] inv1: NOT gate

[0027] Is1, Is2: bias current

[0028] MN1, MP1, MP2, P3: Transistors

[0029] MN2: Switch

[0030] MPSM: Power saving mode signal

[0031] R1, R2: resistors

[0032] VB: Bias voltage

[0033] VBB, VSS: reference voltage

[0034] VDD: power supply voltage

[0035] VG: target voltage

[0036] VNWL: Negative voltage

[0037] VPWL: Positive voltage

[0038] WL: Word Line DETAILED DESCRIPTION

[0039] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0040] The term "coupled (or connected)" used in the entire specification of this case (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. The terms "first", "second", etc. mentioned in the entire specification of this case (including the claims) are used to name the components (element) or to distinguish different embodiments or scopes, and are not used to limit the upper or lower limit of the number of components, nor to limit the order of components. In addition, wherever possible, components / components / steps with the same number in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same number or the same terminology in different embodiments can refer to the relevant descriptions of each other.

[0041] Figure 1 1 is a circuit block diagram of a memory device 100 according to an embodiment of the present invention. Based on actual design, the memory device 100 may be a dynamic random access memory (DRAM) device or other memory devices. Based on the control of the memory controller 10, the memory device 100 may provide data access services to the memory controller 10. Figure 1 In the illustrated embodiment, the memory device 100 includes a command decoder 110, a voltage regulator 120, a driving circuit 130, and a memory cell array 140. Based on the control of the command decoder 110, the driving circuit 130 can drive the memory cell array 140. It should be noted that based on the actual design, the memory device 100 may also include other components not shown in the figure. Figure 1 Other functional blocks, such as well-known functional blocks or other functional blocks.

[0042] The command decoder 110 is coupled to the memory controller 10 to receive access commands and other commands. The command decoder 110 can decode the command of the memory controller 10, and then send a corresponding control signal to one or more corresponding functional blocks (e.g., the drive circuit 130) in the memory device 100 according to the decoding result. For example, according to the decoding result, the command decoder 110 can send an access control signal to the drive circuit 130 so as to access data to the memory cell array 140. This embodiment does not limit the implementation of the command decoder 110, the drive circuit 130, and the memory cell array 140. Based on the actual design, the command decoder 110 may include a well-known command decoder or other command decoding circuits, the drive circuit 130 may include a well-known memory cell drive circuit or other drive circuits, and the memory cell array 140 may include a well-known memory cell array or other memory cell circuits, so the implementation of the command decoder 110, the drive circuit 130, and the memory cell array 140 is not repeated here.

[0043] Based on the control of the memory controller 10, the memory device 100 can enter a power saving mode. Based on actual operation, the power saving mode can be a maximum power saving mode that complies with the DRAM specification or other power saving modes. For example, based on the decoding result, the command decoder 110 can selectively generate a power saving mode signal MPSM to one or more corresponding functional blocks (e.g., the voltage regulator 120) in the memory device 100. The voltage regulator 120 is coupled to the driving circuit 130 to provide a target voltage VG. The driving circuit 130 can use the target voltage VG to turn off at least one word line of the memory cell array 140. The voltage regulator 120 is coupled to the command decoder 110 to receive the power saving mode signal MPSM. The voltage regulator 120 can dynamically adjust the bias current of the voltage regulator 120 based on the power saving mode signal MPSM, wherein the bias current affects the slew rate (SR) of the target voltage VG.

[0044] The voltage regulator 120 can dynamically adjust the bias current of the voltage regulator 120 based on the power saving mode signal MPSM of the memory device 100. For example, when the power saving mode signal MPSM indicates that "the memory device 100 enters the power saving mode", the voltage regulator 120 can adjust the bias current of the voltage regulator 120 from the normal operating current to the power saving mode current. Therefore, the power consumption of the voltage regulator 120 in the power saving mode can be effectively reduced. Conversely, when the power saving mode signal MPSM indicates that "the memory device 100 leaves the power saving mode", the voltage regulator 120 can adjust the bias current of the voltage regulator 120 from the power saving mode current back to the normal operating current. Therefore, in the normal operating mode, the target voltage VG output by the voltage regulator 120 can be maintained at the rated change rate.

[0045] Figure 2 FIG. 1 is a circuit block diagram of the driving circuit 130 according to an embodiment of the present invention. Figure 2 A partial circuit of the driving circuit 130 is shown. Figure 2 The driving circuit 130 and the memory cell array 140 can be used as Figure 1 The driving circuit 130 and the memory cell array 140 are one of many implementation examples. Figure 2 In the illustrated embodiment, the negative voltage VNWL is used as a specific example of the target voltage VG output by the voltage regulator 120. The voltage regulator 120 can generate the driving voltage required for the word line WL of the memory cell array 140, such as the negative voltage VNWL and / or the positive voltage VPWL. Based on the control of the command decoder 110, the driving circuit 130 can choose to use the negative voltage VNWL (target voltage VG) to turn off the word line WL of the memory cell array 140, or choose to use the positive voltage VPWL to turn on the word line WL of the memory cell array 140.

[0046] According to the decoding result, the command decoder 110 can selectively generate a power saving mode signal MPSM to one or more functional circuits in the memory device 100. Based on the power saving mode signal MPSM sent by the command decoder 110 to the functional circuit, the voltage regulator 120 can dynamically adjust the bias current of the voltage regulator 120. For example, when the power saving mode signal MPSM indicates that "the memory device 100 enters the power saving mode", the voltage regulator 120 can adjust the bias current from the normal operation current to the power saving mode current. Conversely, when the power saving mode signal MPSM indicates that "the memory device 100 leaves the power saving mode", the voltage regulator 120 can adjust the bias current from the power saving mode current back to the normal operation current.

[0047] Figure 3 is a circuit block diagram of a voltage regulator 120 according to an embodiment of the present invention. Figure 3 The voltage regulator 120 shown can be used as Figure 1 The voltage regulator 120 is one of many examples of implementation. Figure 3 In the illustrated embodiment, the voltage regulator 120 includes a bias circuit 310 and a voltage generator 320. The voltage generator 320 is used to generate a target voltage for the driving circuit 130. Figure 3 In the illustrated embodiment, the negative voltage VNWL is still used as a specific example of the target voltage VG output by the voltage regulator 120. The voltage generator 320 can generate the negative voltage VNWL (target voltage) required to turn off the word line WL.

[0048] The bias circuit 310 is coupled to the command decoder 110 to receive the power saving mode signal MPSM. The bias circuit 310 is coupled to the voltage generator 320 to provide a bias voltage VB. Based on the power saving mode signal MPSM, the bias circuit 310 can dynamically adjust the bias voltage VB. The voltage generator 320 adjusts the bias current of the voltage generator 320 based on the bias voltage VB, wherein the bias current can affect the slew rate (SR) of the negative voltage VNWL (target voltage). When the power saving mode signal MPSM indicates that "the memory device 100 enters the power saving mode" (the power saving mode can be the maximum power saving mode (maximum power saving mode) or other power saving modes that comply with the DRAM specification), the bias circuit 310 can dynamically adjust the bias voltage VB to reduce the bias current of the voltage generator 320 from the normal operating current to the power saving mode current. Therefore, the power consumption of the voltage regulator 120 can be effectively reduced in the power saving mode. On the contrary, when the power saving mode signal MPSM indicates that the memory device 100 leaves the power saving mode, the bias circuit 310 can dynamically adjust the bias voltage VB to increase the bias current of the voltage generator 320 from the power saving mode current to the normal operation current. Therefore, in the normal operation mode, the negative voltage VNWL (target voltage) output by the voltage regulator 120 can be maintained at a rated change rate.

[0049] Figure 4 FIG. 4 is a circuit block diagram of a bias circuit 310 according to an embodiment of the present invention. Figure 4 The bias circuit 310 shown can be used as Figure 3 The bias circuit 310 is one of many implementation examples. Figure 4In the illustrated embodiment, the bias circuit 310 includes a conversion circuit 311 and a variable resistor circuit 312. The variable resistor circuit 312 is controlled by a power saving mode signal MPSM. The variable resistor circuit 312 dynamically adjusts a master bias current Im flowing through the variable resistor circuit 312 based on the power saving mode signal MPSM. The conversion circuit 311 is coupled to the variable resistor circuit 312. The conversion circuit 311 can convert the master bias current Im into a bias voltage VB for the voltage generator 320. This embodiment does not limit the implementation of the conversion circuit 311. For example, according to the actual design, the conversion circuit 311 can include a well-known current-to-voltage converter or other current-to-voltage conversion circuits.

[0050] When the power saving mode signal MPSM indicates that "the memory device 100 enters the power saving mode", the variable resistance circuit 312 can dynamically reduce the main bias current Im (adjust the bias voltage VB) to reduce the bias current of the voltage generator 320 from the normal operation current to the power saving mode current. Therefore, the power consumption of the voltage regulator 120 in the power saving mode can be effectively reduced. Conversely, when the power saving mode signal MPSM indicates that "the memory device 100 leaves the power saving mode", the variable resistance circuit 312 can dynamically increase the main bias current Im (adjust the bias voltage VB) to increase the bias current of the voltage generator 320 from the power saving mode current to the normal operation current. Therefore, in the normal operation mode, the negative voltage VNWL (target voltage) output by the voltage regulator 120 can be maintained at the rated change rate.

[0051] Figure 5 FIG. 1 is a circuit block diagram of a conversion circuit 311 , a variable resistance circuit 312 and a voltage generator 320 according to an embodiment of the present invention. Figure 5 The conversion circuit 311 and the variable resistor circuit 312 can be used as Figure 4 The conversion circuit 311 and the variable resistance circuit 312 are one of many implementation examples. Figure 5 The voltage generator 320 shown can be used as Figure 3 The voltage generator 320 is one of many implementation examples. Figure 5 In the illustrated embodiment, the conversion circuit 311 includes a transistor P3 , the variable resistance circuit 312 includes a NOT gate inv1 , a switch MN2 , a resistor R1 , and a resistor R2 , and the voltage generator 320 includes a transistor MP1 , a transistor MP2 , a transistor MN1 , and an amplifier Amp1 .

[0052] The first terminal (e.g., source) of transistor MP1 and the first terminal (e.g., source) of transistor MP2 receive power supply voltage VDD. The control terminal (e.g., gate) of transistor MP1 and the control terminal (e.g., gate) of transistor MP2 are coupled to the conversion circuit 311 of the bias circuit 310 to receive bias voltage VB. The second terminal (e.g., drain) of transistor MP2 is coupled to the power supply voltage terminal of amplifier Amp1. The first input terminal (e.g., non-inverting input terminal) of amplifier Amp1 receives reference voltage VnwlRef. The level of reference voltage VnwlRef can be determined according to actual design. The control terminal (e.g., gate) of transistor MN1 is coupled to the output terminal of amplifier Amp1. The first terminal (e.g., drain) of transistor MN1 is coupled to the second terminal (e.g., drain) of transistor MP1 to provide negative voltage VNWL (target voltage) to driving circuit 130. The second terminal of transistor MP1 is also coupled to the second input terminal (e.g., inverting input terminal) of amplifier Amp1.

[0053] The second terminal (eg, source) of the transistor MN1 and the reference voltage terminal of the amplifier Amp1 receive a reference voltage VBB. The reference voltage VBB may be provided by any power supply circuit (eg, charge pump 510). Figure 5 In the embodiment shown, the power supply voltage VDD is a positive voltage, and the reference voltage VBB is a negative voltage. This embodiment does not limit the implementation of the charge pump 510. For example, according to actual design, the charge pump 510 may include a well-known charge pump or other power supply circuits.

[0054] A first terminal (e.g., source) of transistor P3 receives power supply voltage VDD. A control terminal (e.g., gate) and a second terminal (e.g., drain) of transistor P3 are coupled to resistor R1 of variable resistor circuit 312. Transistor P3 can convert main bias current Im into bias voltage VB. A second terminal of transistor P3 provides bias voltage VB to transistors MP1 and MP2 of voltage generator 320. An input terminal of invertor inv1 receives power saving mode signal MPSM. A control terminal of switch MN2 is coupled to an output terminal of invertor inv1. A first terminal of resistor R1 is coupled to conversion circuit 311. A first terminal of resistor R2 is coupled to a second terminal of resistor R1 and a first terminal of switch MN2. A second terminal of resistor R2 is coupled to reference voltage VSS and a second terminal of switch MN2.

[0055] When the power saving mode signal MPSM is at a high logic level (indicating that "the memory device 100 enters the power saving mode"), the switch MN2 is turned off so that the resistance of the variable resistance circuit 312 increases, thereby reducing the main bias current Im (increasing the bias voltage VB). Based on the reduction of the main bias current Im, the slave bias currents Is1 and Is2 (the bias current of the voltage generator 320) flowing through the transistors MP1 and MP2 are also correspondingly reduced. Therefore, the bias current of the voltage generator 320 can be reduced from the normal operating current to the power saving mode current, so that the power consumption of the voltage regulator 120 can be effectively reduced in the power saving mode. Conversely, when the power saving mode signal MPSM is at a low logic level (indicating that "the memory device 100 leaves the power saving mode"), the switch MN2 is turned on so that the resistance of the variable resistance circuit 312 decreases, thereby increasing the main bias current Im (decreasing the bias voltage VB). Since the main bias current Im is increased, the slave bias currents Is1 and Is2 are also increased accordingly. Therefore, the bias current of the voltage generator 320 can be increased from the power saving mode current to the normal operation current, so that the negative voltage VNWL (target voltage) output by the voltage regulator 120 can be maintained at the rated change rate in the normal operation mode.

[0056] In summary, the voltage regulator 120 described in the above embodiments can dynamically adjust the bias currents Im, Is1, and Is2 based on the power saving mode signal MPSM of the memory device 100. For example, when the power saving mode signal MPSM indicates that "the memory device 100 enters the power saving mode", the bias circuit 310 can dynamically adjust the resistance of the variable resistor circuit 312 based on the power saving mode signal MPSM to reduce the bias currents Im, Is1, and Is2. Therefore, the power consumption of the voltage regulator 120 in the power saving mode can be effectively reduced. Conversely, when the power saving mode signal MPSM indicates that "the memory device 100 leaves the power saving mode", the bias circuit 310 can dynamically adjust the resistance of the variable resistor circuit 312 based on the power saving mode signal MPSM to increase the bias currents Im, Is1, and Is2. Therefore, the target voltage VG (e.g., the negative voltage VNWL) output by the voltage regulator 120 can be maintained at a rated change rate in the normal operation mode.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A voltage regulator, characterized in that: The voltage regulator comprises: a voltage generator for generating a target voltage for a driving circuit for driving a memory cell array in a memory device, wherein the voltage generator adjusts a bias current of the voltage generator based on a bias voltage, and the bias current affects a rate of change of the target voltage; and The bias circuit is coupled to the voltage generator to provide the bias voltage, wherein the bias circuit dynamically adjusts the bias voltage based on a power saving mode signal of the memory device.

2. The voltage regulator according to claim 1, characterized in that In response to the power saving mode signal indicating that the memory device enters the power saving mode, the bias circuit dynamically adjusts the bias voltage to reduce the bias current of the voltage generator from a normal operating current to a power saving mode current; as well as In response to the power saving mode signal indicating that the memory device leaves the power saving mode, the bias circuit dynamically adjusts the bias voltage to increase the bias current of the voltage generator from the power saving mode current to the normal operation current.

3. The voltage regulator according to claim 1, characterized in that The power saving mode signal includes a maximum power saving mode signal compliant with a dynamic random access memory specification.

4. The voltage regulator according to claim 1, characterized in that The driving circuit uses the target voltage to turn off at least one word line of the memory cell array.

5. The voltage regulator according to claim 4, characterized in that The target voltage is a negative voltage.

6. The voltage regulator according to claim 1, characterized in that The bias circuit comprises: a variable resistor circuit controlled by the power saving mode signal, wherein the variable resistor circuit dynamically adjusts a main bias current flowing through the variable resistor circuit based on the power saving mode signal; and The conversion circuit is coupled to the variable resistance circuit, wherein the conversion circuit converts the main bias current into the bias voltage.

7. The voltage regulator according to claim 6, characterized in that In response to the power saving mode signal indicating that the memory device enters the power saving mode, the variable resistance circuit reduces the main bias current to reduce the bias current of the voltage generator from a normal operation current to a power saving mode current; as well as In response to the power saving mode signal indicating that the memory device leaves the power saving mode, the variable resistance circuit increases the main bias current to increase the bias current of the voltage generator from the power saving mode current to the normal operation current.

8. The voltage regulator according to claim 6, characterized in that The variable resistance circuit comprises: A NOT gate, used for receiving the power saving mode signal; a switch having a control terminal coupled to the output terminal of the NOT gate; A first resistor having a first end coupled to the conversion circuit; and The second resistor has a first end coupled to the second end of the first resistor and the first end of the switch, wherein the second end of the second resistor is coupled to a reference voltage and the second end of the switch.

9. The voltage regulator according to claim 6, characterized in that: The conversion circuit comprises: The transistor has a first terminal for receiving a power supply voltage, wherein a control terminal and a second terminal of the transistor are coupled to the variable resistance circuit, and the second terminal of the transistor provides the bias voltage to the voltage generator.

10. The voltage regulator according to claim 1, characterized in that The voltage generator comprises: An amplifier having a first input terminal for receiving a first reference voltage; a first transistor having a first terminal for receiving a power supply voltage, wherein a control terminal of the first transistor is coupled to the bias circuit to receive the bias voltage, and a second terminal of the first transistor is coupled to a second input terminal of the amplifier; and The second transistor has a first end coupled to the second end of the first transistor to provide the target voltage to the driving circuit, wherein the control end of the second transistor is coupled to the output end of the amplifier, and the second end of the second transistor is used to receive a second reference voltage.

11. The voltage regulator according to claim 10, characterized in that The power supply voltage is a positive voltage, and the second reference voltage is a negative voltage.

12. The voltage regulator according to claim 10, characterized in that The voltage generator further comprises: The third transistor has a first end for receiving the power supply voltage, wherein the control end of the third transistor is coupled to the bias circuit to receive the bias voltage, the second end of the third transistor is coupled to the power supply voltage end of the amplifier, and the reference voltage end of the amplifier is used to receive the second reference voltage.

13. A memory device, characterized in that: The memory device comprises: a command decoder for selectively generating a power saving mode signal; A memory cell array; A driving circuit, used for driving the memory cell array; and A voltage regulator is coupled to the command decoder to receive the power saving mode signal, and is coupled to the driving circuit to provide a target voltage, wherein the driving circuit uses the target voltage to turn off at least one word line of the memory cell array, and the voltage regulator dynamically adjusts a bias current of the voltage regulator based on the power saving mode signal, and the bias current affects the rate of change of the target voltage.

14. The memory device according to claim 13, wherein: The voltage regulator comprises: a voltage generator configured to generate the target voltage for the driving circuit, wherein the voltage generator adjusts the bias current of the voltage generator based on a bias voltage; and A bias circuit is coupled to the voltage generator to provide the bias voltage, wherein the bias circuit dynamically adjusts the bias voltage based on the power saving mode signal.

15. The memory device according to claim 14, wherein: In response to the power saving mode signal indicating that the memory device enters the power saving mode, the bias circuit dynamically adjusts the bias voltage to reduce the bias current of the voltage generator from a normal operating current to a power saving mode current; as well as In response to the power saving mode signal indicating that the memory device leaves the power saving mode, the bias circuit dynamically adjusts the bias voltage to increase the bias current of the voltage generator from the power saving mode current to the normal operation current.

16. The memory device according to claim 14, wherein: The power saving mode signal includes a maximum power saving mode signal compliant with a dynamic random access memory specification.

17. The memory device according to claim 14, wherein: The target voltage is a negative voltage.

18. The memory device according to claim 14, wherein: The bias circuit comprises: a variable resistor circuit controlled by the power saving mode signal, wherein the variable resistor circuit dynamically adjusts a main bias current flowing through the variable resistor circuit based on the power saving mode signal; and The conversion circuit is coupled to the variable resistance circuit, wherein the conversion circuit converts the main bias current into the bias voltage.

19. The memory device according to claim 18, wherein: In response to the power saving mode signal indicating that the memory device enters the power saving mode, the variable resistance circuit reduces the main bias current to reduce the bias current of the voltage generator from a normal operation current to a power saving mode current; as well as In response to the power saving mode signal indicating that the memory device leaves the power saving mode, the variable resistance circuit increases the main bias current to increase the bias current of the voltage generator from the power saving mode current to the normal operation current.

20. The memory device according to claim 18, wherein: The variable resistance circuit comprises: A NOT gate, used for receiving the power saving mode signal; a switch having a control terminal coupled to the output terminal of the NOT gate; A first resistor having a first end coupled to the conversion circuit; and The second resistor has a first end coupled to the second end of the first resistor and the first end of the switch, wherein the second end of the second resistor is coupled to a reference voltage and the second end of the switch.

21. The memory device according to claim 18, wherein: The conversion circuit comprises: The transistor has a first terminal for receiving a power supply voltage, wherein a control terminal and a second terminal of the transistor are coupled to the variable resistance circuit, and the second terminal of the transistor provides the bias voltage to the voltage generator.

22. The memory device according to claim 14, wherein: The voltage generator comprises: An amplifier having a first input terminal for receiving a first reference voltage; a first transistor having a first terminal for receiving a power supply voltage, wherein a control terminal of the first transistor is coupled to the bias circuit to receive the bias voltage, and a second terminal of the first transistor is coupled to a second input terminal of the amplifier; and The second transistor has a first end coupled to the second end of the first transistor to provide the target voltage to the driving circuit, wherein the control end of the second transistor is coupled to the output end of the amplifier, and the second end of the second transistor is used to receive a second reference voltage.

23. The memory device according to claim 22, wherein: The power supply voltage is a positive voltage, and the second reference voltage is a negative voltage.

24. The memory device according to claim 22, wherein: The voltage generator further comprises: The third transistor has a first end for receiving the power supply voltage, wherein the control end of the third transistor is coupled to the bias circuit to receive the bias voltage, the second end of the third transistor is coupled to the power supply voltage end of the amplifier, and the reference voltage end of the amplifier is used to receive the second reference voltage.

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