Ground via clustering for crosstalk mitigation

Abstract

Embodiments of the present disclosure are directed to techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) components. In some embodiments, an IC package assembly may include a first package substrate configured to route input / output (I / O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate, and at least two ground vias of the same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with a single contact. Other embodiments may be described and / or claimed.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 201580062829.7, application date December 3, 2015, and invention name “Ground Via Cluster for Crosstalk Mitigation”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Patent Application No. 14 / 943,880, filed on November 17, 2015, and entitled “GROUNDVIA CLUSTERING FOR CROSSTALK MITIGATION,” which is a continuation of U.S. Patent Application No. 14 / 575,956, filed on December 18, 2014, and entitled “GROUNDVIA CLUSTERING FOR CROSSTALK MITIGATION.” Technical Field

[0004] Embodiments of the present disclosure relate generally to the field of integrated circuits, and more particularly, to techniques and configurations of ground via clusters for crosstalk mitigation in integrated circuit assemblies. Background Art

[0005] High-speed signal-side buses are widely used in both on-package and off-package lines of communications to address the high bandwidth requirements of integrated circuit (IC) packages. However, crosstalk (particularly crosstalk of vertical interconnects) may limit the data rates that these high-speed signal-side buses can achieve, and therefore, may pose a challenge in the face of signal transmission performance targets. Additional pins may be used for ground connections so that more vertical interconnects can be used to be assigned as grounds, in an effort to isolate signals from each other and thus reduce crosstalk between signals. However, these signal pins may increase the package form factor and may increase the cost of manufacturing.

[0006] The background description provided herein is used to generally present the context of the present disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art or an indication of prior art by inclusion in this section. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments will be easily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals designate similar structural elements. The embodiments are illustrated by way of example and not by way of limitation of the views in the accompanying drawings.

[0008] Figure 1Schematically illustrated are a cross-sectional side view of an exemplary integrated circuit (IC) component with ground via clusters and two three-dimensional (3D) models of interconnects with ground via clusters in one package substrate of the exemplary IC component in accordance with some embodiments.

[0009] Figure 2 Schematically illustrates a top view and a cross-sectional side view of an exemplary two-via cluster pattern in accordance with some embodiments.

[0010] Figure 3 Schematically illustrates a top view of an exemplary three-via cluster pattern in accordance with some embodiments.

[0011] Figure 4 A flow chart schematically illustrates an exemplary process of forming ground via clusters for crosstalk mitigation in an IC assembly, according to some embodiments.

[0012] Figure 5 A computing device including a cluster of ground vias for crosstalk mitigation as described herein is schematically illustrated according to some embodiments. DETAILED DESCRIPTION

[0013] Embodiments of the present disclosure describe techniques and configurations associated with clusters of ground vias for crosstalk mitigation in integrated circuit (IC) components. For example, the techniques described herein can be used to manufacture a package substrate having vertical interconnects with clusters of ground vias. In the following description, various aspects of the exemplary embodiments will be described using terms commonly used by those skilled in the art to convey the essence of their work to other technicians in the field. However, it is obvious to those skilled in the art that embodiments of the present disclosure can be practiced using only some of the described aspects. For the purpose of explanation, specific numbers, materials, and configurations are set forth to provide a thorough understanding of the exemplary embodiments. However, it will be obvious to those skilled in the art that embodiments of the present disclosure can be practiced without specific details. In other examples, well-known features are omitted or simplified so as not to make the exemplary embodiments difficult to understand.

[0014] In the following detailed description, reference is made to the accompanying drawings forming a part of this document, wherein similar reference numerals refer to similar components throughout the text, and wherein illustrative embodiments of the subject matter of the present disclosure are shown by which they can be practiced. In addition, it should be understood that other embodiments can be utilized, and structural and / or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be viewed in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0015] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0016] The description may use perspective-based descriptions, such as top / bottom, in / out, over / under, etc. Such descriptions are merely for facilitating discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

[0017] The description may use the phrases "in one embodiment," "in an embodiment," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. In addition, the terms "comprising," "including," "having," etc., as used with respect to the embodiments of the present disclosure, are synonymous.

[0018] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are indirectly coupled to each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements described as being coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact.

[0019] In various embodiments, the phrase "a first feature is formed, deposited, or otherwise disposed on a second feature" may mean that a first feature is formed, deposited, or disposed on a second feature, and at least a portion of the first feature may be in direct contact (e.g., direct physical contact and / or electrical contact) or indirect contact (e.g., with one or more other features between the first feature and the second feature) with at least a portion of the second feature.

[0020] As used herein, the term "module" may refer to, may be part of, or may include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a System on a Chip (SoC), a processor (shared, dedicated, or group) and / or memory (shared, dedicated, or group) that executes one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory.

[0021] Figure 1A cross-sectional side view of an exemplary IC assembly 100 including packaging substrates 112 and 122 with vertical interconnects having clusters of ground vias is schematically illustrated in accordance with some embodiments.

[0022] As used herein, a first level interconnect (FLI) may refer to an interconnect between a die (e.g., die 110 or 120) and a package substrate (e.g., package substrate 112 or 122), and a second level interconnect (SLI) may refer to an interconnect between a package substrate (e.g., package substrate 112 or 122) and another package substrate (e.g., interposer 140) or a circuit board. In an embodiment, IC assembly 100 may include one or more dies (e.g., dies 110 and 120). Dies 110 and 120 may be electrically and / or physically coupled to package substrates 112 and 122, respectively, via one or more FLI structures. Package substrates 112 and 122 may be further electrically coupled to interposer 140 via one or more SLI structures.

[0023] Either or both of die 110 and 120 may represent discrete units made from semiconductor materials using semiconductor manufacturing techniques (e.g., thin film deposition, photolithography, etching, etc.). In some embodiments, either or both of die 110 and 120 may include a processor, memory, switch, ASIC, or SoC, or be a portion of these components. Dies 110 and 120 may be electrically and / or physically coupled to packaging substrates 112 and 122, respectively, according to various suitable configurations, including flip-chip configurations as depicted or other configurations such as embedded in a packaging substrate.

[0024] In a flip chip configuration, the die 110 can be coupled to the surface 132 of the package substrate 112 using FLI structures (e.g., the interconnect structures depicted). These interconnect structures can be configured to electrically and / or physically couple the die 110 to the package substrate 112. In various embodiments, these interconnect structures can be electrically coupled to electrical routing features of the interposer 140, which are configured to route electrical signals between the die 110 and the die 120, or between the die 110 and any other electrical components. Similarly, the die 120 can be coupled to the surface 136 of the package substrate 122 using FLI structures (e.g., the interconnect structures depicted). These interconnect structures can be configured to electrically and / or physically couple the die 120 to the package substrate 122. In an embodiment, these interconnect structures can be electrically coupled to electrical routing features of the interposer 140, which are configured to route electrical signals between the die 120 and the die 110, or between the die 120 and any other electrical components. In some embodiments, the electrical signals may include input / output (I / O) signals and / or power / ground associated with the operation of dies 110 and / or 120 .

[0025] In some embodiments, Figure 1 The components in can form a package-level high-speed single-ended channel. In this embodiment, package substrate 112 can be stacked via a laminated core (SVLC) package substrate, and package substrate 122 can be a standard core package substrate. In some embodiments, die 110 can be a processor, and die 120 can be another processor, a memory device, or a field programmable gate array (FPGA) device such as a network switch. As depicted, die 110 can be coupled to an SVLC package substrate, and die 120 can be coupled to a standard core package substrate. Both the SVLC package substrate and the standard core package substrate can then be coupled to another package substrate (e.g., an interposer 140) via, for example, a ball grid array (BGA) interconnect structure (e.g., solder balls 114 or 124) to complete a high-speed single-ended channel.

[0026] It will be appreciated that, for ease of discussion, the BGA interconnect structure depicted by solder balls 114 or 124 is meant to be an exemplary interconnect structure only. In other embodiments, a land grid array (LGA) structure may electrically couple one or more lands on package substrate 112 with one or more pads on interposer 140, which may route electrical signals between package substrate 112 and interposer 140. It will be appreciated that the examples discussed above are for illustrative purposes, and any of a variety of suitable interconnect structures and / or layers may be used to electrically couple dies 110 and 120, or other dies (not shown), with interposer 140. It will be appreciated that various embodiments may additionally include other interconnect structures, such as trenches, vias, traces, or conductive layers, etc., which may be used to implement a high-speed single-ended channel to route electrical signals between die 110 and die 120.

[0027] The vertical interconnects in the packaging substrate 112 can be schematically illustrated by the 3D model 150. In one embodiment, the vertical interconnect 116 can correspond to three vertical interconnect subcomponents 152, 154, and 156. In various embodiments, the three vertical interconnect subcomponents 152, 154, and 156 can be used to route ground between the packaging substrate 112 and the interposer 140, for example, through the surface 134. In addition, in some embodiments, the three vertical interconnect subcomponents 152, 154, and 156 can be surrounded by a number of vertical interconnects (e.g., interconnect 158), which can route input / output (I / O) signals between the packaging substrate 112 and the interposer 140. In some embodiments, the vertical interconnects depicted in the 3D model 150 can form a 2:1 signal to ground ratio.

[0028] Similarly, vertical interconnects in the packaging substrate 122 can be schematically illustrated by the 3D model 160. In one embodiment, the vertical interconnect 126 can correspond to three vertical interconnect subcomponents 162, 164, and 166. In various embodiments, the three vertical interconnect subcomponents 162, 164, and 166 can be used to route ground between the packaging substrate 122 and the interposer 140, for example, through the surface 138. In addition, in some embodiments, the three vertical interconnect subcomponents 162, 164, and 166 can be surrounded by a number of vertical interconnects (e.g., interconnect 168), which can route input / output (I / O) signals between the packaging substrate 122 and the interposer 140. In some embodiments, the vertical interconnects depicted in the 3D model 160 can also form a 2:1 signal to ground ratio.

[0029] In various embodiments, the three vertical interconnect subassemblies 152, 154, and 156 can form at least one ground via cluster. Similarly, the three vertical interconnect subassemblies 162, 164, and 166 can also form at least one ground via cluster. The 3D models 150 and 160 reflect the effect of the ground via cluster. In some embodiments, the additional ground interconnect subassemblies (e.g., 154 and 156) can be applied only to the outermost columns of ground interconnects, or the columns of ground interconnects closest to the signal source (e.g., vertical interconnects 116 and 126). Such an embodiment can be beneficial because the first two columns of interconnects can exhibit more crosstalk between the signals carried by these interconnects compared to the inner columns. In other embodiments, the additional ground interconnect subassemblies (e.g., 164 and 166) can also be applied to other inner ground columns.

[0030] Crosstalk from single-ended signaling can be highly sensitive to the ground reference design in vertical interconnects. For example, as the coupling between the first signal and the associated ground becomes stronger, the mutual coupling between the first signal and the second signal may become weaker. As a result, crosstalk between the two signals can be mitigated by increasing the strength of the coupling between the two signals and the respective grounds associated with the two signals. Thus, adding more interconnect structures (e.g., BGA connections) and assigning them to the ground can produce better signal-to-signal isolation. For example, changing from a 2:1 signal-to-ground ratio to a conservative 1:1 signal-to-ground ratio can help mitigate signaling risks, but this configuration would require an additional 80 ground balls for a 2×40 interface, which would increase the cost and size of the package form factor.

[0031] In various embodiments, the ground via cluster design as shown in 3D models 150 and 160 will eliminate or reduce the increase in size of the package form factor discussed above. In this way, clustered ground vias adjacent to each other as shown in 3D models 150 and 160 can increase the size of the ground, and as a result, can improve the coupling between the signal and the associated ground without increasing the corresponding footprint. Therefore, the ground via cluster can be implemented using existing substrate design rules without affecting the rest of the package design.

[0032] In various embodiments, ground via clusters can reduce both far-end and near-end crosstalk. Thus, ground via clusters can be implemented as both terminated and non-terminated high-speed single-ended channels. In some instances, ground via clusters can reduce crosstalk by 50% or more. In addition, ground via cluster designs can also improve the signal-to-noise ratio (SNR) of the signal. Thus, the risk of channel signaling can be reduced without a corresponding increase in the size of the package form factor.

[0033] Figure 2 A top view 200 and a cross-sectional side view 290 of an exemplary two-via cluster pattern according to some embodiments are schematically shown. A three-via cluster pattern or a ground via cluster pattern with more than three ground vias may also be used in other embodiments. In various embodiments, instead of a single ground via, a cluster of ground vias may be used to mitigate or reduce crosstalk without requiring any additional interconnect structure between the two package substrates.

[0034] In some embodiments, such as those depicted, a cluster of ground vias may be surrounded by signal vias of the same layer, such as layer 296, in a hexagonal pattern. For example, one cluster of ground vias (e.g., ground vias 212 and 214) may be surrounded by six signal vias (e.g., signal via 222) having respective ball pads 220 arranged in a hexagonal pattern. In other embodiments, other patterns may also be used, such as four signal vias arranged in a square arrangement surrounding a cluster of ground vias, without departing from the scope of the present disclosure.

[0035] In some embodiments, two ground vias may be formed substantially separate from each other, but may still contact the same underlying contact structure (eg, ball pad). For example, as shown, ground vias 212 and 214 are formed separate from each other, but may still contact the same ball pad 210.

[0036] The cross-sectional side view 290 schematically illustrates an exemplary two-via cluster pattern. The package substrate 230 may have one side (e.g., side 282) for receiving a die and another side (e.g., side 284) for coupling with another package substrate or circuit board. In various embodiments, vertical interconnect structures (e.g., vertical interconnect structures 232, 240, and 250) may be disposed in the package substrate 230. The vertical interconnect structures may electrically couple structures such as traces, trenches, vias, lands, pads, or other structures that may establish corresponding electrical pathways for electrical signals through the package substrate 230.

[0037] In some embodiments, for example, for implementations in server products, the vertical interconnect structure can be longer than 1 millimeter (mm), including a stack of micro vias and core vias and solder balls. The core via can be an opening through a core substrate filled with a conductive material, which can be used to connect wiring features, for example, a metal pad placed on one side of a substrate core having wiring features, for example, another metal pad placed on the opposite side of the substrate core. In various embodiments, the core via can be much larger than the micro via because the core layer can be much thicker than the built-in layer in the organic package. In such an embodiment, the vertical interconnect structure 232 can include a stack of vias disposed on a ball pad 262, which in turn can have a solder ball 272 disposed thereon. The vertical interconnect structure 232 can be used to route signals through the package substrate 230.

[0038] As shown, in some embodiments, vertical interconnect structure 240 may include a stack of vias (e.g., via 242, via 244, and via 246) disposed on ball pad 264, which in turn may have solder ball 274 disposed thereon. Vertical interconnect structure 240 may be used to route ground through package substrate 230. Similarly, vertical interconnect structure 250 may include a stack of vias (e.g., via 252, via 254, and via 256) disposed on the same ball pad 264, which in turn may have solder ball 274 disposed thereon. Vertical interconnect structure 250 may also be used to route ground through package substrate 230.

[0039] In some embodiments, the package substrate 230 may be an epoxy-based laminate substrate having a built-in layer, such as an Ajinomoto built-in film (ABF) substrate. In various embodiments, the package substrate 230 may include other suitable types of substrates, including, for example, substrates formed of glass, ceramic, or semiconductor materials. In various embodiments, vias 242 and vias 252 may be formed in the same substrate layer 292, while vias 244 and vias 254 may be formed in the same substrate layer 294. Similarly, vias 246 and vias 256 may be formed in the same substrate layer 296. In some embodiments, vias 246 and vias 256 may be core vias in a core layer. Therefore, vias 242 and 252 may form a ground via cluster in layer 292, while vias 244 and vias 254 may form another ground via cluster in layer 294. Similarly, vias 246 and vias 256 may form another ground via cluster in layer 296.

[0040] In various embodiments, vias 242 and vias 252 may be formed in layer 292 in any conventional manner known in the art. For example, an opening may be formed over pad 264 by drilling a hole in a dielectric material region disposed over pad 264 using techniques such as using a CO2 or UV laser. In an embodiment, any conventional electroplating operation may be used to deposit a conductive material into the opening to form the via. In some embodiments, an electrolytic plating operation may be used to deposit the conductive material into the drilled opening, and a chemical mechanical polishing (CMP) or copper (Cu) etching operation may be used to remove any excess conductive material after depositing the conductive material. In various embodiments, vias 246 and vias 256 may be formed in layer 296 using similar or different manners as known in the art.

[0041] In various embodiments, layer 292, layer 294, or layer 296 may be a dielectric layer composed of any of a wide variety of suitable dielectric materials, including, for example, epoxy-based laminates, silicon dioxide (e.g., SiO2), silicon carbide (SiC), silicon carbonitride (SiCN), or silicon nitride (e.g., SiN, Si3N4, etc.). In an embodiment, layer 292 or layer 294 may include a polymer (e.g., epoxy), and may also include a filler (e.g., silica) to provide appropriate mechanical properties that meet the reliability standards of the resulting package. In an embodiment, layer 292, layer 294, or layer 296 may be formed as a film of the polymer, for example, by ABF lamination. In an embodiment, layer 292, layer 294, or layer 296 may be formed by depositing the dielectric material using any suitable technique, including, for example, atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD) techniques.

[0042] In an embodiment, substrate 230 may include a plurality of routing features, such as pads 262 or pads 264, which are configured to improve electrical paths within or through the substrate. In various embodiments, pads 262 or pads 264 may be composed of any suitable conductive material such as a metal, including, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), and any combination thereof. In some embodiments, pads 262 or pads 264 may be formed using a patterned metal layer, the metal layer being configured to: electrically couple pads 262 with vertical interconnect structures 232 to route electrical signals through package substrate 230; or electrically couple pads 264 with vertical interconnect structures 240 and 250 to route grounding through package substrate 230. The patterned metal layer may be formed in any conventional manner known in the art. For example, the patterned metal layer may be an inner conductive layer or an outermost conductive layer of a built-up layer formed using a semi-additive process (SAP).

[0043] Figure 3 Schematically illustrates a top view of an exemplary three-via cluster pattern according to some embodiments. In some embodiments, an example of using three-via clusters can be used in a hexagonal arrangement. For example, a cluster of ground vias can be surrounded by signal vias arranged in a hexagonal pattern on the same layer of vias, i.e., one cluster of ground vias is surrounded by six signal vias. Figure 3 As shown in , the cluster of ground vias 322, 324, and 326 is surrounded by signal vias arranged in a hexagon, including signal via 332. Similarly, the cluster of ground vias 352, 354, and 356 can also be surrounded by signal vias arranged in a similar hexagon. In other embodiments, other patterns (e.g., four signal vias arranged in a square arrangement around the cluster of ground vias) can also be used to arrange the signal vias to surround the cluster of ground vias without departing from the scope of the present disclosure.

[0044] As mentioned above Figure 1 As discussed, ground via clusters can be used for both SVLC package substrates and standard core package substrates. SVLC package substrates and standard core package substrates may have to be consistent with a variety of different design rules and different ball pitches. However, as shown, two ground vias can be successfully added to form a three-via cluster without violating these existing design rules. For example, a vertical interconnect structure stack of micro vias and core vias can be formed adjacent to the original ground vias in an existing design, and the form factor of the design can be maintained as a result.

[0045] In some embodiments, the cluster of ground vias can be arranged in a triangular shape. As an example, ground vias 322, 324, and 326 are depicted as being arranged in a triangular shape. Similarly, ground vias 352, 354, and 356 are depicted as being arranged in another triangular shape. In some embodiments, one ground via can be arranged above the center of the contact portion (e.g., a ball pad) below, and two other ground vias can be added to one side of the contact portion below. For example, among the cluster of ground vias 322, 324, and 326, via 322 is placed in the center of ball pad 320 in a manner similar to ground via 342 and its associated ball pad. However, ground vias 324 and 326 can be added to ground via 322 to form a cluster of ground vias arranged in a triangular shape. In some embodiments, the center of the triangular arrangement of ground vias can be arranged above the center of the contact portion below. For example, ground vias 352, 354, and 356 form a triangular arrangement, and the center of the cluster overlaps with the center of ball pad 350.

[0046] In various embodiments, two or more ground vias may be arranged into various cluster designs. For example, the number of ground vias to be clustered may be more than three depending on the design space or other design constraints. In some embodiments, ground via clusters may be placed closer to certain signals for emphasis. As an example, the arrangement of ground vias 322, 324, and 326 places more emphasis on signals near edge 310 because those signals generally exhibit a greater propensity for crosstalk. In some embodiments, ground via clusters may be concentrated, as shown in the arrangement of ground vias 352, 354, and 356, which may provide equal improvements to all surrounding signals. In various embodiments, as shown in FIG. Figure 3 As shown in , the ground via cluster can reduce far-end crosstalk (FEXT) and near-end crosstalk (NEXT). Therefore, the signal-to-noise ratio (SNR) of the channel can be improved.

[0047] Figure 4 Schematically illustrates forming a circuit for an IC component (eg, Figure 1 Flowchart of an exemplary process 400 for implementing a ground via cluster for crosstalk mitigation in an IC assembly 100 of an embodiment of the present invention. The process 400 may be consistent with the embodiments described in conjunction with the previous figures according to various embodiments.

[0048] At block 410, process 400 may include forming a plurality of electrical contacts on one side of a first package substrate, the first package substrate being configured to route input / output (I / O) signals and ground between the die and the second package substrate. In various embodiments, the contacts on this side of the first package substrate may include ball pads. In some embodiments, the ball pads may be solder mask defined (SMD). In other embodiments, the ball pads may be non-solder mask defined (NSMD). In some embodiments, forming contacts on one side of the package substrate may be achieved by embedding contacts (e.g., pads) in a built-up layer (e.g., an outermost built-up layer) as part of the formation of the built-up layer. In some embodiments, forming contacts on one side of the package substrate may be achieved by forming openings in the built-up layer and arranging the contacts (e.g., pads) into the cavity according to any suitable technique after the built-up layer is formed.

[0049] At block 420, process 400 may include forming a cluster of ground vias to electrically couple with a single contact of the plurality of contacts, the cluster of ground vias having at least two ground vias of the same layer of the vias. According to various embodiments, block 420 may be performed during a manufacturing process of the package substrate, such as during the manufacture of various layers (e.g., layer 292 or layer 294) of the package substrate 230. In various embodiments, forming the cluster of ground vias may include forming the cluster of ground vias in a column of ground vias closest to an edge of the package substrate (e.g., a first column of ground vias). The first two columns of a signal may exhibit a higher sensitivity to crosstalk than the inner columns; therefore, forming the cluster of ground vias in a column of ground vias closest to an edge of the package substrate may mitigate such crosstalk. In some embodiments, block 420 may be performed only for the column of ground vias closest to the edge, which may result in a cost-effective solution in reducing such crosstalk.

[0050] In various embodiments, forming the cluster of ground vias may include forming a vertical interconnect structure including the cluster of ground vias between two sides of the first packaging substrate, such as between the side 282 and the side 284 of the packaging substrate 230. Figure 2 In some embodiments, forming the cluster of ground vias may include forming the cluster of ground vias in an outermost layer of the vias adjacent to the side, e.g., Figure 2 In some embodiments, forming a cluster of ground vias may include forming a cluster of ground vias in a second layer of vias directly adjacent to the outermost layer of vias, such as Figure 2 In some embodiments, forming a cluster of ground vias may include forming a cluster of core vias in the same layer of the vias, for example, Figure 2 Via 246 and via 256 in layer 296 in .

[0051] In some embodiments, forming a cluster of ground vias may include forming two ground vias separated from each other. Figure 2 As shown in , the clusters of ground vias 212 and 214 can be formed to be separated from each other, but still contact the same ball pad 210. In some embodiments, forming the cluster of ground vias can include forming three ground vias in a triangular arrangement. In such an embodiment, the center of the triangular arrangement of ground vias can be set above the center of the ball pad. Figure 3 As shown in , ground vias 352, 354, and 356 may form a triangular arrangement, and the center of the cluster may overlap with the center of ball pad 350. In various embodiments, forming a cluster of ground vias may include forming a cluster of ground vias surrounded by signal vias of the same layer of the vias. Figure 3 As shown in , the cluster of ground vias 322 , 324 , and 326 may be surrounded by signal vias including signal via 332 in a hexagonal arrangement.

[0052] At block 430, process 400 may include forming a single solder joint on a single contact portion to electrically couple the first package substrate to a second package substrate or circuit board. In various embodiments, the single contact portion on the first package substrate may be a ball pad, which may correspond to a paired contact portion, such as a solder pad, on the second package substrate. The solder ball may then be used to couple the ball pad with the solder pad, for example in a BGA configuration, to form a corresponding solder joint, which may be configured to further route electrical signals between the first package substrate and the second package substrate. In other embodiments, the single solder joint may be formed into other types of package interconnects, such as a land grid array (LGA) structure or other suitable structures.

[0053] Various operations are described as multiple discrete operations in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations are necessarily order-dependent. The operations of process 400 can be performed in another appropriate order different from that depicted.

[0054] Embodiments of the present disclosure may be implemented into a system using any suitable hardware and / or software for configuring as required. Figure 5A computing device including a ground via cluster for crosstalk mitigation in an integrated circuit assembly as described herein is schematically illustrated in accordance with some embodiments. The computing device 500 may house a board such as a motherboard 502. The motherboard 502 may include a plurality of components including, but not limited to, a processor 504 and at least one communication chip 506. The processor 504 may be physically and electrically coupled to the motherboard 502. In some implementations, the at least one communication chip 506 may also be physically and electrically coupled to the motherboard 502. In other implementations, the communication chip 506 may be part of the processor 504.

[0055] Depending on its application, the computing device 500 may include other components that may or may not be physically and electrically coupled to the motherboard 502. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.).

[0056] The communication chip 506 can implement wireless communications for transmitting data to and from the computing device 500. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data via non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments, it may not contain any wires. The communication chip 506 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects and any amendments, updates, and / or revisions thereof (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16 compatible BWA networks are often referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, and is a certification mark for products that have passed the IEEE 802.16 standard qualification and interoperability tests. The communication chip 506 can operate according to the Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 506 can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 506 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G and higher generations. In other embodiments, the communication chip 506 may operate according to other wireless protocols.

[0057] The computing device 500 may include multiple communication chips 506. For example, a first communication chip 506 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip 506 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0058] The processor 504 of the computing device 500 may be packaged in an IC component (eg, Figure 1In the IC assembly 100), the IC assembly includes a substrate having a vertical interconnect structure (eg Figure 1 The processor 504 may be a die 110 coupled to the package substrate 112 using the interconnect structure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory.

[0059] The communication chip 506 may also include an IC component (eg, Figure 1 One or more dies in an IC assembly 100) including a substrate (eg, Figure 1 The vertical interconnect structure may include a packaging substrate 112 having a ground via cluster formed according to the techniques described herein.

[0060] In other embodiments, another component (e.g., a memory device or other integrated circuit device) housed within computing device 500 may include a device that may be packaged in an IC assembly (e.g., Figure 1 One or more dies in an IC assembly 100) including a substrate (eg, Figure 1 A packaging substrate 122 of the present invention is provided, the vertical interconnect structure having a ground via cluster formed according to the techniques described herein.

[0061] In accordance with some embodiments, multiple processor chips and / or memory chips may be arranged in an IC assembly that includes a packaging substrate having a cluster of ground vias in a vertical interconnect structure that may be part of a channel to electrically route signals between any two of the processor or memory chips.

[0062] In various embodiments, the computing device 500 may be a laptop, a netbook, a notebook, an ultrabook, or a TM , smart phone, tablet computer, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player or digital video recorder. In other embodiments, computing device 500 can be any other electronic device that processes data.

[0063] Example

[0064] According to various embodiments, the present disclosure describes an integrated circuit (IC) package assembly. Example 1 of the IC package assembly may include a first package substrate configured to route input / output (I / O) signals and ground between a die and a second package substrate, the first package substrate having a first side configured to receive the die and a second side opposite to the first side. The first package substrate may include a plurality of contacts disposed on the second side of the first package substrate; and at least two ground vias of the same layer of vias, wherein a single contact of the plurality of contacts is configured to form a single solder joint with the second package substrate, and wherein the at least two ground vias form a cluster of ground vias electrically coupled to the single contact. Example 2 may include the subject matter of Example 1, wherein the cluster of ground vias is part of a vertical interconnect between the first side and the second side of the first package substrate. Example 3 may include the subject matter of Examples 1 or 2, wherein the same layer of the vias is the outermost first layer of the vias adjacent to the second side, the second layer of the vias directly adjacent to the outermost first layer of the vias, or the third layer of the vias directly adjacent to the second layer of the vias. Example 4 may include the subject matter of any of Examples 1-3, wherein the cluster of ground vias is part of a column of ground vias closest to an edge of the first package substrate. Example 5 may include the subject matter of any of Examples 1-4, wherein the cluster of ground vias is surrounded by signal vias of the same layer of the vias. Example 6 may include the subject matter of Example 5, wherein the signal vias are configured in a generally hexagonal arrangement around the cluster of ground vias. Example 7 may include the subject matter of any of Examples 1-6, wherein the cluster of ground vias includes three ground vias arranged in a triangle. Example 8 may include the subject matter of Example 7, wherein the center of the triangular arrangement is disposed above the center of a single contact. Example 9 may include the subject matter of any of Examples 1-8, further comprising a second package substrate, wherein the second package substrate is coupled to the first package substrate via a single solder joint. Example 10 may include the subject matter of any of Examples 1-9, wherein the distance between at least two ground vias is less than the diameter of the single contact. Example 11 may include the subject matter of any of Examples 1-10, wherein at least two ground vias have the same diameter. Example 12 may include the subject matter of any of Examples 1-11, wherein the single solder joint is part of a ball grid array (BGA) configuration of solder joints. Example 13 may include the subject matter of any of Examples 1-12, wherein the first package substrate is a stacked via laminate core package or a core BGA package.

[0065] According to various embodiments, the present disclosure describes a method. Example 14 of a method may include forming a plurality of contacts on one side of a first package substrate, the first package substrate being configured to route input / output (I / O) signals and ground between a die and a second package substrate; forming a cluster of ground vias to electrically couple with a single contact of the plurality of contacts, the cluster of ground vias having at least two ground vias of the same layer of vias; and forming a single solder joint on the single contact to electrically couple the first package substrate to the second package substrate. Example 15 may include the method of Example 14, wherein forming the cluster of ground vias includes forming a vertical interconnect including a cluster of ground vias between two sides of the first package substrate. Example 16 may include the method of claim 14 or 15, wherein forming the cluster of ground vias includes forming a cluster of core vias in the same layer of vias. Example 17 may include any of the methods of claims 14-16, wherein forming the cluster of ground vias includes forming a cluster of ground vias surrounded by signal vias of the same layer of vias. Example 18 may include any of the methods of claims 14-17, wherein forming a cluster of ground vias includes forming three ground vias in a triangular arrangement. Example 19 may include the method of claim 18, wherein a center of the triangular arrangement is disposed above a center of a single contact. Example 20 may include any of the methods of claims 14-19, wherein forming a cluster of ground vias includes forming two ground vias separated from each other. Example 21 may include any of the methods of claims 14-20, wherein forming a cluster of ground vias includes forming a cluster of ground vias in a column of ground vias that is closest to an edge of the first package substrate.

[0066] According to various embodiments, the present disclosure may describe a packaging assembly. Example 22 of the packaging assembly may include: a first die; a first packaging substrate electrically coupled to the first die and configured to route input / output (I / O) signals and ground between the first die and the second packaging substrate, the first packaging substrate having a first side configured to receive the die and a second side opposite to the first side, the first packaging substrate including a plurality of contacts disposed on the second side of the first packaging substrate; and at least two ground vias of the same layer of the via, wherein a single contact of the plurality of contacts is configured to form a single solder joint with the second packaging substrate, and wherein at least two ground vias form a cluster of ground vias electrically coupled to the single contact; the second packaging substrate having an interconnect embedded in the second packaging substrate to electrically couple the first packaging substrate with the third packaging substrate; and a third packaging substrate electrically coupled to the second packaging substrate and the second die, the third packaging substrate being configured to route input / output (I / O) signals and ground between the second die and the second packaging substrate. Example 23 may include the package assembly of claim 21, wherein the first package substrate is a stacked via laminate core package, wherein the second package substrate is an interposer, and wherein the third package substrate is a core ball grid array package. Example 24 may include the package assembly of claim 22 or 23, wherein the first die is a CPU, and wherein the second die is a switch. Example 25 may include any of the package assemblies of claims 22-24, wherein the cluster of ground vias is a portion of a column of ground vias closest to an edge of the first package substrate.

[0067] The embodiments may include any appropriate combination of the above embodiments, including alternative (or) embodiments of the embodiments described above in combination (and) (for example, "and" may be "and / or"). In addition, some embodiments may include one or more articles of manufacture (for example, non-transitory computer-readable media) having instructions stored thereon, which, when executed, result in the actions of any of the above embodiments. In addition, some embodiments may include an apparatus or system having any appropriate modules for implementing the various operations of the above embodiments.

[0068] The above description of the illustrated embodiments (including what is described in the Abstract) is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. Although specific embodiments and examples are described herein for illustrative purposes, those skilled in the relevant art will recognize that various equivalent modifications are possible within the scope of the present disclosure.

[0069] These modifications may be made to the embodiments of the present disclosure in light of the above specific implementations. The terms used in the appended claims should not be interpreted as limiting the embodiments of the present disclosure to the specific implementations disclosed in the specification and claims. Instead, the scope should be determined entirely by the appended claims, which should be interpreted in accordance with established principles for interpreting claims.

Claims

1. A semiconductor package, comprising: A packaging substrate having a first side and a second side opposite to the first side, the packaging substrate comprising: a first layer of dielectric material adjacent to the first side of the packaging substrate; a second layer of dielectric material on the first layer of dielectric material, the first layer of dielectric material being between the second layer of dielectric material and the first side of the packaging substrate; a ground solder ball pad adjacent to the first side of the package substrate; a first via located above the ground solder ball pad and electrically coupled to the ground solder ball pad, the first via located in the first layer of dielectric material of the package substrate; a second via located above and electrically coupled to the ground solder ball pad, the second via located in the first layer of dielectric material of the package substrate, the second via being laterally spaced apart from the first via; a third via located above the first via and electrically coupled to the first via, and the third via is located in the second layer of dielectric material of the packaging substrate; a fourth via located above and electrically coupled to the second via, the fourth via being located in the second layer of dielectric material of the packaging substrate, the fourth via being laterally spaced apart from the third via; wherein a first line perpendicular to a first side of the package substrate intersects the ground solder ball pad, the first via hole, and the third via hole; and wherein a second line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the second via hole, and the fourth via hole; a die coupled to the second side of the packaging substrate; and A solder ball is disposed on the grounding solder ball pad.

2. The semiconductor package according to claim 1, wherein The first layer of dielectric material includes epoxy and silica.

3. The semiconductor package according to claim 1, further comprising: a third layer of dielectric material located on the second layer of dielectric material; a fifth via located above the third via and electrically coupled to the third via, and the fifth via is located in the third layer of dielectric material of the packaging substrate; a sixth via located above and electrically coupled to the fourth via, the sixth via being located in the third layer of dielectric material of the package substrate, the sixth via being laterally spaced apart from the fifth via; wherein the first line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the first via hole, the third via hole, and the fifth via hole; and The second line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the second via hole, the fourth via hole and the sixth via hole.

4. The semiconductor package of claim 1 , further comprising a fifth via located above the ground solder ball pad and electrically coupled to the ground solder ball pad, the fifth via being located in the first layer of dielectric material of the package substrate, the fifth via being laterally spaced apart from the first via and the second via. 5 . The semiconductor package of claim 1 , further comprising a plurality of signal ball pads surrounding the ground ball pad.

6. The semiconductor package according to claim 5, wherein: The plurality of signal ball pads surrounding the ground ball pad are arranged in a hexagonal shape. The semiconductor package of claim 1 , further comprising a second die.

8. The semiconductor package according to claim 7, wherein: The die is a processor die and the second die is a memory die.

9. A method for manufacturing a semiconductor package, comprising: Forming a package substrate, the package substrate having a first side and a second side opposite to the first side, wherein forming the package substrate comprises: forming a first layer of dielectric material adjacent to a first side of the packaging substrate; forming a second layer of dielectric material on the first layer of dielectric material, the first layer of dielectric material being between the second layer of dielectric material and the first side of the packaging substrate; forming a ground solder ball pad adjacent to the first side of the package substrate; forming a first via hole, the first via hole being located above the ground solder ball pad and electrically coupled to the ground solder ball pad, the first via hole being located in the first layer of dielectric material of the package substrate; forming a second via, the second via being located above the ground solder ball pad and electrically coupled to the ground solder ball pad, the second via being located in the first layer of dielectric material of the package substrate, the second via being laterally spaced apart from the first via; forming a third via hole, the third via hole being located above the first via hole and electrically coupled to the first via hole, and the third via hole being located in the second layer of dielectric material of the packaging substrate; forming a fourth via, the fourth via being located above the second via and electrically coupled to the second via, and the fourth via being located in the second layer of dielectric material of the packaging substrate, the fourth via being laterally spaced apart from the third via; wherein a first line perpendicular to a first side of the package substrate intersects the ground solder ball pad, the first via hole, and the third via hole; and wherein a second line perpendicular to the first side of the package substrate intersects the ground solder ball pad, the second via hole, and the fourth via hole; coupling a die to a second side of the packaging substrate; and A solder ball is disposed on the ground solder ball pad.

10. The method for manufacturing a semiconductor package according to claim 9, wherein: The first layer of dielectric material includes epoxy and silica.

11. The method for manufacturing a semiconductor package according to claim 9, further comprising a fifth via, wherein the fifth via is located above the ground solder ball pad and electrically coupled to the ground solder ball pad, the fifth via is located in the first layer of dielectric material of the package substrate, and the fifth via is laterally spaced apart from the first via and the second via. 12 . The method of manufacturing a semiconductor package according to claim 9 , further comprising a plurality of signal ball pads surrounding the ground ball pad.

13. The method for manufacturing a semiconductor package according to claim 12, wherein: The plurality of signal ball pads surrounding the ground ball pad are arranged in a hexagonal shape.

14. A computing device comprising: Touch screen display; Battery; motherboard; A packaging substrate coupled to the motherboard, the packaging substrate comprising: A first layer of dielectric material; a second layer of dielectric material located on the first layer of dielectric material; a ground solder ball pad between the first layer of dielectric material and the motherboard; a first via electrically coupled to the ground solder ball pad, the first via being located in the first layer of dielectric material of the package substrate; a second via electrically coupled to the ground solder ball pad, the second via being located in the first layer of dielectric material of the package substrate, the second via being laterally spaced apart from the first via; a third via electrically coupled to the first via and located in the second layer of dielectric material of the packaging substrate; a fourth via electrically coupled to the second via and located in the second layer of dielectric material of the packaging substrate, the fourth via being laterally spaced apart from the third via; wherein the ground solder ball pad, the first via and the third via are located in a first vertical interconnect stack; and wherein the ground solder ball pad, the second via and the fourth via are located in a second vertical interconnect stack; and A processor die is coupled to the packaging substrate, the packaging substrate being located between the processor die and the motherboard.

15. The computing device of claim 14, wherein: The first layer of dielectric material includes epoxy resin.

16. The computing device of claim 14, further comprising: a third layer of dielectric material located on the second layer of dielectric material; a fifth via electrically coupled to the third via, and the fifth via is located in the third layer of dielectric material of the packaging substrate; a sixth via electrically coupled to the fourth via, the sixth via being located in the third layer of dielectric material of the packaging substrate, the sixth via being laterally spaced apart from the fifth via; wherein the first vertical interconnect stack includes the fifth via; and Wherein, the second vertical interconnect stack includes the sixth via hole.

17. The computing device of claim 14, further comprising a fifth via located above the ground solder ball pad and electrically coupled to the ground solder ball pad, the fifth via being located in the first layer of dielectric material of the packaging substrate, the fifth via being laterally spaced apart from the first via and the second via.

18. The computing device of claim 14, further comprising a plurality of signal ball pads surrounding the ground ball pad.

19. The computing device of claim 18, wherein: The plurality of signal ball pads surrounding the ground ball pad are arranged in a hexagonal shape.

20. The computing device of claim 14, further comprising a wireless communication chip and a memory chip.

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