Ultra-wideband interconnect structure parasitic capacitance optimization structure

Abstract

The present invention discloses an ultra-wideband interconnect structure parasitic capacitance optimization structure, which is applied to the field of signal transmission and addresses the problem of low transmission performance of existing packaging structures. For the interconnection between the external interface and the chip, the present invention adopts an external interface SMA-microstrip line-quasi-coaxial-stripline-quasi-coaxial-BGA solder ball interconnection structure, and for the interconnection between chips, a BGA-quasi-coaxial-stripline-quasi-coaxial-BGA interconnection structure is adopted. Through optimization and adjustment, excellent interconnection performance between the external interface and the chip, and between chips can be achieved within the 0-40GHz ultra-wideband range.

Description

Technical Field

[0001] The invention belongs to the field of signal transmission, and in particular relates to an ultra-wideband device. Background Art

[0002] SiP (System in Package) is an advanced packaging technology that integrates multiple chips or devices with different functions, such as power amplifiers, processors, MEMS filters, and other active and passive components, into a single package using TSV or various 3D packaging technologies to create a module with specific complex functions or even complete system functions.

[0003] With the rapid development of information technology, people's requirements for communication speed, capacity, and confidentiality are constantly increasing. Traditional narrowband communication technologies are unable to meet these requirements due to limited spectrum resources. Therefore, ultra-wideband devices have become a major development trend in current circuit design. To ensure good signal transmission performance between ultra-wideband chips and between ultra-wideband chips and external interfaces, the design of ultra-wideband packaging interconnect structures has also become an important research direction. Summary of the Invention

[0004] To achieve ultra-wideband, low-loss, and low-standing-wave-ratio (SWR) RF interconnect signal transmission, the present invention provides two RF interconnect structure designs based on a low-temperature co-fired ceramic (LTCC) process. The substrate material in these designs is Hitce, with a single-layer thickness of 97 μm, and the conductive material is copper, with a thickness of 10 μm. These two proposed solutions utilize the parasitic capacitance introduced by each layer of quasi-coaxial pads and the parasitic inductance introduced by the transmission lines to form a multi-stage LC matching network. This enables high-performance signal transmission between chips and between chips and external interfaces within the ultra-wideband range of 0-40 GHz.

[0005] One of the technical solutions adopted by the present invention is: an ultra-wideband packaging interconnect structure between a chip and an external interface, based on a low-temperature co-fired ceramic substrate, adopting an interconnect structure of an external interface SMA-microstrip line-first type coaxial line-first stripline-second type coaxial line-BGA solder ball; the microstrip line is located on the top layer ground of the low-temperature co-fired ceramic substrate, the first end of the microstrip line is connected to the external interface SMA, and the second end of the microstrip line is connected to the first end of the first type coaxial line; the second end of the first type coaxial line is connected to the first end of the first stripline, and the first stripline is located on the metal layer of the low-temperature co-fired ceramic substrate; the second end of the first stripline is connected to the first end of the second type coaxial line, and the second end of the second type coaxial line is connected to the BGA solder ball, and the BGA solder ball is connected to the chip interface;

[0006] The first type of coaxial and the second type of coaxial are connected to each layer of the occupied low temperature co-fired ceramic substrate through a welding pad;

[0007] The parasitic capacitance introduced by each pad of the first type coaxial cable and the second type coaxial cable and the parasitic inductance introduced by the transmission line used for the routing of the first type coaxial cable and the second type coaxial cable form a multi-stage LC matching network.

[0008] The first type coaxial and the second type coaxial are vertically interconnected structures; the first type coaxial and the second type coaxial occupy three layers of substrates.

[0009] The distance between the top layer of the low-temperature co-fired ceramic substrate and the bottom metal layer is three substrate layers high.

[0010] The distance between the ground below the low-temperature co-fired ceramic substrate and the metal bottom layer is two substrate heights.

[0011] The microstrip line selects a single-layer substrate height.

[0012] The second technical solution adopted by the present invention is: an ultra-wideband packaging interconnection structure between chips, based on a low-temperature co-fired ceramic substrate, adopting a first BGA solder ball-third type coaxial-second stripline-fourth type coaxial-second BGA solder ball interconnection structure, wherein the first BGA solder ball is connected to the first chip interface, the first BGA solder ball is also connected to the first end of the third type coaxial, the second end of the third type coaxial is connected to the first end of the second stripline, and the second stripline is located in the metal layer of the low-temperature co-fired ceramic substrate; the second end of the second stripline is connected to the first end of the fourth type coaxial, the second end of the fourth type coaxial is connected to the second BGA solder ball, and the second BGA solder ball is connected to the second chip interface;

[0013] The third type of coaxial and the fourth type of coaxial are connected to each layer of the occupied low temperature co-fired ceramic substrate through a welding pad;

[0014] The parasitic capacitance introduced by each layer of the third and fourth coaxial cables and the parasitic inductance introduced by the transmission lines used for the routing of the third and fourth coaxial cables themselves form a multi-stage LC matching network.

[0015] The third type coaxial and fourth type coaxial are vertically interconnected structures; the third type coaxial and fourth type coaxial occupy three layers of substrates.

[0016] The distance between the top layer of the low-temperature co-fired ceramic substrate and the bottom metal layer is three substrate layers high.

[0017] The distance between the ground below the low-temperature co-fired ceramic substrate and the metal bottom layer is two substrate heights.

[0018] The present invention has the following beneficial effects: The substrate material used is Hitce, with a single-layer thickness of 97 μm, and the conductive material is copper, with a thickness of 10 μm. The two proposed solutions utilize the parasitic capacitance introduced by each layer of quasi-coaxial pads and the parasitic inductance introduced by the transmission line to form a multi-stage LC matching network, achieving excellent interconnect performance between external interfaces and chips, and between chips, within the ultra-wideband range of 0-40 GHz. Specifically, the return loss is better than -20 dB, and the insertion loss is better than -1.5 dB. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a top view of a quasi-coaxial vertical transmission structure.

[0020] Figure 2 It is a correspondence diagram between the equivalent lumped elements and physical structure of the coaxial structure.

[0021] Figure 3 This is the interconnection structure diagram of microstrip line-quasi-coaxial-stripline-quasi-coaxial-BGA solder ball.

[0022] Figure 4 This is the interconnection structure diagram of BGA-quasi-coaxial-stripline-quasi-coaxial-BGA.

[0023] Among them, 11 is a quasi-coaxial inner conductor, 12 is a quasi-coaxial outer conductor, 13 is a solder pad, 14 is the parasitic inductance introduced by the quasi-coaxial trace, 15 is the parasitic capacitance introduced by the solder pad, 16 is an anti-pad, 17 is a ceramic dielectric, 18 is a planar transmission line, 21 is a microstrip line, 22 is a quasi-coaxial, 23 is a stripline, 24 is a BGA solder ball, 25 is a signal isolation metal column, 26 is a chip model, 27 is an external signal input interface, 31 is a BGA solder ball, 32 is a quasi-coaxial, 33 is a stripline, 34 is a signal isolation metal column, and 35 is a chip model. DETAILED DESCRIPTION

[0024] To facilitate those skilled in the art to understand the technical content of the present invention, the present invention is further explained below with reference to the accompanying drawings. First, the principles of the two interconnect packaging structures are to use the parasitic capacitance introduced by each layer of the coaxial pad and the parasitic inductance introduced by the transmission line to form a multi-order LC matching network to achieve high-order matching. Figure 1 The figure shows a top view of a quasi-coaxial vertical transmission structure, which includes: a quasi-coaxial inner conductor 11, a quasi-coaxial outer conductor 12 formed by a plurality of circularly distributed grounded metal through-holes, a pad 13 for connecting the quasi-coaxial conductor to each layer of the occupied substrate, and an anti-pad 16 for isolating the quasi-coaxial inner conductor and the pad from the surrounding large-area metal ground. The ceramic dielectric 17 acts as a medium between the inner and outer conductors of the coaxial line. The parasitic effects introduced by the horizontal transmission line 18, such as microstrip line and stripline, can be equivalent to a parasitic inductance, while the parasitic effects introduced by the vertical transmission line quasi-coaxial are as follows: Figure 2As shown, the quasi-coaxial structure can be regarded as a low-pass LC network. The parasitic inductance 14 introduced by the specific quasi-coaxial routing and the parasitic capacitance 15 introduced by the pad form a multi-order LC matching network. After the approximate size of the quasi-coaxial line is determined by the coaxial line characteristic impedance calculation formula, the value of the parasitic capacitance can be adjusted by adjusting the size of the pad and the anti-pad 16, and then a high-order LC matching network is formed together with the parasitic inductance introduced by the transmission line, thereby playing the role of ultra-wideband matching.

[0025] Example 1

[0026] exist Figure 3 In the figure, for the interconnection between the external interface and the chip, an external interface SMA-microstrip line-quasi-coaxial-stripline-quasi-coaxial-BGA solder ball interconnection structure is adopted, wherein the microstrip line 21 located on the surface is used to receive the surface external signal input from the SMA interface 27. When the received signal frequency is high, the microstrip line 21 can be replaced with a coplanar waveguide (not suitable for ultra-wideband structure). In order to avoid signal radiation loss and insufficient wiring space of a single-layer substrate, after the microstrip line 21 travels a certain distance, the signal changes layers through the quasi-coaxial 22 to enter the internal layer of the packaging structure, and is then transmitted between the internal layers using a stripline 23 (since each layer of metal ground is close to each other, the microstrip line cannot be located in the internal layer). After transmitting the required distance, it changes layers through another section of quasi-coaxial 22. After changing layers, the signal enters the chip internal 26 interface through the BGA solder ball 24 inverted on the surface of the substrate. The microstrip line 21 is arranged at a single-layer substrate height and is located on the top layer ground (the metal ground is made of copper). The microstrip line 21 is connected to the quasi-coaxial line 22 after running an appropriate distance. Both sections of the quasi-coaxial line 22 occupy the height of three layers of substrate. The stripline 23 is arranged on the fourth metal layer and is not connected to the metal ground.

[0027] The microstrip line's height and width satisfy the impedance matching formula, resulting in a calculated impedance of 50 ohms to minimize reflections of external input signals. In this example, the microstrip line occupies one substrate layer, has a width of 150 μm, a distance of 155 μm from the edge of the line to the surrounding metal ground plane on the same layer, and a length of 2500 μm. The calculated characteristic impedance of the microstrip line meets the standard 50 ohm.

[0028] By adjusting the size of the transition pad at the microstrip-to-quasi-coaxial connection, reflections and losses can be minimized. In this example, a 195µm top pad radius and a 300µm anti-pad size at the microstrip-to-quasi-coaxial connection achieve the lowest transmission loss.

[0029] Adjusting the stripline's characteristic impedance by adjusting the stripline's width and the height of the upper and lower metal ground planes, and simultaneously adjusting the size of the transition pad at the stripline's quasi-coaxial connection, can reduce reflections and losses at the stripline-BGA interconnect. In this example, the distance between the upper ground plane and the trace is three substrate layers, and the distance between the lower ground plane and the trace is two substrate layers. The stripline is 120 μm wide, the distance from the stripline edge to the metal ground plane on the same layer is 160 μm, the stripline is 250 μm long, and the transition pad radius is 80 μm.

[0030] The characteristic impedance of the quasi-coaxial is adjusted by adjusting the ratio of the inner diameter to the outer diameter, and the discontinuity of the connection between the quasi-coaxial and microstrip lines and BGA is adjusted by adjusting the size of the transition pad and the anti-pad. At the same time, additional pads are introduced as needed to introduce a certain amount of parasitic capacitance to resonate the high-frequency parasitic inductance introduced by the transmission line (when the transmission line is too long and the quasi-coaxial crosses too many substrate layers at one time, the parasitic inductance effect is obvious, and the pads between layers can introduce additional parasitic capacitance to balance the inductance effect), thereby achieving the purpose of broadband matching. In this example, the inner diameter of the quasi-coaxial connected to the microstrip line is 60um, the outer diameter is 680um, the anti-pad size is 305um, and transition pads are provided at the connection with the microstrip line and the stripline respectively. The radius of the microstrip line transition pad is 195um, and the radius of the stripline transition pad is 80um. There are no additional pads; the inner diameter of the quasi-coaxial connected to the BGA is 60um, the outer diameter is 585um, and the anti-pad size is 400um. Transition pads are provided at the connection with the stripline and the BGA respectively. The radius of the stripline transition pad is 80um, and the radius of the BGA transition pad is 140um. There are no additional pads.

[0031] Example 2

[0032] exist Figure 4 In the figure, for the interconnection between chips, a BGA-quasi-coaxial-stripline-quasi-coaxial-BGA interconnection structure is adopted, that is, the signal is output from the port of a chip and vertically input into the quasi-coaxial structure 32 through BGA 31 for layer change to avoid insufficient routing space caused by the routing being concentrated on the surface of the substrate. The quasi-coaxial 32 occupies three layers of substrate height. The signal is input into the stripline 33 through the quasi-coaxial 32. The stripline 33 routing is located on the fourth metal layer and is not connected to the ground. The signal is input into the quasi-coaxial 22 at the other end through the stripline 33, and is input into the BGA 31 solder ball of the other chip through the quasi-coaxial 32, and finally input into the chip 35 at the other end.

[0033] By adjusting the stripline's height and width, reflections and transmission losses at the quasi-coaxial connection can be minimized. In this example, the distance between the upper ground plane and the trace on stripline 33 is three substrate layers, and the distance between the lower ground plane and the trace on stripline 33 is two substrate layers. The line width is 120 μm, the distance between the stripline edge and the surrounding metal ground plane on the same layer is 160 μm, and the line length is 6150 μm.

[0034] By adjusting the ratio of the quasi-coaxial inner diameter to the outer diameter, the anti-pad radius, and the transition pad radius, we can reduce discontinuities at the connections with the stripline and BGA, while also introducing a certain amount of parasitic capacitance to resonate with the parasitic inductance introduced by the transmission line, thereby achieving broadband matching. In this example, the inner diameter of the two quasi-coaxial sections is 60μm, the outer diameter is 585μm, the anti-pad radius is 400μm, the stripline transition pad radius is 80μm, and the BGA transition pad radius is 140μm. There are no additional pads.

[0035] Those skilled in the art will appreciate that the embodiments described herein are intended to aid the reader in understanding the principles of the present invention, and it should be understood that the scope of the present invention is not limited to such specific descriptions and embodiments. Various modifications and variations are readily apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are intended to be included within the scope of the claims.

Claims

1. An ultra-wideband package interconnect structure between a chip and an external interface, characterized in that: Based on a low-temperature co-fired ceramic substrate, an interconnection structure of external interface SMA-microstrip line-first type coaxial line-first stripline-second type coaxial line-BGA solder ball is adopted; the microstrip line is located on the top ground of the low-temperature co-fired ceramic substrate, the first end of the microstrip line is connected to the external interface SMA, and the second end of the microstrip line is connected to the first end of the first type coaxial line; the second end of the first type coaxial line is connected to the first end of the first stripline, and the first stripline is located on the metal layer of the low-temperature co-fired ceramic substrate; the second end of the first stripline is connected to the first end of the second type coaxial line, the second end of the second type coaxial line is connected to the BGA solder ball, and the BGA solder ball is connected to the chip interface; The first type of coaxial and the second type of coaxial are connected to each layer of the occupied low temperature co-fired ceramic substrate through a welding pad; The parasitic capacitance introduced by each pad of the first type coaxial cable and the second type coaxial cable and the parasitic inductance introduced by the transmission line used for the routing of the first type coaxial cable and the second type coaxial cable form a multi-stage LC matching network.

2. The ultra-wideband package interconnect structure between a chip and an external interface according to claim 1, wherein: The material of the low-temperature co-fired ceramic substrate is Hitce.

3. The ultra-wideband package interconnect structure between a chip and an external interface according to claim 2, characterized in that: The first type coaxial and the second type coaxial are vertically interconnected structures; the first type coaxial and the second type coaxial occupy three layers of substrates.

4. The ultra-wideband package interconnect structure between a chip and an external interface according to claim 3, characterized in that: The height of the microstrip line is the height of a single-layer substrate.

5. The ultra-wideband package interconnect structure between a chip and an external interface according to claim 4, characterized in that: The calculated result of the impedance matching formula when the microstrip line height and width meet the requirements is 50 ohms.

6. An ultra-wideband package interconnect structure between chips, characterized in that: Based on a low-temperature co-fired ceramic substrate, an interconnection structure of first BGA solder ball - third-type coaxial - second stripline - fourth-type coaxial - second BGA solder ball is adopted. The first BGA solder ball is connected to the first chip interface, and the first BGA solder ball is also connected to the first end of the third-type coaxial. The second end of the third-type coaxial is connected to the first end of the second stripline. The second stripline is located in the metal layer of the low-temperature co-fired ceramic substrate; the second end of the second stripline is connected to the first end of the fourth-type coaxial, the second end of the fourth-type coaxial is connected to the second BGA solder ball, and the second BGA solder ball is connected to the second chip interface; The third type of coaxial and the fourth type of coaxial are connected to each layer of the occupied low temperature co-fired ceramic substrate through a welding pad; The parasitic capacitance introduced by each layer of the third and fourth coaxial cables and the parasitic inductance introduced by the transmission lines used for the routing of the third and fourth coaxial cables themselves form a multi-stage LC matching network.

7. The ultra-wideband package interconnect structure between chips according to claim 6, characterized in that: The material of the low-temperature co-fired ceramic substrate is Hitce.

8. The ultra-wideband package interconnect structure between chips according to claim 7, characterized in that: The third type coaxial and fourth type coaxial are vertically interconnected structures; the third type coaxial and fourth type coaxial occupy three layers of substrates.

9. The ultra-wideband package interconnect structure between chips according to claim 8, characterized in that: The distance between the ground and the trace above the second stripline is 3 layers of substrate height.

10. The ultra-wideband package interconnect structure between chips according to claim 9, characterized in that: The distance between the ground and the trace under the second stripline is 2 layers of substrate height.

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