Vertical power component

Abstract

The description relates to a vertical power component formed in and on a semiconductor substrate doped with a first conductivity type, and an upper side of the semiconductor substrate is coated with a semiconductor layer doped with the first conductivity type. The component comprises: an active region (100A); and first and second sets of first concentric field limiting rings surrounding the active region. Each first ring includes a first semiconductor region doped with a second conductivity type opposite to the first conductivity type, the first semiconductor region extending vertically from an upper side of the semiconductor layer into a thickness of the semiconductor layer; and a second field limiting ring laterally interposed between the first and second sets of first field limiting rings (GR). The second ring includes a second doped semiconductor region of the second conductivity type extending vertically from above the semiconductor layer into the thickness of the semiconductor layer. A width of the second semiconductor region is at least three times greater than a width of the widest first semiconductor region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to French patent application No. FR 2309013, filed on August 28, 2023, entitled “Composant vertical depuissance”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] The present description relates generally to electronic devices. The present description relates more particularly to vertical power components. Background Art

[0004] Vertical power components have been proposed. Among these components, JBS (junction-barrier Schottky) diodes are more particularly proposed. JBS diodes have advantages similar to conventional Schottky diodes, including low on-state voltage drop, low threshold voltage and low switching losses. In addition, JBS diodes have improved resistance and lower leakage current in the case of current overload compared to conventional Schottky diodes.

[0005] However, existing vertical power components have various disadvantages. More specifically, arcs may occur inside these components when they are subjected to high reverse voltages. The arcs cause irreversible degradation in the vertical power components where the arcs are formed, resulting in failures that render the components at least partially inoperable. Summary of the invention

[0006] It is desirable to overcome all or some of the disadvantages of existing vertical power components. In particular, it is desirable to prevent arcing in existing vertical power components.

[0007] To this end, one embodiment provides a vertical power component, which is formed in and on a semiconductor substrate doped with a first conductivity type and coated with a semiconductor layer doped with the first conductivity type on the upper side of the semiconductor substrate, the component comprising:

[0008] active area; and

[0009] a first and a second set of first concentric field limiting rings surrounding the active region, each first ring comprising a first semiconductor region doped with a second conductivity type opposite to the first conductivity type, extending vertically from an upper side of the semiconductor layer into the thickness of the semiconductor layer;

[0010] a second field limiting ring, laterally interposed between the first and second groups of first field limiting rings, the second ring comprising a second doped semiconductor region of a second conductivity type extending vertically from above the semiconductor layer into the thickness of the semiconductor layer; and

[0011] a first insulating region (109) located on top of the entire upper surface of the second doped semiconductor region (305P) and in mechanical contact therewith,

[0012] The width of the second semiconductor region is at least three times greater than the width of the widest first semiconductor region.

[0013] According to one embodiment, the second ring reduces the electric field present near the interface between the first insulating region arranged on the upper side of the semiconductor layer and in contact therewith and the second insulating region located in the peripheral area of ​​the vertical power component by at least half, for example by at least two thirds.

[0014] According to one embodiment, the second ring enables reducing the electric field present near the interface between the first insulating region arranged on the upper side of the semiconductor layer and in contact therewith and the molding resin of the encapsulation of the vertical power component by at least half, for example by at least two thirds.

[0015] According to one embodiment, the first set and the second set comprise exactly the same number of first rings.

[0016] According to one embodiment, the first and second field limiting rings are floating guard rings.

[0017] According to one embodiment, the component further comprises at least a third group of first rings, and at least one third field limiting ring interposed between the second group of first rings and the at least one third group of first rings.

[0018] According to one embodiment, the semiconductor layer has a doping level strictly lower than a doping level of the semiconductor substrate.

[0019] According to one embodiment, the component comprises:

[0020] a first conductive electrode formed in the active region and including a conductive region on the semiconductor layer; and

[0021] The second conductive electrode is arranged on a side of the semiconductor substrate opposite to the semiconductor layer.

[0022] According to one embodiment, the semiconductor substrate is made of silicon or silicon carbide.

[0023] According to one embodiment, the first conductivity type is N and the second conductivity type is P.

[0024] According to one embodiment, the component is a JBS diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0026] Figure 1A and Figure 1B Along the Figure 1A A schematic and partial view of an example of a vertical power component from the top and in section of the plane BB shown in FIG.

[0027] Figure 2 yes Figure 1A and Figure 1B A schematic and partial top view of a peripheral area of ​​a vertical power component shown in;

[0028] Figure 3 is a detailed schematic and partial view of a peripheral area of ​​a vertical power component according to one embodiment; and

[0029] Figure 4 It is a graphic Figure 3 Graph showing the changes in the electric field and electrostatic potential in the peripheral area of ​​a vertical power component shown in FIG. DETAILED DESCRIPTION

[0030] Similar features are denoted by similar reference numerals in the various figures. In particular, common structural and / or functional features between various embodiments may have the same reference numerals and may have exactly the same structure, size, and material properties.

[0031] For clarity, operations and elements useful for understanding the embodiments described herein have been detailed and described. In particular, various applications implementing vertical power components are not described in detail, and the described embodiments are compatible with all or most applications that may utilize one or more vertical power components.

[0032] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0033] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.), or referring to relative position qualifiers (such as terms "above", "below", "higher", "lower", etc.), or referring to orientation qualifiers (such as "horizontal", "vertical", etc.), the orientation shown in the figure is referenced.

[0034] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "around" all mean within 10%, and in some cases within 5%.

[0035] In the following description, unless otherwise specified, the qualifiers “insulating” and “conductive” mean electrical insulation and electrical conductivity, respectively.

[0036] Figure 1A is a schematic partial top view illustrating an example of a vertical power component 100 . Figure 1B is the vertical power component 100 along Figure 1A Cross-sectional view of plane BB.

[0037] In the example shown, the vertical power component 100 is a JBS (junction-barrier Schottky) diode, including an active region 100A, which corresponds to, for example, a region where a power signal may flow during component operation. In this example, the active region 100A of the vertical power component 100 is surrounded (flanked) by a peripheral region 100P through which a power signal is not intended to flow during component operation. The active region 100A is, for example, substantially located at the center of the vertical power component 100. The peripheral region 100P of the vertical power component 100 surrounds the active region 100A and, for example, has a ring shape in a top view. The peripheral region 100P is laterally inserted between the active region 100A and the edge of the vertical power component 100. Figure 1A An example is illustrated in which the vertical power component 100 has a generally rectangular shape in a top view. However, such an example is not limiting, as the vertical power component 100 may have any general shape in variations, such as a square shape, an oval shape, a circular shape, etc.

[0038] In the example shown, the vertical power component 100 is formed in and on a semiconductor substrate 101. The substrate 101 is, for example, a wafer or a piece of a wafer made of a semiconductor material, such as silicon (Si) or silicon carbide (SiC). The semiconductor substrate 101 is doped with a first conductivity type, such as N-type, and has a conductivity of, for example, between 1*10 17 and 5*10 20 at. / cm 3 The doping level between (N in the case where the first conductivity type is N type) + As an example, the semiconductor substrate 101 has a thickness greater than or equal to about 50 μm, the thickness of the semiconductor substrate 101 being selected, for example, to ensure the mechanical strength of the structure of the vertical power component 100 .

[0039] exist Figure 1B, a semiconductor layer 103 is coated on the semiconductor substrate 101 in the direction shown in FIG. The semiconductor layer 103 is made of, for example, the same material as the substrate 101 (for example, silicon or silicon carbide). As an example, the semiconductor layer 103 is an epitaxial layer, that is, formed by epitaxial growth on the upper surface of the semiconductor substrate 101. The semiconductor layer 103 is, for example, doped with a first conductivity type (in this example, N-type). The semiconductor layer 103 has, for example, a doping level strictly lower than the doping level of the semiconductor substrate 101, for example, between 1*10 13 and 5*10 17 at. / cm 3 The semiconductor layer 103 has a doping level and a thickness selected, for example, according to a voltage tolerance to be achieved by the vertical power component 100 .

[0040] In the example shown, the vertical power component 100 further includes semiconductor regions 105A, 105I, and 105P, which are formed from the surface of the semiconductor layer 103 opposite to the semiconductor substrate 101 (at Figure 1B 100A, and the semiconductor regions 105I and 105P form a portion of the peripheral region 100P of the vertical power component 100, with the region 105I being laterally inserted between the regions 105A and 105P. The semiconductor regions 105A, 105I, and 105P are doped with a second conductivity type (in this example, P-type) that is opposite to the first conductivity type. As an example, the semiconductor regions 105A, 105I, and 105P have a thickness between 1*10 17 and 5*10 20 at. / cm 3 The maximum doping level between (in the case where the second conductivity type is P type, P + The semiconductor regions 105A, 105I, and 105P are formed on the side of the semiconductor layer 103 opposite to the semiconductor substrate 101 by, for example, an ion implantation step and then an annealing step. Figure 1A In the embodiment, the semiconductor regions 105A and 105P are not shown in detail, but some semiconductor regions 105P (in this case, three semiconductor regions 105P) are shown to avoid overloading the drawing. Moreover, the number of semiconductor regions 105A and 105P may be the same as that of Figure 1A and 1B As an example, the number of semiconductor regions 105P is between five and three hundred, such as between ten and fifty, such as equal to about fifteen.

[0041] In the example shown, the semiconductor regions 105P and 105I have a concentric annular shape in the top view, and each semiconductor region 105P, 105I surrounds all semiconductor regions 105A. As an example, each semiconductor region 105P, 105I has a rectangular outline with rounded corners. The semiconductor region 105A forms, for example, strips parallel to each other and extending laterally in a direction orthogonal to the plane BB in the top view. In a variant, the semiconductor region 105A can form a grid in the top view, which includes first strips parallel to each other and orthogonal to the plane BB, and second strips parallel to each other and orthogonal to the first strips, a hexagonal shape, an elliptical or circular shape, a discontinuous strip, etc.

[0042] In the example shown, the vertical power component 100 further comprises a conductive region 107, which is arranged on and in contact with a portion of the upper surface of the semiconductor layer 103, the portion of the upper surface of the semiconductor layer 103 forming a portion of the active region 100A of the component 100, and the conductive region 107 is in contact with the upper surfaces of the semiconductor regions 105A and 105I. The conductive region 107, for example, defines the active region 100A of the component 100. The conductive region 107 is, for example, made of a metal stack, for example including aluminum (Al). In this case, the region 107 forms a Schottky contact (metal-semiconductor contact) with the semiconductor layer 103.

[0043] In the example shown, the insulating region 109 is arranged on and in contact with a portion of the upper surface of the semiconductor layer 103, which portion of the upper surface of the semiconductor layer 103 is part of the peripheral region 100P of the vertical power component 100, and the insulating region 109 is in contact with the upper surface of the semiconductor region 105P and a portion of the semiconductor region 105I. The insulating region 109 has, for example, a ring shape surrounding the active region 100A of the component 100 in a top view. In the example shown, the conductive region 107 extends laterally on and in contact with a portion of the upper surface of the insulating region 109. The insulating region 109 serves, for example, as a passivation layer of the vertical power component 100. As an example, the insulating region 109 is made of an oxide (e.g., silicon dioxide).

[0044] In the example shown, the vertical power component 100 further comprises another insulating region 113 in the peripheral region 100P of the component 100, which is arranged on and in contact with a portion of the upper surface of the conductive region 107 and in contact with the upper surface of the insulating region 109. The insulating region 113 has, for example, a ring shape in a top view surrounding the active region 100A of the component 100. The insulating region 113 forms, for example, a passivation layer of the vertical power component 100. As an example, the insulating region 113 is made of an organic material, for example, a polymer, for example, polybutylene oxide (PBO) or polyimide.

[0045] As a variant, the insulating region 113 may be omitted, in the case of a molded package assembly, the insulating region 109 being in contact with the molding resin.

[0046] The vertical power component 100 further includes a conductive layer disposed on a surface of the semiconductor substrate 101 opposite to the semiconductor layer 103 (at Figure 1B In the orientation shown in FIG. 1 , on the side of the lower side of the semiconductor substrate 101). Such a conductive layer is, for example, part of another conductive electrode (e.g., cathode) of the vertical power component 100. The conductive layer coating the lower side of the substrate 101 is, for example, made of the same material as the conductive region 107 (e.g., metal (e.g., nickel) or a metal alloy).

[0047] Also, although not shown, the vertical power component 100 may be surrounded by a package (eg, a package made of a polymer resin molded around the structure of the vertical power component 100 ).

[0048] Figure 2 yes Figure 1A and Figure 1B Schematic and partially detailed view of a peripheral area 100P of a vertical power component 100 is shown in FIG. Figure 2 More precisely Figure 1B 1 corresponds to a detailed cross-sectional view of the area 150 defined by the dotted box in FIG.

[0049] exist Figure 2 In the example shown in , the semiconductor regions 105P have exactly the same size within the manufacturing dispersion and are substantially regularly spaced. However, this example is not restrictive, and as a variant, the semiconductor regions 105P can have different sizes and / or spacings. In this case, the semiconductor regions 105P have, for example, exactly the same width and a variable pitch, or a variable width and a constant pitch. The semiconductor regions 105P of the peripheral region 100P of the vertical power component 100 enable the depletion region of the main junction formed at the interface between the semiconductor layer 103 and the conductive region 105I to be extended over a distance suitable for ensuring the voltage tolerance of the component 100.

[0050] In the example shown, the semiconductor region 105P is respectively part of a field limiting ring (GR) (e.g., a floating guard ring (FGR)), each GR ring including a single semiconductor region 105P. As an example, the field limiting ring GR has a pitch and a width, which are sized so that a substantially constant electric field can be obtained near the interface between the insulating regions 109 and 113 when the vertical power component 100 is subjected to a nominal voltage applied between its conductive electrodes. As an example, the absolute value of the nominal voltage is greater than or equal to 350V, for example, between 600V and 15kV.

[0051] In the example shown, the field limiting rings GR of the vertical power component 100 are divided into three sets (or groups) S1, S2 and S3 of rings GR, each set (or group) including a substantially equal number of rings GR and, therefore, a substantially equal number of semiconductor regions 105P. In the example shown, group S1 includes rings GR whose semiconductor regions 105P are closest to the active region 100A of the vertical power component 100, group S3 includes rings GR whose semiconductor regions 105P are farthest from the active region 100A, and group S2 includes rings GR whose semiconductor regions 105P are laterally inserted between the semiconductor regions of group S1 and the semiconductor regions of group S3. Figure 2 In the semiconductor substrate 101, the upper surface and Figure 1A An axis parallel to the plane BB shown in FIG. 1 and oriented from the active region 100A toward the peripheral region 100P of the vertical power component 100 enables identification of the distance (D) separating each GR or each semiconductor region 105P from the active region 100A.

[0052] The disadvantages of the vertical power component 100 are due to the fact that delamination or detachment phenomena may occur, in particular between the package and the vertical power component 100 or between the insulating region 113 and the insulating region 109. In the case of the vertical power component 100 without the insulating region 113, delamination phenomena may occur between the insulating region 109 and the molded resin of the package. The delamination phenomenon leads to the appearance of a gaseous layer (e.g., an air layer), in which arcs may form, for example, when the vertical power component is subjected to a high reverse voltage. The arcs cause irreversible damage in the vertical power component 100, resulting in a malfunction, which renders the vertical power component 100 at least partially inoperable.

[0053] Figure 3 is a schematic and partially detailed view of a peripheral area of ​​a vertical power component 300 according to one embodiment. In the example shown, the vertical power component 300 is a JBS diode. Figure 3 The vertical power component 300 shown in FIG. 1 includes Figure 1A , Figure 1B and Figure 2 Such common elements will not be discussed in detail below. Figure 3 The vertical power component 300 shown in FIG. Figure 1A , Figure 1B and Figure 2 The vertical power component 100 shown in FIG. 1 differs in that the component 300 includes a peripheral region 300P similar to the peripheral region 100P of the component 100, but in addition to the groups S1, S2 and S3 of field limiting rings GR including the semiconductor region 105P, it also includes other field limiting rings (LGRs), such as floating guard rings, each of which includes a semiconductor region 305P.

[0054] The semiconductor regions 105P and 305P are, for example, concentric, and each semiconductor region 305P is laterally inserted between two groups of semiconductor regions 105P. In other words, each field limiting ring LGR is laterally inserted between two groups (S1 and S2, or S2 and S3) of field limiting rings GR. In the example shown, the field limiting rings LGR form two gaps or spaces G1 and G2, separating the group S1 from the group S2 and the group S2 from the group S3, respectively.

[0055] exist Figure 3 In the example shown in FIG. 1 , each semiconductor region 305P is formed from a surface of the semiconductor layer 103 opposite to the semiconductor substrate 101 (in Figure 3 10 , the semiconductor region 305P extends vertically into the thickness of the semiconductor layer 103. The semiconductor region 305P has a thickness that is strictly less than the thickness of the semiconductor layer 103, for example, a thickness that is substantially equal to the thickness of the semiconductor region 105P. In the example shown, the semiconductor region 305P forms a portion of the peripheral region 300P of the vertical power component 300. The semiconductor region 305P is doped with a second conductivity type (in this example, a P type). As an example, the 305P semiconductor region has a thickness between 1*10 17 and 5*10 20 at. / cm3 doping level (P + The semiconductor region 305P is doped, in the case where the second conductivity type is P type), for example, a doping level substantially equal to the doping level of the semiconductor region 105P. The semiconductor region 305P is formed on the side of the semiconductor layer 103 opposite to the semiconductor substrate 101, for example, by an ion implantation step and then an annealing step. As an example, the semiconductor regions 105P and 305P are formed simultaneously.

[0056] According to one embodiment, each semiconductor region 305P has a width that is strictly greater than the width of each semiconductor region 105P. In other words, the field limiting ring LGR has a width that is strictly greater than the width of the field limiting ring GR. As an example, the width of each 305P semiconductor region is at least three times greater than the width of the widest 105P semiconductor region. Figure 3 In the example shown in , semiconductor regions 305P have exactly the same size within the manufacturing spread.

[0057] According to one embodiment, the insulating region 109 is located on top of the entire upper side of each semiconductor region 305P and is in mechanical contact with it. In particular, the vertical power component 300 does not have any conductive elements in contact with the upper side of the semiconductor region 305P. In the example shown, the insulating region 109 is also located on top of the entire upper side of each semiconductor region 105P and is in mechanical contact with it. In particular, the vertical power component 300 does not have any electrically conductive elements in contact with the upper side of the semiconductor region 105P.

[0058] As an example, the number of field limiting rings LGR or the number of groups of field limiting rings GR is selected according to the target voltage tolerance of the vertical power component 300. Moreover, for example, the number of field limiting rings GR in each group S1, S2, S3 is selected depending on the minimum voltage at which an arc is formed in the event of delamination or detachment in the vertical power component 300. For example, the minimum voltage is given by Paschen's law applied to the vertical power component 300. The geometry, number and distribution of the field limiting rings GR are defined so that the electric field near the interface between the insulating regions 109 and 113 is substantially constant over the groups S1, S2 and S3.

[0059] One advantage of the vertical power component 300 is that the presence of the ring LGR including the semiconductor region 305P reduces the intensity of the electric field present near the interface between the insulating regions 109 and 113. Thus, the risk of arcing in the event of delamination or detachment in the vertical power component 300 can be advantageously prevented or limited.

[0060] Figure 4 is a graph 400, which illustrates through curves 401 and 403 respectively Figure 3 The change of the electric field E and the electrostatic potential (V) in the peripheral area 300P of the vertical power component 300 shown in FIG. 1 , where the electric field E is expressed in volts per centimeter (V.cm -1 ), and the electrostatic potential (V) is expressed in volts (V). For comparison, the graph 400 also illustrates the changes of the electric field E and the electrostatic potential V in the peripheral region 100P of the vertical power component 100 by dashed curves 405 and 407, respectively. The graph 400 more accurately represents the changes of the electric field E in the insulating region 109 of the vertical power component 100 or 300 (for example, near the interface with the insulating region 113), and the changes of the electrostatic potential V in the semiconductor material near the interface with the insulating region 109. This change is expressed as a function of the distance D.

[0061] In the example shown, the curve 401 indicates that directly below each group S1, S2, S3 of the rings GR, the electric field E is substantially constant and equal to approximately 2*10 5 V.cm -1, and in each gap G1, G2 located directly below the LGR ring, the electric field E is sharply reduced, for example, by a factor of 2 or 3. In other words, the field limiting ring LGR reduces the electric field E by half, for example, by at least two thirds, compared to the constant field region. As a comparison, curve 405 indicates that in the case of a vertical power component 100, the electric field E along the distance axis D is substantially constant and equal to about 2*10 5 V.cm -1 .

[0062] exist Figure 4 In the example shown in , the curve 403 indicates that the electrostatic potential V increases by a value V1 between the two ends of the group S1 of the ring GR, by a value V2 between the two ends of the group S2 of the ring GR, and by a value V3 between the two ends of the group S3 of the ring GR. For example, each of the values ​​V1, V2 and V3 is strictly below a minimum voltage, above which arcing may occur in the vertical power component 300 in the event of delamination or detachment. As an example, each value V1, V2, V3 is below 280V, for example, around 250V, and the sum of the values ​​V1, V2 and V3 is, for example, equal to about 750V. Moreover, in the example shown, the electrostatic potential V is substantially constant in the gaps G1 and G2, and the curve 403 includes a platform corresponding to the position of the ring LGR. In comparison, the curve 407 does not have such a platform.

[0063] like Figure 4 As shown in the graph 400 in FIG. 1 , an advantage of the vertical power component 300 lies in the fact that the presence of field limiting rings LGR inserted laterally between the groups S1 , S2 and S3 of field limiting rings GR creates a weak electric field region, which prevents the formation of arcs that adversely affect the operation of the component 300 when delamination or detachment occurs.

[0064] Various embodiments and variations have been described. It will be appreciated by those skilled in the art that certain features of these embodiments may be combined, and other variations will be readily apparent to those skilled in the art. In particular, the embodiments are not limited to the case where the vertical power component 300 is a JBS diode, but are more generally applicable to any type of vertical power component including a field limiting ring, such as a bipolar diode, a MOS (metal oxide semiconductor) transistor, a thyristor, etc., for example, to any type of vertical power component that may be subjected to a voltage greater than 350V between its conductive electrodes. It is within the scope of those skilled in the art to apply the embodiments to such components, as indicated above.

[0065] Finally, based on the functional description provided above, the actual implementation of the embodiments and variants described herein is within the capabilities of those skilled in the art. In particular, those skilled in the art are able to adjust the number of groups of field limiting rings GR, the number of field limiting rings GR in each group of field limiting rings GR, and the lateral size of each field limiting ring LGR according to the application. Moreover, the embodiments are not limited to the examples of materials and dimensions described.

[0066] A vertical power component (300) can be formed in and on a semiconductor substrate (101) that is doped with a first conductivity type and coated on its upper side with a semiconductor layer (103) doped with the first conductivity type. The component (300) can be summarized as comprising: an active area (100A); and first and second groups (S1, S2) of first concentric field limiting rings (GR) surrounding the active area (100A), each first ring (GR) comprising a first semiconductor region (105P) doped with a second conductivity type opposite to the first conductivity type, extending vertically from the upper side of the semiconductor layer (103) into the thickness of the semiconductor layer (103); and - a second field limiting ring (LGR) that is laterally inserted between the first group and the second group (S1, S2) S2) between the first field limiting ring (GR), the second ring (LGR) includes a second doped semiconductor region (305P) of the second conductivity type, which extends vertically from the top of the semiconductor layer (103) into the thickness of the semiconductor layer (103); and a first insulating region (109), which is located on top of the entire top of the second doped semiconductor region (305P) and is in mechanical contact with it, wherein the width of the second semiconductor region (305P) is at least three times the width of the widest first semiconductor region (105P).

[0067] The second ring (LGR) reduces the electric field (E) present near the interface between the first insulating region (109) arranged on the upper surface of the semiconductor layer (103) and in contact with it and the second insulating region (113) located in the peripheral region (100P) of the vertical power component (300) by at least half, preferably by at least two thirds.

[0068] The second ring (LGR) enables the electric field (E) present near the interface between the first insulating region (109) arranged on the upper side of the semiconductor layer (103) and in contact therewith and the molded resin of the package of the vertical power component (300) to be reduced by at least half, preferably by at least two thirds.

[0069] The first and second groups (S1, S2) include exactly the same number of first rings (GR).

[0070] The first and second field limiting rings (GR, LGR) are floating guard rings.

[0071] The component (300) further comprises at least a third group (S3) of first rings (GR), and at least one third field limiting ring (LGR) interposed between the second group (S2) of first rings and the at least one third group (S3) of first rings.

[0072] The semiconductor layer (103) has a doping level strictly lower than the doping level of the semiconductor substrate (101).

[0073] The component (300) may include: a first conductive electrode formed in the active region (100A) and including a conductive region (107) located on the semiconductor layer (103); and a second conductive electrode arranged on a side of the semiconductor substrate (101) opposite to the semiconductor layer.

[0074] The semiconductor substrate (101) is made of silicon or silicon carbide.

[0075] The first conductivity type is N, and the second conductivity type is P.

[0076] The component is a JBS diode.

[0077] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A vertical power component, comprising: a semiconductor substrate doped with a first conductivity type; a semiconductor layer doped with a first conductivity type, on a semiconductor substrate; Active area; a first and a second set of first field limiting rings surrounding the active region, each first field limiting ring comprising a first semiconductor region doped with a second conductivity type opposite to the first conductivity type, extending into the thickness of the semiconductor layer; a second field limiting ring, laterally interposed between the first and second groups of first field limiting rings, the second field limiting ring comprising a second semiconductor region doped with a second conductivity type extending into the thickness of the semiconductor layer; as well as a first insulating region over the entire surface of the second semiconductor region and in mechanical contact therewith, The width of the second semiconductor region is at least three times greater than the width of the widest first semiconductor region.

2. The vertical power component of claim 1 , further comprising: a second insulating region, located in a peripheral region of the vertical power component, The second field limiting ring is configured to reduce an electric field present near an interface between the first insulating region and the second insulating region by at least half. 3 . The vertical power component according to claim 1 , wherein the second field limiting ring enables reducing the electric field present near the interface between the first insulating region and the molding resin of the package of the vertical power component by at least half. 4 . The vertical power component of claim 1 , wherein the first group and the second group include the same number of first field limiting rings.

5. The vertical power component of claim 1, wherein the first field limiting ring and the second field limiting ring are floating guard rings.

6. The vertical power component of claim 1, further comprising: at least one third set of first field limiting rings; as well as At least one third field limiting ring is inserted between the second group of first field limiting rings and the at least one third group of first field limiting rings. The vertical power component of claim 1 , wherein a doping level of the semiconductor layer is lower than a doping level of the semiconductor substrate.

8. The vertical power component of claim 1, further comprising: a first conductive electrode formed in the active region and comprising a conductive region located on the semiconductor layer; as well as The second conductive electrode is arranged on a side of the semiconductor substrate opposite to the semiconductor layer.

9. The vertical power component of claim 1, wherein the semiconductor substrate is made of silicon or silicon carbide. 10 . The vertical power component of claim 1 , wherein the first conductivity type is N and the second conductivity type is P.

11. The vertical power component of claim 1, wherein the vertical power component is a Junction-Barrier Schottky (JBS) diode.

12. A device comprising: a semiconductor substrate having a first conductivity type; a semiconductor layer on the semiconductor substrate, the semiconductor layer having a first conductivity type; as well as A power component on a semiconductor layer, the power component comprising an active area and a peripheral area surrounding the active area, the peripheral area comprising: a first plurality of first semiconductor regions extending into the semiconductor layer, the first semiconductor regions having a second conductivity type; a second semiconductor region extending into the semiconductor layer, the second semiconductor region having a width greater than each of the widths of the first semiconductor region; and A second plurality of first semiconductor regions extends into the semiconductor layer, the first plurality of first semiconductor regions being separated from the second plurality of first semiconductor regions by second semiconductor regions. 13 . The device of claim 12 , wherein a width of the second semiconductor region is at least three times greater than each of the widths of the first semiconductor region.

14. The apparatus according to claim 12, further comprising: A first insulating region is on the semiconductor layer, the first plurality of first semiconductor regions, the second semiconductor region, and the second plurality of first semiconductor regions. The device of claim 14 , wherein the first insulating region physically contacts an entire face of the second semiconductor region.

16. The device of claim 14, wherein the active region comprises a conductive region on the semiconductor layer, and the first insulating region is on the conductive region.

17. The apparatus according to claim 16, further comprising: A second insulating region is over the first insulating region and the conductive region.

18. The device of claim 12, wherein the semiconductor layer is an epitaxial layer.

19. A device comprising: a semiconductor substrate having a first conductivity type; A semiconductor layer on the semiconductor substrate, the semiconductor layer having a first conductivity type; active regions in and on the semiconductor layer; as well as A peripheral region surrounding the active region, the peripheral region comprising: a first plurality of first semiconductor regions in the semiconductor layer; a second plurality of first semiconductor regions in the semiconductor layer, the first semiconductor regions having a second conductivity type; a second semiconductor region in the semiconductor layer and between the first plurality of first semiconductor regions and the second plurality of first semiconductor regions, the second semiconductor region having a width greater than each of the widths of the first semiconductor regions; and A first insulating region is on the semiconductor layer, the first plurality of first semiconductor regions, the second plurality of first semiconductor regions, and the second semiconductor region. 20 . The device of claim 19 , wherein each of the first semiconductor region and the second semiconductor region has a thickness smaller than that of the semiconductor layer.

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