Edge termination region for super junction device

Abstract

A semiconductor power device has an active region and an edge termination region surrounding the active region. The device includes a plurality of drift regions of a first conductivity type and a plurality of separation regions of a second conductivity type in alternating contact with each other to form a plurality of mutually parallel p-n junctions extending in a vertical direction between adjacent drift regions and separation regions. In the edge termination region, the depths of adjacent drift regions and separation regions are reduced by the edge termination region. The device further includes one or more electrically floating regions of the first conductivity type within the edge termination region.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device, and in particular, but not exclusively, to an edge termination region of a super junction metal oxide semiconductor field effect transistor (MOSFET). Background Art

[0002] Power semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs) require high breakdown voltages. High breakdown voltage (BV) values ​​can be achieved in the active region of superjunction MOSFETS. However, the breakdown voltage of prior art superjunction devices is reduced due to charge balance interruptions or discontinuities at the edge termination region.

[0003] US 10,205,009 B2 and US 9,595,596 B2 both relate to superjunction semiconductor devices. Summary of the invention

[0004] Various aspects and preferred features are set out in the appended claims.

[0005] According to a first aspect of the present disclosure, there is provided a semiconductor power device, the semiconductor power device having an active region and an edge termination region surrounding the active region, wherein the edge termination region is laterally located between the active region and a side surface of the semiconductor device, the device comprising:

[0006] a semiconductor substrate including a semiconductor substrate region of a first conductivity type;

[0007] A plurality of drift regions of the first conductivity type and a plurality of separation regions of the second conductivity type are each disposed on the semiconductor substrate region and are alternately in contact with each other to form a plurality of mutually parallel pn junctions extending in a vertical direction between adjacent drift regions and separation regions,

[0008] wherein in the edge termination region, two or more of the plurality of separation regions extend to form a layer of the second conductivity type over two or more of the plurality of drift regions, and wherein depths of adjacent drift regions and separation regions decrease from the transition region to a side surface of the device through the edge termination region; and

[0009] One or more electrically floating regions of the first conductivity type are located above the layer of the second conductivity type and within the edge termination region.

[0010] The electrically floating region improves the charge balance, thereby increasing the breakdown voltage of the edge termination region. As the depth of the adjacent drift region and the separation region is reduced through the edge termination region, the edge termination length of the device can be significantly reduced.

[0011] In the active region, one or more drift regions of the plurality of drift regions may extend such that the separation regions within the active region form physically separated separation regions.

[0012] The semiconductor power device may further include a plurality of second conductivity type floating pillar regions. Each second conductivity type floating pillar region may be located below the second conductivity type separation region.

[0013] The semiconductor power device may further include an insulating layer formed over the electrically floating region.

[0014] The device may further include a transition region laterally located between the active region and the edge termination region.

[0015] The layer of the second conductivity type may extend laterally over one or more drift regions of the plurality of drift regions within the transition region.

[0016] Each of the plurality of pillars of the second conductivity type may include a plurality of implant regions of the second conductivity type arranged above one another along a depth of the pillar of the second conductivity type.

[0017] Each of the plurality of pillars of the first conductivity type may include a plurality of implant regions of the first conductivity type arranged above one another along a depth of the pillar of the first conductivity type.

[0018] The one or more electrically floating regions of the first conductivity type may form a plurality of laterally separated concentric ring structures.

[0019] Each of the one or more electrically floating regions of the first conductivity type may have substantially the same width.

[0020] The one or more electrically floating regions of the first conductivity type may form a variable lateral doping (VLD) structure. The VLD structure has the ability to support a high reverse bias voltage.

[0021] The semiconductor power device may further include a buffer region of the first conductivity type located above the semiconductor substrate region of the first conductivity type. The buffer region of the first conductivity type may have a lower doping concentration than the semiconductor substrate region of the first conductivity type.

[0022] The device may further include a channel stop region laterally located between the edge termination structure and the side surface of the semiconductor device. The channel stop region may extend to the side surface of the semiconductor device. The channel stop region may have a higher doping concentration than the drift region.

[0023] The device may include a super junction power device.

[0024] The device may include a metal oxide semiconductor field effect transistor (MOSFET).

[0025] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor power device, the semiconductor power device having an active region and an edge termination region surrounding the active region, wherein the edge termination region is laterally located between the active region and a side surface of the semiconductor device, the method comprising:

[0026] providing a semiconductor substrate including a first region of a first conductivity type;

[0027] A plurality of drift regions of the first conductivity type and a plurality of separation regions of the second conductivity type are formed on the semiconductor substrate region and are alternately contacted with each other to form a plurality of mutually parallel pn junctions extending in a vertical direction between adjacent drift regions and separation regions,

[0028] wherein in the edge termination region, two or more of the plurality of separation regions extend to form a layer of the second conductivity type over two or more of the plurality of drift regions, and wherein depths of adjacent drift regions and separation regions decrease from the transition region to a side surface of the device through the edge termination region; and

[0029] One or more electrically floating regions of the first conductivity type are formed over the layer of the second conductivity type and within the edge termination region.

[0030] Forming a plurality of drift regions and a plurality of separation regions, and forming one or more electrically floating regions of the first conductivity type, may include performing each of steps (i) to (v) one or more times:

[0031] (i) depositing a semiconductor layer over the semiconductor substrate region;

[0032] (ii) forming a first mask over the semiconductor layer. The first mask may expose an upper surface of a first plurality of regions of the semiconductor layer. The first plurality of regions may be laterally spaced apart from each other;

[0033] (iii) selectively doping the first plurality of regions of the semiconductor layer to form a first plurality of regions of the first conductivity type;

[0034] (iv) forming a second mask over the semiconductor layer. The second mask may expose an upper surface of a second plurality of regions of the semiconductor layer. The second plurality of regions may be laterally spaced apart from one another and may be located between adjacent regions of the first plurality of regions of the first conductivity type;

[0035] (v) selectively doping the second plurality of regions of the semiconductor layer to form a first plurality of regions of the second conductivity type.

[0036] Each first mask and / or each second mask may expose additional regions in addition to the exposed regions of the first mask or the second mask on the previously deposited semiconductor layer.

[0037] The exposed region of the first mask closest to the side surface of the device or the exposed region of the second mask closest to the side surface of the device has a different width from other exposed regions of the first mask and the second mask between the exposed region closest to the side surface and the active region.

[0038] An exposed region of the first mask closest to the side surface of the device or an exposed region of the second mask closest to the side surface of the device may be smaller in width than other exposed regions of the first and second masks between the exposed region closest to the side surface and the active region.

[0039] The exposed region of the first mask closest to the side surface of the device or the exposed region of the second mask closest to the side surface of the device can be about half the width of other exposed regions of the first mask and the second mask between the exposed region closest to the side surface and the active region.

[0040] The further exposed regions of each of the semiconductor layers closest to the side surface of the device may have different widths such that they extend to substantially the same lateral position in the device.

[0041] The exposed region of the first mask closest to the side surface of the device or the exposed region of the second mask closest to the side surface of the device may be used herein to refer to an exposed region forming a drift region or a separation region, and may not be used to refer to a region forming a channel stop region.

[0042] The method may further include: depositing an additional semiconductor layer over the previously deposited semiconductor layer; forming a mask over the additional semiconductor layer, wherein the mask may expose an upper surface of a plurality of regions of the additional semiconductor layer; and selectively doping the plurality of regions of the additional semiconductor layer to form a plurality of regions of the second conductivity type. The regions of the additional semiconductor layer may be substantially aligned with the plurality of regions of the second conductivity type.

[0043] The method may further include: depositing an additional semiconductor layer on top of a previously deposited semiconductor layer; forming a mask on top of the additional semiconductor layer, wherein the mask may expose an upper surface of a plurality of regions of the additional semiconductor layer; and selectively doping the plurality of regions of the additional semiconductor layer to form a plurality of island regions of the first conductivity type in the edge termination region. The regions of the additional semiconductor layer may be substantially aligned with the plurality of regions of the second conductivity type in the edge termination region. The mask may not expose the additional semiconductor layer in the active region. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Some preferred embodiments of the present disclosure will now be described, by way of example only, and with reference to the accompanying drawings, in which:

[0045] FIG1 schematically illustrates a VLD edge termination region of a power semiconductor device according to an embodiment of the present disclosure;

[0046] Figure 2 Schematically illustrates a ring-shaped structure edge termination region of a power semiconductor device according to an embodiment of the present disclosure;

[0047] FIG3 shows FIG1 and Figure 2 p-type doping concentration of the device shown;

[0048] Figure 4 schematically illustrates a first set of steps in a method of manufacturing a device according to an embodiment of the present disclosure;

[0049] Figure 5 schematically illustrates a second set of steps in a method of manufacturing a device according to an embodiment of the present disclosure;

[0050] Figure 6 schematically illustrates a third set of steps in a method of manufacturing a device according to an embodiment of the present disclosure;

[0051] Figure 7 Shows Figure 6 Doping profile of the device shown;

[0052] Figure 8 schematically illustrates a fourth set of steps in a method of manufacturing a device according to an embodiment of the present disclosure;

[0053] Fig. 9 schematically illustrates a fifth set of steps in a method of manufacturing a device according to an embodiment of the present disclosure;

[0054] Fig.10 Shows Fig. 9 Doping profile of the device shown;

[0055] Fig.11 schematically illustrates a sixth set of steps in a method of manufacturing a device according to an embodiment of the present disclosure;

[0056] Fig.12 Figure 1 and Figure 2 The simulated breakdown voltage of the device is shown.

[0057] Fig.13 illustrates an alternative edge termination region of a power semiconductor device according to an embodiment of the present disclosure;

[0058] Fig.14 illustrates an alternative edge termination region of a power semiconductor device according to an embodiment of the present disclosure; and

[0059] Fig.15 An alternative edge termination region of a power semiconductor device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0060] FIG1(a) schematically illustrates a lateral variable doping (VLD) edge termination region of a power semiconductor device 100 according to an embodiment of the present disclosure. FIG1(b) illustrates region A of FIG1(a) in more detail. The power semiconductor device 100 includes a semiconductor substrate. In an example, the semiconductor substrate is formed of silicon, although other semiconductor materials may be used.

[0061] The device 100 includes three regions: an active region 102 for current conduction, an edge termination region 104, and a transition region 106. The active region 102 is located in the center of the semiconductor device, while the edge termination region 104 surrounds the active region 102 and is located between the active region 102 and the side surface of the semiconductor device. The transition region 106 also surrounds the active region 102 and is located between the active region 102 and the edge termination region 104. It should be understood that FIG. 1 only shows a cross section through a portion of the semiconductor device.

[0062] In this embodiment, the semiconductor substrate includes an n-type substrate region 108. An n-type buffer region or drift region 110 is located above the n-type substrate region 108. The buffer region 110 has a lower doping concentration than the n-type substrate region 108.

[0063] A plurality of n-type columns 114 and a plurality of p-type columns 116 (or separation regions) are located above the drift region 110. The n-type column regions 114 extend from the drift region 110 and can be considered as additional drift regions. The n-type columns 114 and the p-type columns 116 are alternately contacted with each other so that each p-type column 116 is located between two adjacent n-type columns 114 to form parallel pn junctions extending in a vertical direction between the adjacent n-type columns 114 and the p-type columns 116.

[0064] In the edge termination region 104, the n-type column region 114 and the p-type column region 116 have different lengths and therefore extend to different depths within the semiconductor substrate. The column with the greatest depth or height is positioned closest to the transition region 106, and the column with the smallest depth is positioned closest to the side surface of the device, wherein the depths of the n-type column 114 and the p-type column 116 decrease toward the side surface of the device. The column with the greatest depth has the same depth as the n-type column within the transition region 106 and the active region 102, and each subsequent n-type column 114 or p-type column has a smaller depth than the adjacent column. By providing the n-type column 114 and the p-type column 116 in such a triangular arrangement, the edge termination length of the device can be significantly reduced.

[0065] In the active region 102, an n-type doped junction field transistor (JFET) region 136 is located above the n-type pillar 114, so that the n-type doped region extends to the upper surface of the semiconductor substrate. A gate polysilicon region 140 is located above the JFET n-type region 136 and is used to control the conductive channel in the active region. A gate insulating region 138, such as a silicon dioxide layer, is located above the gate polysilicon region 140. A source metal layer 148 is located on the upper surface of the device, above the gate insulating region 148.

[0066] In the edge termination region 104 and the transition region 106, a p-type layer 120 is located above the n-type pillars 114. The p-type layer 120 extends from the p-type pillars 116.

[0067] In the edge termination region 104, a plurality of n-type island regions 122 are located above the p-type layer 120 and the top surface of the semiconductor substrate. The island region 122 is electrically isolated or decoupled from the surrounding components of the device. The n-type island region 122 is formed on the top surface of the semiconductor substrate, and an insulating layer 134 such as a silicon dioxide layer is formed on the n-type island region 122. Compared with the device of the prior art, the floating n-type island region improves the charge balance, thereby increasing the breakdown voltage of the edge termination region.

[0068] A gate metal layer 154 is formed over the insulating layer 134. A polysilicon field plate 156 is over the channel stop region 118, and a metal field plate 158 is over the polysilicon field plate.

[0069] In the example shown in Figure 1, the independent island region 122 is wider towards the active area 102, and narrower towards the side surface of the device, to provide a VLD edge termination region. The VLD edge termination region has such a doping profile, wherein the doping concentration of the island-shaped region 122 gradually decreases from the source region to the drain region, which provides a more uniform surface electric field distribution so that the breakdown voltage is improved. This can be achieved by using a mask with different width openings, and the openings expose the region forming the island region 122. The VLD edge termination region has the ability to support a high reverse bias voltage.

[0070] The channel stop region 118 is located at a side surface of the semiconductor device, on a side of the edge termination region 104 opposite the active region 102. The channel stop region 118 includes an n-type region having a higher doping concentration than regions of the semiconductor substrate laterally adjacent to the channel stop region 118. The channel stop region 118 prevents a conductive channel from forming at the edge of the device.

[0071] It should be understood that the island regions 122 may alternatively have substantially the same width and the same doping concentration, thus forming a Figure 2 The ring terminal structure shown. Figure 2 Many of the features shown are identical to those shown in Figure 1 and therefore have the same reference numerals. It will also be appreciated that the gate contact region will have the same structure as the gate contact region shown in Figure 1(b).

[0072] FIG3(a) shows the p-type doping concentration of the device shown in FIG1, and FIG3(b) shows Figure 2 3(a) decreases from the transition region 106 toward the side surface of the device (as shown from left to right in this example) within the edge termination region 104. For the ring termination structure, the p-type doping concentration (in this example, the boron doping concentration) shown in FIG. 3(b) is substantially constant between the n-type islands 122.

[0073] Figure 4 The first set of steps in a method of manufacturing a semiconductor device such as that shown in FIG. 1 or 2 is schematically shown. This involves forming a semiconductor substrate having an n-type substrate region 108 and a buffer region 110 on the n-type substrate region 108. The buffer region 110 may be thermally grown on the substrate region 108.

[0074] Figure 5 A second group of steps in the method of manufacturing a semiconductor device is schematically illustrated. Figure 5 The steps are Figure 4Steps (i) to (v) are each performed multiple times in sequence. Figure 5 In the example shown, steps (i) to (v) are performed seven times, although they may be performed fewer or more times to form n-type pillars 114 and p-type pillars 116 of different depths.

[0075] Figure 5 The steps are:

[0076] (i) depositing a semiconductor layer 124 over the buffer region 110. Depositing a subsequent semiconductor layer over the previously deposited semiconductor layer. Epitaxial growth may be used to deposit the semiconductor layer 124;

[0077] (ii) forming a first mask over the semiconductor layer 124. The first mask exposes the upper surface of multiple laterally spaced regions of the semiconductor layer 124 to be doped with n-type doping. For example, the first mask may expose all regions that will subsequently become n-type regions (n-type column regions and channel stop regions). Except for the channel stop region 118 and the exposed region of each semiconductor layer 126a closest to the side surface of the device, each exposed laterally spaced region has substantially the same width. The width of each exposed region 126a of the side surface of the semiconductor layer closest to the device is smaller than the width of the other exposed regions. In the example shown, the exposed region 124 of each semiconductor layer closest to the side surface of the device is approximately half the width of the other exposed regions. This improves the charge balance of the manufactured device, thereby increasing the breakdown voltage of the manufactured device;

[0078] (iii) selectively doping the regions exposed using the mask of step (ii) by implanting an n-type dopant to form a plurality of n-type drift regions 126 and a plurality of channel stop regions 118. In the example, this is performed using vapor diffusion. In the example, the n-type dopant is phosphorus, however, it should be understood that other n-type implant elements or dopants may be used;

[0079] (iv) forming a second mask over the semiconductor layer 124. The second mask exposes the upper surface of a plurality of laterally spaced regions of the semiconductor layer 124 to be doped with p-type doping. For example, the second mask may expose all regions that will become p-type pillar regions. These regions are exposed by the second mask between adjacent n-type drift regions 126; except for the channel stop region 118 and the exposed region 126a of each semiconductor layer 124 closest to the side surface of the device, the regions exposed by the first mask and the second mask have approximately the same width;

[0080] (v) The regions exposed using the mask of step (iv) are selectively doped by implanting p-type dopants to form a plurality of p-type separation regions 128. In an example, this is performed using diffusion of boron.

[0081] Each time step (ii) is performed, the first mask exposes additional regions of the semiconductor layer, so that each layer has an additional n-type drift region 126, wherein only the exposed area of ​​each semiconductor layer 126a closest to the side surface of the device is smaller than other areas. Each time step (iv) is performed, the second mask also exposes additional regions of the semiconductor layer, so that each layer has an additional p-type separation region 128. It should be understood that steps (ii) and (iii) and steps (iv) and (v) can be interchanged in order so that the p-type region is formed before the n-type region.

[0082] Steps (i) to (v) are performed so that each semiconductor layer 124 has a repeating pattern of alternating n-type drift regions 126 and p-type separation regions 128 , wherein the region closest to the channel stop region 118 is the n-type drift region.

[0083] After performing steps (i) to (v) a plurality of times, perform the following additional steps:

[0084] (vi) depositing an additional semiconductor layer 130 over the previously deposited semiconductor layer 124. The semiconductor layer 130 may be deposited using epitaxial growth;

[0085] (vii) forming a first mask over the semiconductor layer 130. The first mask exposes the upper surface of a plurality of laterally spaced apart regions of the semiconductor layer 130 to be doped with an n-type dopant. The first mask over the semiconductor layer 130 exposes the same regions as the first mask used in the final repetition of step (ii), although the exposed regions 126a of the side surface of the semiconductor layer 130 closest to the device have the same width as the other exposed regions;

[0086] (viii) selectively doping the areas exposed using the mask of step (vii) to form a further plurality of layers of n-type drift regions 126 and channel stop regions 118. The doping concentration implanted in step (viii) is the same as the doping concentration implanted in step (iii). In an example, this is performed using vapor diffusion of phosphorus;

[0087] (ix) forming a second mask over semiconductor layer 130. The second mask exposes the upper surface of a plurality of laterally spaced apart regions of semiconductor layer 130 that are to be doped with p-type doping. For example, the second mask may expose all of the regions that are to become p-type pillar regions. The second mask over semiconductor layer 130 exposes the same regions as the second mask used in the last iteration of step (iv), although the second mask over semiconductor layer 130 exposes additional regions proximate the side surfaces of the device;

[0088] (x) The regions exposed using the mask of step (ix) are selectively doped to form a further plurality of p-type separation regions 128. The doping concentration implanted in step (x) is the same as the doping concentration implanted in step (v). In an example, this is performed using boron vapor diffusion.

[0089] Figure 6 A third group of steps in the method of manufacturing a semiconductor device is schematically illustrated. Figure 6 The steps are Figure 5 Follow the steps shown.

[0090] Figure 6 The steps are:

[0091] (xi) Previously in Figure 5 A further semiconductor layer 132 is deposited over the semiconductor layer 130 deposited in the step shown. The semiconductor layer 132 may be deposited using epitaxial growth;

[0092] (xii) A first mask is formed over the semiconductor layer 132. The first mask exposes the upper surface of a plurality of laterally spaced apart regions of the semiconductor layer 132 to be doped with the n-type doping. Figure 6 The first mask exposes the active region 102 and the transition region 106 and the channel stop region 118. Figure 5 The first mask of FIG. 1 is used to expose the same area as the first mask of FIG. 1 , but only a single area above the n-type drift region in the edge termination region 104 is exposed. The exposed area in the edge termination region 104 is closest to the transition region 106. This means that only a single n-type drift region 126 is formed in the edge termination region 104 of the semiconductor layer 132;

[0093] (xiii) selectively doping the areas exposed using the mask of step (xii) to form a further plurality of layers of n-type drift regions 126 and channel stop regions 118. The doping concentration implanted in step (viii) is the same as the doping concentration implanted in step (iii). In an example, this is performed using vapor diffusion of phosphorus;

[0094] (xiv) A second mask is formed on the semiconductor layer 132. The second mask exposes the upper surface of a plurality of laterally spaced regions to be doped with the p-type doped semiconductor layer 132. For example, the second mask may expose all regions to be p-type pillar regions. Figure 6 The second mask is exposed with Figure 6 the same area as the second mask formed on the semiconductor layer 130 in step (ix);

[0095] (xv) The regions exposed using the mask of step (xiv) are selectively doped to form a plurality of additional p-type separation regions 128. The doping concentration implanted in step (xv) is the same as the doping concentration implanted in step (v) and step (x). In an example, this is performed using boron vapor diffusion.

[0096] As about Figure 5 and 6 As described above, after the vapor diffusion of boron and phosphorus, an additional step of driving in dopants is performed to further diffuse or redistribute the dopants. The diffusion length of the initial diffusion is generally less than the diffusion length of the drive-in diffusion, so the drive-in process causes the dopants to diffuse further into the semiconductor substrate. The drive-in process increases the temperature of the wafer and causes impurities deposited on the surface of the semiconductor layer to diffuse into the semiconductor layer. This causes the n-type column 114 and the p-type column 116 to be formed by a separate n-type drift region 126 and a separate p-type separation region 128, respectively. This also causes the layer of the channel stop region 118 to become a single region, and causes the Figure 6 The p-type spacer layer 128 formed in the illustrated step becomes the p-type layer 120 located above the n-type pillars 114 and the p-type pillars 116 in the edge termination region 104 . Figure 7 It is shown that once the drive-in process is performed, Figure 6 Doping profile of the device shown.

[0097] Figure 8 A fourth group of steps in the method of manufacturing a semiconductor device is schematically illustrated. Figure 8 The steps are Figure 6 Follow the steps shown.

[0098] Figure 8 The steps are:

[0099] (xvi) Previously in Figure 6 An additional further semiconductor layer 152 is deposited over the semiconductor layer 132 deposited in the step shown. The semiconductor layer 152 may be deposited using epitaxial growth;

[0100] (xvii) A mask is formed over the semiconductor layer 152. The mask exposes the upper surface of a plurality of laterally spaced apart regions of the semiconductor layer 152 to be doped with the n-type doping. Figure 8 The mask is exposed in the edge termination region 104 and in the Figure 6 The second mask formed in step (xiv) is shown to cover the same area over the semiconductor layer 132 and expose the channel stop region 118 . Figure 8 The mask does not expose any area of ​​the active region 102 or the transition region 106 and does not expose any area in the edge termination region 104 above the previously formed n-type drift region 126;

[0101] (xviii) selectively doping the regions exposed using the mask of step (xvii) to form a plurality of n-type island regions 122 and additional layers of channel stop region 118. The doping concentration implanted in step (xviii) may be the same as the doping concentration implanted in steps (iii), (viii) and (xiii). In an example, this is performed using vapor diffusion of phosphorus.

[0102] As about Figure 8 As described, after the vapor diffusion of phosphorus, another additional step of driving in the diffused dopant is performed. The driving-in process increases the temperature of the wafer and causes the impurities deposited on the surface of the semiconductor layer to diffuse into the semiconductor layer. The formed n-type island region 122 improves the charge balance of the device, thereby increasing the breakdown voltage of the device.

[0103] Fig. 9 A fifth group of steps in the method of manufacturing a semiconductor device is schematically shown. Fig. 9 The steps are Figure 8 This involves forming an insulating layer 134 over the n-type island region 122 in the edge termination region 104. In this example, the insulating layer 134 is an oxide layer such as silicon dioxide, and can be formed by depositing or thermally growing a silicon dioxide layer over the upper surface of the entire semiconductor substrate and etching the silicon dioxide so that it covers the edge termination region 104.

[0104] Fig.10 Shows Fig. 9 Doping profile of the device shown.

[0105] Fig.11 A sixth group of steps in the method of manufacturing a semiconductor device is schematically shown. Fig.11 The steps are Fig. 9 Follow the steps shown.

[0106] Fig.11 The steps are:

[0107] (xv) The region of the upper surface of the semiconductor substrate within the active region 102 (JFET region) is doped with n-type impurities to form a JFET n-type region 136. This can be done in the same manner as described above with respect to Figure 5 , Figure 6 and Figure 8 The n-type region is formed in the same manner as described in ;

[0108] (xvi) depositing an interlayer dielectric (ILD (not shown);

[0109] (xvii) depositing a polysilicon region 140 in the gate insulation region 140 and over the JFET n-type region 136. The polysilicon region 140 is used to control the conduction channel in the active region. In some examples, the polysilicon region 140 is then etched using a mask so that it does not extend over the edge termination region;

[0110] (xviii) forming or implanting a p-type body region 142 at the upper surface of the semiconductor substrate in the active region 102 and the transition region 106;

[0111] (xix) forming or implanting highly doped n+ source regions 144 on either side of the p-type body region 142;

[0112] (xx) forming a gate insulating region 138 over the n-type JFET region 136. The gate insulating region 138 may be an oxide layer, such as silicon dioxide, which may be deposited or thermally grown;

[0113] (xxi) etching the upper surface of the device and implanting a highly doped p+ contact region 146 in the etched area;

[0114] (xxii) depositing a source metal layer 148 on the front (upper) surface of the device;

[0115] (xxiii) Grinding or planarizing the rear (lower) surface of the device and forming a drain metal contact 150.

[0116] Fig.12 1 and 2 shows the simulated breakdown voltage of the edge termination region device shown in FIG. 1 and 2. This shows the reduced breakdown voltage of the device as described herein compared to the prior art device. This shows the active region of device 802, VLD edge termination region 806 (as shown in FIG. 1), and ring structure edge termination region 804 (as shown in FIG. 2). Figure 2 The simulated breakdown voltage (BV) of the active region is shown in FIG. 2 . The VLD edge termination region and the ring structure edge termination region both have a BV of 99% of the active region.

[0117] Fig.13 An alternative edge termination region of a power semiconductor device according to an embodiment of the present disclosure is shown. Many features are similar to Fig.11 The features shown in FIG. 1 are the same and therefore have the same reference numerals. In this embodiment, during steps (i) to (v), each of the first mask and the second mask is configured so that each semiconductor layer has a p-type separation region 128a closest to the channel stop region, rather than the n-drift region 126.

[0118] exist Fig.13In the example shown, each time step (iv) is performed, the second mask exposes additional regions of the semiconductor layer, so that each layer has an additional p-type separation region 128, wherein only the exposed area of ​​each semiconductor layer 128a closest to the side surface of the device is smaller than the other regions. Each time step (ii) is performed, the first mask also exposes additional regions of the semiconductor layer, so that each layer has an additional n-type drift region 126.

[0119] Fig.14 An alternative edge termination region of a power semiconductor device according to an embodiment of the present disclosure is shown. Many features are similar to Fig.11 The features shown are identical and therefore have the same reference numerals.

[0120] In this embodiment, during steps (i) to (v), each of the first mask and the second mask is configured so that each semiconductor layer has the p-type separation region 128 a closest to the channel stop region, rather than the n-drift region 126 .

[0121] exist Fig.14 In the example shown, each time step (iv) is performed, the second mask exposes additional regions of the semiconductor layers so that each layer has an additional p-type separation region 128, wherein the exposed regions of each semiconductor layer closest to the side surface of the device have different widths so that they extend to substantially the same lateral position in the device. This forms p-type separation regions 128a with different widths closest to the side surface of the device, wherein the separation region 128a of the lowest semiconductor layer has the largest width, and the width of the separation region decreases for each semiconductor layer so that the top semiconductor layer 124 has the smallest p-type separation region. Each time step (ii) is performed, the first mask also exposes additional regions of the semiconductor layers so that each layer has an additional n-type drift region 126.

[0122] Fig.15 An alternative edge termination region of a power semiconductor device according to an embodiment of the present disclosure is shown. Many features are similar to Fig.11 The features shown are identical and therefore have the same reference numerals.

[0123] exist Fig.15In the example shown, each time step (ii) is performed, the first mask exposes additional regions of the semiconductor layer so that each layer has an additional n-type drift region 126. Each time step (iv) is performed, the second mask exposes a region 128a of the semiconductor layer that is adjacent to the additional n-type drift region 126 closest to the side surface of the device and is smaller than other exposed regions between the smaller region 128a and the active area 102. In step (iv), additional regions 128b are exposed by the mask, which are laterally spaced apart from the smaller region 126a at regular intervals and have the same width as the smaller region 126a. Each semiconductor layer has a reduced number of additional regions 128b, and the additional exposed regions 128b are aligned with the smaller regions 126a of the semiconductor layer 124. The additional p-type regions 128b form floating p-type columns. These floating p-type columns can be connected to each other or can be separated. Alternatively, they can be connected to adjacent p-type columns.

[0124] Reference Numbers

[0125] 100 power semiconductor device 118 channel stop region

[0126] 102 Active area 120p type layer

[0127] 104 edge termination region 122 floating n-type region

[0128] 106 transition region 124 semiconductor layer

[0129] 108n-type substrate 126n-type drift region

[0130] 110 buffer area 128p type separation area

[0131] 114n-type column 130 semiconductor layer

[0132] 116p type column 132 semiconductor layer

[0133] 134 insulation layer 148 source metal layer

[0134] 136 JFET n-type region 150 drain metal layer

[0135] 138 gate insulation region 152 semiconductor layer

[0136] 140 polysilicon region 154 gate metal layer

[0137] 142p-type body region 156 polysilicon field plate

[0138] 144n+ source region 158 metal field plate

[0139] 146p+ contact area

[0140] Those skilled in the art will appreciate that in the foregoing description and the appended claims, positional terms such as "above," "overlapping," "below," "lateral," and the like are made with reference to conceptual illustrations of the device, such as those showing standard cross-sectional perspective views and those shown in the accompanying drawings. These terms are used for ease of reference and are not intended to be limiting. Therefore, these terms should be understood to refer to the device in the orientation shown in the accompanying drawings.

[0141] It should be understood that all of the doping polarities described above may be reversed and the resulting device still conform to embodiments of the present invention.

[0142] Although the present disclosure has been described according to the preferred embodiments described above, it should be understood that these embodiments are merely illustrative and the claims are not limited to these embodiments. In view of this disclosure, those skilled in the art will be able to make modifications and substitutions, which are expected to fall within the scope of the appended claims. Each feature disclosed or shown in this specification may be incorporated into the present disclosure, either alone or in any appropriate combination with any other features disclosed or shown herein.

Claims

1. A semiconductor power device, the semiconductor power device having an active area and an edge termination area surrounding the active area, wherein the edge termination area is laterally located between the active area and a side surface of the semiconductor device, the device comprising: a semiconductor substrate including a semiconductor substrate region of a first conductivity type; A plurality of drift regions of the first conductivity type and a plurality of separation regions of the second conductivity type are each disposed on the semiconductor substrate region and are alternately in contact with each other to form a plurality of mutually parallel pn junctions extending in a vertical direction between adjacent drift regions and separation regions, wherein in the edge termination region, two or more of the plurality of separation regions extend to form a layer of a second conductivity type over two or more of the plurality of drift regions, and wherein depths of adjacent drift regions and separation regions decrease from the transition region to a side surface of the device through the edge termination region; as well as One or more electrically floating regions of the first conductivity type are located above the layer of the second conductivity type and within the edge termination region. 2 . The semiconductor power device according to claim 1 , wherein in the active area, one or more of the plurality of drift regions extend such that the separation region in the active area forms a physically separated separation region. 3 . The semiconductor power device according to claim 1 , further comprising a plurality of floating column regions of the second conductivity type, each floating column region being located below the separation region of the second conductivity type.

4. A semiconductor power device according to any preceding claim, further comprising an insulating layer formed over the electrically floating region.

5. A semiconductor power device according to any preceding claim, wherein the device further comprises a transition region laterally located between the active region and the edge termination region. 6 . The semiconductor power device of claim 5 , wherein the layer of the second conductivity type extends laterally over a drift region of the plurality of drift regions within the transition region.

7. A semiconductor power device according to any preceding claim, wherein each of the plurality of pillars of the second conductivity type comprises a plurality of implanted regions of the second conductivity type arranged on top of each other; and Each of the plurality of first conductivity type pillars includes a plurality of first conductivity type implant regions arranged on top of each other.

8. A semiconductor power device according to any preceding claim, wherein the one or more electrically floating regions of the first conductivity type form a plurality of laterally separated concentric ring structures.

9. A semiconductor power device as claimed in any preceding claim, wherein each of the one or more electrically floating regions of the first conductivity type have substantially the same width.

10. A semiconductor power device according to any preceding claim, wherein the one or more electrically floating regions of the first conductivity type form a Variant Lateral Doping (VLD) structure.

11. The semiconductor power device according to any preceding claim, further comprising a buffer region of the first conductivity type located above the semiconductor substrate region of the first conductivity type and having a lower doping concentration than the semiconductor substrate region of the first conductivity type.

12. A semiconductor power device according to any preceding claim, wherein the device further comprises a channel stop region laterally located between the edge termination structure and a side surface of the semiconductor device and extending to the side surface of the semiconductor device, and The channel stop region has a higher doping concentration than the drift region.

13. A semiconductor power device according to any preceding claim, wherein the device comprises a super junction power device.

14. A semiconductor power device as claimed in any preceding claim, wherein the device comprises a metal oxide semiconductor field effect transistor (MOSFET).

15. A method for manufacturing a semiconductor power device, the semiconductor power device having an active area and an edge termination area surrounding the active area, wherein the edge termination area is laterally located between the active area and a side surface of the semiconductor device, the method comprising: providing a semiconductor substrate including a first region of a first conductivity type; A plurality of drift regions of the first conductivity type and a plurality of separation regions of the second conductivity type are formed on the semiconductor substrate region and are alternately contacted with each other to form a plurality of mutually parallel pn junctions extending in a vertical direction between adjacent drift regions and separation regions, wherein in the edge termination region, two or more of the plurality of separation regions extend to form a layer of a second conductivity type over two or more of the plurality of drift regions, and wherein depths of adjacent drift regions and separation regions decrease from the transition region to the side surface of the device through the edge termination region; as well as One or more electrically floating regions of the first conductivity type are formed over the layer of the second conductivity type and within the edge termination region.

16. The method of claim 15, wherein the method of forming the plurality of drift regions and the plurality of separation regions, and forming the one or more electrically floating regions of the first conductivity type comprises: Perform each of steps (i) to (v) one or more times: (i) depositing a semiconductor layer on the semiconductor substrate region; (ii) forming a first mask over the semiconductor layer, wherein the first mask exposes an upper surface of a first plurality of regions of the semiconductor layer, wherein the first plurality of regions are laterally spaced apart from one another; (iii) selectively doping the first plurality of regions of the semiconductor layer to form a first plurality of regions of the first conductivity type; (iv) forming a second mask over the semiconductor layer, wherein the second mask exposes an upper surface of a second plurality of regions of the semiconductor layer, wherein the second plurality of regions are laterally spaced apart from each other and are located between adjacent regions of the first plurality of regions of the first conductivity type; (v) selectively doping the second plurality of regions of the semiconductor layer to form a first plurality of regions of the second conductivity type, Wherein each first mask and / or each second mask exposes additional areas in addition to the exposed areas of the first mask or the second mask on the previously deposited semiconductor layer.

17. The method of claim 16, wherein an exposed region of the first mask closest to the side surface of the device or an exposed region of the second mask closest to the side surface of the device has a different width from other exposed regions of the first mask and the second mask between the exposed region closest to the side surface and the active region.

18. The method according to claim 16 or 17, wherein the method further comprises: depositing an additional semiconductor layer over the previously deposited semiconductor layer; forming a mask over the further semiconductor layer, wherein the mask exposes an upper surface of a plurality of regions of the further semiconductor layer, wherein the regions of the further semiconductor layer are substantially aligned with the plurality of regions of the second conductivity type; as well as The plurality of regions of the further semiconductor layer are selectively doped to form a plurality of regions of the second conductivity type.

19. The method according to any one of claims 16 to 18, wherein the method further comprises: depositing an additional further semiconductor layer over the previously deposited semiconductor layer; forming a mask over the additional further semiconductor layer, wherein the mask exposes an upper surface of a plurality of regions of the additional further semiconductor layer, wherein said region of said additional further semiconductor layer is substantially aligned with said plurality of regions of the second conductivity type in said edge termination region, and wherein the mask does not expose the additional further semiconductor layer in the active region; and the plurality of regions of the additional further semiconductor layer are selectively doped to form a plurality of island regions of the first conductivity type in the edge termination region.

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