Edge termination region for super junction device

Abstract

A semiconductor power device has an active region and an edge termination region surrounding the active region. The device includes a plurality of drift regions of a first conductivity type and a plurality of separation regions of a second conductivity type in alternating contact with each other to form a plurality of mutually parallel p-n junctions extending in a vertical direction between adjacent drift regions and separation regions. In the edge termination region, the depths of adjacent drift regions and separation regions are reduced by the edge termination region. The device further includes one or more electrically floating regions of the first conductivity type within the edge termination region.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device, and in particular, but not exclusively, to an edge termination region of a super junction metal oxide semiconductor field effect transistor (MOSFET). Background Art

[0002] Power semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs) require high breakdown voltages. High breakdown voltage (BV) values ​​can be achieved in the active region of superjunction MOSFETS. However, the breakdown voltage of prior art superjunction devices is reduced due to charge balance interruptions or discontinuities at the edge termination region.

[0003] US 10,205,009 B2 and US 9,595,596 B2 both relate to superjunction semiconductor devices. Summary of the invention

[0004] Various aspects and preferred features are set out in the appended claims.

[0005] According to a first aspect of the present disclosure, there is provided a semiconductor power device, the semiconductor power device having an active region and an edge termination region surrounding the active region, wherein the edge termination region is laterally located between the active region and a side surface of the semiconductor device, the device comprising:

[0006] a semiconductor substrate including a semiconductor substrate region of a first conductivity type;

[0007] A plurality of drift regions of the first conductivity type and a plurality of separation regions of the second conductivity type are each disposed on the semiconductor substrate region and are alternately in contact with each other to form a plurality of mutually parallel pn junctions extending in a vertical direction between adjacent drift regions and separation regions,

[0008] wherein in the edge termination region, two or more of the plurality of separation regions extend to form a layer of the second conductivity type over two or more of the plurality of drift regions; and

[0009] One or more electrically floating regions of the first conductivity type are located above the layer of the second conductivity type and within the edge termination region.

[0010] The electrically floating region improves the charge balance, thereby increasing the breakdown voltage of the edge termination region.

[0011] In the active region, one or more drift regions of the plurality of drift regions may extend such that the separation regions within the active region form physically separated separation regions.

[0012] The semiconductor power device may further include an insulating layer formed over the electrically floating region.

[0013] The device may further include a transition region laterally located between the active region and the edge termination region.

[0014] The layer of the second conductivity type may extend laterally over one or more drift regions of the plurality of drift regions within the transition region.

[0015] Each of the plurality of pillars of the second conductivity type may include a plurality of implant regions of the second conductivity type arranged above one another along a depth of the pillar of the second conductivity type.

[0016] Each of the plurality of pillars of the first conductivity type may include a plurality of implant regions of the first conductivity type arranged above one another along a depth of the pillar of the first conductivity type.

[0017] The one or more electrically floating regions of the first conductivity type may form a plurality of laterally separated concentric ring structures.

[0018] Each of the one or more electrically floating regions of the first conductivity type may have substantially the same width. This may form a ring-shaped terminal structure.

[0019] The one or more electrically floating regions of the first conductivity type may form a variable lateral doping (VLD) structure. The VLD structure has the ability to support a high reverse bias voltage.

[0020] The semiconductor power device may further include a buffer region of the first conductivity type located above the semiconductor substrate region of the first conductivity type. The buffer region of the first conductivity type may have a lower doping concentration than the semiconductor substrate region of the first conductivity type.

[0021] The device may further include a channel stop region laterally located between the edge termination structure and the side surface of the semiconductor device. The channel stop region may extend to the side surface of the semiconductor device. The channel stop region may have a higher doping concentration than the drift region.

[0022] The device may include a super junction power device.

[0023] The device may include a metal oxide semiconductor field effect transistor (MOSFET).

[0024] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor power device, the semiconductor power device having an active region and an edge termination region surrounding the active region, wherein the edge termination region is laterally located between the active region and a side surface of the semiconductor device, the method comprising:

[0025] providing a semiconductor substrate including a first region of a first conductivity type;

[0026] A plurality of drift regions of the first conductivity type and a plurality of separation regions of the second conductivity type are formed on the semiconductor substrate region and are alternately contacted with each other to form a plurality of mutually parallel pn junctions extending in a vertical direction between adjacent drift regions and separation regions,

[0027] wherein in the edge termination region, two or more of the plurality of separation regions extend to form a layer of the second conductivity type over two or more of the plurality of drift regions; and

[0028] One or more electrically floating regions of the first conductivity type are formed over the layer of the second conductivity type and within the edge termination region.

[0029] Forming a plurality of drift regions and a plurality of separation regions, and forming one or more electrically floating regions of the first conductivity type, may include performing each of steps (i) to (v) one or more times:

[0030] (i) depositing a semiconductor layer over the semiconductor substrate region;

[0031] (ii) forming a first mask over the semiconductor layer. The first mask may expose an upper surface of a first plurality of regions of the semiconductor layer. The first plurality of regions may be laterally spaced apart from each other;

[0032] (iii) selectively doping the first plurality of regions of the semiconductor layer to form a first plurality of regions of the first conductivity type;

[0033] (iv) forming a second mask over the semiconductor layer. The second mask may expose an upper surface of a second plurality of regions of the semiconductor layer. The second plurality of regions may be laterally spaced apart from one another and may be located between adjacent regions of the first plurality of regions of the first conductivity type;

[0034] (v) selectively doping the second plurality of regions of the semiconductor layer to form a first plurality of regions of the second conductivity type.

[0035] The method may further include: depositing an additional semiconductor layer over the previously deposited semiconductor layer; forming a mask over the additional semiconductor layer, wherein the mask may expose an upper surface of a plurality of regions of the additional semiconductor layer; and selectively doping the plurality of regions of the additional semiconductor layer to form a plurality of regions of the second conductivity type. The regions of the additional semiconductor layer may be substantially aligned with the plurality of regions of the second conductivity type.

[0036] The method may further include: depositing an additional semiconductor layer on top of a previously deposited semiconductor layer; forming a mask on top of the additional semiconductor layer, wherein the mask may expose an upper surface of a plurality of regions of the additional semiconductor layer; and selectively doping the plurality of regions of the additional semiconductor layer to form a plurality of island regions of the first conductivity type in the edge termination region. The regions of the additional semiconductor layer may be substantially aligned with the plurality of regions of the second conductivity type in the edge termination region. The mask may not expose the additional semiconductor layer in the active region. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Some preferred embodiments of the present disclosure will now be described, by way of example only, and with reference to the accompanying drawings, in which:

[0038] FIG1 schematically illustrates a VLD edge termination region of a power semiconductor device according to an embodiment of the present disclosure;

[0039] Figure 2 shows a ring-shaped structure edge termination region of a power semiconductor device according to an embodiment of the present disclosure;

[0040] Figure 3 schematically illustrates a first set of steps in a method of manufacturing a device according to an embodiment of the present disclosure;

[0041] FIG4 schematically illustrates a second set of steps in a method of manufacturing a device according to an embodiment of the present disclosure;

[0042] Figure 5 schematically illustrates a third set of steps in a method of manufacturing a device according to an embodiment of the present disclosure;

[0043] Figure 6 Shows Figure 5 Doping profile of the device shown;

[0044] Figure 7 schematically illustrates a fourth set of steps in a method of manufacturing a device according to an embodiment of the present disclosure;

[0045] Figure 8 Shows Figure 7 Doping profile of the device shown;

[0046] Fig. 9 schematically illustrates a fifth set of steps in a method of manufacturing a device according to an embodiment of the present disclosure;

[0047] Fig.10 schematically illustrates a sixth set of steps in a method of manufacturing a device according to an embodiment of the present disclosure; and

[0048] Fig.11 Figure 1 and Figure 2 The simulated breakdown voltage of the device is shown. DETAILED DESCRIPTION

[0049] FIG1(a) schematically illustrates a lateral variable doping (VLD) edge termination region of a power semiconductor device 100 according to an embodiment of the present disclosure. FIG1(b) illustrates region A of FIG1(a) in more detail. The power semiconductor device 100 includes a semiconductor substrate. In an example, the semiconductor substrate is formed of silicon, although other semiconductor materials may be used.

[0050] The device 100 includes three regions: an active region 102 for current conduction, an edge termination region 104, and a transition region 106. The active region 102 is located in the center of the semiconductor device, while the edge termination region 104 surrounds the active region 102 and is located between the active region 102 and the side surface of the semiconductor device. The transition region 106 also surrounds the active region 102 and is located between the active region 102 and the edge termination region 104. It should be understood that FIG. 1 only shows a cross section through a portion of the semiconductor device.

[0051] In this embodiment, the semiconductor substrate includes an n-type substrate region 108. An n-type buffer region or drift region 110 is located above the n-type substrate region 108. The buffer region 110 has a lower doping concentration than the n-type substrate region 108.

[0052] A plurality of n-type columns 114 and a plurality of p-type columns 116 (or separation regions) are located above the drift region 110. The n-type column regions 114 extend from the drift region 110 and can be considered as additional drift regions. The n-type columns 114 and the p-type columns 116 are alternately contacted with each other so that each p-type column 116 is located between two adjacent n-type columns 114 to form parallel pn junctions extending in a vertical direction between the adjacent n-type columns 114 and the p-type columns 116.

[0053] In the active region 102, an n-type doped junction field effect transistor (JFET) region 136 is located above the n-type pillar 114, so that the n-type doped region extends to the upper surface of the semiconductor substrate. A gate polysilicon region 140 is located above the JFET n-type region 136 and is used to control the conductive channel in the active region. A gate insulating region 138, such as a silicon dioxide layer, is located above the gate polysilicon region 140. A source metal layer 148 is located on the upper surface of the device, above the gate insulating region 138.

[0054] In the edge termination region 104 and the transition region 106, a p-type layer 120 is located above the n-type pillars 114. The p-type layer 120 extends from the p-type pillars 116.

[0055] In the edge termination region 104, a plurality of n-type island regions 122 are located above the p-type layer 120 and the top surface of the semiconductor substrate. The island region 122 is electrically isolated or decoupled from the surrounding components of the device. The n-type island region 122 is formed on the top surface of the semiconductor substrate, and an insulating layer 134 such as a silicon dioxide layer is formed on the n-type island region 122. Compared with the device of the prior art, the floating n-type island region improves the charge balance, thereby increasing the breakdown voltage of the edge termination region.

[0056] A gate metal layer 154 is formed over the insulating layer 134. A polysilicon field plate 156 is over the channel stop region 118, and a metal field plate 158 is over the polysilicon field plate.

[0057] In the example shown in Figure 1, the independent island region 122 is wider towards the active area 102, and narrower towards the side surface of the device, to provide a VLD edge termination region. The VLD edge termination region has such a doping profile, wherein the doping concentration of the island-shaped region 122 gradually decreases from the source region to the drain region, which provides a more uniform surface electric field distribution so that the breakdown voltage is improved. This can be achieved by using a mask with different width openings, and the openings expose the region forming the island region 122. The VLD edge termination region has the ability to support a high reverse bias voltage.

[0058] The channel stop region 118 is located at a side surface of the semiconductor device, on a side of the edge termination region 104 opposite the active region 102. The channel stop region 118 includes an n-type region having a higher doping concentration than regions of the semiconductor substrate laterally adjacent to the channel stop region 118. The channel stop region 118 prevents a conductive channel from forming at the edge of the device.

[0059] It should be understood that the island regions 122 may alternatively have substantially the same width and the same doping concentration, thus forming a Figure 2 Many features are the same as those shown in FIG. 1 and therefore have the same reference numerals. It should also be understood that the gate contact region will have the same structure as the gate contact region shown in FIG. 1( b). In this example, the individual island regions 122 have substantially the same size or width across the edge termination region.

[0060] Figure 3 The first set of steps in a method of manufacturing a semiconductor device such as that shown in FIG. 1 or 2 is schematically shown. This involves forming a semiconductor substrate having an n-type substrate region 108 and a buffer region 110 above the n-type substrate region 108. The buffer region 110 may be thermally grown on the substrate region 108.

[0061] FIG. 4( a) schematically shows a second set of steps in a method for manufacturing a semiconductor device. Figure 3 The steps shown are then performed. Each of steps (i) to (v) is performed multiple times in sequence. In the example shown in FIG. 4 , steps (i) to (v) are performed 8 times, although they may be performed fewer or more times to form n-type pillars 114 and p-type pillars 116 of different depths.

[0062] The steps in Figure 4 are:

[0063] (i) depositing a semiconductor layer 124 over the buffer region 110. Depositing a subsequent semiconductor layer over the previously deposited semiconductor layer. Epitaxial growth may be used to deposit the semiconductor layer 124;

[0064] (ii) forming a first mask over the semiconductor layer 124. The first mask exposes the upper surface of multiple laterally separated regions of the semiconductor layer 124 that will be doped with n-type doping. For example, the first mask can expose all regions that will become n-type regions (n-type column regions and channel stop regions). In the example shown in FIG. 4( a), the width of each exposed region 126 that will become an n-type column region is substantially the same, except that the width of the region 126a closest to the side surface of the device is substantially half the width of the other exposed regions. This improves the charge balance of the device. It should be understood that in other embodiments, the region closest to the side surface can have the same width as the other exposed regions (as shown in FIG. 4( b));

[0065] (iii) selectively doping the regions exposed using the mask of step (ii) by implanting an n-type dopant to form a plurality of n-type drift regions 126 and a plurality of channel stop regions 118. In the example, this is performed using vapor diffusion. In the example, the n-type dopant is phosphorus, however, it should be understood that other n-type implant elements or dopants may be used;

[0066] (iv) forming a second mask over the semiconductor layer 124. The second mask exposes the upper surface of a plurality of laterally spaced regions of the semiconductor layer 124 to be doped with p-type doping. For example, the second mask may expose all regions that will become p-type pillar regions. These regions are exposed by the second mask between adjacent n-type drift regions 126;

[0067] (v) The regions exposed using the mask of step (iv) are selectively doped by implanting p-type dopants to form a plurality of p-type separation regions 128. In an example, this is performed using diffusion of boron.

[0068] Each time step (ii) is performed, the first mask will expose the same area as the previous repetition of step (ii), and each time step (iv) is performed, the second mask will expose the same area as the previous repetition of step (iv). It should be understood that steps (ii) and (iii) and steps (iv) and (v) can be interchanged in order so that the p-type region is formed before the n-type region.

[0069] Figure 5 A third group of steps in the method of manufacturing a semiconductor device is schematically illustrated. Figure 5 The steps are performed after the steps shown in FIG. 4 .

[0070] Figure 5 The steps are:

[0071] (vi) depositing an additional semiconductor layer 130 on the semiconductor layer 124 previously deposited in the step shown in Figure 4. The semiconductor layer 130 may be deposited using epitaxial growth;

[0072] (vii) A first mask is formed over the semiconductor layer 130. The first mask exposes the upper surface of a plurality of laterally spaced apart regions of the semiconductor layer 130 to be doped with the n-type doping. Figure 5 The first mask of FIG. 4 exposes the same areas as the first mask of FIG. 4 in the active region 102 and the transition region 106 and the channel stop region 118, but does not expose any area above the n-type drift region in the edge termination region 104. This means that the n-type drift region 126 is not formed in the edge termination region 104 of the semiconductor layer 130;

[0073] (viii) selectively doping the areas exposed using the mask of step (vii) to form a further plurality of layers of n-type drift regions 126 and channel stop regions 118. The doping concentration implanted in step (viii) is the same as the doping concentration implanted in step (iii). In an example, this is performed using vapor diffusion of phosphorus;

[0074] (ix) A second mask is formed over the semiconductor layer 130. The second mask exposes the upper surface of a plurality of laterally spaced regions to be doped with the p-type doped semiconductor layer 130. For example, the second mask may expose all regions to be p-type pillar regions. Figure 5 The second mask of FIG. 4 exposes the same area as the second mask of FIG. 4 ;

[0075] (x) The regions exposed using the mask of step (ix) are selectively doped to form a further plurality of p-type separation regions 128. The doping concentration implanted in step (x) is the same as the doping concentration implanted in step (v). In an example, this is performed using boron vapor diffusion.

[0076] As about Figure 3 As described in FIG. 4 , after the vapor diffusion of boron and phosphorus, an additional step of driving in dopants is performed to further diffuse or redistribute the dopants. The diffusion length of the initial diffusion is typically less than the diffusion length of the drive-in diffusion, so the drive-in process causes the dopants to diffuse further into the semiconductor substrate. The drive-in process increases the temperature of the wafer and causes impurities deposited on the surface of the semiconductor layer to diffuse into the semiconductor layer. This causes the n-type column 114 and the p-type column 116 to be formed of a separate n-type drift region 126 and a separate p-type separation region 128, respectively. This also causes the layer of the channel stop region 118 to become a single region, and causes the channel stop region 118 to be formed of a separate n-type drift region 126 and a separate p-type separation region 128. Figure 5 The p-type spacer layer 128 formed in the illustrated step becomes the p-type layer 120 located above the n-type pillars 114 and the p-type pillars 116 in the edge termination region 104 . Figure 6 It is shown that once the drive-in process is performed, Figure 5 Doping profile of the device shown.

[0077] Figure 7 A fourth group of steps in the method of manufacturing a semiconductor device is schematically illustrated. Figure 7 The steps are Figure 5 Follow the steps shown.

[0078] Figure 7 The steps are:

[0079] (xi) Previously in Figure 5 An additional further semiconductor layer 132 is deposited over the semiconductor layer 130 deposited in the step shown. The semiconductor layer 132 may be deposited using epitaxial growth;

[0080] (xii) A mask is formed over the semiconductor layer 132. The mask exposes the upper surface of a plurality of laterally spaced apart regions of the semiconductor layer 132 to be doped with the n-type doping. Figure 7 The mask exposes the edge termination region 104 in Figure 5 The second mask is applied to the same area and exposes the channel stop region 118. Figure 7 The mask does not expose any area of ​​the active region 102 or the transition region 106 and does not expose any area above the previously formed n-type drift region 126 in the edge termination region 104;

[0081] (xiii) selectively doping the areas exposed using the mask of step (xii) to form a plurality of n-type island regions 122 and additional layers of channel stop region 118. The doping concentration implanted in step (xiii) may be the same as the doping concentration implanted in steps (viii) and (iii). In an example, this is performed using vapor diffusion of phosphorus.

[0082] As about Figure 7 As described, after the vapor diffusion of phosphorus, a further step of driving in the diffused dopants is performed. The drive-in process increases the temperature of the wafer and causes the impurities deposited on the surface of the semiconductor layer to diffuse into the semiconductor layer. Figure 8 It is shown that once the additional drive-in process is performed, Figure 7 Doping profile of the device shown.

[0083] Fig. 9 A fifth group of steps in the method of manufacturing a semiconductor device is schematically shown. Fig. 9 The steps are Figure 7 This involves forming an insulating layer 134 over the n-type island region 122 in the edge termination region 104. In this example, the insulating layer 134 is an oxide layer, such as silicon dioxide, and can be formed by depositing or thermally growing a silicon dioxide layer over the upper surface of the entire semiconductor substrate and etching the silicon dioxide so that it only covers the edge termination region 104.

[0084] Fig.10 A sixth group of steps in the method of manufacturing a semiconductor device is schematically shown. Fig.10 The steps are Fig. 9 Follow the steps shown.

[0085] Fig.10 The steps are:

[0086] (xv) The region on the upper surface of the semiconductor substrate within the active region 102 (JFET region) is doped with n-type impurities to form a JFET n-type region 136. This can be done in the same manner as described with respect to FIG. Figure 5 and Figure 7 The n-type region formed in the same manner as described;

[0087] (xvi) forming a gate insulating region over the n-type JFET region 136. The gate insulating region may be a thin oxide layer, such as silicon dioxide, which may be deposited or thermally grown;

[0088] (xvii) depositing a polysilicon region 140 on the gate insulating region and over the JFET n-type region 136. The polysilicon region 140 is used to control the conduction channel in the active region. In some examples, the polysilicon region 140 is then etched using a mask so that it does not extend over the edge termination region;

[0089] (xviii) forming or implanting a p-type body region 142 at the upper surface of the semiconductor substrate in the active region 102 and the transition region 106;

[0090] (xix) forming or implanting highly doped n+ source regions 144 on either side of the p-type body region 142;

[0091] (xx) depositing an interlayer dielectric (ILD) 138. The ILD 138 covers the polysilicon region 140. The ILD 138 may also cover the insulating layer 134;

[0092] (xxi) etching the upper surface of the device and implanting a highly doped p+ contact region 146 in the etched area;

[0093] (xxii) depositing a source metal layer 148 on the front (upper) surface of the device;

[0094] (xxiii) Grinding or planarizing the rear (lower) surface of the device and forming a drain metal contact 150.

[0095] Fig.11 Figure 1 and Figure 2 The simulated breakdown voltage of the edge termination region device shown in FIG. 1 shows that the breakdown voltage of both devices described herein is reduced compared to the prior art devices. This shows the active region of device 802, the ring structure edge termination region 804 (as shown in FIG. 1 ), and the VLD edge termination region 804 (as shown in FIG. 2 ). Figure 2 The simulated breakdown voltage (BV) of the ring structure edge termination region has 95.7% of the BV of the active region, while the VLD edge termination region has 96.4% of the BV of the active region.

[0096] Reference Numbers

[0097] 100 power semiconductor device 124 semiconductor layer

[0098] 102 active region 126 n-type drift region

[0099] 104 edge termination region 128 p type separation region

[0100] 106 transition region 130 semiconductor layer

[0101] 108n-type substrate 132 semiconductor layer

[0102] 110 buffer area 134 insulation layer

[0103] 114n-type column 136JFET n-type region

[0104] 116p-type pillar 138 gate insulation area

[0105] 118 channel stop region 140 polysilicon region

[0106] 120p type layer 142p type main area

[0107] 122 floating n-type region 144n+ source region

[0108] 146p+ contact area 150 drain metal layer

[0109] 148 source metal layer

[0110] Those skilled in the art will appreciate that in the foregoing description and the appended claims, positional terms such as "above," "overlapping," "below," "lateral," and the like are made with reference to conceptual illustrations of the device, such as those showing standard cross-sectional perspective views and those shown in the accompanying drawings. These terms are used for ease of reference and are not intended to be limiting. Therefore, these terms should be understood to refer to the device in the orientation shown in the accompanying drawings.

[0111] It should be understood that all of the doping polarities described above may be reversed and the resulting device still conform to embodiments of the present invention.

[0112] Although the present disclosure has been described according to the preferred embodiments described above, it should be understood that these embodiments are merely illustrative and the claims are not limited to these embodiments. In view of this disclosure, those skilled in the art will be able to make modifications and substitutions, which are expected to fall within the scope of the appended claims. Each feature disclosed or shown in this specification may be incorporated into the present disclosure, either alone or in any appropriate combination with any other features disclosed or shown herein.

Claims

1. A semiconductor power device, the semiconductor power device having an active area and an edge termination area surrounding the active area, wherein the edge termination area is laterally located between the active area and a side surface of the semiconductor device, the device comprising: a semiconductor substrate including a semiconductor substrate region of a first conductivity type; A plurality of drift regions of the first conductivity type and a plurality of separation regions of the second conductivity type are each disposed on the semiconductor substrate region and alternately contact each other to form a plurality of mutually parallel pn junctions extending in a vertical direction between adjacent drift regions and separation regions, wherein in the edge termination region, two or more of the plurality of separation regions extend to form a layer of a second conductivity type over two or more of the plurality of drift regions; as well as One or more electrically floating regions of the first conductivity type are located above the layer of the second conductivity type and within the edge termination region. 2 . The semiconductor power device according to claim 1 , wherein in the active area, a drift region among the plurality of drift regions extends such that the separation region in the active area forms a physically separated separation region. 3 . The semiconductor power device of claim 1 , wherein the device further comprises a transition region laterally located between the active region and the edge termination region. 4 . The semiconductor power device of claim 3 , wherein the layer of the second conductivity type extends laterally over a drift region of the plurality of drift regions within the transition region.

5. The semiconductor power device of any preceding claim, wherein each of the plurality of pillars of the second conductivity type comprises a plurality of implanted regions of the second conductivity type arranged above one another along a depth of the pillar of the second conductivity type; and Each of the plurality of first conductivity type pillars includes a plurality of first conductivity type implant regions arranged above each other along a depth of the first conductivity type pillar.

6. A semiconductor power device according to any preceding claim, wherein the one or more electrically floating regions of the first conductivity type form a plurality of laterally separated concentric ring structures.

7. A semiconductor power device according to any preceding claim, wherein each of the one or more electrically floating regions of the first conductivity type have substantially the same width.

8. A semiconductor power device according to any preceding claim, wherein the one or more electrically floating regions of the first conductivity type form a Variant Lateral Doping (VLD) structure.

9. The semiconductor power device according to any preceding claim, further comprising a buffer region of the first conductivity type located above the semiconductor substrate region of the first conductivity type and having a lower doping concentration than the semiconductor substrate region of the first conductivity type.

10. A semiconductor power device according to any preceding claim, wherein the device further comprises a channel stop region laterally located between the edge termination structure and a side surface of the semiconductor device and extending to the side surface of the semiconductor device, and The channel stop region has a higher doping concentration than the drift region.

11. A semiconductor power device according to any preceding claim, wherein the device comprises a super junction power device.

12. A semiconductor power device as claimed in any preceding claim, wherein the device comprises a metal oxide semiconductor field effect transistor (MOSFET).

13. A method for manufacturing a semiconductor power device, the semiconductor power device having an active area and an edge termination area surrounding the active area, wherein the edge termination area is laterally located between the active area and a side surface of the semiconductor device, the method comprising: providing a semiconductor substrate including a first region of a first conductivity type; A plurality of drift regions of the first conductivity type and a plurality of separation regions of the second conductivity type are formed on the semiconductor substrate region and are alternately contacted with each other to form a plurality of mutually parallel pn junctions extending in a vertical direction between adjacent drift regions and separation regions, wherein in the edge termination region, two or more of the plurality of separation regions extend to form a layer of a second conductivity type over two or more of the plurality of drift regions; as well as One or more electrically floating regions of the first conductivity type are formed over the layer of the second conductivity type and within the edge termination region.

14. The method of claim 13, wherein the method of forming the plurality of drift regions and the plurality of separation regions and forming the one or more electrically floating regions of the first conductivity type comprises: Perform each of steps (i) to (v) one or more times: (i) depositing a semiconductor layer on the semiconductor substrate region; (ii) forming a first mask over the semiconductor layer, wherein the first mask exposes an upper surface of a first plurality of regions of the semiconductor layer, wherein the first plurality of regions are laterally spaced apart from one another; (iii) selectively doping the first plurality of regions of the semiconductor layer to form a first plurality of regions of the first conductivity type; (iv) forming a second mask over the semiconductor layer, wherein the second mask exposes an upper surface of a second plurality of regions of the semiconductor layer, wherein the second plurality of regions are laterally spaced apart from each other and are located between adjacent regions of the first plurality of regions of the first conductivity type; (v) selectively doping the second plurality of regions of the semiconductor layer to form a first plurality of regions of the second conductivity type.

15. The method according to claim 14, wherein the method further comprises: depositing an additional semiconductor layer over the previously deposited semiconductor layer; forming a mask over the further semiconductor layer, wherein the mask exposes an upper surface of a plurality of regions of the further semiconductor layer, wherein the regions of the further semiconductor layer are substantially aligned with the plurality of regions of the second conductivity type; The plurality of regions of the further semiconductor layer are selectively doped to form a plurality of regions of the second conductivity type.

16. The method according to claim 14 or 15, wherein the method further comprises: depositing an additional further semiconductor layer over the previously deposited semiconductor layer; forming a mask over the additional further semiconductor layer, wherein the mask exposes an upper surface of a plurality of regions of the additional further semiconductor layer, wherein said region of said additional further semiconductor layer is substantially aligned with said plurality of regions of the second conductivity type in said edge termination region, and wherein said mask does not expose said additional further semiconductor layer in said active area; The plurality of regions of the additional further semiconductor layer are selectively doped to form a plurality of regions of the first conductivity type in the edge termination region.

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