Image sensor

Abstract

Disclosed is an image sensor including: a first semiconductor substrate including a first pixel region and a second pixel region; a first photoelectric conversion element on the first pixel region; a second photoelectric conversion element on the second pixel region; a first floating diffusion on the first pixel region; a second floating diffusion on the second pixel region; a first transfer gate electrode between the first photoelectric conversion element and the first floating diffusion; a second transfer gate electrode between the second photoelectric conversion element and the second floating diffusion; a second semiconductor substrate on the first semiconductor substrate; and a pixel transistor connected to the first photoelectric conversion element and the second photoelectric conversion element. A width of the second photoelectric conversion element is smaller than a width of the first photoelectric conversion element. At least one of the pixel transistors is on the second semiconductor substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0112852 filed on August 28, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to an image sensor, and more particularly, to an image sensor having small pixels while maintaining a high dynamic range. Background Art

[0004] Image sensors convert photon images into electrical signals. Recent advances in the computer and communications industries have led to a strong demand for high-performance image sensors in various consumer electronic devices, such as digital cameras, video cameras, PCS (personal communication systems), game consoles, security cameras, and medical miniature cameras. Image sensors are generally classified as charge coupled device (CCD) sensors or CMOS image sensors. CMOS image sensors have a relatively simple operation method, and since their signal processing circuits are integrated into a single chip, the size of their products may be minimized. In addition, CMOS image sensors require relatively small power consumption, which is useful in battery-powered applications. In addition, since the process technology used to manufacture CMOS image sensors is compatible with CMOS process technology, CMOS image sensors can reduce manufacturing costs. Therefore, due to technological advances and the realization of high-resolution devices, the use of CMOS image sensors has increased rapidly. Summary of the invention

[0005] Some example embodiments provide an image sensor having small pixels while securing a dynamic range.

[0006] The objects of the present exemplary embodiment are not limited to the above objects, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0007] According to some example embodiments, an image sensor may include: a first semiconductor substrate including a first pixel region and a second pixel region; a first photoelectric conversion element on the first pixel region; a second photoelectric conversion element on the second pixel region; a first floating diffusion on the first pixel region; a second floating diffusion on the second pixel region; a first transfer gate electrode between the first photoelectric conversion element and the first floating diffusion; a second transfer gate electrode between the second photoelectric conversion element and the second floating diffusion; a second semiconductor substrate on the first semiconductor substrate; and a plurality of pixel transistors connected to the first photoelectric conversion element and the second photoelectric conversion element. The width of the second photoelectric conversion element may be smaller than the width of the first photoelectric conversion element. At least one of the plurality of pixel transistors may be on the second semiconductor substrate.

[0008] According to some example embodiments, an image sensor may include: a photoelectric conversion circuit layer including a first photoelectric conversion element and a second photoelectric conversion element on a first semiconductor substrate; a pixel circuit layer including a second semiconductor substrate and on the photoelectric conversion circuit layer; and a logic circuit layer on the pixel circuit layer and including a logic circuit on a third semiconductor substrate. The photoelectric conversion circuit layer may include: a dual conversion gain transistor on the first semiconductor substrate and connected between a first floating diffusion and a third floating diffusion; a source follower transistor on the first semiconductor substrate and connected to the first floating diffusion; a first transfer gate electrode between the first photoelectric conversion element and the first floating diffusion; and a second transfer gate electrode between the second photoelectric conversion element and the second floating diffusion. The pixel circuit layer may include: a reset transistor on the second semiconductor substrate and connected to the third floating diffusion; a first switch transistor on the second semiconductor substrate and connected to the dual conversion gain transistor; and a second switch transistor on the second semiconductor substrate and connected to the second floating diffusion. The width of the second photoelectric conversion element may be smaller than the width of the first photoelectric conversion element.

[0009] According to some example embodiments, an image sensor may include: a photoelectric conversion circuit layer including a first photoelectric conversion element and a second photoelectric conversion element on a first semiconductor substrate; a pixel circuit layer including a second semiconductor substrate and on the photoelectric conversion circuit layer; and a logic circuit layer on the pixel circuit layer and including a logic circuit on a third semiconductor substrate. The photoelectric conversion circuit layer may include: a first transmission gate electrode between the first photoelectric conversion element and the first floating diffusion; and a second transmission gate electrode between the second photoelectric conversion element and the second floating diffusion. The pixel circuit layer may include: a dual conversion gain transistor on the second semiconductor substrate and connected between the first floating diffusion and the third floating diffusion; a source follower transistor on the second semiconductor substrate; a reset transistor on the second semiconductor substrate and connected to the third floating diffusion; a first switch transistor on the second semiconductor substrate and connected to the dual conversion gain transistor; a second switch transistor on the second semiconductor substrate and connected to the second floating diffusion; and a third switch transistor on the second semiconductor substrate and connected to the source follower transistor and the first floating diffusion. The width of the second photoelectric conversion element may be smaller than the width of the first photoelectric conversion element. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A block diagram illustrating an image sensor is shown according to some example embodiments.

[0011] Figure 2A and Figure 2B A simplified perspective view of an image sensor is shown in accordance with some example embodiments.

[0012] Figure 3A and Figure 3B A circuit diagram illustrating a unit pixel of a pixel array according to some example embodiments is illustrated.

[0013] Figure 4A Shown with Figure 3A A plan view of an example of a unit pixel of the circuit configuration shown.

[0014] Figure 4B Shown with Figure 3B A plan view of an example of a unit pixel of the circuit configuration shown.

[0015] FIG. 5A to FIG. 6 illustrates a cross-sectional view of an image sensor according to some example embodiments.

[0016] Figure 7 A plan view of an image sensor according to some example embodiments is illustrated.

[0017] Figure 8A timing diagram illustrating the operation of an image sensor according to some example embodiments is shown.

[0018] Fig.9A and Fig. 9B illustrates a cross-sectional view of an image sensor according to some example embodiments. DETAILED DESCRIPTION

[0019] Various example embodiments are described below with reference to the accompanying drawings. Throughout the specification, the same reference numerals may represent the same components.

[0020] Figure 1 A block diagram illustrating an image sensor is shown according to some example embodiments.

[0021] Reference Figure 1 , the image sensor may include an active pixel sensor array (or pixel array) 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7 and an input / output (I / O) buffer 8.

[0022] The active pixel sensor array 1 may include a plurality of unit pixels arranged two-dimensionally, each of which is configured to convert an optical signal into an electrical signal. The active pixel sensor array 1 may be driven by a plurality of driving signals (such as a pixel selection signal, a reset signal, and a charge transfer signal) from a row driver 3. The converted electrical signal may be provided to a correlated double sampler 6.

[0023] The row driver 3 may provide a number of driving signals for driving a number of unit pixels to the active pixel sensor array 1 according to the decoding result obtained from the row decoder 2. When the unit pixels are arranged in a matrix shape, a driving signal may be provided for each row.

[0024] The timing generator 5 may provide timing and control signals to the row decoder 2 and the column decoder 4 .

[0025] The correlated double sampler 6 may receive the electrical signal generated in the active pixel sensor array 1, and hold and sample the received electrical signal. The correlated double sampler 6 may perform a double sampling operation to sample a specific noise level and signal level of the electrical signal, and then output a difference level corresponding to the difference between the noise level and the signal level.

[0026] The analog-to-digital converter 7 may convert an analog signal corresponding to the difference level received from the correlated double sampler 6 into a digital signal and then output the converted digital signal.

[0027] The input / output buffer 8 may latch the digital signal, and may sequentially output the latched digital signal to an image signal processor (not shown) in response to a decoding result obtained from the column decoder 4 .

[0028] Figure 2A and Figure 2B A simplified perspective diagram illustrating an image sensor is shown in accordance with some example embodiments.

[0029] Reference Figure 2A , the image sensor may include a sensor chip C1 and a logic chip C2.

[0030] The sensor chip C1 may convert an image of an external substance into an electrical signal or a data signal. The sensor chip C1 may include the above-mentioned Figure 1 The pixel array discussed (see Figure 1 1). For example, the sensor chip C1 may include a plurality of unit pixels, and as shown below Figure 2A and Figure 2B As discussed, each of the unit pixels may include a photoelectric conversion circuit 10P and a pixel circuit 20P.

[0031] The sensor chip C1 may include a pixel array region R1 and a pad region R2. The pixel array region R1 may include a plurality of unit pixels two-dimensionally arranged along a first direction D1 and a second direction D2 intersecting each other. Each unit pixel of the pixel array region R1 may output an electrical signal generated from incident light.

[0032] The pixel array region R1 may include a light receiving region AR and a light shielding region OB. When viewed in a plan view, the light shielding region OB may surround the light receiving region AR. For example, when viewed in a plan view, the light shielding region OB may be disposed on the upper side, the lower side, the left side, and the right side of the light receiving region AR. The light shielding region OB may include a reference pixel on which no light is incident, and the amount of charge sensed in the unit pixel of the light receiving region AR may be compared with the amount of reference charge appearing at the reference pixel, which may result in calculation of the amplitude of the electrical signal sensed in the unit pixel.

[0033] The pad region R2 may include a plurality of conductive pads CP for input and output of control signals and photoelectric conversion signals. For easy connection with an external device, the pad region R2 may surround the pixel array region R1 when viewed in a plan view. Electrical signals may be transmitted between the unit pixel and the external device through the conductive pads CP.

[0034] The sensor chip C1 may include a photoelectric conversion circuit layer 10, a pixel circuit layer 20, and a light transmission layer (not shown). When viewed in cross section, the pixel circuit layer 20 may be disposed between the photoelectric conversion circuit layer 10 and the light transmission layer. The pixel circuit layer 20 may be adjacent to the logic chip C2.

[0035] The sensor chip C1 may include pixel transistors, and the pixel transistors may be disposed on the photoelectric conversion circuit layer 10 and the pixel circuit layer 20. However, the present example embodiment is not limited thereto, and the pixel transistors may be disposed only on the pixel circuit layer 20.

[0036] The photoelectric conversion circuit layer 10 may include a first semiconductor substrate (not shown) and a photoelectric conversion circuit 10P. The photoelectric conversion circuit 10P may include a first transfer transistor and a second transfer transistor (not shown), and may further include some of the pixel transistors disposed on the first semiconductor substrate. The photoelectric conversion circuit 10P may be arranged two-dimensionally along a first direction D1 and a second direction D2 that intersect each other.

[0037] The pixel circuit layer 20 may include a second semiconductor substrate (not shown) and a pixel circuit 20P. The pixel circuit 20P may include at least some pixel transistors disposed on the second semiconductor substrate.

[0038] The logic chip C2 may include a logic circuit (see Figure 1 2, 3, 4, 5, 6, 7 and 8), a power supply circuit, an input / output interface and / or an image signal processor. For example, the logic chip C2 may include Figure 1 Components other than the pixel array 1 of the image sensor shown. The logic chip C2 may include, for example, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler 6, an analog-to-digital converter 7, and an input / output buffer 8.

[0039] The logic chip C2 may include a logic pad area R3 corresponding to the pad area R2 of the sensor chip C1. The logic pad area R3 may include a plurality of conductive pads CP for input / output of control signals. The conductive pads CP of the sensor chip C1 may be electrically connected to the conductive pads CP of the logic chip C2. The logic chip C2 may be bonded to the sensor chip C1 so as to be adjacent to the pixel circuit layer 20 of the sensor chip C1.

[0040] Reference Figure 2B , the image sensor may include a first chip C1a including a photoelectric conversion circuit 10P including a plurality of unit pixels, a second chip C1b including a pixel circuit 20P including a plurality of unit pixels, and a logic chip C2.

[0041] The first chip C1a may include a pixel array region R1 and a pad region R2, and the pixel array region R1 may include a light receiving region AR and a light shielding region OB. The first chip C1a may include a plurality of photoelectric conversion circuits 10P of unit pixels. The photoelectric conversion circuits 10P may be two-dimensionally arranged along a first direction D1 and a second direction D2 on the pixel array region R1.

[0042] The second chip C1b may include a plurality of pixel circuits 20P of unit pixels. The pixel circuits 20P may be provided corresponding to the photoelectric conversion circuits 10P. The second chip C1b may include a conductive pad CP corresponding to the conductive pad CP of the first chip C1a. The conductive pad CP of the first chip C1a may be electrically connected to the conductive pad CP of the second chip C1b.

[0043] As described above, the logic chip C2 may include a logic circuit (see Figure 1 2, 3, 4, 5, 6, 7 and 8), a power supply circuit, an input / output interface and / or an image signal processor. The conductive pads CP of the logic chip C2 may be electrically connected to the conductive pads CP of the second chip C1b.

[0044] Figure 3A and Figure 3B A circuit diagram illustrating a unit pixel of a pixel array according to some example embodiments is illustrated.

[0045] Reference Figure 3A , the unit pixel UP may include a photoelectric conversion circuit 10P and a pixel circuit 20P.

[0046] The photoelectric conversion circuit 10P may include first and second photoelectric conversion elements PD1 and PD2, first and second transfer transistors TX1 and TX2, a dual conversion gain transistor DCX, a source follower transistor SF, and first, second and third floating diffusions FD1, FD2 and FD3.

[0047] The pixel circuit 20P may include a selection transistor SX, a reset transistor RX, a first switch transistor (or switch element) SW1 and a second switch transistor SW2, a capacitor (or charge storage element) C FD and a second floating diffusion FD2 and a third floating diffusion FD3.

[0048] The first semiconductor substrate (not shown) may be provided with the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2, the first transfer transistor TX1 and the second transfer transistor TX2, the dual conversion gain transistor DCX, and the source follower transistor SF included in the photoelectric conversion circuit 10P. In contrast, the second semiconductor substrate (not shown) may be provided with the selection transistor SX, the reset transistor RX, the first switch transistor SW1 and the second switch transistor SW2, and the capacitor C included in the pixel circuit 20P. FD .

[0049] In some embodiments, it is disclosed that each unit pixel UP includes six pixel transistors RX, DCX, SF, SX, SW1, and SW2, but the present example embodiment is not limited thereto and the number of pixel transistors may be variously changed.

[0050] For example, the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may generate and accumulate charges in proportion to the amount of incident light. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may each be one of a photodiode, a phototransistor, a grating, a pinned photodiode (PPD), and any combination thereof.

[0051] The first transfer transistor TX1 may enable the first floating diffusion FD1 to receive charges accumulated in the first photoelectric conversion element PD1 .

[0052] The second transfer transistor TX2 may enable the second floating diffusion FD2 to receive charges accumulated in the second photoelectric conversion element PD2 .

[0053] When the second transfer transistor TX2 is turned on, the charges generated from the second photoelectric conversion element PD2 may be accumulated or stored in the capacitor C. FD middle.

[0054] The first and second transmission transistors TX1 and TX2 may be controlled by the first and second transmission signals TG1 and TG2 .

[0055] The first floating diffusion portion FD1 may receive and accumulate stored charges generated from the first photoelectric conversion element PD1. The source follower transistor SF may be controlled according to the number of photocharges accumulated in the first floating diffusion portion FD1.

[0056] The first switching transistor SW1 may be connected between the second floating diffusion FD2 and the third floating diffusion FD3. In response to the first switching signal SG1, the first switching transistor SW1 may change the capacitance of the third floating diffusion FD3 to change the conversion gain of the unit pixel UP.

[0057] The second switch transistor SW2 can be connected to the capacitor (or charge storage element) C FD In response to the second switching signal SG2, the second switching transistor SW2 may change the capacitance of the second floating diffusion FD2 to change the conversion gain of the unit pixel UP.

[0058] Capacitor C FD The second floating diffusion FD2 can be connected to the pixel power supply voltage V DD Capacitor C FD The second switch transistor SW2 can be connected to the pixel power supply voltage V DD For example, capacitor C FDThe capacitor C may be a metal oxide semiconductor (MOS) capacitor, a metal insulator semiconductor (MIS) capacitor, or a metal insulator metal (MIM) capacitor. In response to the amount of charge generated from the second photoelectric conversion element PD2 and the operation of the second transfer transistor TX2, the capacitor C FD Can store charge.

[0059] The dual conversion gain transistor DCX may be connected between the first floating diffusion FD1 and the third floating diffusion FD3. The dual conversion gain transistor DCX may be connected in series to the reset transistor RX through the third floating diffusion FD3. For example, the dual conversion gain transistor DCX may be connected between the first floating diffusion FD1 and the reset transistor RX. In response to the dual conversion gain control signal DCG, the dual conversion gain transistor DCX may change the capacitance of the first floating diffusion FD1 to change the conversion gain of the unit pixel UP.

[0060] The reset transistor RX may periodically reset the charges accumulated in the first floating diffusion FD1 and the third floating diffusion FD3 in response to a reset signal RG applied to the reset gate electrode. A drain terminal of the reset transistor RX may be connected to the third floating diffusion FD3, and a source terminal of the reset transistor RX may be connected to the pixel power supply voltage V DD For example, the reset transistor RX may be connected to the pixel supply voltage V DD When the reset transistor RX and the dual conversion gain transistor DCX are turned on, the pixel power supply voltage V DD The electric charges accumulated in the first floating diffusion FD1 and the third floating diffusion FD3 may be discharged to reset the first floating diffusion FD1 and the third floating diffusion FD3.

[0061] In a plurality of pixels, the first floating diffusion FD1, the second floating diffusion FD2, and the third floating diffusion FD3 may accumulate charges generated from the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 such as a photodiode, and the charges accumulated in the first floating diffusion FD1, the second floating diffusion FD2, and the third floating diffusion FD3 may be converted into a voltage. A conversion gain may be defined as a ratio representing the conversion of charges accumulated in the floating diffusions FD1, FD2, and FD3 into a voltage, and the conversion gain may be changed according to the capacitance of the floating diffusions FD1, FD2, and FD3.

[0062] For example, an increase in the capacitance of the floating diffusions FD1, FD2, and FD3 may cause a decrease in the conversion gain, and a decrease in the capacitance of the floating diffusions FD1, FD, and FD3 may cause an increase in the conversion gain. In some example embodiments, each pixel may operate in a dual gain mode (dual conversion gain). The dual conversion gain mode may include a first conversion gain mode (or low conversion gain (LCG)) and a second conversion gain mode (or high conversion gain (HCG)). The ratio at which the charge is converted into a voltage may be greater in the second conversion gain mode than in the first conversion gain mode. For example, in response to low illumination, the second conversion gain mode may be applied to the operation of generating a pixel signal.

[0063] The first conversion gain mode or the second conversion gain mode may operate based on the operation of the dual conversion gain transistor DCX.

[0064] When the dual conversion gain transistor DCX is turned off, the first floating diffusion FD1 may have a small capacitance, and the unit pixel UP may operate in the first conversion gain mode.

[0065] When the dual conversion gain transistor DCX is turned on, the first and second floating diffusions FD1 and FD2 may be connected to increase the capacitance of the first and second floating diffusions FD1 and FD2. For example, when the dual conversion gain transistor DCX is turned on, the unit pixel UP may operate in the second conversion gain mode.

[0066] For example, when the dual conversion gain transistor DCX is turned on, the capacitance of the first floating diffusion FD1 or the second floating diffusion FD2 may increase to reduce the conversion gain, and when the dual conversion gain transistor DCX is turned off, the capacitance of the first floating diffusion FD1 may decrease to increase the conversion gain.

[0067] The first to fourth pixel signals generated by the dual conversion gain mode of each of the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may be synthesized into one image, and the synthesized image may have a high dynamic range.

[0068] The source follower transistor SF may be a source follower buffer amplifier that generates a source-drain current proportional to the amount of charge applied from the first floating diffusion FD1 to the source follower gate electrode. The source follower transistor SF may amplify a change in the potential of the first floating diffusion FD1 and may output the amplified signal to the output line V through the selection transistor SX. OUT The source terminal of the source follower transistor SF may be connected to a pixel supply voltage V DD , and the drain terminal of the source follower transistor SF may be connected to the source terminal of the select transistor SX.

[0069] The selection transistor SX can select each row of the unit pixel UP to be read out. When the selection transistor SX is turned on in response to the selection signal SEL applied to the selection gate electrode, the output line V OUT An electrical signal output from the drain terminal of the source follower transistor SF may be output.

[0070] Reference Figure 3B The photoelectric conversion circuit 10P may include first and second photoelectric conversion elements PD1 and PD2 , first and second transfer transistors TX1 and TX2 , and first and second floating diffusions FD1 and FD2 .

[0071] The pixel circuit 20P may include a dual conversion gain transistor DCX, a source follower transistor SF, a selection transistor SX, a reset transistor RX, a first switch transistor (or switch element) SW1, a second switch transistor SW2 and a third switch transistor SW3, a capacitor (or charge storage element) C FD , and a first floating diffusion FD1 , a second floating diffusion FD2 , and a third floating diffusion FD3 .

[0072] The first semiconductor substrate (not shown) may be provided with the first and second transfer transistors TX1 and TX2 and the first and second photoelectric conversion elements PD1 and PD2 included in the photoelectric conversion circuit 10P. In contrast, the second semiconductor substrate (not shown) may be provided with the dual conversion gain transistor DCX, the source follower transistor SF, the selection transistor SX, the reset transistor RX, the first switching transistor SW1, the second switching transistor SW2, and the third switching transistor SW3, and the capacitor C included in the pixel circuit 20P. FD .

[0073] The unit pixel UP may further include a third switch transistor SW3 connected between the first floating diffusion portion FD1 and the source follower transistor SF. The amount of charge generated from the first photoelectric conversion element PD1 may be accumulated in the source / drain terminals of the third switch transistor SW3.

[0074] In some embodiments, it is disclosed that each unit pixel UP includes seven pixel transistors RX, DCX, SF, SX, SW1, SW2, and SW3, but the present example embodiment is not limited thereto and the number of pixel transistors may be variously changed.

[0075] Figure 4A Shown with Figure 3A A plan view of an example of a unit pixel of the circuit configuration shown. Figure 5A illustrates a cross-sectional view of an image sensor according to some example embodiments.

[0076] Reference Figure 3A , Figure 4A and Figure 5A , the image sensor may include a plurality of unit pixels UP, each of which may include a first pixel region PR1 and a second pixel region PR2. The first pixel region PR1 and the second pixel region PR2 may be arranged two-dimensionally along rows and columns. When viewed from above, each of the first pixel region PR1 and the second pixel region PR2 may be surrounded by a pixel isolation structure PIS.

[0077] When viewed in a plan view, the first pixel region PR1 or the first photoelectric conversion element PD1 may have an octagonal shape. When viewed in a plan view, the second pixel region PR2 or the second photoelectric conversion element PD2 may have a quadrilateral shape and may be adjacent to one of the side surfaces of the first pixel region PR1. The planar shapes of the first pixel region PR1 and the second pixel region PR2 are not limited thereto and may be variously changed.

[0078] The first pixel region PR1 may be provided with a first transfer gate electrode TG1, a source follower transistor SF, and a dual conversion gain transistor DCX, and the second pixel region PR2 may be provided with a second transfer gate electrode TG2. For example, the first semiconductor substrate 100 may be provided with a first transfer gate electrode TG1 and a second transfer gate electrode TG2, a source follower transistor SF, and a dual conversion gain transistor DCX, and the second semiconductor substrate 200 may be provided with the remaining pixel transistors.

[0079] According to some example embodiments, at least some of the pixel transistors may not be disposed on the first semiconductor substrate 100 but on the second semiconductor substrate 200, and thus the unit pixel UP may have a reduced size. The length W1 of the unit pixel UP in the second direction D2 may be equal to or less than about 2.4 μm, for example, equal to or less than about 2.1 μm. The length W1 of the unit pixel UP in the second direction D2 may indicate a distance in the second direction D2 between vertices located at opposite ends in the unit pixel UP along the second direction D2. For example, referring to Figure 4A , the length W1 in the second direction D2 may represent the distance in the second direction D2 between the vertex PR1a (the lowermost end point in the second direction D2) of the first pixel region PR1 and the vertex PR2a (the uppermost end point in the second direction D2) of the second pixel region PR2.

[0080] The first semiconductor substrate 100 may have a first top surface (or front surface) 100a and a second surface (or rear surface) 100b opposite to each other, and the second semiconductor substrate 200 may have a first top surface (or front surface) 200a and a second surface (or rear surface) 200b opposite to each other. The first semiconductor substrate 100 and the second semiconductor substrate 200 may be substrates in which an epitaxial layer is formed on a bulk silicon substrate having a first conductivity type (e.g., p-type) that is the same as the first conductivity type of the epitaxial layer, or substrates formed only of a p-type epitaxial layer from which the bulk silicon substrate is removed in the manufacture of the image sensor. Alternatively, the first semiconductor substrate 100 and the second semiconductor substrate 200 may be bulk semiconductor substrates including a well of the first conductivity type.

[0081] The pixel isolation structure PIS may be disposed in the first semiconductor substrate 100 and may define a first pixel region PR1 and a second pixel region PR2. The pixel isolation structure PIS may be disposed between the first pixel region PR1 and the second pixel region PR2 of the first semiconductor substrate 100. When viewed from above, the pixel isolation structure PIS may surround each of the first pixel region PR1 and the second pixel region PR2.

[0082] The pixel isolation structure PIS may have a top surface that is substantially coplanar with the first surface 100a of the first semiconductor substrate 100. The pixel isolation structure PIS may extend from the first surface 100a to the second surface 100b.

[0083] The pixel isolation structure PIS may be formed by patterning the first surface 100a of the first semiconductor substrate 100 to form a deep trench, and then filling the deep trench with a liner dielectric layer and a doped semiconductor layer. In this case, the pixel isolation structure PIS may have a width that gradually decreases in a direction from the first surface 100a of the first semiconductor substrate 100 toward the second surface 100b. Alternatively, the pixel isolation structure PIS may have a substantially constant width between the first surface 100a and the second surface 100b of the first semiconductor substrate 100.

[0084] The pixel isolation structure PIS may be formed by patterning the second surface 100b of the first semiconductor substrate 100 to form a deep trench, and then filling the deep trench with a liner dielectric layer and a doped semiconductor layer. In this case, the pixel isolation structure PIS may have a width that gradually increases in a direction from the first surface 100a of the first semiconductor substrate 100 toward the second surface 100b.

[0085] The pixel isolation structure PIS may be formed of a dielectric material (eg, silicon) having a refractive index lower than that of the first semiconductor substrate 100 , and may include a single or a plurality of dielectric layers.

[0086] The pixel isolation structure PIS may include a liner dielectric pattern 111, a semiconductor pattern 113, and a capping dielectric pattern 115. The semiconductor pattern 113 may vertically penetrate a portion of the first semiconductor substrate 100, and the liner dielectric pattern 111 may be disposed between the semiconductor pattern 113 and the first semiconductor substrate 100. The capping dielectric pattern 115 may be disposed on the semiconductor pattern 113 and may have a top surface substantially coplanar with the first surface 100a of the first semiconductor substrate 100. The liner dielectric pattern 111 and the capping dielectric pattern 115 may include at least one selected from a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer. The semiconductor pattern 113 may include an undoped polysilicon layer or a doped polysilicon layer. The semiconductor pattern 113 may have an air gap or a void.

[0087] The pixel isolation structure PIS may penetrate the first semiconductor substrate 100. The pixel isolation structure PIS may extend vertically from the first surface 100a of the first semiconductor substrate 100 to the second surface 100b. For example, the pixel isolation structure PIS may have a vertical length in a direction perpendicular to the surface of the first semiconductor substrate 100, and the vertical length may be substantially the same as the vertical thickness of the first semiconductor substrate 100. Alternatively, the pixel isolation structure PIS may vertically penetrate a portion of the first semiconductor substrate 100 and may be spaced apart from the second surface 100b of the first semiconductor substrate 100.

[0088] The pixel isolation structure PIS can prevent the first pixel region PR1 and the second pixel region PR2 from receiving randomly drifting photo charges generated from light incident on the first pixel region PR1 and the second pixel region PR2. In this configuration, the pixel isolation structure PIS can help prevent crosstalk between the adjacent first pixel region PR1 and the second pixel region PR2.

[0089] According to some embodiments, the first photoelectric conversion element PD1 may be disposed in the first semiconductor substrate 100 on the first pixel region PR1. The second photoelectric conversion element PD2 may be disposed in the first semiconductor substrate 100 on the second pixel region PR2. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may convert external incident light into electrical signals.

[0090] Each of the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may be doped with an impurity having a second conductivity type (e.g., n-type) opposite to the conductivity type of the first semiconductor substrate 100. The photodiode may be composed of the first semiconductor substrate 100 of the first conductivity type and the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2. For example, the photodiode may be composed of a structure between the first semiconductor substrate 100 of the first conductivity type and one of the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 of the second conductivity type. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 constituting the photodiode may generate and accumulate photocharges proportional to the intensity of incident light.

[0091] In some embodiments, the first photoelectric conversion element PD1 may have a light receiving area larger than the light receiving area of ​​the second photoelectric conversion element PD2. For example, the first photoelectric conversion element PD1 may have a volume larger than the volume of the second photoelectric conversion element PD2. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may have substantially the same vertical depth, and the width of the first photoelectric conversion element PD1 may be greater than the width of the second photoelectric conversion element PD2.

[0092] When viewed in a plane, each of the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may be surrounded by the pixel isolation structure PIS. Therefore, light charges accumulated in the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may be prevented from overflowing into their adjacent first photoelectric conversion elements PD1 and PD2.

[0093] On each of the first pixel region PR1 and the second pixel region PR2 , the device isolation layer 105 may define at least one active portion on the first surface 100 a of the first semiconductor substrate 100 .

[0094] On each of the pixel regions PR1 and PR2, a device isolation layer 105 may be disposed adjacent to the first surface 100a of the first semiconductor substrate 100. A bottom surface of the device isolation layer 105 may be spaced apart from the first and second photoelectric conversion elements PD1 and PD2.

[0095] The device isolation layer 105 may be disposed in a groove formed by recessing the first surface 100a of the first semiconductor substrate 100. The device isolation layer 105 may be formed of a dielectric material. For example, the device isolation layer 105 may include a liner oxide layer and a liner nitride layer that conformally cover the surface of the groove, and may also include a buried oxide layer that fills the groove, in which the liner oxide layer and the liner nitride layer are formed. The top surface of the device isolation layer 105 may be substantially coplanar with the first surface 100a of the first semiconductor substrate 100. In addition, the top surface of the device isolation layer 105 may be substantially coplanar with the top surface of the pixel isolation structure PIS. For example, the top surface of the device isolation layer 105 may be substantially coplanar with the first surface 100a of the first semiconductor substrate 100.

[0096] The first semiconductor substrate 100 may be provided with the first and second transfer transistors TX1 and TX2, the source follower transistor SF, and the dual conversion gain transistor DCX included in the photoelectric conversion circuit 10P. Therefore, the first semiconductor substrate 100 may be provided with the first and second transfer gate electrodes TG1 and TG2, the source follower gate electrode SFG, and the dual conversion gain gate electrode DCGE on its first surface 100a.

[0097] For example, on the first pixel region PR1, the first transfer gate electrode TG1 may be disposed on the first surface 100a of the first semiconductor substrate 100. The first floating diffusion FD1 may be disposed on one side of the first transfer gate electrode TG1 and may be connected to the dual conversion gain transistor DCX. The dual conversion gain gate electrode DCGE may be disposed on the first surface 100a of the first semiconductor substrate 100, and the first floating diffusion FD1 and the third floating diffusion FD3a may be disposed on opposite sides of the dual conversion gain gate electrode DCGE.

[0098] On the second pixel region PR2, the second transfer gate electrode TG2 may be disposed on the first surface 100a of the first semiconductor substrate 100. The second floating diffusion portion FD2a may be disposed in the first semiconductor substrate 100 on one side of the second transfer gate electrode TG2.

[0099] When viewed in a plane, the first transmission gate electrode TG1 and the second transmission gate electrode TG2 may overlap with portions of the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2, respectively. The first transmission gate electrode TG1 and the second transmission gate electrode TG2 may be disposed in the first semiconductor substrate 100. The first transmission gate electrode TG1 and the second transmission gate electrode TG2 may each include a lower portion inserted into the first semiconductor substrate 100 and an upper portion connected to the lower portion and protruding upward from the first surface 100a of the first semiconductor substrate 100. The lower portions of the first transmission gate electrode TG1 and the second transmission gate electrode TG2 may vertically penetrate a portion of the first semiconductor substrate 100. The bottom surfaces of the first transmission gate electrode TG1 and the second transmission gate electrode TG2 may be located at a level different from that of the first surface 100a of the first semiconductor substrate 100. A gate dielectric layer may be inserted between the first semiconductor substrate 100 and each of the first transmission gate electrode TG1 and the second transmission gate electrode TG2.

[0100] On the first pixel region PR1, a source follower gate electrode SFG may be disposed on the first surface 100a of the first semiconductor substrate 100. Source / drain regions SDR may be disposed on opposite sides of the source follower gate electrode SFG.

[0101] The second floating diffusions FD2a and FD2b may be correspondingly disposed in the first semiconductor substrate 100 and the second semiconductor substrate 200. The second floating diffusion FD2a disposed in the first semiconductor substrate 100 may be electrically connected to the second floating diffusion FD2b disposed in the second semiconductor substrate 200 through the conductive line ML and the contact plug CT.

[0102] Likewise, third floating diffusions FD3a and FD3b may be correspondingly disposed in the first semiconductor substrate 100 and the second semiconductor substrate 200. The third floating diffusion FD3a disposed in the first semiconductor substrate 100 may be electrically connected to the third floating diffusion FD3b disposed in the second semiconductor substrate 200 through the conductive line ML and the contact plug CT.

[0103] Since the dual conversion gain gate electrode DCGE and the source follower gate electrode SFG are disposed in the first semiconductor substrate 100 , the first floating diffusion FD1 may be disposed only in the first semiconductor substrate 100 , unlike the second and third floating diffusions FD2 a , FD2 b , and FD3 a and FD3 b .

[0104] When the dual conversion gain transistor DCX is turned off, the image sensor can operate in the first conversion gain mode (or high illumination mode). For example, the charge generated from the first photoelectric conversion element PD1 can be stored in the first floating diffusion FD1, and the stored charge can be transmitted to the source follower gate electrode SFG through the contact plug CT and the wire ML. The source follower transistor SF can generate a source-drain current proportional to the amount of charge input to the first floating diffusion FD1 of the source follower gate electrode SFG.

[0105] For example, even when the first floating diffusion FD1 is disposed on the second semiconductor substrate 200, the first transfer gate electrode TG1 disposed on the first semiconductor substrate 100 and the first floating diffusion FD1 disposed on the second semiconductor substrate 200 may need to be connected by a wire or a contact plug. Therefore, the parasitic capacitance of the first floating diffusion FD1 may increase, and the conversion gain of the first conversion gain mode may decrease. According to an embodiment of the present example embodiment, the dual conversion gain transistor DCX may be disposed on the first semiconductor substrate 100 so that the first floating diffusion FD1 can be located only on the first semiconductor substrate 100, and thus the increase of the parasitic capacitance of the first floating diffusion FD1 may be prevented.

[0106] Some pixel transistors RX, SX, SW1, and SW2 may be disposed on the second semiconductor substrate 200. For example, the second semiconductor substrate 200 may be provided with a selection transistor SX, a reset transistor RX, and a first switch transistor SW1 and a second switch transistor SW2 included in the pixel circuit 20P. Therefore, the second semiconductor substrate 200 may be provided with a selection gate electrode SXG, a reset gate electrode RXG, and a first switch gate electrode SWG1 and a second switch gate electrode SWG2 on its first surface 200a.

[0107] The first interlayer dielectric layer 110 and the second interlayer dielectric layer 210 may be disposed on each of the first semiconductor substrate 100 and the second semiconductor substrate 200, and may cover the pixel transistors RX, DCX, SF, SX, SW1, and SW2 or the first and second transfer gate electrodes TG1 and TG2. For example, the first interlayer dielectric layer 110 may cover the first surface 100a of the first semiconductor substrate 100, the first and second transfer gate electrodes TG1 and TG2, the source follower gate electrode SFG, and the dual conversion gain gate electrode DCGE. The second interlayer dielectric layer 210 may cover the first surface 200a of the second semiconductor substrate 200, the selection gate electrode SXG, the reset gate electrode RXG, and the first and second switch gate electrodes SWG1 and SWG2.

[0108] The first interlayer dielectric layer 110 and the second interlayer dielectric layer 210 may have conductive lines ML, contact plugs CT, the first interlayer dielectric layer 110 and the second interlayer dielectric layer 210 , and capacitors CAP disposed therein.

[0109] The conductive line ML may be coupled to the contact plug CT in the first interlayer dielectric layer 110 and the second interlayer dielectric layer 210. For example, the conductive line ML and the contact plug CT may include a metal such as tungsten, copper, aluminum, or an alloy thereof.

[0110] The first bonding pad BP1 may be disposed on top of the first interlayer dielectric layer 110 disposed on the first semiconductor substrate 100, and the second bonding pad BP2 may be disposed on top of the second interlayer dielectric layer 210 disposed on the second semiconductor substrate 200. The first interlayer dielectric layer 110 and the second interlayer dielectric layer 210 may contact each other, and thus the first bonding pad BP1 disposed at the top of the first interlayer dielectric layer 110 may contact the second bonding pad BP2 disposed at the top of the second interlayer dielectric layer 210.

[0111] The first and second bonding pads BP1 and BP2 may be connected to the first and second transfer gate electrodes TG1 and TG2 , the floating diffusions FD1 , FD2 a , FD2 b , FD3 a , and FD3 b , and the source / drain regions SDR through the contact plugs CT and the wires ML.

[0112] Since the first bonding pad BP1 and the second bonding pad BP2 are electrically connected to each other, the third floating diffusion FD3a disposed on the first semiconductor substrate 100 may be electrically connected to the third floating diffusion FD3b disposed on the second semiconductor substrate 200. Likewise, the second floating diffusion FD2a disposed on the first semiconductor substrate 100 may be electrically connected to the second floating diffusion FD2b disposed on the second semiconductor substrate 200.

[0113] A hybrid bonding method may be used to electrically connect the first bonding pad BP1 directly to the second bonding pad BP2. In the present specification, the term "hybrid bonding" may mean that two components of the same kind are merged at the interface between them. For example, when the first bonding pad BP1 and the second bonding pad BP2 are formed of copper, copper-to-copper bonding may be used to physically and electrically connect the first bonding pad BP1 and the second bonding pad BP2 to each other. In addition, dielectric-to-dielectric bonding may be used to bond the surface of the first interlayer dielectric layer 110 of the photoelectric conversion circuit layer 10 to the surface of the second interlayer dielectric layer 210 of the pixel circuit layer 20.

[0114] Reference Figure 5A, the capacitor CAP may be disposed in the second interlayer dielectric layer 210. As described above, the capacitor CAP may be connected between the second switch transistor SW2 and the pixel power supply voltage V DD capacitor between Figure 3A and Figure 3B C FD ). For example, the capacitor CAP may be a metal oxide semiconductor (MOS) capacitor, a metal insulator semiconductor (MIS) capacitor, or a metal insulator metal (MIM) capacitor.

[0115] The source / drain region SDR of the second switching transistor SW2 may be connected to one side of the capacitor CAP. Figure 5A CAP may be connected to a pixel supply voltage (see FIG. Figure 3A V DD ).

[0116] The planarized dielectric layer 310 may cover the second surface 100b of the first semiconductor substrate 100. The planarized dielectric layer 310 may be formed of a transparent dielectric material and may include a plurality of layers. The planarized dielectric layer 310 may be formed of a dielectric material having a refractive index different from that of the first semiconductor substrate 100. The planarized dielectric layer 310 may include one or more of a metal oxide and a silicon oxide.

[0117] The grid structure 320 may be disposed on the planarized dielectric layer 310. Similar to the pixel isolation structure PIS, the grid structure 320 may have a grid or mesh shape when viewed in a plane. The grid structure 320 may overlap the pixel isolation structure PIS when viewed in a plane. For example, the grid structure 320 may include a first portion extending in a first direction D1 and a second portion extending in a second direction D2 while crossing the first portion. The grid structure 320 may have a width substantially equal to or less than the minimum width of the pixel isolation structure PIS.

[0118] The grid structure 320 may include one or more of a conductive pattern and a low refractive index pattern. The conductive pattern may include a metal material such as titanium, tantalum, or tungsten. The low refractive index pattern may be formed of a material with a refractive index less than that of the conductive pattern. The low refractive index pattern may be formed of an organic material and may have a refractive index of about 1.1 to about 1.3. For example, the grid structure 320 may be a polymer layer including silicon dioxide nanoparticles.

[0119] The planarized dielectric layer 310 may be provided thereon with a protection layer 330 having a substantially uniform thickness, which covers the surface of the grid structure 320. The protection layer 330 may be a single layer or a multilayer, including, for example, at least one selected from aluminum oxide and silicon oxide carbon layers.

[0120] The color filter 340 may be formed corresponding to each unit pixel UP. For example, the first pixel region PR1 and the second pixel region PR2 of each unit pixel UP may share one color filter 340. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may convert light released from the color filter 340 into an electrical signal.

[0121] The color filter 340 may fill the space defined by the grid structure 320. Based on the unit pixel UP, the color filter 340 may include one of a red filter, a green filter, and a blue filter or one of a magenta filter, a cyan filter, and a yellow filter. Alternatively, one or more color filters 340 may include a white filter or an infrared filter.

[0122] The microlenses 350 may be disposed on the color filter 340. The microlenses 350 may each have a convex shape with a specific radius of curvature. The microlenses 350 may be formed of a light-transmitting resin. The color filter 340 may be provided with microlenses 350 corresponding to the first pixel region PR1 and the second pixel region PR2.

[0123] Since the sum of the light receiving areas of the first photoelectric conversion element PD1 is greater than the sum of the light receiving areas of the second photoelectric conversion element PD2, the area of ​​the microlens 350 disposed on the first photoelectric conversion element PD1 may be greater than the area of ​​the microlens 350 disposed on the second photoelectric conversion element PD2. The radius of curvature of the microlens 350 disposed on the first photoelectric conversion element PD1 may be different from the radius of curvature of the microlens 350 disposed on the second photoelectric conversion element PD2.

[0124] Figure 5B and Figure 5C A cross-sectional view of an image sensor according to some example embodiments is shown. For the sake of brevity of description, the above reference will be omitted. Figure 3A , Figure 4A and Figure 5A The same technical features of the image sensors are discussed, and their differences will be explained.

[0125] Reference Figure 3A and Figure 5B , the first capacitor CAP1 and the second capacitor CAP2 may be disposed in the first interlayer dielectric layer 110 and the second interlayer dielectric layer 210 , respectively. For example, the first capacitor CAP1 may be disposed in the first interlayer dielectric layer 110 , and the second capacitor CAP2 may be disposed in the second interlayer dielectric layer 210 .

[0126] The first electrode CAP2_a of the second capacitor CAP2 may be connected to the source / drain region SDR of the second switch transistor SW2. Although not shown, the second electrode CAP2_b of the second capacitor CAP2 may be connected to the pixel power supply voltage V DD.

[0127] The first capacitor CAP1 and the second capacitor CAP2 may be electrically connected to each other. For example, the first electrode CAP1_a of the first capacitor CAP1 and the first electrode CAP2_a of the second capacitor CAP2 may be electrically connected through the contact plug CT, the wire ML, and the first bonding pad BP1 and the second bonding pad BP2. Similarly, the second electrode CAP1_b of the first capacitor CAP1 and the second electrode CAP2_b of the second capacitor CAP2 may be electrically connected through the contact plug CT, the wire ML, and the first bonding pad BP1 and the second bonding pad BP2.

[0128] According to some example embodiments, even if the first capacitor CAP1 and the second capacitor CAP2 have a small size due to the small size of the unit pixel UP, the first capacitor CAP1 and the second capacitor CAP2 may be connected to each other in parallel to secure a total capacitance.

[0129] Reference Figure 5C , the first semiconductor substrate 100 may be provided with a source follower gate electrode SFG, a dual conversion gain gate electrode DCGE, and a first transmission gate electrode TG1 and a second transmission gate electrode TG2 on its first surface 100a. The first interlayer dielectric layer 110 may be provided on the first surface 100a of the first semiconductor substrate 100 to cover the source follower gate electrode SFG, the dual conversion gain gate electrode DCGE, and the first transmission gate electrode TG1 and the second transmission gate electrode TG2. The first interlayer dielectric layer 110 may be provided under the second semiconductor substrate 200 to contact the second surface 200b of the second semiconductor substrate 200.

[0130] The second semiconductor substrate 200 may be provided with a selection gate electrode SXG, a reset gate electrode RXG, and a first switch gate electrode SWG1 and a second switch gate electrode SWG2 on a first surface 200a thereof. The second interlayer dielectric layer 210 may cover the first surface 200a, the selection gate electrode SXG, the reset gate electrode RXG, and the first switch gate electrode SWG1 and the second switch gate electrode SWG2 of the second semiconductor substrate 200. The first surface 200a and the second surface 200b of the second semiconductor substrate 200 may be covered by the first interlayer dielectric layer 110 and the second interlayer dielectric layer 210, respectively.

[0131] The capacitor CAP may be disposed in the second interlayer dielectric layer 210 , but the present example embodiment is not limited thereto. For example, the capacitor CAP may be disposed on the first interlayer dielectric layer 110 and may be electrically connected to the source / drain region SDR through the conductive line ML, the contact plug CT, and the through plug TP.

[0132] The through plugs TP may penetrate the second semiconductor substrate 200 . Portions of the through plugs TP may be disposed in the second interlayer dielectric layer 210 on the second semiconductor substrate 200 and in the first interlayer dielectric layer 110 on the first semiconductor substrate 100 .

[0133] The through plug TP may be connected to the conductive line ML and the contact plug CT. The source / drain regions SDR and the floating diffusions FD2a, FD2b, FD3a, and FD3b in the first semiconductor substrate 100 and the second semiconductor substrate 200 may be electrically connected through the through plug TP, the conductive line ML, and the contact plug CT. The through plug TP may include a metal such as tungsten, copper, aluminum, or any alloy thereof.

[0134] The through dielectric pattern TIP may surround the sidewall of the through plug TP. For example, the through dielectric pattern TIP may be disposed between the through plug TP and the second semiconductor substrate 200. The top surface of the through dielectric pattern TIP may be coplanar with the first surface 200a of the second semiconductor substrate 200, and the bottom surface of the through dielectric pattern TIP may be coplanar with the second surface 200b of the second semiconductor substrate 200. The through dielectric pattern TIP may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0135] The second floating diffusion FD2a disposed in the first semiconductor substrate 100 may be electrically connected to the second floating diffusion FD2b disposed in the second semiconductor substrate 200 through the conductive line ML, the contact plug CT, and the through plug TP. Similarly, the third floating diffusion FD3a disposed in the first semiconductor substrate 100 may be electrically connected to the third floating diffusion FD3b disposed in the second semiconductor substrate 200 through the conductive line ML, the contact plug CT, and the through plug TP.

[0136] Reference Figure 3B , Figure 4B and Figure 6 , the image sensor according to some example embodiments will be described below. For the sake of brevity of description, the above reference Figure 3A , Figure 4A and Figure 5A The same technical features of image sensors are discussed and their differences will be explained.

[0137] Figure 4B Shown with Figure 3B A plan view of an example of a unit pixel of the circuit configuration shown. Figure 6 illustrates a cross-sectional view of an image sensor according to some example embodiments.

[0138] Reference Figure 3B , Figure 4B and Figure 6, the image sensor may include a plurality of unit pixels UP, and each unit pixel UP may include a first pixel region PR1 and a second pixel region PR2. The first pixel region PR1 and the second pixel region PR2 may be arranged two-dimensionally along rows and columns. When viewed in a plane, each of the first pixel region PR1 and the second pixel region PR2 may be surrounded by a pixel isolation structure PIS.

[0139] The first semiconductor substrate 100 may be provided thereon with the first transfer transistor TX1 and the second transfer transistor TX2 of the photoelectric conversion circuit 10P. Therefore, the first transfer gate electrode TG1 and the second transfer gate electrode TG2 may be provided on the first surface 100 a of the first semiconductor substrate 100 .

[0140] For example, on the first pixel region PR1, the first transfer gate electrode TG1 may be disposed on the first surface 100a of the first semiconductor substrate 100. The first floating diffusion portion FD1a may be disposed on one side of the first transfer gate electrode TG1.

[0141] The first floating diffusions FD1a and FD1b may be respectively disposed in the first semiconductor substrate 100 and the second semiconductor substrate 200. The first floating diffusion FD1a disposed in the first semiconductor substrate 100 may be electrically connected to the first floating diffusion FD1b disposed in the second semiconductor substrate 200 through the conductive line ML, the contact plug CT, and the first and second bonding pads BP1 and BP2.

[0142] On the second pixel region PR2, the second transfer gate electrode TG2 may be disposed on the first surface 100a of the first semiconductor substrate 100. The second floating diffusion portion FD2a may be disposed in the first semiconductor substrate 100 on one side of the second transfer gate electrode TG2.

[0143] The second floating diffusions FD2a and FD2b may be respectively disposed in the first semiconductor substrate 100 and the second semiconductor substrate 200. The second floating diffusion FD2a disposed in the first semiconductor substrate 100 may be electrically connected to the second floating diffusion FD2b disposed in the second semiconductor substrate 200 through the conductive line ML, the contact plug CT, and the first and second bonding pads BP1 and BP2.

[0144] The pixel transistors DCX, SF, RX, SX, SW1, and SW2 may be disposed on the second semiconductor substrate 200. For example, the second semiconductor substrate 200 may be provided with the dual conversion gain transistor DCX, the source follower transistor SF, the selection transistor SX, the reset transistor RX, and the first switch transistor SW1, the second switch transistor SW2, and the third switch transistor SW3 included in the pixel circuit 20P. Therefore, the second semiconductor substrate 200 may be provided with the dual conversion gain gate electrode DCGE, the source follower gate electrode SFG, the selection gate electrode SXG, the reset gate electrode RXG, and the first switch gate electrode SWG1, the second switch gate electrode SWG2, and the third switch gate electrode SWG3 on its first surface 200a.

[0145] According to some example embodiments, the pixel transistors DCX, SF, RX, SX, SW1, SW2, and SW3 may not be disposed on the first semiconductor substrate 100 but on the second semiconductor substrate 200. Therefore, only the first transfer transistor TX1 and the second transfer transistor TX2 may be disposed on the first semiconductor substrate 100, and the unit pixel UP may have a reduced size.

[0146] The length W2 of the unit pixel UP in the second direction D2 may be equal to or less than about 2.4 μm, for example, equal to or less than about 1.8 μm. The length W2 of the unit pixel UP in the second direction D2 may indicate the distance in the second direction D2 between vertices located at opposite ends in the unit pixel UP along the second direction D2. Figure 4B , the length W2 in the second direction D2 may indicate a distance in the second direction D2 between a vertex PR1a (the lowermost endpoint in the second direction D2) of the first pixel region PR1 and a vertex PR2a (the uppermost endpoint in the second direction D2) of the second pixel region PR2.

[0147] However, since the dual conversion gain transistor DCX and the source follower transistor SF are disposed on the second semiconductor substrate 200, the first floating diffusions FD1a and FD1b may be disposed on the first semiconductor substrate 100 and the second semiconductor substrate 200, respectively. Therefore, the first floating diffusion FD1a disposed in the first semiconductor substrate 100 may be connected to the first floating diffusion FD1b disposed in the second semiconductor substrate 200 through the conductive line ML and the contact plug CT. Since only the first transfer transistor TX1 and the second transfer transistor TX2 are disposed on the first semiconductor substrate 100, the unit pixel UP may have a reduced size.

[0148] Figure 7 A plan view of an image sensor according to some example embodiments is illustrated.

[0149] Reference Figure 7, each of the first photoelectric conversion elements PD1R, PD1G, and PD1B may have an octagonal shape when viewed in a plane. Each of the first photoelectric conversion elements PD1R, PD1G, and PD1B may have a first width in the first direction D1. The first width may be a width measured on the first surface 100a of the first semiconductor substrate 100. In addition, the first width may correspond to a spacing between portions of the pixel isolation structure PIS.

[0150] When viewed in a plane, each of the second photoelectric conversion elements PD2R, PD2G, and PD2B may have a quadrilateral shape. The size of the second photoelectric conversion elements PD2R, PD2G, and PD2B may be smaller than the size of the first photoelectric conversion elements PD1R, PD1G, and PD1B. In this sense, the light receiving area of ​​the second photoelectric conversion elements PD2R, PD2G, and PD2B may be smaller than the light receiving area of ​​the first photoelectric conversion elements PD1R, PD1G, and PD1B. For example, each of the second photoelectric conversion elements PD2R, PD2G, and PD2B may have a second width in the first direction D1 that is smaller than the first width. In the present specification, the widths of two components may be compared in the same direction at the same level.

[0151] When viewed in a plane, each of the plurality of second photoelectric conversion elements PD2R, PD2G, and PD2B or each of the second pixel regions PR2 may be surrounded by four adjacent first photoelectric conversion elements PD1R, PD1G, and PD1B. When viewed in a plane, the second photoelectric conversion elements PD2R, PD2G, and PD2B may be two-dimensionally arranged along the first direction D1 and the second direction D2.

[0152] The first photoelectric conversion elements PD1R, PD1G, and PD1B and the second photoelectric conversion elements PD2R, PD2G, and PD2B may be alternately arranged along the first diagonal direction D3 and the second diagonal direction D4. The second photoelectric conversion elements PD2R, PD2G, and PD2B may be correspondingly arranged between the first photoelectric conversion elements PD1R, PD1G, and PD1B in the first diagonal direction D3 and the second diagonal direction D4.

[0153] The first photoelectric conversion elements PD1R, PD1G, and PD1B and the second photoelectric conversion elements PD2R, PD2G, and PD2B may be alternately disposed along the first direction D1. The second photoelectric conversion elements PD2R, PD2G, and PD2B may be correspondingly disposed between the first photoelectric conversion elements PD1R, PD1G, and PD1B in the first direction D1 and the second direction D2.

[0154] According to some embodiments, due to the adjustment of the planar shape and the first width of the first photoelectric conversion elements PD1R, PD1G, and PD1B and due to the adjustment of the planar shape and the second width of the second photoelectric conversion elements PD2R, PD2G, and PD2B, the arrangement of the unit pixels can be highly integrated. Therefore, the optical characteristics of the image sensor can be improved.

[0155] Figure 8 A timing diagram illustrating the operation of an image sensor according to some example embodiments is shown.

[0156] Reference Figure 3A and Figure 8 , the reset signal RG may be activated to turn on the reset transistor RX. Therefore, the pixel power supply voltage V may be provided to the first floating diffusion FD1. DD The charges are discharged from the first floating diffusion FD1 , and as a result, the first floating diffusion FD1 may be reset (or initialized).

[0157] When the reset signal RG is activated, the first switching signal SG1 and the second switching signal SG2 may be activated to further provide the pixel power supply voltage V to the second floating diffusion FD2 and the third floating diffusion FD3. DD Therefore, the second floating diffusion FD2 and the third floating diffusion FD3 may also be reset.

[0158] The reset signal RG may be deactivated to turn off the reset transistor RX. Therefore, the first floating diffusion FD1, the second floating diffusion FD2, and the third floating diffusion FD3 may become a state capable of storing charges.

[0159] After the reset transistor RX is turned off, the selection signal SEL may be activated immediately to turn on the selection transistor SX. When the selection transistor SX is turned on, the output line V OUT A pixel signal can be output.

[0160] At time t0 , a first reset signal proportional to the potential of the first floating diffusion FD1 may be output.

[0161] After the first reset signal is read out, the first transfer signal TRG1 may be activated to turn on the first transfer transistor TX1. Therefore, in the first conversion gain mode, charges accumulated in the first photoelectric conversion element PD1 may be transferred to the first floating diffusion FD1.

[0162] The first transmission signal TRG1 may be deactivated to turn off the first transmission transistor TX1 , and at time t1 , a first pixel signal proportional to the amount of photocharges accumulated in the first photoelectric conversion element PD1 in the first conversion gain mode may be output.

[0163] After the first pixel signal is output, the dual conversion gain control signal DCG may be activated to turn on the dual conversion gain transistor DCX. Therefore, the first photoelectric conversion element PD1 may operate in a second conversion gain mode whose conversion gain is smaller than that of the first conversion gain mode.

[0164] Turning on the dual conversion gain transistor DCX may output a second pixel signal that is a sum of the capacitances of the first floating diffusion FD1 and the third floating diffusion FD3 .

[0165] After the dual conversion gain transistor DCX is turned on, at time t2, the first transfer signal TRG1 may be activated to turn on the first transfer transistor TX1 again. Therefore, in the second conversion gain mode, the charge accumulated in the first photoelectric conversion element PD1 may be transferred to the first and third floating diffusions FD1 and FD3.

[0166] The first transfer signal TRG1 may be deactivated to turn off the first transfer transistor TX1, and at time t3, a second pixel signal proportional to the amount of photocharge accumulated in the first photoelectric conversion element PD1 in the second conversion gain mode may be output. For example, the second pixel signal may be proportional to the amount of charge stored in the first floating diffusion FD1 and the third floating diffusion FD3.

[0167] The reset signal RG may be activated again to turn on the reset transistor RX. Therefore, charges may be discharged from the first and third floating diffusions FD1 and FD3, and thus the first and third floating diffusions FD1 and FD3 may be reset.

[0168] After the first floating diffusion FD1 and the third floating diffusion FD3 are reset, the first switching signal SG1 may be activated to turn on the first switching transistor SW1. Therefore, a third pixel signal corresponding to the sum of the capacitances of the first floating diffusion FD1, the second floating diffusion FD2, and the third floating diffusion FD3 may be output. Therefore, the image sensor may operate in a third conversion gain mode in which the conversion gain thereof is less than the conversion gain of the second conversion gain mode.

[0169] At time t4, the second transfer signal TRG2 may be activated to turn on the second transfer transistor TX2. Therefore, in the third conversion gain mode, charges accumulated in the second photoelectric conversion element PD2 may be transferred to the first floating diffusion FD1, the second floating diffusion FD2, and the third floating diffusion FD3.

[0170] The second transfer signal TRG2 may be deactivated to turn off the second transfer transistor TX2, and at time t5, a third pixel signal proportional to the amount of photocharge accumulated in the second photoelectric conversion element PD2 may be output. For example, the third pixel signal may be proportional to the amount of charge stored in the first floating diffusion FD1, the second floating diffusion FD2, and the third floating diffusion FD3.

[0171] After the third pixel signal is output, the second switching signal SG2 may be activated to turn on the second switching transistor SW2. Thus, the first floating diffusion FD1, the second floating diffusion FD2, and the third floating diffusion FD3 and the capacitor C may be output. FD Therefore, the image sensor can be operated in a fourth conversion gain mode whose conversion gain is smaller than the conversion gain of the third conversion gain mode.

[0172] At time t6, the second transfer signal TRG2 may be activated to turn on the second transfer transistor TX2. Therefore, in the fourth conversion gain mode, the charge accumulated in the second photoelectric conversion element PD2 may be transferred to the first floating diffusion FD1, the second floating diffusion FD2, and the third floating diffusion FD3 and the capacitor C FD .

[0173] The second transfer signal TRG2 may be deactivated to turn off the second transfer transistor TX2, and at time t7, a fourth pixel signal proportional to the amount of photocharge accumulated in the second photoelectric conversion element PD2 may be output. For example, the fourth pixel signal may be proportional to the photocharge stored in the first floating diffusion FD1, the second floating diffusion FD2, and the third floating diffusion FD3 and the capacitor C FD is proportional to the amount of charge in it.

[0174] Fig.9A and Fig. 9B illustrates a cross-sectional view of an image sensor according to some example embodiments.

[0175] Reference Fig.9A , the image sensor may include a sensor chip C1 and a logic chip C2. The sensor chip C1 may include a pixel array region R1 and a pad region R2.

[0176] As described above, the pixel array region R1 may include a plurality of unit pixels arranged two-dimensionally along the first direction D1 and the second direction D2 intersecting each other. Each of the unit pixels may include a first photoelectric conversion element and a second photoelectric conversion element and a pixel transistor. Each unit pixel of the pixel array region R1 may output an electrical signal generated from incident light.

[0177] The pixel array region R1 may include a light receiving region AR and a light shielding region OB. When viewed in a plane, the light shielding region OB may surround the light receiving region AR. For example, when viewed in a plane, the light shielding region OB may be disposed on the upper side, the lower side, the left side, and the right side of the light receiving region AR. The light shielding region OB may include a reference pixel on which no light is incident, and the amount of charge sensed in the unit pixel of the light receiving region AR may be compared with the amount of reference charge appearing at the reference pixel, which may result in calculating the amplitude of the electrical signal sensed in the unit pixel.

[0178] The pad area R2 may include a plurality of conductive pads PAD for input and output of control signals and photoelectric conversion signals. For easy connection with an external device, the pad area R2 may surround the pixel array area R1 when viewed in a plane. The conductive pads PAD may enable an external device to receive an electrical signal generated from a unit pixel.

[0179] The sensor chip C1 may include a photoelectric conversion circuit layer 10 between the pixel circuit layer 20 and the light transmission layer 30. As described above, the photoelectric conversion circuit layer 10 of the sensor chip C1 may include a first semiconductor substrate 100, a pixel isolation structure PIS defining a pixel area, and a first photoelectric conversion element PD1 and a second photoelectric conversion element PD2. As described above, the pixel circuit layer 20 may include a second semiconductor substrate 200, a pixel transistor TR disposed on at least a portion of the second semiconductor substrate 200, and a second interlayer dielectric layer 210. On the light receiving area AR, the sensor chip C1 may have the same technical features as those of the above-mentioned image sensor.

[0180] The pixel isolation structure PIS may extend from the light receiving region AR toward the light shielding region OB. A portion of the pixel isolation structure PIS may be electrically connected to the contact plug 522 on the light shielding region OB.

[0181] The planarized dielectric layer 310 may extend from the light receiving region AR toward the light shielding region OB and the pad region R2 .

[0182] On the light shielding area OB, a light shielding pattern OBP may be disposed on the planarized dielectric layer 310. The light shielding pattern OBP may not allow light to travel toward the photoelectric conversion element PD disposed on the light shielding area OB. On the reference pixel area of ​​the light shielding area OB, the photoelectric conversion element PD may output a noise signal instead of outputting a photoelectric signal. The noise signal may be generated from electrons generated due to heat or dark current. The light shielding pattern OBP may include a metal such as tungsten, copper, aluminum, or any alloy thereof.

[0183] The filter layer 545 may be disposed on the light shielding pattern OBP. The filter layer 545 may block light having a wavelength different from that of light generated from the color filter 340. For example, the filter layer 545 may block infrared rays. The filter layer 545 may include a blue color filter, but the present example embodiment is not limited thereto.

[0184] On the light shielding area OB, the first through conductive pattern 511 may penetrate the first semiconductor substrate 100 to be electrically connected to the metal line 221 of the pixel circuit layer 20 and the wiring structure 1111 of the logic chip C2. The first through conductive pattern 511 may have a first bottom surface and a second bottom surface located at different levels. The first mask pattern 521 may be disposed in the first through conductive pattern 511. The first mask pattern 521 may include a low refractive index material and may have dielectric properties.

[0185] On the pad region R2, the conductive pad PAD may be disposed on the second surface 100b of the first semiconductor substrate 100. The conductive pad PAD may be buried in the second surface 100b of the first semiconductor substrate 100. For example, on the pad region R2, the conductive pad PAD may be disposed in a pad groove formed on the second surface 100b of the first semiconductor substrate 100. The conductive pad PAD may include a metal such as aluminum, copper, tungsten, titanium, tantalum, or any alloy thereof. In the mounting process of the image sensor, a bonding wire may be bonded to the conductive pad PAD. The conductive pad PAD may be electrically connected to an external device through a bonding wire.

[0186] On the pad region R2, the second through conductive pattern 513 may penetrate the first semiconductor substrate 100 to be electrically connected to the wiring structure 1111 of the logic chip C2. The second through conductive pattern 513 may extend to the second surface 100b of the first semiconductor substrate 100 to be electrically connected to the conductive pad PAD. A portion of the second through conductive pattern 513 may cover the bottom surface and sidewall of the conductive pad PAD. The second mask pattern 523 may be disposed in the second through conductive pattern 513. The second mask pattern 523 may include a low refractive index material and may have dielectric properties. On the pad region R2, a pixel isolation structure PIS may be disposed around the second through conductive pattern 513.

[0187] The logic chip C2 may include a third semiconductor substrate 1000, a logic circuit LC, a wiring structure 1111 connected to the logic circuit LC, and a logic interlayer dielectric layer 1100. The uppermost one of the logic interlayer dielectric layers 1100 may be coupled to the pixel circuit layer 20 of the sensor chip C1. The logic chip C2 may be electrically connected to the sensor chip C1 through the first through conductive pattern 511 and the second through conductive pattern 513.

[0188] In the embodiment, as described above, the sensor chip C1 and the logic chip C2 are electrically connected by the first through conductive pattern 511 and the second through conductive pattern 513 , but the present example embodiment is not limited thereto.

[0189] according to Fig. 9B In the illustrated embodiment, the sensor chip C1 and the logic chip C2 may be electrically connected due to direct contact between the third bonding pad BP3 and the fourth bonding pad BP4 disposed at the uppermost metal layers of the sensor chip C1 and the logic chip C2.

[0190] For example, the image sensor may be configured such that the sensor chip C1 may include a third bonding pad BP3 disposed at the uppermost metal layer of the pixel circuit layer 20, and the logic chip C2 may include a fourth bonding pad BP4 disposed at the uppermost metal layer of the wiring structure 1111. The third bonding pad BP3 and the fourth bonding pad BP4 may include, for example, at least one selected from tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0191] A hybrid bonding method may be used to electrically connect the third bonding pad BP3 of the sensor chip C1 directly to the fourth bonding pad BP4 of the logic chip C2. In the present specification, the term "hybrid bonding" may refer to two components of the same kind being merged at the interface between them. For example, when the third bonding pad BP3 and the fourth bonding pad BP4 are formed of copper (Cu), copper-to-copper bonding may be used to physically and electrically connect the third bonding pad BP3 and the fourth bonding pad BP4 to each other. In addition, dielectric-to-dielectric bonding may be used to couple the surface of the dielectric layer included in the sensor chip C1 to the surface of the dielectric layer included in the logic chip C2.

[0192] According to some example embodiments, the pixel transistors may be arranged to be distributed on the first semiconductor substrate and the second semiconductor substrate. Due to the pixel transistors arranged on the first semiconductor substrate and the first transfer gate electrode, the transfer gate electrode and the second transfer gate electrode, a high dynamic range (HDR) may be ensured, and further, due to the pixel transistors arranged on the second semiconductor substrate, the size of the unit pixel may be reduced.

[0193] Although some example embodiments have been discussed with reference to the accompanying drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present example embodiments. Therefore, it will be understood that the above embodiments are illustrative in all aspects and not restrictive.

[0194] In various example embodiments herein, reference may be made to various circuit elements, including but not limited to capacitors, resistors, inductors, switches, amplifiers, comparators, filters, and transistors. Various types of digital, analog, active and / or passive components may be used to implement the example embodiments. For example, as described above, pseudo resistors may replace passive resistors. In addition, various transistor types may be used depending on the implementation, whether positive logic or negative logic is used, the manufacturing process used, etc. In addition, unless otherwise specifically stated herein, there are many available types of filters, comparators, switches, etc., which may be used to implement the example embodiments.

[0195] Any functional blocks shown in the figures and described above may be implemented in a processing circuit, such as hardware including logic circuits, a hardware / software combination (such as a processor executing software), or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0196] Although the terms "same" or "equivalent" are used in the description of the exemplary embodiments, it should be understood that some imprecision may exist. Therefore, when one element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0197] When any of the terms "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "generally" or "substantially" are used in conjunction with a geometric shape, it is expected that the accuracy of the geometric shape is not required, but the freedom of the shape is within the scope of the present invention. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

Claims

1. An image sensor, comprising: A first semiconductor substrate including a first pixel region and a second pixel region; A first photoelectric conversion element, which is on the first pixel area; a second photoelectric conversion element, which is on the second pixel area; a first floating diffusion portion, which is on the first pixel region; a second floating diffusion portion, which is on the second pixel region; a first transfer gate electrode between the first photoelectric conversion element and the first floating diffusion; a second transfer gate electrode between the second photoelectric conversion element and the second floating diffusion; a second semiconductor substrate, which is on the first semiconductor substrate; as well as a plurality of pixel transistors connected to the first photoelectric conversion element and the second photoelectric conversion element, wherein the width of the second photoelectric conversion element is smaller than the width of the first photoelectric conversion element, and At least one pixel transistor among the plurality of pixel transistors is on the second semiconductor substrate.

2. The image sensor according to claim 1, wherein: One or more of the plurality of pixel transistors are on the first pixel region of the first semiconductor substrate.

3. The image sensor according to claim 1, wherein: The plurality of pixel transistors include: a dual conversion gain transistor on the first semiconductor substrate and connected to the first floating diffusion; and A source follower transistor is on the first semiconductor substrate.

4. The image sensor according to claim 3, wherein: The plurality of pixel transistors include: a select transistor on the second semiconductor substrate and connected to the source follower transistor; a reset transistor on the second semiconductor substrate and connected to the dual conversion gain transistor; a first switch transistor on the second semiconductor substrate and connected to the second floating diffusion; and A second switch transistor is on the second semiconductor substrate and connected to the second floating diffusion.

5. The image sensor according to claim 1, wherein: The plurality of pixel transistors include: a dual conversion gain transistor on the second semiconductor substrate and connected to the first floating diffusion; and A source follower transistor is on the second semiconductor substrate.

6. The image sensor of claim 5, wherein the plurality of pixel transistors comprises: a select transistor on the second semiconductor substrate and connected to the source follower transistor; a reset transistor on the second semiconductor substrate and connected to the dual conversion gain transistor; a first switch transistor on the second semiconductor substrate and connected to the dual conversion gain transistor; as well as A second switch transistor is on the second semiconductor substrate and connected to the second floating diffusion.

7. The image sensor according to claim 5, wherein: The plurality of pixel transistors further include a third switch transistor on the second semiconductor substrate and connected to the first floating diffusion and the source follower transistor. 8 . The image sensor of claim 1 , further comprising a capacitor connected between the second floating diffusion and a pixel power supply voltage.

9. The image sensor of claim 1, further comprising: a first capacitor in a first interlayer dielectric layer on the first semiconductor substrate; as well as a second capacitor in a second interlayer dielectric layer on the second semiconductor substrate, Wherein, the first capacitor and the second capacitor are connected in parallel with each other.

10. The image sensor according to claim 1, wherein: Each of the first transfer gate electrode and the second transfer gate electrode vertically penetrates a portion of the first semiconductor substrate. 11 . The image sensor according to claim 1 , further comprising a pixel isolation structure in the first semiconductor substrate and between the first photoelectric conversion element and the second photoelectric conversion element.

12. The image sensor of claim 1, further comprising: a first interlayer dielectric layer on the first semiconductor substrate and covering the first transfer gate electrode and the second transfer gate electrode; a second interlayer dielectric layer on the second semiconductor substrate and covering the at least one pixel transistor among the plurality of pixel transistors; a first bonding pad in the first interlayer dielectric layer; as well as a second bonding pad in the second interlayer dielectric layer and contacting the first bonding pad.

13. The image sensor of claim 1, further comprising: a first interlayer dielectric layer on the first semiconductor substrate and covering the first transfer gate electrode and the second transfer gate electrode; a second interlayer dielectric layer on the second semiconductor substrate and covering the at least one pixel transistor among the plurality of pixel transistors; as well as A through plug penetrates the second semiconductor substrate and is connected to the conductive lines of the first interlayer dielectric layer and the second interlayer dielectric layer.

14. An image sensor, comprising: a photoelectric conversion circuit layer including a first photoelectric conversion element and a second photoelectric conversion element on a first semiconductor substrate; a pixel circuit layer, which includes a second semiconductor substrate and is on the photoelectric conversion circuit layer; as well as a logic circuit layer, which is on the pixel circuit layer and includes a logic circuit on the third semiconductor substrate, Wherein, the photoelectric conversion circuit layer comprises: a dual conversion gain transistor on the first semiconductor substrate and connected between the first floating diffusion and the third floating diffusion; a source follower transistor on the first semiconductor substrate and connected to the first floating diffusion; a first transfer gate electrode between the first photoelectric conversion element and the first floating diffusion; and a second transfer gate electrode between the second photoelectric conversion element and the second floating diffusion, Wherein, the pixel circuit layer comprises: a reset transistor on the second semiconductor substrate and connected to the third floating diffusion; a first switching transistor on the second semiconductor substrate and connected to the dual conversion gain transistor; and a second switching transistor on the second semiconductor substrate and connected to the second floating diffusion, Wherein, the width of the second photoelectric conversion element is smaller than the width of the first photoelectric conversion element.

15. The image sensor of claim 14, further comprising a capacitor between the second switch transistor and a pixel supply voltage.

16. The image sensor of claim 14, further comprising: a first capacitor in a first interlayer dielectric layer on the first semiconductor substrate; as well as a second capacitor in a second interlayer dielectric layer on the second semiconductor substrate, Wherein, the first capacitor and the second capacitor are connected in parallel with each other.

17. The image sensor of claim 14, wherein The photoelectric conversion circuit layer includes a plurality of first bonding pads connected to the first transfer gate electrode and the second transfer gate electrode, and The pixel circuit layer includes a plurality of second bonding pads contacting the plurality of first bonding pads.

18. An image sensor, comprising: a photoelectric conversion circuit layer including a first photoelectric conversion element and a second photoelectric conversion element on a first semiconductor substrate; a pixel circuit layer, which includes a second semiconductor substrate and is on the photoelectric conversion circuit layer; as well as a logic circuit layer, which is on the pixel circuit layer and includes a logic circuit on the third semiconductor substrate, Wherein, the photoelectric conversion circuit layer comprises: a first transfer gate electrode between the first photoelectric conversion element and a first floating diffusion; and a second transfer gate electrode between the second photoelectric conversion element and the second floating diffusion, Wherein, the pixel circuit layer comprises: a dual conversion gain transistor on the second semiconductor substrate and connected between the first floating diffusion and a third floating diffusion; a source follower transistor on the second semiconductor substrate; a reset transistor on the second semiconductor substrate and connected to the third floating diffusion; a first switch transistor on the second semiconductor substrate and connected to the dual conversion gain transistor; a second switch transistor on the second semiconductor substrate and connected to the second floating diffusion; and a third switch transistor on the second semiconductor substrate and connected to the source follower transistor and the first floating diffusion, Wherein, the width of the second photoelectric conversion element is smaller than the width of the first photoelectric conversion element.

19. The image sensor of claim 18, further comprising: a first capacitor in a first interlayer dielectric layer on the first semiconductor substrate; as well as a second capacitor in a second interlayer dielectric layer on the second semiconductor substrate, Wherein, the first capacitor and the second capacitor are connected in parallel with each other.

20. The image sensor of claim 18, wherein: The photoelectric conversion circuit layer includes a plurality of first bonding pads connected to the first transfer gate electrode and the second transfer gate electrode, and The pixel circuit layer includes a plurality of second bonding pads contacting the plurality of first bonding pads.

Images