Display device

Abstract

Provided herein may be a display device including: a display panel including sub-pixels and a light sensor configured to generate a sensing signal corresponding to an amount of received light; and a display panel driver configured to drive the display panel, and the light sensor includes: a first sensing transistor configured to generate a sensing signal, and including a back gate electrode configured to receive a sensing gate signal; a second sensing transistor configured to provide a sensing signal to the readout line in response to a sensing gate signal; and a light receiving element connected to a control node of the first sensing transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0116308 filed in the Korean Intellectual Property Office on September 1, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Various embodiments of the present disclosure relate to a display device including a light sensor and an electronic device including the display device. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has been highlighted. Due to the importance of display devices, the use of various types of devices such as liquid crystal display devices and organic light emitting display devices has increased. The display device may use a light sensor to sense a user's fingerprint and perform a user authentication function. Summary of the invention

[0005] Various embodiments of the present disclosure are directed to a display device including a light sensor having improved performance.

[0006] Various embodiments of the present disclosure are directed to an electronic device including a display device.

[0007] One or more embodiments of the present disclosure may provide a display device, comprising: a display panel including sub-pixels and a light sensor configured to generate a sensing signal corresponding to the amount of received light; and a display panel driver configured to drive the display panel, and the light sensor comprises: a first sensing transistor configured to generate the sensing signal and including a back gate electrode configured to receive a sensing gate signal; a second sensing transistor configured to provide the sensing signal to a readout line in response to the sensing gate signal; and a light receiving element connected to a control node of the first sensing transistor.

[0008] The first sensing transistor may be configured to receive a common voltage having a negative value, wherein the second sensing transistor includes a P-channel metal oxide semiconductor (PMOS) transistor.

[0009] One frame may include a sensing-on period in which the sensing gate signal has an enable level and a sensing-off period in which the sensing gate signal has a disable level.

[0010] The first sensing transistor and the second sensing transistor may include P-channel metal oxide semiconductor (PMOS) transistors.

[0011] The sub-pixel may include a light emitting element configured to be initialized by an anode initialization voltage, wherein the first sensing transistor is configured to receive the anode initialization voltage.

[0012] The second sensing transistor may include a back gate electrode configured to receive a sensing gate signal.

[0013] The light sensor may further include a third sensing transistor configured to initialize a control node of the first sensing transistor in response to a reset signal.

[0014] The reset signal may have an enable period within a sensing off period in which the sensing gate signal has a disable level.

[0015] The first sensing transistor may receive a common voltage, wherein the third sensing transistor receives a reset voltage that is less than the common voltage.

[0016] The first sensing transistor may further include a control electrode, a first electrode, and a second electrode, wherein the control electrode is connected to the first sensing node and the first electrode is configured to receive a common voltage, wherein the second sensing transistor includes a control electrode configured to receive a sensing gate signal, a first electrode connected to the second electrode of the first sensing transistor, and a second electrode connected to a readout line, and wherein the light receiving element includes a first electrode connected to the first sensing node and a second electrode configured to receive a bias voltage.

[0017] One or more embodiments of the present disclosure may provide a display device, comprising: a display panel including sub-pixels and a light sensor configured to generate a sensing signal corresponding to the amount of received light; and a display panel driver configured to drive the display panel, and the light sensor comprises: a first sensing transistor configured to generate the sensing signal; a second sensing transistor configured to provide the sensing signal to a readout line in response to a sensing gate signal and comprising a back gate electrode configured to receive the sensing gate signal; and a light receiving element connected to a control node of the first sensing transistor.

[0018] The first sensing transistor may be configured to receive a common voltage having a negative value, wherein the second sensing transistor includes a P-channel metal oxide semiconductor (PMOS) transistor.

[0019] One frame may include a sensing-on period in which the sensing gate signal has an enable level and a sensing-off period in which the sensing gate signal has a disable level.

[0020] The first sensing transistor and the second sensing transistor may include P-channel metal oxide semiconductor (PMOS) transistors.

[0021] The sub-pixel may include a light emitting element configured to be initialized by an anode initialization voltage, wherein the first sensing transistor is configured to receive the anode initialization voltage.

[0022] The light sensor may further include a third sensing transistor configured to initialize a control node of the first sensing transistor in response to a reset signal.

[0023] The reset signal may have an enable period within a sensing off period in which the sensing gate signal has a disable level.

[0024] The first sensing transistor may be configured to receive a common voltage, wherein the third sensing transistor is configured to receive a reset voltage that is less than the common voltage.

[0025] The first sensing transistor may further include a control electrode, a first electrode, and a second electrode, wherein the control electrode is connected to the first sensing node and the first electrode is configured to receive a common voltage, wherein the second sensing transistor includes a control electrode configured to receive a sensing gate signal, a first electrode connected to the second electrode of the first sensing transistor, and a second electrode connected to a readout line, wherein the light receiving element includes a first electrode connected to the first sensing node and a second electrode configured to receive a bias voltage.

[0026] One or more embodiments of the present disclosure may provide an electronic device, comprising: a processor configured to provide input image information; a power supply configured to provide power; and a display device configured to receive power and display an image based on input image data, and comprising a display driver and a display panel configured to be driven by the display panel driver, and the display panel comprises sub-pixels and a light sensor configured to generate a sensing signal corresponding to the amount of received light, and the light sensor comprises: a first sensing transistor configured to generate a sensing signal, and comprising a back gate electrode configured to receive a sensing gate signal; a second sensing transistor configured to provide a sensing signal to a readout line in response to the sensing gate signal; and a light receiving element connected to a control node of the first sensing transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It is shown Figure 1 A circuit diagram of an example of a sub-pixel of a display device.

[0029] Figure 3 It is shown Figure 1 A circuit diagram of an example of a light sensor of a display device.

[0030] Figure 4 Is shown driving Figure 1 A timing diagram of an example of a light sensor in a display device.

[0031] Figure 5 It is shown in Figure 3 FIG. 1 is a graph of an example of a voltage-current relationship within a sensing-off period of a first sensing transistor.

[0032] Figure 6 It is shown in Figure 3 FIG. 1 is a graph of an example of a voltage-current relationship within a sensing on-period of a first sensing transistor.

[0033] Figure 7 is a circuit diagram showing a light sensor of a display device according to an embodiment of the present disclosure.

[0034] Figure 8 is a circuit diagram showing a light sensor of a display device according to an embodiment of the present disclosure.

[0035] Fig. 9 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0036] Fig.10 It is shown Fig. 9 A schematic diagram of an example in which the electronic device is implemented as a smart phone.

[0037] Fig.11 It is shown Fig. 9 A schematic diagram of an example in which the electronic device is implemented as a tablet PC. DETAILED DESCRIPTION

[0038] Aspects of some embodiments of the present disclosure and methods for completing them can be more easily understood by referring to the detailed description and drawings of the embodiments. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and aspects of the present disclosure will be fully conveyed to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments or unnecessary processes, elements and techniques for a complete understanding of aspects of the present disclosure by those of ordinary skill in the art can be omitted. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals, symbols and combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0039] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments described herein. The use of "can", "may" or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure covers all modifications, equivalents and substitutions within the thought and technical scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in its entirety, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another or may be implemented together in association.

[0040] It will be understood that when an element, layer, region, or component is referred to as being "formed" "on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to another element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to another element, layer, region, or component, so that there may be one or more intervening elements, layers, regions, or components. Furthermore, this may collectively mean a direct or indirect coupling or a direct or indirect connection as well as an integral or non-integral coupling or an integral or non-integral connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, capacitors, and / or the like. When describing embodiments, unless explicitly described as being directly connected, a connected statement means an electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component, or is on another component, without intervening components.

[0041] For the purposes of this disclosure, when following a list of elements, expressions such as "at least one of" or "any one of" or "one or more of" modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the related listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, when following a list of elements, expressions such as "at least one of", "multiple of", "one of", and other postpositional phrases modify the entire list of elements and do not modify the individual elements in the list.

[0042] It will be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or advantage, and are only used to distinguish an element, member, component, region, area, layer, part or part from another element, member, component, region, area, layer, part or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first part described below can be referred to as the second element, second component, second area, second layer or second part. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish between elements of different categories or groups. For the sake of brevity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0043] The terms used herein are only used for the purpose of describing the embodiments, and are not intended to limit the present disclosure. As used herein, the singular forms "one" and "an" are intended to also include the plural forms, and the plural forms are also intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises", "comprising", "have", "having", "includes" and "including" specify the stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0044] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for inherent deviations in measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. In view of the measurement discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms "approximately" or "approximately" as used herein include the values ​​and mean within an acceptable deviation range of a particular value as determined by those of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, "may" used in describing embodiments of the present disclosure refers to one or more embodiments of the present disclosure.

[0045] In some embodiments, known structures and devices may be described in conjunction with one or more functional blocks (e.g., block diagrams), units and / or modules in the accompanying drawings to avoid unnecessary confusion of various embodiments. It will be appreciated by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, single components, microprocessors, hard-wired circuits, memory elements, line connectors and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein, and can be selectively driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors or related circuits) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, without departing from the scope of the present disclosure, blocks, units and / or modules may be physically separated into two or more interacting separate blocks, units and / or modules. Furthermore, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0047] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0048] refer to Figure 1 , the display device may include a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200, a gate driver 300, a data driver 400, an emission driver 500, a readout circuit 600, and a reset driver 700. In one or more embodiments, the drive controller 200 and the data driver 400 may be integrated into a single chip.

[0049] The display panel 100 may include a display area DA formed to display an image and a non-display area NDA located adjacent to the display area DA. In one or more embodiments, the gate driver 300 and the emission driver 500 may be installed in the non-display area NDA.

[0050] The display panel 100 may include a plurality of pixel gate lines PGL, a plurality of data lines DL, and a plurality of emission lines EL, and a plurality of sub-pixels SP electrically connected to the pixel gate lines PGL, the data lines DL, and the emission lines EL. The pixel gate lines PGL and the emission lines EL may extend in a first direction D1. The data lines DL may extend in a second direction D2 that intersects or crosses the first direction D1.

[0051] The display panel 100 may include a plurality of sensing gate lines SGL, a plurality of reset lines RSL, a plurality of readout lines RL, and a plurality of light sensors LS electrically connected to the sensing gate lines SGL, the reset lines RSL, and the readout lines RL.

[0052] In the present embodiment, the sensing gate line SGL is shown to be connected to the gate driver 300, but the present disclosure is not limited thereto. For example, the display panel driver may include an independent driver configured to drive the sensing gate line SGL.

[0053] In this embodiment, the reset line RSL is shown as being connected to the reset driver 700, but the present disclosure is not limited thereto. For example, the reset line RSL may be driven by the gate driver 300, the emission driver 500, or an independent driver configured to drive the sensing gate line SGL, instead of the reset driver 700.

[0054] The drive controller 200 may receive input image data IMG and an input control signal CONT from a processor (e.g., a graphics processing unit (GPU)). For example, the input image data IMG may include red image data, green image data, and blue image data. In one or more embodiments, the input image data IMG may also include white image data. In another example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may include a vertical synchronization signal and a horizontal synchronization signal.

[0055] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , a fifth control signal CONT5 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0056] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and may output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 includes a vertical start signal and a gate clock signal.

[0057] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 400 based on the input control signal CONT, and may output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0058] The driving controller 200 may receive input image data IMG and an input control signal CONT and may generate a data signal DATA. The driving controller 200 may output the data signal DATA to the data driver 400.

[0059] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the emission driver 500 based on the input control signal CONT, and may output the third control signal CONT3 to the emission driver 500. The third control signal CONT3 may include a vertical start signal and an emission clock signal.

[0060] The driving controller 200 may generate a fourth control signal CONT4 for controlling the operation of the readout circuit 600 based on the input control signal CONT, and may output the fourth control signal CONT4 to the readout circuit 600 .

[0061] The driving controller 200 may generate a fifth control signal CONT5 for controlling the operation of the reset driver 700 based on the input control signal CONT, and may output the fifth control signal CONT5 to the reset driver 700 .

[0062] The gate driver 300 may generate a gate signal for driving the pixel gate line PGL and the sensing gate line SGL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the pixel gate line PGL and the sensing gate line SGL. For example, the gate driver 300 may output the gate signal to the pixel gate line PGL and the sensing gate line SGL in sequence.

[0063] The data driver 400 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200. The data driver 400 may generate a data voltage by converting the data signal DATA into an analog voltage. The data driver 400 may output the data voltage to the data line DL.

[0064] The emission driver 500 may generate an emission signal for driving the emission line EL in response to the third control signal CONT3 received from the driving controller 200. The emission driver 500 may output the emission signal to the emission line EL. For example, the emission driver 500 may output the emission signal to the emission line EL in sequence.

[0065] The readout circuit 600 may generate sensing information based on the sensing signal received from the readout line RL in response to the fourth control signal CONT4 received from the drive controller 200. For example, the sensing information may correspond to a fingerprint image. The processor or the drive controller 200 may use the sensing information provided from the readout circuit 600 to perform a user identity authentication function.

[0066] The reset driver 700 may provide a reset signal to the reset line RSL in response to the fifth control signal CONT5 received from the driving controller 200. In one or more embodiments, the reset driver 700 may be commonly connected to all of the light sensors LS through the reset line RSL. In one or more other embodiments, the reset driver 700 may be connected to the respective light sensors LS through a plurality of reset lines RSL.

[0067] The sub-pixel SP may include a light emitting element. The light emitting element may be a light emitting diode. The light emitting element may be formed of an organic light emitting diode, an inorganic light emitting diode, a quantum dot / well light emitting diode, etc. The light emitting element may emit light in any one of the first color, the second color, and the third color.

[0068] The light sensor LS may include a light receiving element. In one or more embodiments, the light receiving element may be a photodiode. In one or more other embodiments, the light receiving element may be formed of a phototransistor.

[0069] The light emitted from the light emitting element may be reflected by the user's fingerprint and then may be applied to the light receiving element adjacent to the light emitting element. The light sensor LS may generate a sensing signal corresponding to the amount of light applied to the light receiving element. The processor or the drive controller 200 may distinguish between valleys and ridges of the fingerprint based on the intensity of the sensing signal, thereby obtaining a fingerprint image of the user.

[0070] Figure 2 It is shown Figure 1 A circuit diagram of an example of a sub-pixel of a display device.

[0071] refer to Figure 2 The subpixel SP may include a first pixel transistor TP1 (eg, a driving transistor), a second pixel transistor TP2, a third pixel transistor TP3, a fourth pixel transistor TP4, a fifth pixel transistor TP5, a sixth pixel transistor TP6, a seventh pixel transistor TP7, a storage capacitor CST, and a light emitting element EE.

[0072] The first pixel transistor TP1 may include a control electrode connected to the first pixel node PN1 , a first electrode connected to the second pixel node PN2 , and a second electrode connected to the third pixel node PN3 .

[0073] The second pixel transistor TP2 may include a control electrode configured to receive the write gate signal GW, a first electrode configured to receive the data voltage VDATA, and a second electrode connected to the second pixel node PN2.

[0074] The third pixel transistor TP3 may include a control electrode configured to receive the write gate signal GW, a first electrode connected to the third pixel node PN3 , and a second electrode connected to the first pixel node PN1 .

[0075] The fourth pixel transistor TP4 may include a control electrode configured to receive the initialization gate signal GI, a first electrode configured to receive the first initialization voltage VINT, and a second electrode connected to the first pixel node PN1.

[0076] The fifth pixel transistor TP5 may include a control electrode configured to receive the emission signal EM, a first electrode configured to receive a first power voltage ELVDD (eg, a high power voltage), and a second electrode connected to the second pixel node PN2 .

[0077] The sixth pixel transistor TP6 may include a control electrode configured to receive the emission signal EM, a first electrode connected to the third pixel node PN3 , and a second electrode connected to the fourth pixel node PN4 .

[0078] The seventh pixel transistor TP7 may include a control electrode configured to receive a bias gate signal GB (or a write gate signal GW(n+1) of a subsequent pixel row), a first electrode configured to receive a second initialization voltage VAINT (e.g., an anode initialization voltage), and a second electrode connected to a fourth pixel node PN4.

[0079] The storage capacitor CST may include a first electrode configured to receive the first power voltage ELVDD and a second electrode connected to the first pixel node PN1 .

[0080] The light emitting element EE may include a first electrode (eg, an anode electrode) connected to the fourth pixel node PN4 and a second electrode (eg, a cathode electrode) configured to receive a second power voltage ELVSS (eg, a low power voltage).

[0081] However, the structure of the sub-pixel SP according to the present disclosure is not limited to the aforementioned structure. For example, each of the sub-pixels SP may have a 3T1C structure including three transistors and one capacitor, a 5T2C structure including five transistors and two capacitors, a 7T1C structure including seven transistors and one capacitor, a 9T1C structure including nine transistors and one capacitor, etc.

[0082] One or more of the first pixel transistor TP1, the second pixel transistor TP2, the third pixel transistor TP3, the fourth pixel transistor TP4, the fifth pixel transistor TP5, the sixth pixel transistor TP6, and the seventh pixel transistor TP7 can be implemented using a P-channel metal oxide semiconductor (PMOS) transistor. In this case, the low voltage level can be an enable level, and the high voltage level can be a disable level. For example, if the signal applied to the control electrode of the PMOS transistor has a low voltage level, the PMOS transistor can be turned on. For example, if the signal applied to the control electrode of the PMOS transistor has a high voltage level, the PMOS transistor can be turned off.

[0083] However, the present disclosure is not limited to the aforementioned examples. For example, one or more of the first pixel transistor TP1, the second pixel transistor TP2, the third pixel transistor TP3, the fourth pixel transistor TP4, the fifth pixel transistor TP5, the sixth pixel transistor TP6, and the seventh pixel transistor TP7 can be implemented using an N-channel metal oxide semiconductor (NMOS) transistor. In this case, the low voltage level can be a disable level, and the high voltage level can be an enable level. For example, if the signal applied to the control electrode of the NMOS transistor has a low voltage level, the NMOS transistor can be turned off. For example, if the signal applied to the control electrode of the NMOS transistor has a high voltage level, the NMOS transistor can be turned on. In other words, the enable level and the disable level can be determined based on the type of transistor.

[0084] For example, during the initialization period, the initialization gate signal GI may have an enable level, and the fourth pixel transistor TP4 may be turned on. Therefore, the first initialization voltage VINT may be applied to the first pixel node PN1. In other words, the control electrode of the first pixel transistor TP1 (e.g., the second electrode of the storage capacitor CST) may be initialized.

[0085] For example, in the data writing period, the write gate signal GW has an enable level so that the second pixel transistor TP2 and the third pixel transistor TP3 may be turned on. Therefore, the data voltage VDATA may be applied to the storage capacitor CST.

[0086] For example, in the anode initialization period, the bias gate signal GB may have an enable level, and the seventh pixel transistor TP7 may be turned on. Therefore, the second initialization voltage VAINT may be applied to the first electrode (eg, the anode electrode) of the light emitting element EE.

[0087] For example, during the emission period, the emission signal EM has an enable level, so that the fifth pixel transistor TP5 and the sixth pixel transistor TP6 can be turned on, and therefore, the first power supply voltage ELVDD is applied to the first pixel transistor TP1, so that a driving current can be generated. The driving current can be applied to the light emitting element EE. In other words, the light emitting element EE can emit light with a brightness corresponding to the driving current.

[0088] Figure 3 It is shown Figure 1 A circuit diagram of an example of a light sensor of a display device. Figure 4 Is shown driving Figure 1 A timing diagram of an example of a light sensor in a display device.

[0089] refer to Figure 3 , the light sensor LS may include a first sensing transistor TS1 configured to generate a sensing signal and including a back gate electrode for receiving a sensing gate signal GS, a second sensing transistor TS2 configured to provide the sensing signal to a readout line RL in response to the sensing gate signal GS, and a light receiving element OPD connected to a control node of the first sensing transistor TS1. The light sensor LS may further include a third sensing transistor TS3 configured to initialize the control node of the first sensing transistor TS1 in response to a reset signal RS. For example, the sensing signal may be a current generated by the first sensing transistor TS1.

[0090] For example, the first sensing transistor TS1 may further include a control electrode connected to the first sensing node SN1 , a first electrode configured to receive the common voltage VCOM, and a second electrode connected to the first electrode of the second sensing transistor TS2 .

[0091] The second sensing transistor TS2 may include a control electrode configured to receive the sensing gate signal GS, a first electrode connected to the second electrode of the first sensing transistor TS1 , and a second electrode connected to the readout line RL.

[0092] The light receiving element OPD may include a first electrode connected to the first sensing node SN1 and a second electrode configured to receive a bias voltage VBIAS.

[0093] The third sensing transistor TS3 may include a control electrode configured to receive the reset signal RS, a first electrode configured to receive the reset voltage VRST, and a second electrode connected to the first sensing node SN1.

[0094] In one or more embodiments, the first sensing transistor TS1 and / or the second sensing transistor TS2 may be implemented using a PMOS transistor. The third sensing transistor TS3 may be implemented as an NMOS transistor. However, the present disclosure is not limited to the foregoing examples.

[0095] refer to Figure 3 and Figure 4 , one frame FR may include a sensing on period ONP in which the sensing gate signal GS has an enable level and a sensing off period OFFP in which the sensing gate signal GS has a disable level. Figure 3 As shown in , in the case where the second sensing transistor TS2 is a PMOS transistor, the enable level of the sensing gate signal GS may be a low voltage level, and the disable level of the sensing gate signal GS may be a high voltage level.

[0096] The reset signal RS may have an enable period (e.g., reset period RSP) within the sensing cut-off period OFFP in which the sensing gate signal GS has a disable level. In addition, the reset signal RS may have a disable period (e.g., light receiving period LRP) within the sensing cut-off period OFFP. Here, the enable period may be a period having an enable level, and the disable period may be a period having a disable level.

[0097] For example, Figure 3 As shown in , in the case where the third sensing transistor TS3 is an NMOS transistor, the enable level of the reset signal RS may be a high voltage level, and the disable level of the reset signal RS may be a low voltage level.

[0098] Although a case where the reset period RSP is located at the beginning of the sensing off period OFFP is illustrated, the present disclosure is not limited thereto.

[0099] For example, during the reset period RSP, the reset signal RS may have an enable level, and the sensing gate signal GS may have a disable level. Therefore, the third sensing transistor TS3 may be turned on, and the second sensing transistor TS2 may be turned off. The reset voltage VRST may be applied to the first sensing node SN1. In other words, the first sensing node SN1 and the first electrode of the light receiving element OPD may be initialized.

[0100] For example, within the light receiving period LRP, each of the reset signal RS and the sensing gate signal GS may have a disable level. Therefore, the second sensing transistor TS2 and the third sensing transistor TS3 may be turned off. When light is applied to the light receiving element OPD, the light receiving element OPD may generate a current toward the first sensing node SN1, and the voltage of the first sensing node SN1 may be reduced. Therefore, the size of the sensing signal generated in the sensing on period ONP to be described below may vary. In addition, since the amount of light applied to the light receiving element OPD varies according to the valleys and ridges of the fingerprint, the size of the sensing signal may vary according to the valleys and ridges of the fingerprint.

[0101] For example, during the sensing on period ONP, the reset signal RS may have a disable level, and the sensing gate signal GS may have an enable level. Therefore, the second sensing transistor TS2 may be turned on, and the third sensing transistor TS3 may be turned off. The first sensing transistor TS1 may generate a sensing signal corresponding to the gate-source voltage. The sensing signal may be applied to the readout circuit 600 through the readout line RL.

[0102] refer to Figure 2 and Figure 3 In one or more embodiments, the common voltage VCOM may be a second initialization voltage VAINT. For example, the common voltage VCOM and the second initialization voltage VAINT may be approximately -3.5V.

[0103] In one or more embodiments, the reset voltage VRST may be lower than the common voltage VCOM. For example, the common voltage VCOM may be approximately -3.5V, and the reset voltage VRST may be approximately -4.5V.

[0104] In one or more embodiments, the bias voltage VBIAS may be the second power supply voltage ELVSS. For example, the bias voltage VBIAS and the second power supply voltage ELVSS may be approximately -2.5V.

[0105] Figure 5 It is shown in Figure 3 FIG. 1 is a graph of an example of a voltage-current relationship within a sensing-off period of a first sensing transistor.

[0106] exist Figure 5 , the horizontal axis represents the gate-source voltage VGS of the first sensing transistor TS1 , and the vertical axis represents the current ID generated by the first sensing transistor TS1 .

[0107] refer to Figures 3 to 5 , the first sensing transistor TS1 may include a back gate electrode configured to receive the sensing gate signal GS. The first sensing transistor TS1 may receive a common voltage VCOM having a negative value.

[0108] During the sensing off period OFFP, the sensing gate signal GS may have a high voltage level, and a voltage of the high voltage level may be applied to the back gate electrode of the first sensing transistor TS1. In this case, the body-source voltage of the first sensing transistor TS1 may increase. Figure 5 As shown in , the voltage-current relationship may be shifted in a negative direction (eg, due to a body effect). Since the voltage-current relationship may be shifted in a negative direction, the leakage current of the first sensing transistor TS1 may be reduced.

[0109] Figure 6 It is shown in Figure 3FIG. 1 is a graph of an example of a voltage-current relationship within a sensing on-period of a first sensing transistor.

[0110] exist Figure 6 , the horizontal axis represents the gate-source voltage VGS of the first sensing transistor TS1 , and the vertical axis represents the current ID generated by the first sensing transistor TS1 .

[0111] refer to Figure 3 , Figure 4 and Figure 6 , the first sensing transistor TS1 may include a back gate electrode configured to receive the sensing gate signal GS. The first sensing transistor TS1 may receive a common voltage VCOM having a negative value.

[0112] During the sensing on period ONP, the sensing gate signal GS may have a low voltage level, and a voltage of the low voltage level may be applied to the back gate electrode of the first sensing transistor TS1. In this case, the body-source voltage of the first sensing transistor TS1 may be reduced. Figure 6 As shown in , the voltage-current relationship may be shifted in a positive direction (eg, due to a body effect). Since the voltage-current relationship is shifted in a positive direction, the magnitude of the sense signal (eg, the current generated from the first sense transistor TS1) may increase.

[0113] Figure 7 is a circuit diagram showing a light sensor of a display device according to an embodiment of the present disclosure.

[0114] In addition to the back gate electrode of the second sensing transistor TS2 and the first sensing transistor TS1, according to Figure 7 The light sensor LS of the corresponding embodiment may have Figure 3 The light sensor LS has substantially the same configuration. Therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant explanations thereof will be omitted.

[0115] refer to Figure 4 and Figure 7 , the second sensing transistor TS2 may further include a back gate electrode configured to receive the sensing gate signal GS.

[0116] During the sensing off period OFFP, the sensing gate signal GS may have a high voltage level, and a voltage of the high voltage level may be applied to the back gate electrode of the second sensing transistor TS2. In this case, the body-source voltage of the second sensing transistor TS2 may increase. Figure 5 As shown in , the voltage-current relationship of the second sensing transistor TS2 can be shifted in the negative direction. Since the voltage-current relationship can be shifted in the negative direction, the leakage current of the second sensing transistor TS2 can be reduced.

[0117] In the sensing on period ONP, the sensing gate signal GS may have a low voltage level, and a voltage of the low voltage level may be applied to the back gate electrode of the second sensing transistor TS2. In this case, the body-source voltage of the second sensing transistor TS2 may be relatively reduced compared to that in the sensing off period OFFP. Figure 6 As shown in , the voltage-current relationship of the second sensing transistor TS2 may be shifted in the positive direction. Since the voltage-current relationship is shifted in the positive direction, the magnitude of the sensing signal transmitted to the readout line RL may be increased.

[0118] Figure 8 is a circuit diagram showing a light sensor of a display device according to an embodiment of the present disclosure.

[0119] In addition to the back gate electrode of the second sensing transistor TS2, according to Figure 8 The light sensor LS of the corresponding embodiment may have Figure 3 The light sensor LS has substantially the same configuration. Therefore, the same or similar components are denoted by the same reference numerals and symbols, and redundant explanations thereof will be omitted.

[0120] refer to Figure 4 and Figure 8 , each of the first sensing transistor TS1 and the second sensing transistor TS2 may further include a back gate electrode configured to receive the sensing gate signal GS. Therefore, the leakage current of the first sensing transistor TS1 and the second sensing transistor TS2 may be reduced, and the magnitude of the sensing signal may be increased. Figures 3 to 7 A detailed description related thereto is provided. Therefore, redundant explanation will be omitted.

[0121] Fig. 9 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Fig.10 It is shown Fig. 9 A schematic diagram of an example in which the electronic device is implemented as a smart phone. Fig.11 It is shown Fig. 9 A schematic diagram of an example in which the electronic device is implemented as a tablet PC.

[0122] refer to Figures 9 to 11 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 The electronic device 1000 may also include various ports for communicating with a graphics card, a sound card, a memory card, a USB device, or other systems. In one or more embodiments, as Fig.10 As shown in , the electronic device 1000 may be implemented as a smart phone. In one or more embodiments, as Fig.11 As shown in , the electronic device 1000 can be implemented as a tablet PC. However, the foregoing examples are illustrative, and the electronic device 1000 is not limited to the foregoing examples. For example, the electronic device 1000 can be implemented as a mobile phone, a video phone, a smart tablet, a smart watch, a navigation device for a vehicle, a computer monitor, a laptop computer, a head-mounted display device, etc.

[0123] The processor 1010 may perform specific calculations or tasks. In one or more implementations, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 may be connected to other components via an address bus, a control bus, a data bus, etc. In one or more implementations, the processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0124] The memory device 1020 may store data required to perform operations of the electronic device 1000. For example, the memory device 1020 may include a nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.

[0125] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.

[0126] The I / O device 1040 may include input devices such as a keyboard, a keypad, a touch pad, a touch screen, and a mouse, and output devices such as a speaker and a printer. In one or more implementations, the display device 1060 may be included in the I / O device 1040 .

[0127] The power supply 1050 may provide power required to perform operations of the electronic device 1000. For example, the power supply 1050 may be a power management integrated circuit (PMIC).

[0128] The display device 1060 may display an image corresponding to the visual information of the electronic device 1000. Here, the display device 1060 may be an organic light emitting display device or a quantum dot light emitting display device, but is not limited thereto. The display device 1060 may be connected to other components via a bus or other communication links.

[0129] The present disclosure can be applied to display devices and electronic devices including display devices. For example, the present disclosure can be applied to digital TVs, 3D TVs, mobile phones, smart phones, tablet computers, VR devices, PCs, home appliances, laptop computers, PDAs, portable media players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0130] In the optical sensor according to the embodiment of the present disclosure, a sensing gate signal may be applied to the back gate electrode of the first sensing transistor and / or the second sensing transistor, thereby reducing leakage current caused by the sensing transistor. Therefore, the signal-to-noise ratio (SNR) of the optical sensor may be improved.

[0131] In the optical sensor according to the embodiment of the present disclosure, a sensing gate signal may be applied to the back gate electrode of the first sensing transistor and / or the second sensing transistor, thereby increasing the magnitude of the sensing signal. Therefore, the signal-to-noise ratio (SNR) of the optical sensor may be improved.

[0132] However, aspects of the present disclosure are not limited to the above-mentioned aspects, and various modifications are possible without departing from the spirit and scope of the present disclosure.

[0133] While embodiments are described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure as claimed in the accompanying claims and their functional equivalents which should be included therein.

Claims

1. A display device, comprising: Display panel, including: sub-pixels; and A light sensor configured to generate a sensing signal corresponding to an amount of received light, and comprising: a first sensing transistor configured to generate the sensing signal and comprising a back gate electrode configured to receive a sensing gate signal; a second sensing transistor configured to provide the sensing signal to a readout line in response to the sensing gate signal; and a light receiving element connected to a control node of the first sensing transistor; and The display panel driver is configured to drive the display panel.

2. The display device according to claim 1, wherein: The first sensing transistor is configured to receive a common voltage having a negative value, and The second sensing transistor includes a P-channel metal oxide semiconductor transistor.

3. The display device according to claim 1, wherein: One frame includes a sensing-on period in which the sensing gate signal has an enable level and a sensing-off period in which the sensing gate signal has a disable level.

4. The display device according to claim 1, wherein: The first sensing transistor and the second sensing transistor include P-channel metal oxide semiconductor transistors.

5. The display device according to claim 1, wherein: The sub-pixel includes a light emitting element configured to be initialized by an anode initialization voltage, and The first sensing transistor is configured to receive the anode initialization voltage.

6. The display device according to claim 1, wherein: The second sensing transistor includes a back gate electrode configured to receive the sensing gate signal.

7. The display device according to claim 1, wherein: The light sensor also includes a third sensing transistor configured to initialize the control node of the first sensing transistor in response to a reset signal.

8. The display device according to claim 7, wherein: The reset signal has an enable period within a sensing off period in which the sensing gate signal has a disable level.

9. The display device according to claim 7, wherein: The first sensing transistor receives a common voltage, and The third sensing transistor receives a reset voltage that is smaller than the common voltage.

10. The display device according to claim 1, wherein: The first sensing transistor further includes a control electrode, a first electrode, and a second electrode, wherein the control electrode is connected to the first sensing node, and the first electrode is configured to receive a common voltage. wherein the second sensing transistor comprises a control electrode configured to receive the sensing gate signal, a first electrode connected to the second electrode of the first sensing transistor, and a second electrode connected to the readout line, and The light receiving element includes a first electrode connected to the first sensing node and a second electrode configured to receive a bias voltage.

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