Display panel, preparation method thereof and display device

Abstract

The invention discloses a display panel and a preparation method thereof and a display device.The display panel comprises a display area and a frame area located outside the display area, the display panel comprises a substrate, a first conductive layer, an isolation material layer, a second conductive layer and a pixel limiting layer which are sequentially arranged in a stacked mode, and the first conductive layer comprises conductive wires located in the frame area; the isolation material layer comprises a connection via hole located in the frame area; the second conductive layer comprises a first connecting part located in the frame area, and the first connecting part is connected with the conductive wire through a connecting via hole; the pixel limiting layer comprises a first opening used for exposing the first connecting part, the edge of the orthographic projection of the first opening on the substrate is not overlapped with the edge of the orthographic projection of the connecting via hole on the substrate, and the slope angle of the first opening is smaller than that of the connecting via hole. The yield of the display panel provided by the invention is improved.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular, relates to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Flat display panels such as Organic Light Emitting Diode (OLED) display panels and display panels using Light Emitting Diode (LED) devices have the advantages of high image quality, power saving, thin body and wide application range. They are widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, etc., becoming the mainstream in display devices.

[0003] The display panel includes a substrate, an anode and a cathode formed on one side of the substrate and located in the display area, and a cathode ring located in the frame area. An isolation structure layer and a pixel definition layer are included between the cathode and the cathode ring. Since the total thickness of the isolation structure layer and the pixel definition layer is relatively high, the cathode is prone to failure when it is overlapped with the cathode ring in the frame area through a via that penetrates the isolation structure layer and the pixel definition layer, thereby seriously affecting the yield of the display panel. Summary of the invention

[0004] The purpose of this application is to at least solve the problem of poor yield of display panels. This purpose is achieved through the following technical solutions:

[0005] A first aspect of the present application provides a display panel, comprising a display area and a frame area outside the display area, wherein the display panel comprises:

[0006] substrate;

[0007] A first conductive layer, located on one side of the substrate, the first conductive layer comprising conductive traces located in the border area;

[0008] an isolation material layer, located on a side of the first conductive layer away from the substrate, and including a connection via located in the border area;

[0009] A second conductive layer, located on a side of the isolation material layer away from the substrate, the second conductive layer comprising a first connecting portion located in the border area, the first connecting portion being connected to the conductive trace through the connecting via;

[0010] A pixel defining layer is located on a side of the second conductive layer away from the substrate, the pixel defining layer includes a first opening for exposing the first connecting portion, an edge of the first opening projected on the substrate has no overlap with an edge of the connecting via projected on the substrate, and a slope angle of the first opening is smaller than a slope angle of the connecting via.

[0011] The display panel provided in the present application includes a substrate, a first conductive layer, an isolation material layer, a second conductive layer and a pixel defining layer, wherein the first conductive layer is used to form a conductive trace located in the border area, the second conductive layer is used to form a first connecting portion located in the border area, the isolation material layer is located between the first conductive layer and the second conductive layer, and includes a portion located between the conductive trace and the first connecting portion, the portion is formed with a connecting via, and the first connecting portion is connected to the conductive trace through the connecting via. The display panel also includes a pixel defining layer located on the side of the second conductive layer facing away from the substrate, the pixel defining layer is located on the side of the second conductive layer facing away from the substrate, and is used to define the light-emitting unit. Specifically, the pixel defining layer includes a first opening for exposing the first connecting portion, so that a subsequent film layer (such as a cathode) can be connected to the first connecting portion through the first opening. The edge of the orthographic projection of the first opening on the substrate does not overlap with the edge of the orthographic projection of the connecting via on the substrate, that is, the edge of the orthographic projection of the first opening on the substrate is located on the inner side or outer side of the edge of the orthographic projection of the connecting via on the substrate, so that a step is formed between the sidewall of the first opening and the sidewall of the connecting via, or the pixel defining layer extends into the connecting via, and the pixel defining layer forms a step when it transitions from the side of the isolation material layer away from the substrate to the connecting via. The existence of the step can avoid the sidewall of the first opening and the sidewall of the connecting via being connected and smoothly transitioning to form a large step difference at the position where the first opening and the connecting via are connected, thereby reducing the climbing difficulty of the subsequent film layer at the first opening and the connecting via, improving the yield of the subsequent film layer, and reducing the probability of the product failing to display, increasing the series resistance, and increasing the power consumption due to the poor yield of the subsequent film layer. The increase in the series resistance is likely to cause the problem of excessively high voltage or increased power consumption of the product at low grayscale. Specifically, the climbing difficulty of the cathode in the frame area can be reduced, thereby helping to improve the yield of the cathode and the overlap yield of the cathode and the first adapter.

[0012] In some embodiments of the present application, the edge of the first opening projected onto the substrate is located on the inner side of the edge of the connecting via projected onto the substrate, and the portion of the pixel defining layer located within the connecting via includes an inclined portion and a flat portion that are connected to each other, the inclined portion is located on the side wall of the connecting via, and the flat portion is located on the bottom wall of the connecting via and surrounds the first opening.

[0013] In some embodiments of the present application, the edge of the orthographic projection of the first opening on the substrate is located outside the edge of the orthographic projection of the connecting via on the substrate, the first connecting portion includes a first portion located inside the connecting via and a second portion located outside the connecting via, and the boundary of the orthographic projection of the first opening on the substrate is located between the inner boundary and the outer boundary of the orthographic projection of the second portion on the substrate.

[0014] In some embodiments of the present application, the slope angle of the first opening ranges from 20° to 50°, and / or the slope angle of the connecting via ranges from 40° to 50°.

[0015] In some embodiments of the present application, the first conductive layer further includes at least a first conductive portion and a second conductive portion located in the display area;

[0016] The isolation material layer further includes at least a first via hole and a second via hole located in the display area;

[0017] The second conductive layer also includes at least a first electrode portion and a second electrode portion located in the display area, the first electrode portion corresponds to the first conductive portion, and the first electrode portion is connected to the first conductive portion through the first via hole; the second electrode portion corresponds to the second conductive portion, and the second electrode portion is connected to the second conductive portion through the second via hole; the thickness of the isolation material layer between the first electrode portion and the first conductive portion is h1, the thickness of the isolation material layer between the second electrode portion and the second conductive portion is h2, and the thickness of the isolation material layer between the first connecting portion and the conductive trace is h3, h1>h2, h3≥h1.

[0018] In some embodiments of the present application, the pixel defining layer includes a first film layer, a second film layer, and a third film layer stacked in a direction away from the substrate, the first opening includes a first sub-opening, a second sub-opening, and a third sub-opening that are interconnected, the first sub-opening passes through the first film layer, the second sub-opening passes through the second film layer, and the third sub-opening passes through the third film layer, and the orthographic projections of the third sub-opening, the second sub-opening, and the first sub-opening on the substrate are nested in sequence from the outside to the inside.

[0019] In some embodiments of the present application, the isolation material layer includes a first isolation layer, a second isolation layer, and a third isolation layer stacked in a direction away from the substrate, the connecting via includes a first sub-via and a first through hole that are interconnected, the first sub-via penetrates the first isolation layer, the first through hole penetrates the second isolation layer and the third isolation layer, and the orthographic projection of the first sub-via on the substrate is located on the inner side of the orthographic projection of the first through hole on the substrate.

[0020] In some embodiments of the present application, the first through hole includes a second sub-via and a third sub-via, the second sub-via penetrates the second isolation layer, the third sub-via penetrates the third isolation layer, and the orthographic projections of the third sub-via, the second sub-via and the first sub-via on the substrate are nested in sequence from outside to inside.

[0021] In some embodiments of the present application, the pixel defining layer includes a second opening for exposing the first electrode portion and the second electrode portion, and the second opening includes a fourth sub-opening, a fifth sub-opening and a sixth sub-opening stacked in sequence along a direction away from the substrate, and an outer boundary of the fifth sub-opening is larger than an outer boundary of the fourth sub-opening and larger than an outer boundary of the sixth sub-opening.

[0022] In some embodiments of the present application, the pixel defining layer includes a first film layer, a second film layer, and a third film layer stacked in a direction away from the substrate, the fourth sub-opening penetrates the first film layer, the fifth sub-opening penetrates the second film layer, and the sixth sub-opening penetrates the third film layer.

[0023] In some embodiments of the present application, an organic material layer and a third conductive layer are stacked and arranged away from the second conductive layer, wherein the organic material layer includes a plurality of light-emitting layers, the light-emitting layers are located at the second opening, the third conductive layer is located at a side of the organic material layer and the pixel defining layer away from the substrate, and the third conductive layer is connected to the first connecting portion through the first opening;

[0024] The conductive traces are arranged around the display area.

[0025] In some embodiments of the present application, the material of the second conductive layer includes a transparent conductive material, the display panel also includes a first metal layer located between the second conductive layer and the isolation material layer, the first metal layer includes a first transition portion, a second transition portion and a third transition portion, the first electrode portion is connected to the first conductive portion through the first transition portion, the second electrode portion is connected to the second conductive portion through the second transition portion, and the first connection portion is connected to the conductive trace through the third transition portion.

[0026] In some embodiments of the present application, the first conductive layer also includes a third conductive portion located in the display area, the isolation material layer also includes a third via hole located in the display area, the second conductive layer also includes a third electrode portion located in the display area, the third electrode portion corresponds to the third conductive portion, the third electrode portion is connected to the third conductive portion through the third via hole, and the thickness of the isolation material layer between the third electrode portion and the third conductive portion is h4, h1>h4.

[0027] In some embodiments of the present application, the isolation material layer includes a first isolation layer, a second isolation layer, and a third isolation layer stacked in a direction away from the substrate, the first isolation layer, the second isolation layer, and the third isolation layer are arranged between the first electrode portion and the first conductive portion, the second isolation layer and the third isolation layer are arranged between the second electrode portion and the second conductive portion, the third isolation layer is arranged between the third electrode portion and the third conductive portion, and the first isolation layer, the second isolation layer, and the third isolation layer are arranged between the first connecting portion and the conductive trace.

[0028] In some embodiments of the present application, a filling portion is further provided in the same layer as the first conductive layer, and a height difference between a surface of the first conductive layer facing away from the substrate and a surface of the filling portion facing away from the substrate is less than 50 angstroms.

[0029] In some embodiments of the present application, the slope angles of the first via hole, the second via hole, and the third via hole range from 40° to 50°.

[0030] A second aspect of the present application further provides a method for preparing a display panel, wherein the display panel comprises a display area and a frame area outside the display area, and the preparation method comprises:

[0031] providing a substrate;

[0032] forming a first conductive layer on one side of the substrate, the first conductive layer comprising conductive traces located in the border area;

[0033] forming an isolation material layer on a side of the first conductive layer away from the substrate, wherein the isolation material layer includes a connection via located in the frame area;

[0034] A second conductive layer is formed on a side of the isolation material layer away from the substrate, wherein the second conductive layer includes a first connecting portion located in the border area, and the first connecting portion is connected to the conductive trace through the connecting via;

[0035] A pixel defining layer is formed on a side of the second conductive layer facing away from the substrate, the pixel defining layer includes a first opening for exposing the first connecting portion, an edge of the first opening projected onto the substrate has no overlap with an edge of the connecting via projected onto the substrate, and a slope angle of the first opening is smaller than a slope angle of the connecting via.

[0036] The third aspect of the present application further provides a display device, comprising any display panel provided in the first aspect of the present application, or comprising a display panel prepared by the preparation method provided in the second aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0038] Figure 1 is a structural schematic diagram of a display panel provided by the present application;

[0039] Figure 2 yes Figure 1 A schematic diagram of a first cross-sectional view along P-P';

[0040] Figure 3 yes Figure 1 A schematic cross-sectional view of the middle line Q-Q';

[0041] Figure 4 yes Figure 1 A schematic diagram of a second cross-sectional view along the P-P' line;

[0042] Figure 5 yes Figure 4 Enlarged view of the middle M region;

[0043] Figure 6 yes Figure 1 A schematic diagram of a third cross-sectional view along the P-P' line;

[0044] Figure 7 yes Figure 1 A schematic diagram of a fourth cross-sectional view along the P-P' line;

[0045] Figure 8 yes Figure 1 A schematic diagram of a fifth cross-sectional view along the middle line P-P';

[0046] Fig. 9 yes Figure 1 A sixth cross-sectional view schematically shown along the middle line P-P';

[0047] Fig.10 yes Figure 1 A schematic diagram of a seventh cross-sectional view along the middle line P-P';

[0048] Fig.11 yes Figure 1 A schematic diagram of an eighth cross-sectional view along the middle line P-P';

[0049] Fig.12 yes Fig.11 Enlarged view of the middle N region;

[0050] Fig.13 yes Figure 1A schematic diagram of a ninth cross-sectional view along the middle line P-P';

[0051] Fig.14 yes Figure 1 a schematic diagram of a tenth cross-sectional view along the middle line P-P';

[0052] Fig.15 is a flow chart of a method for preparing a display panel provided in the present application;

[0053] Figures 16 to 31 It is a schematic diagram of film layer changes in a method for preparing a display panel provided in the present application;

[0054] Fig.32 It is a structural schematic diagram of a display device provided by the present application.

[0055] The reference numerals are as follows:

[0056] 1. Display panel; AA, display area; B1, frame area; B2, cutting path area; 11, substrate; 110, substrate; 111, driving circuit layer; 12, first conductive layer; 120, conductive part; 121, first conductive part; 122, second conductive part; 123, third conductive part; 124, conductive trace; 125, test terminal; 13, isolation material layer; 130, via; 131, first via; 132, second via; 133, connecting via; 134, third via; 135, first isolation layer; 1350, first opening 136, second isolation layer; 1360, second opening; 137, third isolation layer; 138, first through hole; 1331, first sub-via hole; 1332, second sub-via hole; 1333, third sub-via hole; 14, second conductive layer; 140, electrode portion; 141, first electrode portion; 142, second electrode portion; 143, third electrode portion; 144, first connecting portion; 145, first portion; 146, second portion; 15, pixel defining layer; 151, first opening; 1511, first sub-opening; 1512, second sub-opening ; 1513, third sub-opening; 152, inclined portion; 153, flat portion; 154, first film layer; 155, second film layer; 156, third film layer; 157, second opening; 1571, fourth sub-opening; 1572, fifth sub-opening; 1573, sixth sub-opening; 16, organic material layer; 160, light-emitting layer; 161, red light-emitting layer; 162, green light-emitting layer; 163, blue light-emitting layer; 17, third conductive layer; 18, first metal layer; 181, first transition portion; 182, second transition portion; 183, third transition portion Connecting part; 184, fourth adapter; 19, filling part; 20, light-emitting unit; 201, light-emitting unit of the first light-emitting color; 202, light-emitting unit of the second light-emitting color; 203, light-emitting unit of the third light-emitting color; 21, filling material layer; 22, first isolation material layer; 23, second isolation material layer; 24, third isolation material layer; 25, conductive material layer; 26, top metal; 261, conductive metal strip; 27, filling layer; 28, insulating layer; 281, electrical connection hole; 29, electrical connection part; 30, metal layer; 2, display device. DETAILED DESCRIPTION

[0057] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0058] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0059] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0060] For ease of description, spatial relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, then the elements described as "below other elements or features" or "below other elements or features" will subsequently be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or in other directions) and the spatial relative descriptors used in the text are interpreted accordingly.

[0061] like Figure 1 and Figure 2As shown, according to an embodiment of the present application, a display panel 1 is proposed, including a display area AA and a frame area B1 located outside the display area AA, and the display panel 1 includes a substrate 11, a first conductive layer 12, an isolation material layer 13, a second conductive layer 14 and a pixel defining layer 15. The first conductive layer 12 is located on one side of the substrate 11, and the first conductive layer 12 includes a conductive trace 124 located in the frame area B1. The isolation material layer 13 is located on the side of the first conductive layer 12 away from the substrate 11, and includes a connecting via 133 located in the frame area B1. The second conductive layer 14 is located on the side of the isolation material layer 13 away from the substrate 11, and the second conductive layer 14 includes a first connecting portion 144 located in the frame area B1, and the first connecting portion 144 is connected to the conductive trace 124 through the connecting via 133. The pixel defining layer 15 is located on the side of the second conductive layer 14 facing away from the substrate 11, and the pixel defining layer 15 includes a first opening 151 for exposing the first connecting portion 144. The edge of the first opening 151 projected on the substrate 11 does not overlap with the edge of the connecting via 133 projected on the substrate 11, and the slope angle of the first opening 151 is smaller than the slope angle of the connecting via 133.

[0062] The display panel 1 provided in the present application includes a display area AA and a frame area B1 located outside the display area AA, the display area AA is used for display, the frame area B1 is arranged around at least a portion of the display area AA, and the frame area B1 is used to set the wiring for power supply to the display area AA.

[0063] The display panel 1 provided in the present application includes a substrate 11, a first conductive layer 12, an isolation material layer 13, a second conductive layer 14 and a pixel defining layer 15, wherein the first conductive layer 12 is used to form a conductive trace 124 located in the border area B1, and the second conductive layer 14 is used to form a first connecting portion 144 located in the border area B1, and the isolation material layer 13 is located between the first conductive layer 12 and the second conductive layer 14, and includes a portion located between the conductive trace 124 and the first connecting portion 144, and the portion is formed with a connecting via 133, and the first connecting portion 144 is connected to the conductive trace 124 through the connecting via 133. The display panel 1 also includes a pixel defining layer 15 located on the side of the second conductive layer 14 away from the substrate 11, and the pixel defining layer 15 is located on the side of the second conductive layer 14 away from the substrate 11, and is used to define the light-emitting unit. Specifically, the pixel defining layer 15 includes a first opening 151 for exposing the first connecting portion 144, so that the subsequent film layer (such as the cathode) is connected to the first connecting portion 144 through the first opening 151. The edge of the orthographic projection of the first opening 151 on the substrate 11 does not overlap with the edge of the orthographic projection of the connecting via 133 on the substrate 11, that is, the edge of the orthographic projection of the first opening 151 on the substrate 11 is located on the inner side or the outer side of the edge of the orthographic projection of the connecting via 133 on the substrate 11, so that a step is formed between the side wall of the first opening 151 and the side wall of the connecting via 133, or the pixel defining layer 15 extends into the connecting via 133, and the pixel defining layer 15 forms a step when it transitions from the side of the isolation material layer 13 away from the substrate 11 to the inside of the connecting via 133. The existence of the step can avoid the side wall of the first opening 151 and the side wall of the connecting via 133 from connecting and transitioning smoothly to form a large step difference at the connecting position of the first opening 151 and the connecting via 133, thereby reducing the climbing difficulty of the subsequent film layer at the first opening 151 and the connecting via 133, improving the yield of the subsequent film layer, and reducing the probability of problems such as the product failing to display, increased series resistance, and increased power consumption caused by the poor yield of the subsequent film layer, wherein the increased series resistance is prone to cause the problem of excessive voltage or increased power consumption of the product at low grayscale. Specifically, the climbing difficulty of the cathode in the frame area can be reduced, thereby helping to improve the yield of the cathode and the overlap yield of the cathode and the first transition portion.

[0064] like Figure 1 and Figure 3 As shown, the display panel 1 may further include a cutting line area B2 located outside the frame area B1 , and the cutting line area B2 may be formed with a test terminal 125 located in the first conductive layer 12 .

[0065] In a possible implementation, Figure 2 As shown, the slope angle of the first opening 151 is α1, and the slope angle range of the first opening 151 is 20°-50°.

[0066] In the above embodiment, the cross-sectional shape of the first opening 151 along the thickness direction of the display panel 1 may be an inverted trapezoid, and the bottom angle of the inverted trapezoid may range from 130° to 160°, so that the slope angle of the first opening 151 ranges from 20° to 50°, so as to make the side wall slope of the first opening 151 gentler, thereby improving the preparation yield of subsequent film layers and reducing the risk of subsequent film layers being interrupted here.

[0067] Specifically, the slope angle of the first opening 151 may be 20°, 25°, 31°, 45°, 49°, 50°, or the like.

[0068] In a possible implementation, Figure 2 As shown, the slope angle of the connecting via 133 is α2, and the slope angle range of the connecting via 133 is 40°-50°, so as to improve the preparation yield of the film layer prepared after the isolation material layer 13.

[0069] Specifically, in order to ensure the yield of subsequent film layers prepared after the isolation material layer 13 and the pixel defining layer 15 and prevent the subsequent film layers from breaking at the connecting vias 133 and causing yield loss, the slope angle should not be too large.

[0070] Specifically, the slope angle may be 40°, 41°, 43°, 45°, 46°, 48°, 49°, 50°, and so on.

[0071] In a possible implementation, Figure 4 and Figure 5 As shown, the edge of the first opening 151 projected on the substrate 11 is located on the inner side of the edge of the connecting via 133 projected on the substrate 11, and the portion of the pixel defining layer 15 located in the connecting via 133 includes an inclined portion 152 and a flat portion 153 that are connected to each other, the inclined portion 152 is located on the side wall of the connecting via 133, and the flat portion 153 is located on the bottom wall of the connecting via 133 and surrounds the first opening 151.

[0072] In the above embodiment, the edge of the orthographic projection of the first opening 151 on the substrate 11 is located inside the edge of the orthographic projection of the connecting via 133 on the substrate 11, that is, the pixel defining layer 15 partially extends to the inside of the connecting via 133, and the portion of the pixel defining layer 15 located inside the connecting via 133 includes an inclined portion 152 and a flat portion 153 connected to each other, the inclined portion 152 is located on the side wall of the connecting via 133, the flat portion 153 is located on the bottom wall of the connecting via 133 and connected to the inclined portion 152, the flat portion 153 surrounds the first opening 151, and the bottom of the first opening 151 overlaps with a portion of the bottom wall of the connecting via 133, so that a step is formed between the side of the flat portion 153 away from the bottom wall of the connecting via 133 and the bottom wall of the connecting via 133. The existence of the step can reduce the difficulty of climbing the subsequent film layer during the preparation process, thereby improving the preparation yield of the subsequent film layer.

[0073] In a possible implementation, Figure 2 As shown, the edge of the orthographic projection of the first opening 151 on the substrate 11 is located outside the edge of the orthographic projection of the connecting via 133 on the substrate 11, the first connecting portion 144 includes a first portion 145 located inside the connecting via 133 and a second portion 146 located outside the connecting via 133, and the boundary of the orthographic projection of the first opening 151 on the substrate 11 is located between the inner boundary and the outer boundary of the orthographic projection of the second portion 146 on the substrate 11.

[0074] In the above embodiment, the edge of the orthographic projection of the first opening 151 on the substrate 11 is located outside the edge of the orthographic projection of the connecting via 133 on the substrate 11, that is, the orthographic projection of the first opening 151 on the substrate 11 covers and exceeds the orthographic projection of the connecting via 133 on the substrate 11, and the part where the orthographic projection of the first opening 151 on the substrate 11 and the orthographic projection of the connecting via 133 on the substrate 11 do not overlap makes the first opening 151 expose the film layer below, thereby forming a step surface in the part of the side surface of the lower film layer facing away from the substrate 11 that is exposed by the first opening 151, so as to reduce the climbing difficulty of subsequent film layers, thereby improving the preparation yield of subsequent film layers.

[0075] Specifically, the lower film layer may be the first connecting portion 144. The first connecting portion 144 includes a first portion 145 located inside the connecting via 133 and a second portion 146 located outside the connecting via 133. The first portion 145 and the second portion 146 are connected to each other, and the second portion 146 is arranged around the connecting via 133. The boundary of the orthographic projection of the first opening 151 on the substrate 11 is located between the inner boundary and the outer boundary of the orthographic projection of the second portion 146 on the substrate 11, so that the first opening 151 exposes a part of the area in the second portion 146. During the preparation process, the subsequent film layer transitions from the side wall of the first opening 151 to the side of the second portion 146 away from the substrate 11, and then transitions to the surface of the side wall of the first portion 145 away from the connecting via 133, thereby reducing the climbing difficulty of the subsequent film layer.

[0076] In a possible implementation, Figure 2 As shown, the first conductive layer 12 further includes at least a first conductive portion 121 and a second conductive portion 122 located in the display area AA. The isolation material layer 13 further includes at least a first via hole 131 and a second via hole 132 located in the display area AA. The second conductive layer 14 further includes at least a first electrode portion 141 and a second electrode portion 142 located in the display area AA, the first electrode portion 141 corresponds to the first conductive portion 121, and the first electrode portion 141 is connected to the first conductive portion 121 through the first via hole 131; the second electrode portion 142 corresponds to the second conductive portion 122, and the second electrode portion 142 is connected to the second conductive portion 122 through the second via hole 132; the thickness of the isolation material layer 13 between the first electrode portion 141 and the first conductive portion 121 is h1, the thickness of the isolation material layer 13 between the second electrode portion 142 and the second conductive portion 122 is h2, and the thickness of the isolation material layer 13 between the first connecting portion 144 and the conductive trace 124 is h3, h1>h2, h3≥h1.

[0077] In the above embodiment, the first conductive portion 121 and the second conductive portion 122 may be used as reflective electrodes, and the first electrode portion 141 and the second electrode portion 142 may be used as transmissive electrodes. A first via hole 131 is formed in a portion of the isolation material layer 13 located between the first conductive portion 121 and the first electrode portion 141, and the first electrode portion 141 is connected to the first conductive portion 121 through the first via hole 131 to form a first control electrode. A second via hole 132 is formed in a portion of the isolation material layer 13 located between the second conductive portion 122 and the second electrode portion 142, and the second electrode portion 142 is connected to the second conductive portion 122 through the second via hole 132 to form a second control electrode. The thickness of the portion of the isolation material layer 13 located between the first conductive portion 121 and the first electrode portion 141 is h1, and the thickness of the portion of the isolation material layer 13 located between the second conductive portion 122 and the second electrode portion 142 is h2, h1>h2, that is, the thickness of the isolation material layer 13 in the first control electrode and the second control electrode is different, so that the first control electrode and the second control electrode are respectively adapted to light-emitting units with different light-emitting colors. Specifically, the isolation material layers 13 of different thicknesses have an enhancing effect on light of different wavelengths. The thicker isolation material layer 13 can enhance the color light with a longer wavelength, while the thinner isolation material layer 13 can enhance the color light with a shorter wavelength. That is, the first control electrode can enhance the color light with a longer wavelength, and the second control electrode can enhance the color light with a shorter wavelength.

[0078] The first conductive layer 12 is also used to form a conductive trace 124 located in the frame area B1, and the second conductive layer 14 is also used to form a first connection portion 144 located in the frame area B1. The isolation material layer 13 is located between the first conductive layer 12 and the second conductive layer 14, and includes a portion located between the conductive trace 124 and the first connection portion 144, and the portion is formed with a connection via 133, and the first connection portion 144 is connected to the conductive trace 124 through the connection via 133. The thickness of the portion of the isolation material layer 13 located between the conductive trace 124 and the first connection portion 144 is h3, and h3≥h1, that is, the depth of the connection via 133 in the isolation material layer 13 is greater than or equal to the depth of the first via 131, so that in the process of forming the first via 131 and the second via 132, the connection via 133 area can be prevented from being over-etched, so as to protect the first connection portion 144 and prevent the first connection portion 144 from being over-etched, thereby helping to improve the yield of the display panel 1.

[0079] The above-mentioned “thickness” refers to the maximum thickness.

[0080] Specifically, Figure 2As shown, the isolation material layer 13 may include a plurality of vias 130, and the plurality of vias 130 include a first via 131, a second via 132, and a connecting via 133, and may also include other vias 130. The depth of the connecting via 133 may be the same as the depth of the deepest via 130 in the isolation material layer 13, or the connecting via 133 is the deepest via 130 in the isolation material layer 13. In the process of forming the plurality of vias 130 in the isolation material layer 13, the etching depth of the connecting via 133 is the deepest, so that in the process of forming the other vias 130 except the connecting via 133, the first connecting portion 144 will not be over-etched, so as to improve the preparation yield of the first connecting portion 144.

[0081] Specifically, Figure 2 As shown, the first conductive layer 12 includes a plurality of conductive parts 120 located in the display area AA, and the plurality of conductive parts 120 include at least a first conductive part 121 and a second conductive part 122. The second conductive layer 14 includes a plurality of electrode parts 140 located in the display area AA, and the plurality of electrode parts 140 include at least a first electrode part 141 and a second electrode part 142. The display panel 1 includes a plurality of control electrodes, the first conductive part 121 is connected to the first electrode part 141 to form a first control electrode, the second conductive part 122 is connected to the second electrode part 142 to form a second control electrode, and the plurality of control electrodes include at least the above-mentioned first control electrode and the second control electrode. The portion of the isolation material layer 13 located between the first conductive portion 121 and the first electrode portion 141 forms a first strong microcavity, and the portion of the isolation material layer 13 located between the second conductive portion 122 and the second electrode portion 142 forms a second strong microcavity. The thickness of the portion of the isolation material layer 13 located between the first conductive portion 121 and the first electrode portion 141 is h1, and the thickness of the portion of the isolation material layer 13 located between the second conductive portion 122 and the second electrode portion 142 is h2, h1>h2, that is, the thickness of the first strong microcavity is greater than the thickness of the second strong microcavity.

[0082] like Figure 6 As shown, the display panel 1 includes light-emitting units 20 of multiple colors located on one side of the substrate 11, and the light-emitting units 20 of different colors emit light of different colors respectively. Each light-emitting unit 20 includes a control electrode, and the light-emitting units 20 of different colors correspond to different control electrodes. Compared with the second control electrode, the thickness of the first strong microcavity in the first control electrode is thicker, so that the light emitted by the light-emitting unit 20 with a longer wavelength can be adjusted to enhance, and the thickness of the second strong microcavity in the second control electrode is thinner, so that the light emitted by the light-emitting unit 20 with a shorter wavelength can be adjusted to enhance, therefore, the wavelength of the light emitted by the light-emitting unit 20 corresponding to the first control electrode is greater than the wavelength of the light emitted by the light-emitting unit 20 corresponding to the second control electrode.

[0083] like Figure 6As shown, specifically, the first control electrode and the second control electrode can be anodes, and the light-emitting unit 20 can also include a cathode, which is formed by a third conductive layer 17, and the third conductive layer 17 is located on the side of the pixel defining layer 15 away from the substrate 11. The cathode can be arranged on the entire surface of the display panel 1, and the cathode is connected to the first connecting portion 144, and the first connecting portion 144 and the conductive trace 124 are connected through the connecting via 133, so that the cathode is connected to the conductive trace 124 through the first connecting portion 144, so as to power the cathode.

[0084] Specifically, Figure 7 As shown, the substrate 11 includes a substrate 110 and a driving circuit layer 111 located on one side of the substrate 110. The driving circuit layer 111 includes a pixel circuit. The pixel circuit is connected to the light emitting unit 20 and is used to drive the light emitting unit 20 to emit light.

[0085] In a possible implementation, Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 7 As shown, the first conductive layer 12 also includes a third conductive portion 123 located in the display area AA, the isolation material layer 13 also includes a third via hole 134 located in the display area AA, and the second conductive layer 14 also includes a third electrode portion 143 located in the display area AA, the third electrode portion 143 corresponds to the third conductive portion 123, and the third electrode portion 143 is connected to the third conductive portion 123 through the third via hole 134, and the thickness of the isolation material layer 13 between the third electrode portion 143 and the third conductive portion 123 is h4, and h1>h4.

[0086] In the above embodiment, the first conductive layer 12 includes a plurality of conductive parts 120 located in the display area AA, the plurality of conductive parts 120 include a first conductive part 121, a second conductive part 122, and a third conductive part 123. The second conductive layer 14 includes a plurality of electrode parts 140 located in the display area AA, the plurality of electrode parts 140 include a first electrode part 141 and a second electrode part 142, and also include a third electrode part 143. The isolation material layer 13 includes a plurality of vias 130, the plurality of vias 130 include a first via 131, a second via 132 and a connecting via 133, and also include a third via 134. The display panel 1 includes a plurality of control electrodes, the plurality of control electrodes include a first control electrode and a second control electrode, and also include a third control electrode, the third control electrode includes a third conductive part 123 and a third electrode part 143 connected to each other. The portion of the isolation material layer 13 between the third conductive portion 123 and the third electrode portion 143 forms a third strong microcavity, and the thickness of the isolation material layer 13 between the third electrode portion 143 and the third conductive portion 123 is h4, that is, the thickness of the third strong microcavity is h4. h1>h4, and h1>h2, so the thickness of the portion of the isolation material layer 13 between the first electrode portion 141 and the first conductive portion 121 can be the thickest region of the isolation material layer 13 in the display area AA, and the thickness h3 of the portion of the isolation material layer 13 between the conductive trace 124 and the first connecting portion 144 is set to be greater than or equal to h1, so that in the process of forming the first via hole 131, the second via hole 132 and the third via hole 134, over-etching of the connecting via hole 133 area can be prevented, so as to protect the first connecting portion 144 and prevent over-etching of the first connecting portion 144, thereby helping to improve the yield of the display panel 1.

[0087] Specifically, h3 may be equal to h1, that is, the thickness of the portion of the isolation material layer 13 located between the first electrode portion 141 and the first conductive portion 121 is the same as the thickness of the portion of the isolation material layer 13 located between the first connection portion 144 and the conductive trace 124, thereby simplifying the manufacturing process and reducing the manufacturing cost. That is, when the thickness of the portion of the isolation material layer 13 located between the first electrode portion 141 and the first conductive portion 121 is the thickest region of the isolation material layer 13 in the display area AA, the thickness of the portion of the isolation material layer 13 located in the frame area B1 may be the same as the thickness of the portion located between the first electrode portion 141 and the first conductive portion 121.

[0088] In the above implementation mode, if Figure 6As shown, the display panel 1 may include at least three light-emitting units with different light-emitting colors, specifically, may include a light-emitting unit 201 of a first light-emitting color, a light-emitting unit 202 of a second light-emitting color, and a light-emitting unit 203 of a third light-emitting color, the light-emitting unit 201 of the first light-emitting color includes a first control electrode, the light-emitting unit 202 of the second light-emitting color includes a second control electrode, the light-emitting unit 203 of the third light-emitting color includes a third control electrode, h1>h2, h1>h4, h3≥h1, and h2 is greater than or less than h4.

[0089] When h2>h4, the wavelength of the light emitted by the light emitting unit 201 of the first light emitting color, the light emitting unit 202 of the second light emitting color, and the light emitting unit 203 of the third light emitting color gradually decreases. When h2<h4, the wavelength of the light emitted by the light emitting unit 201 of the first light emitting color, the light emitting unit 203 of the third light emitting color, and the light emitting unit 202 of the second light emitting color gradually decreases. The first strong microcavity, the second strong microcavity, and the third strong microcavity in the present application are set according to the different wavelengths of the light emitted by different light emitting units, thereby significantly improving the light extraction efficiency of the light emitting units.

[0090] Taking h2>h4 as an example, the light emitting unit 201 of the first light emitting color may be a light emitting unit emitting red light, the light emitting unit 202 of the second light emitting color may be a light emitting unit emitting green light, and the light emitting unit 203 of the third light emitting color may be a light emitting unit emitting blue light.

[0091] In a possible implementation, Figure 8 As shown, the isolation material layer 13 includes a first isolation layer 135, a second isolation layer 136 and a third isolation layer 137 which are stacked in a direction away from the substrate 11, the first isolation layer 135, the second isolation layer 136 and the third isolation layer 137 are arranged between the first electrode portion 141 and the first conductive portion 121, the second isolation layer 136 and the third isolation layer 137 are arranged between the second electrode portion 142 and the second conductive portion 122, the third isolation layer 137 is arranged between the third electrode portion 143 and the third conductive portion 123, and the first isolation layer 135, the second isolation layer 136 and the third isolation layer 137 are arranged between the first connecting portion 144 and the conductive trace 124.

[0092] In the above embodiment, during the preparation process, the portion of the isolation material layer 13 located in the border area B1 can only perform the step of opening the connecting via 133 during the patterning process, and there is no need to perform large-scale removal of the first isolation layer 135 adjacent to the conductive trace 124, thereby reducing damage to the conductive trace 124 and further improving the preparation yield.

[0093] In a first possible implementation, if Fig. 9As shown, the pixel defining layer 15 may include a plurality of film layers stacked in a direction away from the substrate 11, the first opening 151 includes sub-openings located in each film layer and interconnected, and the orthographic projections of the plurality of sub-openings arranged in a direction away from the substrate 11 on the substrate 11 are nested in sequence from the inside to the outside, so that steps are formed between the side walls of adjacent sub-openings, thereby achieving buffering for subsequent film layers, wherein the plurality of film layers may include a first film layer 154, a second film layer 155, and a third film layer 156 stacked in a direction away from the substrate 11, and the plurality of sub-openings may include a first sub-opening 1511 formed in the first film layer 154, a second sub-opening 1512 formed in the second film layer 155, and a third sub-opening 1513 formed in the third film layer 156.

[0094] Specifically, Fig. 9 As shown, the pixel defining layer 15 includes a first film layer 154, a second film layer 155 and a third film layer 156 stacked in a direction away from the substrate 11, and the first opening 151 includes a first sub-opening 1511, a second sub-opening 1512 and a third sub-opening 1513 that are interconnected, the first sub-opening 1511 penetrates the first film layer 154, the second sub-opening 1512 penetrates the second film layer 155, and the third sub-opening 1513 penetrates the third film layer 156, and the orthographic projections of the third sub-opening 1513, the second sub-opening 1512 and the first sub-opening 1511 on the substrate 11 are nested in sequence from the outside to the inside.

[0095] In the above embodiment, the pixel defining layer 15 may include a first film layer 154, a second film layer 155, and a third film layer 156 stacked in a direction away from the substrate 11, wherein the first film layer 154 is formed with a first sub-opening 1511, the second film layer 155 is formed with a second sub-opening 1512, and the third film layer 156 is formed with a third sub-opening 1513, and the third sub-opening 1513, the second sub-opening 1512, and the first sub-opening 1511 are connected to form the first opening 151. The orthographic projections of the third sub-opening 1513, the second sub-opening 1512, and the first sub-opening 1511 on the substrate 11 are nested in sequence from outside to inside, so that a step can be formed between the side walls of any two adjacent sub-openings among the third sub-opening 1513, the second sub-opening 1512, and the first sub-opening 1511, so as to achieve buffering for subsequent film layers and improve the preparation yield of subsequent film layers.

[0096] In a second possible implementation, if Fig.10As shown, the pixel defining layer 15 includes a plurality of film layers stacked in a direction away from the substrate 11, the first opening 151 includes sub-openings located in each film layer and interconnected, steps are formed between the side walls of some adjacent sub-openings, thereby achieving buffering for subsequent film layers, and the side walls of some adjacent sub-openings are continuously arranged and smoothly transitioned to reduce the preparation cost, wherein the plurality of film layers may include a first film layer 154, a second film layer 155 and a third film layer 156 stacked in a direction away from the substrate 11, and the plurality of sub-openings may include a first sub-opening 1511 formed in the first film layer 154, a second sub-opening 1512 formed in the second film layer 155 and a third sub-opening 1513 formed in the third film layer 156.

[0097] In a possible implementation, Fig.11 and Fig.12 As shown, the isolation material layer 13 may include a plurality of film layers stacked in a direction away from the substrate 11, and the number of film layers is not limited to the three layers in the above embodiment, and may be two layers or more than three layers. The connecting via 133 includes sub-vias located in each film layer and interconnected. The orthographic projections of the plurality of sub-vias arranged in a direction away from the substrate 11 on the substrate 11 are nested in sequence from the inside to the outside, so that steps are formed between the side walls of adjacent sub-vias, thereby achieving buffering for subsequent film layers.

[0098] In another possible implementation, if Fig.13 As shown, the isolation material layer 13 includes a first isolation layer 135, a second isolation layer 136 and a third isolation layer 137 stacked in a direction away from the substrate 11, and the connecting via 133 includes a first sub-via 1331 and a first through hole 138 that are interconnected. The first sub-via 1331 penetrates the first isolation layer 135, and the first through hole 138 penetrates the second isolation layer 136 and the third isolation layer 137. The orthographic projection of the first sub-via 1331 on the substrate 11 is located on the inner side of the orthographic projection of the first through hole 138 on the substrate 11.

[0099] In the above embodiment, the isolation material layer 13 may include a first isolation layer 135, a second isolation layer 136, and a third isolation layer 137 stacked in a direction away from the substrate 11, wherein the first isolation layer 135 is formed with a first sub-via 1331, and the second isolation layer 136 and the third isolation layer 137 are formed with a first through hole 138, and the first through hole 138 penetrates the second isolation layer 136 and the third isolation layer 137. The first through hole 138 is connected with the first sub-via 1331 to form a connecting via 133. The orthographic projection of the first sub-via 1331 on the substrate 11 is located on the inner side of the orthographic projection of the first through hole 138 on the substrate 11, so that a step can be formed between the first sub-via 1331 and the first through hole 138, so as to achieve buffering for subsequent film layers and improve the preparation yield of subsequent film layers.

[0100] In the above embodiment, the isolation material layer 13 may include a plurality of film layers stacked in a direction away from the substrate 11. The number of film layers is not limited to the three layers in the above embodiment, and may be two layers or more than three layers. The connecting via 133 includes sub-vias located in each film layer and interconnected. Steps are formed between the side walls of some adjacent sub-vias so that buffering of subsequent film layers can be achieved at the step position. The side walls of some adjacent sub-vias have a smooth transition to simplify the preparation process and reduce the preparation cost.

[0101] or, Fig.14 As shown, a first sub-via 1331 is formed in the first isolation layer 135, a second sub-via 1332 is formed in the second isolation layer 136, and a third sub-via 1333 is formed in the third isolation layer 137. A step may be formed only between the sidewall of the second sub-via 1332 and the sidewall of the third sub-via 1333, and the sidewall of the first sub-via 1331 and the sidewall of the second sub-via 1332 may be continuously arranged and smoothly transitioned to achieve buffering for subsequent film layers.

[0102] In a possible implementation, Fig.10 As shown, the pixel defining layer 15 includes a second opening 157 for exposing the first electrode portion 141 and the second electrode portion 142. The second opening 157 includes a fourth sub-opening 1571, a fifth sub-opening 1572 and a sixth sub-opening 1573 stacked in sequence along a direction away from the substrate 11. The outer boundary of the fifth sub-opening 1572 is larger than the outer boundary of the fourth sub-opening 1571, and larger than the outer boundary of the sixth sub-opening 1573.

[0103] In the above embodiment, the second conductive layer 14 includes a plurality of electrode portions 140 located in the display area AA. The plurality of electrode portions 140 are arranged at intervals. The plurality of electrode portions 140 include the first electrode portion 141 and the second electrode portion 142 described above, and may further include a third electrode portion 143 .

[0104] The pixel defining layer 15 includes a second opening 157 located in the display area AA, and the second opening 157 exposes the electrode portion 140. Specifically, part of the second opening 157 corresponds to part of the first electrode portion 141 one-to-one, and in each pair of the one-to-one corresponding second openings 157 and the first electrode portion 141, the second opening 157 exposes a partial area in the first electrode portion 141. Part of the second opening 157 corresponds to part of the second electrode portion 142 one-to-one, and in each pair of the one-to-one corresponding second openings 157 and the second electrode portion 142, the second opening 157 exposes a partial area in the second electrode portion 142. Part of the second opening 157 corresponds to part of the third electrode portion 143 one-to-one, and in each pair of the one-to-one corresponding second openings 157 and the third electrode portion 143, the second opening 157 exposes a partial area in the third electrode portion 143. The second opening 157 includes a fourth sub-opening 1571, a fifth sub-opening 1572 and a sixth sub-opening 1573, which are stacked in sequence in a direction away from the substrate 11. The outer boundary of the fifth sub-opening 1572 is larger than the outer boundary of the fourth sub-opening 1571, and larger than the outer boundary of the sixth sub-opening 1573, so that the side wall of the sixth sub-opening 1573 extends out of the side wall of the fifth sub-opening 1572 to form a step portion, which can be used to isolate part of the film layer in adjacent light-emitting units, thereby reducing crosstalk between adjacent light-emitting units.

[0105] In a possible implementation, Fig.10 As shown, the pixel defining layer 15 includes a first film layer 154, a second film layer 155 and a third film layer 156 stacked in a direction away from the substrate 11, the fourth sub-opening 1571 penetrates the first film layer 154, the fifth sub-opening 1572 penetrates the second film layer 155, and the sixth sub-opening 1573 penetrates the third film layer 156.

[0106] In the above embodiment, the pixel defining layer 15 includes a first film layer 154, a second film layer 155 and a third film layer 156 stacked in a direction away from the substrate 11, a fourth sub-opening 1571 is formed in the first film layer 154, a fifth sub-opening 1572 is formed in the second film layer 155, and a sixth sub-opening 1573 is formed in the third film layer 156.

[0107] Alternatively, the pixel defining layer 15 may also include multiple film layers stacked in a direction away from the substrate 11, specifically two layers, three layers, four layers, or more than four layers. The second opening 157 penetrates the multiple film layers in the thickness direction of the pixel defining layer 15, and the outer diameter of the second opening 157 on the side away from the substrate 11 may be set to be smaller than the outer diameter on the side close to the substrate 11, so as to isolate part of the film layers in adjacent light-emitting units.

[0108] In a possible implementation, Fig.10As shown, it also includes an organic material layer 16 and a third conductive layer 17 stacked along a path away from the second conductive layer 14, the organic material layer 16 includes a plurality of light-emitting layers 160, the light-emitting layers 160 are located at the second opening 157, the third conductive layer 17 is located at a side of the organic material layer 16 and the pixel defining layer 15 away from the substrate 11, and the third conductive layer 17 is connected to the first connecting portion 144 through the first opening 151.

[0109] In the above embodiment, the organic material layer 16 includes a plurality of light-emitting layers 160. When the display panel 1 includes a light-emitting unit for emitting red light, a light-emitting unit for emitting green light, and a light-emitting unit for emitting blue light, the light-emitting layer 160 may specifically include a red light-emitting layer 161 for emitting red light, a green light-emitting layer 162 for emitting green light, and a blue light-emitting layer 163 for emitting blue light.

[0110] The organic material layer 16 may further include a first functional layer group and a second functional layer group stacked with the light-emitting layer 160, the first functional layer group including a hole injection layer, a hole transport layer and an electron blocking layer, the second functional layer group including a hole blocking layer, an electron transport layer and an electron injection layer, and the first functional layer group and the second functional layer group may be located on both sides of the light-emitting layer 160 along the thickness direction of the display panel 1. The first functional layer group and the second functional layer group may be prepared as a whole layer, and then may be separated by a pixel definition layer, thereby reducing the probability of lateral crosstalk between light-emitting units, thereby improving the display effect of the display panel 1.

[0111] In the above embodiment, the third conductive layer 17 can be used to form a cathode. The material of the third conductive layer can be MgAg, which has good conductivity, thereby reducing the power consumption of the product.

[0112] In a feasible implementation manner, the conductive trace 124 is disposed around the display area AA. The conductive trace 124 is a cathode ring structure, which is used to supply power to the third conductive layer 17 .

[0113] In a possible implementation, Fig.10 As shown, the material of the second conductive layer 14 includes a transparent conductive material, and the display panel 1 also includes a first metal layer 18 located between the second conductive layer 14 and the isolation material layer 13. The first metal layer 18 includes a first transition portion 181, a second transition portion 182 and a third transition portion 183. The first electrode portion 141 is connected to the first conductive portion 121 through the first transition portion 181, the second electrode portion 142 is connected to the second conductive portion 122 through the second transition portion 182, and the first connection portion 144 is connected to the conductive trace 124 through the third transition portion 183.

[0114] In the above embodiment, the first metal layer 18 can be used as an insulating layer. Specifically, the second conductive layer 14 can be made of a transparent metal oxide with conductive properties, such as indium tin oxide or indium zinc oxide. The first conductive layer 12 can be made of titanium and aluminum, and can include a stacked titanium metal layer and an aluminum metal layer. If the second conductive layer 14 is in direct contact with the first conductive layer 12, the aluminum atoms in the first conductive layer 12 will rob the oxygen atoms in the indium tin oxide, resulting in the precipitation of the indium element. Therefore, it is necessary to set the first metal layer 18 as an insulating layer to protect the first conductive layer 12 and the second conductive layer 14, and use the conductive properties of the first metal layer 18 to achieve the connection between the substructure in the first conductive layer 12 and the substructure in the second conductive layer 14.

[0115] Specifically, the first metal layer 18 includes a first transition portion 181, a second transition portion 182 and a third transition portion 183. The first transition portion 181 is located in the first via hole 131, and is used to connect the first electrode portion 141 with the first conductive portion 121. The first transition portion 181 is used to prevent the first conductive portion 121 from directly contacting the first electrode portion 141. The second transition portion 182 is located in the second via hole 132, and is used to connect the second electrode portion 142 with the second conductive portion 122. The second transition portion 182 is used to prevent the second conductive portion 122 from directly contacting the second electrode portion 142. The third transition portion 183 is located in the connecting via hole 133, and is used to connect the first electrode portion 141 with the conductive trace 124. The third transition portion 183 is used to prevent the conductive trace 124 from directly contacting the first connecting portion 144.

[0116] For ease of preparation, the first metal layer 18 can be prepared on the entire surface, that is, the first metal layer 18 includes portions located in the first via 131, the second via 132 and the connecting via 133, and a portion located on the side of the isolation material layer 13 away from the substrate 11. The first metal layer 18 is then patterned, including removing portions of the first metal layer 18 located on the side of the isolation material layer 13 away from the substrate 11, so as to form first transition portions 181, second transition portions 182 and third transition portions 183 that are independent and insulated from each other.

[0117] Specifically, when the isolation material layer 13 includes the third via hole 134, the first metal layer 18 further includes a fourth transition portion 184, which is located in the third via hole 134 and is used to connect the third electrode portion 143 with the third conductive portion 123. The fourth transition portion 184 at least covers the surface of the third conductive portion 123 exposed through the third via hole 134 to prevent the third conductive portion 123 from directly contacting the third electrode portion 143.

[0118] In a possible implementation, Fig.10 , Fig.11 , Fig.13 and Fig.14As shown, it also includes a filling portion 19 disposed on the same layer as the first conductive layer 12, and the height difference between the surface of the first conductive layer 12 facing away from the substrate 11 and the surface of the filling portion 19 facing away from the substrate 11 is less than 50 angstroms.

[0119] In the above embodiment, by forming a filling portion 19 between adjacent conductive portions 120 (the conductive portion 120 includes a first conductive portion 121, a second conductive portion 122, and a third conductive portion 123), the step difference between the conductive portion 120 area and the non-conductive portion 120 area can be reduced, thereby ensuring the thickness stability of the isolation material layer 13 located in the first control electrode, the second control electrode, and the third control electrode, thereby improving the performance of the display panel 1.

[0120] Specifically, the height difference between the surface of the first conductive layer 12 facing away from the substrate 11 and the surface of the filling portion 19 facing away from the substrate 11 is less than 50 angstroms, and can be 50 angstroms, 49 angstroms, 43 angstroms, 38 angstroms, 35 angstroms, 30 angstroms, 22 angstroms, 16 angstroms, 3 angstroms, 0 angstroms, etc., which is not particularly limited in this application. When the surface of the first conductive layer 12 facing away from the substrate 11 is flush with the surface of the filling portion 19 facing away from the substrate 11, the performance of the display panel 1 is optimal.

[0121] In a possible implementation, Fig.14 As shown, the slope angle α2 of the first via hole 131 , the second via hole 132 and the third via hole 134 ranges from 40° to 50°.

[0122] In the above embodiment, the slope angles of the first via hole 131 , the second via hole 132 and the third via hole 134 are limited to a range of 40° to 50°, so as to ensure the yield of the film layer prepared after the isolation material layer 13 .

[0123] Specifically, the film layer prepared after the isolation material layer 13 may include a first metal layer 18 prepared on the entire surface. To ensure the yield of the first metal layer 18 and prevent the first metal layer 18 from being broken at the first via hole 131, the second via hole 132, and the third via hole 134, which may cause the yield to be damaged, the slope angle should not be too large. To ensure the light transmittance, the orthographic projection area of ​​the first transition portion 181, the second transition portion 182, and the third transition portion 183 formed in the first metal layer 18 and located in the display area AA on the substrate 11 should be as small as possible, so the slope angle should not be too small.

[0124] Specifically, the slope angle may be 40°, 41°, 43°, 45°, 46°, 48°, 49°, 50°, and so on.

[0125] The present application also provides a method for preparing the display panel 1, such as Fig.15As shown, the display panel 1 includes a display area AA and a frame area B1 located outside the display area AA, and the preparation method includes:

[0126] S200, such as Fig.16 As shown, a substrate 11 is provided.

[0127] S400, such as Fig.16 As shown, a first conductive layer 12 is formed on one side of the substrate 11 , and the first conductive layer 12 includes a conductive trace 124 located in the border area B1 .

[0128] Specifically, the first conductive layer 12 may be formed in its entirety by chemical vapor deposition, that is, the orthographic projection of the first conductive layer 12 on the substrate 11 covers the substrate 11. The first conductive layer 12 is then patterned to form conductive traces 124 located in the border area B1.

[0129] Specifically, the material of the first conductive layer 12 may include a stacked titanium metal layer and an aluminum metal layer.

[0130] S600, such as Fig.17 As shown, an isolation material layer 13 is formed on the side of the first conductive layer 12 facing away from the substrate 11 , and the isolation material layer 13 includes a connecting via 133 located in the border area B1 .

[0131] Specifically, the isolation material layer 13 may be formed by a chemical vapor deposition process, and the connection via 133 may be formed by a dry etching process.

[0132] S800, such as Fig.18 As shown, a second conductive layer 14 is formed on the side of the isolation material layer 13 facing away from the substrate 11 . The second conductive layer 14 includes a first connecting portion 144 located in the border area B1 . The first connecting portion 144 is connected to the conductive trace 124 through a connecting via 133 .

[0133] S1000, such as Figure 2 As shown, a pixel defining layer 15 is formed on the side of the second conductive layer 14 facing away from the substrate 1, and the pixel defining layer 15 includes a first opening 151 for exposing the first connecting portion 144, and the edge of the first opening 151 projected on the substrate 11 does not overlap with the edge of the connecting via 133 projected on the substrate 11, and the slope angle of the first opening 151 is smaller than the slope angle of the connecting via 133.

[0134] In the method for preparing the display panel 1 provided in the present application, a pixel defining layer 15 is formed on the side of the second conductive layer 14 facing away from the substrate 11, and the pixel defining layer 15 includes a first opening 151 for exposing the first connecting portion 144, so that the subsequent film layer (for example, the cathode) is connected to the first connecting portion 144 through the first opening 151. The edge of the first opening 151 projected on the substrate 11 does not overlap with the edge of the connecting via 133 projected on the substrate 11, that is, the edge of the first opening 151 projected on the substrate 11 is located on the inner side or the outer side of the edge of the connecting via 133 projected on the substrate 11, so that a step is formed between the side wall of the first opening 151 and the side wall of the connecting via 133, or the pixel defining layer 15 extends into the connecting via 133, and the pixel defining layer 15 forms a step when it transitions from the side of the isolation material layer 13 facing away from the substrate 11 to the inside of the connecting via 133. The existence of the step can avoid the side wall of the first opening 151 and the side wall of the connecting via 133 from connecting and transitioning smoothly to form a large step difference at the connecting position of the first opening 151 and the connecting via 133, thereby reducing the climbing difficulty of the subsequent film layer at the first opening 151 and the connecting via 133, improving the yield of the subsequent film layer, and reducing the probability of problems such as the product failing to display, increased series resistance, and increased power consumption caused by the poor yield of the subsequent film layer, wherein the increased series resistance is prone to cause the problem of excessive voltage or increased power consumption of the product at low grayscale. Specifically, the climbing difficulty of the cathode in the frame area can be reduced, thereby helping to improve the yield of the cathode and the overlap yield of the cathode and the first transition portion.

[0135] In the above implementation, the climbing difficulty of the cathode can be reduced without increasing the number of masking times, thereby reducing the process difficulty and process cost.

[0136] In a feasible embodiment, the preparation method further comprises:

[0137] like Fig.16 As shown, at least a first conductive portion 121 and a second conductive portion 122 located in the display area AA are formed in the first conductive layer 12 .

[0138] Specifically, the first conductive layer 12 may further include a third conductive portion 123 located in the display area AA.

[0139] like Fig.17 As shown, at least a first via hole 131 and a second via hole 132 are formed in the isolation material layer 13 and located in the display area AA.

[0140] Specifically, the isolation material layer 13 may further include a third via hole 134 located in the display area AA.

[0141] like Fig.18As shown, at least a first electrode portion 141 and a second electrode portion 142 are formed in the second conductive layer 14 in the display area AA, the first electrode portion 141 corresponds to the first conductive portion 121, and the first electrode portion 141 is connected to the first conductive portion 121 through the first via 131; the second electrode portion 142 corresponds to the second conductive portion 122, and the second electrode portion 142 is connected to the second conductive portion 122 through the second via 132; the second conductive layer 14 also includes a first connecting portion 144 located in the frame area B1, and the first connecting portion 144 is connected to the conductive trace 124 through the connecting via 133; the thickness of the insulating material layer 13 between the first electrode portion 141 and the first conductive portion 121 is h1, the thickness of the insulating material layer 13 between the second electrode portion 142 and the second conductive portion 122 is h2, and the thickness of the insulating material layer 13 between the first connecting portion 144 and the conductive trace 124 is h3, h1>h2, h3≥h1.

[0142] In the above embodiment, by preparing the thickness of the portion of the isolation material layer 13 located in the border area B1 to be greater than or equal to the thickness of the region with the largest thickness in the portion of the isolation material layer 13 located in the display area AA, the depth of the connecting via 133 in the isolation material layer 13 is made greater than or equal to the depth of the first via 131. This can prevent over-engraving of the connecting via 133 area during the process of forming the first via 131 and the second via 132, thereby protecting the first connecting portion 144 and preventing over-engraving of the first connecting portion 144, thereby helping to improve the yield of the display panel 1.

[0143] In a feasible implementation manner, after step S400, the method further includes:

[0144] like Fig.19 and Fig. 20 As shown, a filling material layer 21 is formed on the side of the first conductive layer 12 facing away from the substrate 11, and then the filling material layer 21 is thinned, and the portion of the filling material layer 21 located on the surface of the first conductive layer 12 facing away from the substrate 11 is removed, and only the portion arranged on the same layer as the filling material layer 21 is retained to form a filling portion 19, and the height difference between the surface of the side of the filling portion 19 facing away from the substrate 11 and the surface of the side of the first conductive layer 12 facing away from the substrate 11 is less than 50 angstroms.

[0145] Specifically, the filling material layer 21 is formed by a chemical vapor deposition process, and then the filling material layer 21 is thinned by a chemical mechanical polishing process.

[0146] In a possible implementation, Fig.21As shown, when the isolation material layer 13 is formed in step S600, the isolation material layer 13 may include three layers stacked in a direction away from the substrate 11, that is, the isolation material layer 13 includes a first isolation layer 135, a second isolation layer 136 and a third isolation layer 137 stacked in a direction away from the substrate 11.

[0147] The first isolation layer 135 , the second isolation layer 136 , and the third isolation layer 137 are all made of silicon oxide.

[0148] In the process of preparing the isolation material layer 13, first, Fig. 22 and Fig.23 As shown, the first isolation material layer 22 is formed by a chemical vapor deposition process, and the first isolation material layer 22 is patterned. An etching process can be used to form a first opening 1350 in the first isolation material layer 22 to expose the second conductive part 122 and the third conductive part 123. The etching process here needs to strictly control the over-etching level to ensure that the height difference between the side surface of the second conductive part 122 and the third conductive part 123 facing away from the substrate 11 and the side surface of the filling part 19 facing away from the substrate 11 after etching is less than 75 angstroms.

[0149] Then, if Fig.24 and Fig.25 As shown, the second isolation material layer 23 is formed by a chemical vapor deposition process, and the second isolation material layer 23 is patterned. An etching process can be used to form a second opening 1360 exposing the third conductive portion 123 in the second isolation material layer 23. The etching process here needs to strictly control the over-etching level to ensure that the height difference between the side surface of the third conductive portion 123 facing away from the substrate 11 and the side surface of the filling portion 19 facing away from the substrate 11 after etching is less than 100 angstroms.

[0150] Finally, if Fig.26 and Fig. 27As shown, the third isolation material layer 24 is formed by a chemical vapor deposition process, and the first isolation material layer 22, the second isolation material layer 23 and the third isolation material layer 24 are patterned synchronously to form the first via hole 131, the second via hole 132, the connecting via hole 133 and the third via hole 134. Specifically, the first isolation material layer 22, the second isolation material layer 23 and the third isolation material layer 24 are patterned synchronously by a single etching process, and the same mask process can be used at this time, so that the number of masks in the display panel 1 does not increase, which helps to save the preparation cost. At this time, since the thickness of the portion of the isolation material layer 13 located in the border area B1 is prepared to be greater than or equal to the thickness of the region with the largest thickness in the portion of the isolation material layer 13 located in the display area AA, the depth of the connecting via 133 in the isolation material layer 13 is greater than or equal to the depth of the first via 131. This can prevent over-engraving of the connecting via 133 area during the formation of the first via 131 and the second via 132, thereby protecting the first connecting portion 144 and preventing over-engraving of the first connecting portion 144, thereby helping to improve the yield of the display panel 1.

[0151] In the process of forming the first via 131, the second via 132, the connecting via 133 and the third via 134, it is necessary to control the slope angle range of the first via 131, the second via 132, the connecting via 133 and the third via 134 to be 40°-50° so as to reduce the risk of subsequent film breakage.

[0152] Alternatively, the third isolation material layer 24 may be etched using a first etching process to form a third via 134 exposing a portion of the third conductive portion 123; the third isolation material layer 24 and the second isolation material layer 23 that are stacked may be etched using a second etching process to form a second via 132 that exposes a portion of the second conductive portion 122; the third isolation material layer 24, the second isolation material layer 23 and the first isolation material layer 22 that are stacked may be etched using a third etching process to form a first via 131 that exposes a portion of the first conductive portion 121 and a connecting via 133 that exposes a portion of the conductive trace 124, thereby completing the patterning of the first isolation material layer 22 to form a first isolation layer 135, the patterning of the second isolation material layer 23 to form a second isolation layer 136, and the patterning of the third isolation material layer 24 to form a third isolation layer 137.

[0153] Specifically, before the first etching process is performed, a mask layer may be formed by coating, exposing, and developing, and the position of the third via hole 134 is defined by the mask layer. Before the second etching process is performed, a mask layer may be formed by coating, exposing, and developing, and the position of the second via hole 132 is defined by the mask layer. Before the third etching process is performed, a mask layer may be formed by coating, exposing, and developing, and the positions of the first via hole 131 and the connecting via hole 133 are defined by the mask layer.

[0154] Specifically, the connecting via 133 can also be prepared separately from the first via 131. When preparing the connecting via 133, after preparing the stacked first isolation material layer 22, the second isolation material layer 23, and the third isolation material layer 24, multiple etching processes can be used to etch the first isolation material layer 22, the second isolation material layer 23, and the third isolation material layer 24 respectively, so that the connecting via 133 includes a first sub-via 1331 and a first through hole 138 that are interconnected, the first sub-via 1331 penetrates the first isolation material layer 22, the first through hole 138 penetrates the second isolation material layer 23 and the third isolation material layer 24, and the orthographic projection of the first sub-via 1331 on the substrate 11 is located on the inner side of the orthographic projection of the first through hole 138 on the substrate 11.

[0155] Specifically, the first through hole 138 includes a second sub-via 1332 and a third sub-via 1333 . The second sub-via 1332 penetrates the second isolation material layer 23 , and the third sub-via 1333 penetrates the third isolation material layer 24 .

[0156] In another feasible implementation manner, the orthographic projections of the third sub-via 1333 , the second sub-via 1332 , and the first sub-via 1331 on the substrate 11 are nested in sequence from outside to inside.

[0157] Alternatively, the first sub-via 1331 may be formed by etching after forming the first isolation material layer 22, the second sub-via 1332 may be formed by etching after forming the second isolation material layer 23, and the third sub-via 1333 may be formed by etching after forming the third isolation material layer 24, and the present application does not make any special limitation on this.

[0158] In a possible implementation, Fig.28 and Fig.29 As shown, before the step of forming the second conductive layer 14 in step S800, the following steps are also included:

[0159] The first metal layer 18 is formed by a physical vapor deposition process and patterned to form a first transition portion 181 , a second transition portion 182 , and a third transition portion 183 , and a fourth transition portion 184 located in the third via hole 134 may also be formed.

[0160] The first adapter portion 181 is located in the first via hole 131, and the first adapter portion 181 at least covers the surface of the first conductive portion 121 exposed through the first via hole 131. The second adapter portion 182 is located in the second via hole 132, and the second adapter portion 182 at least covers the surface of the second conductive portion 122 exposed through the second via hole 132. The third adapter portion 183 at least covers the surface of the conductive trace 124 exposed through the connecting via hole 133, and the third adapter portion 183 at least covers the surface of the third conductive portion 123 exposed through the third via hole 134.

[0161] In a feasible implementation manner, the step of forming the second conductive layer 14 in step S800 further includes:

[0162] It also includes forming a transparent conductive material layer 25 by a physical vapor deposition process, and patterning the transparent conductive material layer 25 to form a second conductive layer 14, the second conductive layer 14 includes at least a first electrode portion 141 and a second electrode portion 142 located in the display area AA, and may also include a third electrode portion 143, the first electrode portion 141 corresponds to the first conductive portion 121, and the first electrode portion 141 is connected to the first conductive portion 121 through a first via 131; the second electrode portion 142 corresponds to the second conductive portion 122, and the second electrode portion 142 is connected to the second conductive portion 122 through a second via 132; the third electrode portion 143 corresponds to the third conductive portion 123, and the third electrode portion 143 is connected to the third conductive portion 123 through a third via 134; the second conductive layer 14 also includes a first connecting portion 144 located in the border area B1, and the first connecting portion 144 is connected to the conductive trace 124 through the connecting via 133.

[0163] In a possible implementation, Fig.30 As shown, after step S800 , the process further includes: forming a pixel defining layer 15 .

[0164] Specifically, the first film layer 154 , the second film layer 155 and the third film layer 156 are sequentially prepared by chemical vapor deposition process, and the first opening 151 for exposing the first connection portion 144 and the second opening 157 located in the display area AA are formed by dry etching process.

[0165] Specifically, the first opening 151 may include a first sub-opening 1511, a second sub-opening 1512 and a third sub-opening 1513 that are interconnected. The first sub-opening 1511 penetrates the first film layer 154, the second sub-opening 1512 penetrates the second film layer 155, and the third sub-opening 1513 penetrates the third film layer 156. The orthographic projections of the third sub-opening 1513, the second sub-opening 1512 and the first sub-opening 1511 on the substrate 11 are nested in sequence from the outside to the inside.

[0166] The second opening 157 may include a fourth sub-opening 1571, a fifth sub-opening 1572 and a sixth sub-opening 1573 stacked in sequence along the direction away from the substrate 11, and the outer boundary of the fifth sub-opening 1572 is larger than the outer boundary of the fourth sub-opening 1571, and larger than the outer boundary of the sixth sub-opening 1573, thereby helping to isolate the subsequently prepared film layers and improve the lateral crosstalk problem between adjacent light-emitting units.

[0167] In a feasible implementation, the material of the first film layer 154 includes silicon oxide, the material of the second film layer 155 includes silicon nitride, and the material of the third film layer 156 includes silicon oxide. When forming the second opening 157, a mask layer may be formed first, the mask layer includes an opening area to define the position of the second opening 157, and then:

[0168] A first step of dry etching is performed to form a pre-through hole penetrating the first film layer 154, the second film layer 155 and the third film layer 156 at the position of the second opening 157. The first step of dry etching can use CF4 gas, and the etching selectivity ratio of silicon oxide and silicon nitride is less than 1.5.

[0169] The second step of dry etching is used to etch the mask layer at a position in the mask layer opposite to the second opening 157 to expand the opening area, so that the opening area exposes the third film layer 156 below, and a step is formed between the mask layer and the third film layer 156 at the position of the opening area. The material of the mask layer can be optical glue (PR glue), and oxygen can be used for the second step of dry etching.

[0170] The third step of dry etching is used to remove the third film layer 156 exposed through the opening area. The third step of dry etching can use CF4 gas, and the etching selectivity ratio of silicon oxide and silicon nitride is less than 1.5. The fourth step of dry etching is used to etch the sidewalls of the pre-through hole located in the first film layer 154 and the second film layer 155. The fourth step of dry etching can use CF6 gas, and the etching selectivity ratio of silicon nitride and silicon oxide is greater than 6, so that the etching rate of silicon nitride is much greater than that of silicon oxide, so that the outer boundary of the fifth sub-opening 1572 in the formed second opening 157 is greater than the outer boundary of the fourth sub-opening 1571, and greater than the outer boundary of the sixth sub-opening 1573.

[0171] In another feasible embodiment, the first opening 151 and the second opening 157 can be prepared separately. The first opening 151 can be formed by one etching. The edge of the first opening 151 projected on the substrate 11 is located on the inner side or the outer side of the edge of the connecting via 133 projected on the substrate 11.

[0172] In a possible implementation, Fig.31As shown, in step S200, the substrate 11 includes a substrate 110 and a driving circuit layer 111 located on one side of the substrate 110, and a top metal 26 is formed on the side of the driving circuit layer 111 away from the substrate. The top metal 26 includes a portion located in the display area AA and a portion located in the frame area B1. The top metal 26 is used to form a conductive metal strip 261 to achieve connection between the electrode portion 140 and the internal structure of the driving circuit layer 111, and between the conductive trace 124 and the internal structure of the driving circuit layer 111. The top metal 26 can be prepared and patterned by a physical vapor deposition (PVD) process. Patterning can be performed by a dry etching process.

[0173] Specifically, it also includes forming a filling layer 27 through a high-density plasma chemical vapor deposition process and a chemical mechanical polishing (CMP) process. The filling layer 27 is arranged in the same layer as the top metal 26 to fill the gaps in the top metal 26, for example, the gaps between adjacent conductive metal strips 261.

[0174] The above steps also include: Fig.31 As shown, an insulating layer 28 is formed on the side of the top metal 26 facing away from the substrate 110, and the insulating layer 28 is patterned to form an electrical connection hole 281. The electrical connection hole 281 corresponds to the conductive metal strip 261, that is, the orthographic projection of the electrical connection hole 281 on the substrate 110 is located within the orthographic projection of the conductive metal strip 261 on the substrate 110, so that subsequent film layers can be connected to the conductive metal strip 261 through the electrical connection hole 281.

[0175] Specifically, the first conductive layer 12 is connected to the conductive metal strip 261 through the electrical connection hole 281 .

[0176] The above steps also include: Fig.31 As shown, the electrical connection portion 29 is formed in the electrical connection hole 281 .

[0177] Specifically, the entire metal layer 30 is formed, and then the portion of the insulating layer 28 located away from the substrate 110 is removed by a chemical mechanical polishing process, leaving only the portion of the metal layer 30 located in the electrical connection hole 281 to form the electrical connection portion 29 .

[0178] Specifically, the material of the metal layer 30 may include any one of Al, Cu, W, and Ti.

[0179] The present application also provides a display device 2, such as Fig.32 As shown, it includes any one of the display panels 1 provided in the above embodiments of the present application, or includes a display panel 1 prepared by any one of the display panel 1 preparation methods provided in the above embodiments of the present application.

[0180] In the display device 2 , the yield of the display panel 1 is significantly improved, thereby improving the yield of the display device 2 .

[0181] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a frame area outside the display area, and the display panel includes: substrate; A first conductive layer, located on one side of the substrate, the first conductive layer comprising conductive traces located in the border area; an isolation material layer, located on a side of the first conductive layer away from the substrate, and including a connection via located in the border area; A second conductive layer, located on a side of the isolation material layer away from the substrate, the second conductive layer comprising a first connecting portion located in the border area, the first connecting portion being connected to the conductive trace through the connecting via; A pixel defining layer is located on a side of the second conductive layer away from the substrate, the pixel defining layer includes a first opening for exposing the first connecting portion, an edge of the first opening projected on the substrate has no overlap with an edge of the connecting via projected on the substrate, and a slope angle of the first opening is smaller than a slope angle of the connecting via.

2. The display panel according to claim 1, characterized in that: The edge of the first opening projected onto the substrate is located on the inner side of the edge of the connecting via projected onto the substrate, and the portion of the pixel defining layer located within the connecting via includes an inclined portion and a flat portion that are connected to each other, the inclined portion is located on the side wall of the connecting via, and the flat portion is located on the bottom wall of the connecting via and surrounds the first opening.

3. The display panel according to claim 1, characterized in that: The edge of the orthographic projection of the first opening on the substrate is located outside the edge of the orthographic projection of the connecting via on the substrate, the first connecting portion includes a first portion located inside the connecting via and a second portion located outside the connecting via, and the boundary of the orthographic projection of the first opening on the substrate is located between the inner boundary and the outer boundary of the orthographic projection of the second portion on the substrate.

4. The display panel according to claim 1, characterized in that: The slope angle of the first opening is in the range of 20°-50°, and / or the slope angle of the connecting via is in the range of 40°-50°.

5. The display panel according to any one of claims 1 to 4, characterized in that: The first conductive layer further comprises at least a first conductive portion and a second conductive portion located in the display area; The isolation material layer further includes at least a first via hole and a second via hole located in the display area; The second conductive layer also includes at least a first electrode portion and a second electrode portion located in the display area, the first electrode portion corresponds to the first conductive portion, and the first electrode portion is connected to the first conductive portion through the first via hole; the second electrode portion corresponds to the second conductive portion, and the second electrode portion is connected to the second conductive portion through the second via hole; the thickness of the isolation material layer between the first electrode portion and the first conductive portion is h1, the thickness of the isolation material layer between the second electrode portion and the second conductive portion is h2, and the thickness of the isolation material layer between the first connecting portion and the conductive trace is h3, h1>h2, h3≥h1.

6. The display panel according to claim 5, characterized in that: The pixel defining layer includes a first film layer, a second film layer and a third film layer stacked in a direction away from the substrate, the first opening includes a first sub-opening, a second sub-opening and a third sub-opening that are interconnected, the first sub-opening passes through the first film layer, the second sub-opening passes through the second film layer, and the third sub-opening passes through the third film layer, and the orthographic projections of the third sub-opening, the second sub-opening and the first sub-opening on the substrate are nested in sequence from the outside to the inside.

7. The display panel according to claim 6, characterized in that: The isolation material layer includes a first isolation layer, a second isolation layer and a third isolation layer stacked in a direction away from the substrate, the connecting via includes a first sub-via and a first through hole that are interconnected, the first sub-via penetrates the first isolation layer, the first through hole penetrates the second isolation layer and the third isolation layer, and the orthographic projection of the first sub-via on the substrate is located on the inner side of the orthographic projection of the first through hole on the substrate.

8. The display panel according to claim 7, characterized in that: The first through hole includes a second sub-via and a third sub-via, the second sub-via passes through the second isolation layer, the third sub-via passes through the third isolation layer, and the orthographic projections of the third sub-via, the second sub-via and the first sub-via on the substrate are nested in sequence from outside to inside.

9. The display panel according to claim 2, characterized in that: The pixel defining layer includes a second opening for exposing the first electrode portion and the second electrode portion, and the second opening includes a fourth sub-opening, a fifth sub-opening and a sixth sub-opening stacked in sequence along a direction away from the substrate, and an outer boundary of the fifth sub-opening is larger than an outer boundary of the fourth sub-opening and larger than an outer boundary of the sixth sub-opening.

10. The display panel according to claim 9, characterized in that: The pixel defining layer includes a first film layer, a second film layer and a third film layer stacked in a direction away from the substrate, the fourth sub-opening penetrates the first film layer, the fifth sub-opening penetrates the second film layer, and the sixth sub-opening penetrates the third film layer.

11. The display panel according to claim 9, characterized in that: It also includes an organic material layer and a third conductive layer stacked along a direction away from the second conductive layer, the organic material layer includes a plurality of light-emitting layers, the light-emitting layers are located at the second opening, the third conductive layer is located at a side of the organic material layer and the pixel defining layer away from the substrate, and the third conductive layer is connected to the first connecting portion through the first opening; The conductive traces are arranged around the display area.

12. The display panel according to claim 1, characterized in that: The material of the second conductive layer includes a transparent conductive material, and the display panel also includes a first metal layer located between the second conductive layer and the isolation material layer, the first metal layer includes a first transition portion, a second transition portion and a third transition portion, the first electrode portion is connected to the first conductive portion through the first transition portion, the second electrode portion is connected to the second conductive portion through the second transition portion, and the first connection portion is connected to the conductive trace through the third transition portion.

13. The display panel according to claim 1, characterized in that: The first conductive layer also includes a third conductive portion located in the display area, the isolation material layer also includes a third via hole located in the display area, the second conductive layer also includes a third electrode portion located in the display area, the third electrode portion corresponds to the third conductive portion, the third electrode portion is connected to the third conductive portion through the third via hole, and the thickness of the isolation material layer between the third electrode portion and the third conductive portion is h4, h1>h4.

14. The display panel according to claim 13, characterized in that: The isolation material layer includes a first isolation layer, a second isolation layer and a third isolation layer stacked in a direction away from the substrate, the first isolation layer, the second isolation layer and the third isolation layer are arranged between the first electrode part and the first conductive part, the second isolation layer and the third isolation layer are arranged between the second electrode part and the second conductive part, the third isolation layer is arranged between the third electrode part and the third conductive part, and the first isolation layer, the second isolation layer and the third isolation layer are arranged between the first connecting part and the conductive trace.

15. The display panel according to claim 1, characterized in that: It also includes a filling portion disposed in the same layer as the first conductive layer, and a height difference between a surface of the first conductive layer facing away from the substrate and a surface of the filling portion facing away from the substrate is less than 50 angstroms.

16. The display panel according to claim 13, characterized in that: The slope angles of the first via hole, the second via hole and the third via hole range from 40° to 50°.

17. A method for preparing a display panel, characterized in that: The display panel includes a display area and a frame area outside the display area, and the preparation method includes: providing a substrate; forming a first conductive layer on one side of the substrate, the first conductive layer comprising conductive traces located in the border area; forming an isolation material layer on a side of the first conductive layer away from the substrate, wherein the isolation material layer includes a connection via located in the frame area; A second conductive layer is formed on a side of the isolation material layer away from the substrate, wherein the second conductive layer includes a first connecting portion located in the border area, and the first connecting portion is connected to the conductive trace through the connecting via; A pixel defining layer is formed on a side of the second conductive layer facing away from the substrate, the pixel defining layer includes a first opening for exposing the first connecting portion, an edge of the first opening projected onto the substrate has no overlap with an edge of the connecting via projected onto the substrate, and a slope angle of the first opening is smaller than a slope angle of the connecting via.

18. A display device, characterized in that: A display panel comprising any one of claims 1 to 16, or a display panel prepared by the preparation method according to claim 17.

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