Discrete semiconductor device package

Abstract

A package (10) includes a semiconductor die (130) attached to a substrate (100) and a mold body (140) encapsulating the semiconductor die. A first portion (1-1, 2-1, 3-1) of the lead is directly bonded to a contact pad (SP, SSP, GP) on the semiconductor die without an intermediate feature between the first portion of the lead and the contact pad. The second portion of the lead extends out of the mold body to form a packaged external terminal (1-0, 2-0, 3-0, 4-0, 5-0, 6-0, 7-0). The lead is a double gauge lead in which a first portion of the lead has a thickness perpendicular to the contact pad that is less than a thickness of a second portion of the lead extending outside the die body.

Description

[0001] Related Applications

[0002] This application claims priority to and the benefit of U.S. patent application No. 18 / 185,514, filed on March 17, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] This specification relates to packaging of semiconductor dies and integrated circuits. Background Art

[0004] A semiconductor package consists of a metal, plastic, glass, or ceramic housing that contains one or more semiconductor devices or integrated circuits. Individual components are manufactured on semiconductor wafers (usually silicon or silicon carbide wafers) before being cut into dies, tested, and packaged. The package provides a means of connecting the semiconductor device or integrated circuit to an external environment such as a printed circuit board via leads such as pads, balls, or pins; as well as protection against threats such as mechanical shock, chemical contamination, and light exposure. With the growing demand for high-performance ICs, new improvements in packaging technology are needed to maximize the performance and reliability of ICs. Summary of the invention

[0005] In a general aspect, a package includes a semiconductor die attached to a substrate and a mold body encapsulating the semiconductor die. A first portion of a lead is directly bonded to a contact pad on the semiconductor die without an intermediate component between the first portion of the lead and the contact pad. A second portion of the lead extends outside the mold body to form an external terminal of the package.

[0006] In yet another aspect, the lead is a dual gauge lead wherein a first portion of the lead has a thickness perpendicular to the contact pad that is less than a thickness of a second portion of the lead extending outside the mold body.

[0007] In a general aspect, a package includes a semiconductor die attached to a substrate and a mold body encapsulating the semiconductor die. A first portion of a first lead is directly attached to a source contact pad on the semiconductor die, and a second portion of the first lead extends outside the mold body to form an external source terminal of the package. The first portion of the first lead is directly attached to the source contact pad, and there is no intermediate component between the first portion of the first lead and the source contact pad. In addition, a first portion of a second lead is directly attached to a gate contact pad on the semiconductor die, wherein the second portion of the second lead extends outside the mold body to form an external gate terminal of the package. The first portion of the second lead is directly attached to the gate contact pad, and there is no intermediate component between the first portion of the first lead and the source contact pad.

[0008] In a general aspect, a method includes: placing a semiconductor device die on a substrate, and directly attaching a second portion of a lead to a device contact pad on the semiconductor device die without an intermediate component between the lead and the device contact pad. The lead is a double gauge lead, wherein the thickness of the second portion of the lead is less than the thickness of the first portion of the lead. The method also includes encapsulating the semiconductor device die in a mold body, wherein the first portion of the lead extends outside the mold body.

[0009] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A semiconductor device package is shown in cross-section.

[0011] Figure 2 An example direct lead attach (DLA) clip is shown in a top plan view and includes pre-formed leads that can be attached directly to device contact pads of a semiconductor die in a package.

[0012] FIG. 3A to FIG. 3C Various views of a package assembly including a DLA clip coupled to a substrate are shown.

[0013] Figure 4 An example rolled substrate frame including an array of substrates and an array of DLA clips is shown.

[0014] Figure 5 An example method for manufacturing a semiconductor device package is shown.

[0015] FIG. 6A to FIG. 6G Cross-sectional views of a device package at different stages of construction are shown. DETAILED DESCRIPTION

[0016] A semiconductor device package includes a semiconductor die mounted on a lead frame structure that includes leads that provide external electrical connections (external to the package) for a single device or integrated circuit in the semiconductor die. The semiconductor die can be mounted on a paddle or flag in the lead frame structure using solder or a conductive adhesive. In addition, the device contact pads on the semiconductor die are electrically connected to corresponding leads in the leads using wire bonding (e.g., aluminum wire bonding). The leads extending outside the package body form external terminal pins that can be used to mount the package on a printed circuit board or terminal strips. In example embodiments, the terminal pins can be mounted in a socket or soldered to a printed circuit board (PCB) or terminal strips.

[0017] There are a variety of package types used in various applications. Some are defined by international, national or industry standards, while others are specific to a single manufacturer. The number and configuration of the external terminal pins of a package type may be defined by international, national or industry standards.

[0018] For device or IC packaging, the coefficient of thermal expansion (CTE) mismatch between the semiconductor die and the lead frame (e.g., copper lead frame) or the CTE mismatch between the clip (e.g., copper clip) and the semiconductor die can introduce high stress on the solder between the components. Cracks can be observed after temperature cycling. In addition, wire fatigue (of the aluminum wire connecting the gate of the semiconductor die and the lead frame) can be a weak point in typical packages during power cycling.

[0019] The packaging embodiments described herein address these issues and provide a cost-effective and reliable solution for packaging a semiconductor die (eg, a power transistor, a silicon carbide (SiC) MOSFET, or another device).

[0020] In accordance with principles of the present disclosure, in example packaging implementations, a frit (eg, a silver (Ag) frit, a silver-based frit) may be used to couple, join, or attach two different components of a semiconductor die package to one another.

[0021] During the sintering process, the sintering substance (e.g., Ag atoms) can diffuse into the two different components and hold the two different components together. Sintering improves the reliability of attaching (bonding) the two components together by avoiding the use of an intermediate bonding layer (e.g., solder or adhesive) that may crack during temperature cycling, for example. In an example embodiment, for example, the Ag-based sinter can be used to attach a semiconductor die to a die attach pad (DAP) in a lead frame structure.

[0022] In addition, according to the principles of the present disclosure, a direct lead attachment (DLA) process can be used to directly (e.g., directly contact without wire connections or other intermediate elements) attach leads forming external terminals of the package to device contact pads (e.g., source contact pads, gate contact pads, sense contact pads, and drain contact pads) on the semiconductor die.

[0023] The first portion of the lead forms an external terminal of the package, and the second portion of the lead is attached to a device contact pad (e.g., a source contact pad, a gate contact pad, a sense contact pad, and a drain contact pad) on the semiconductor die. In an example embodiment, the lead can be a double-gauge lead, wherein the first portion of the lead has a first thickness and the second portion of the lead has a second thickness. The second thickness can be the same as or less than the first thickness.

[0024] The first thickness can determine the strength and rigidity of external terminals used to couple the package to a socket or PCB (e.g., in a customer application). However, using large external terminals for leads within the package (which are attached to device contact pads on the semiconductor die) can reduce the structural integrity of the package (e.g., during thermal cycling). Large leads within the package can cause proportionally large expansion and contraction stresses at the lead-device contact pad interface or in the mold body, for example, during power cycling of the package, which can cause cracking. Using leads of smaller thickness (e.g., a second thickness less than the first thickness) within the package can reduce expansion and contraction stresses that may be generated at the lead-device contact pad interface or in the mold body, for example, during power cycling of the package.

[0025] The use of dual gauge leads allows issues of external terminal strength and reliability to be addressed independently of issues of the internal structural integrity and reliability of the package during power cycling.

[0026] Figure 1 A cross-sectional view of a package 10 is shown, according to the principles of the present disclosure, which includes components coupled together by sintering (eg, Ag sintering, etc.) and uses dual gauge leads.

[0027] In the package 10 (e.g., a discrete semiconductor device package), a semiconductor die 130 (e.g., a 1200V SiC MOSFET, with a maximum current of about 600A and a power of about 500KW) is encapsulated in a mold (e.g., mold 140) made of epoxy resin or molding compound. The semiconductor die 130 may be disposed on a die attach pad (e.g., DAP 120) on a surface S of a substrate 100 in the package. The semiconductor die 130 may be attached to the DAP 120 by a sinter (e.g., a silver-based sinter (e.g., Ag sinter 131)). A lead (e.g., lead 3) may be attached to a device contact pad (e.g., a source contact pad, not shown) on the semiconductor die 130. In an example embodiment, the source contact pad may have a width greater than 1.0 mm and a current carrying capacity greater than 200 amperes.

[0028] Lead 3 may include a lead portion (e.g., lead portion 3-0) forming an external terminal of the package and a lead portion (e.g., source lead extension 3-1) terminating in a source contact lead region SL attached to a device contact pad on semiconductor die 130. The source contact lead region SL may be attached to the device contact pad on semiconductor die 130 by a sinter (e.g., Ag sinter (e.g., Ag sinter 132)).

[0029] In an example embodiment, the lead portion 3-0 forming the external terminal of the package may extend in the y direction and generally lie in the xy plane. The source contact lead region SL may generally lie in another xy plane (parallel to the device contact pads on the semiconductor die 130) that is offset from the xy plane of the lead portion 3-0 by a distance Z1. In the lead 3.0, the source lead extension 3-1 may be bent to continuously transition over the distance Z1 from the xy plane of the lead portion 3-0 to the xy plane of the source contact lead region SL.

[0030] Lead 3 may be a dual gauge lead, in which one lead portion 3-0 has a thickness TE and one lead portion (e.g., source lead extension 3-1) has a different thickness TI (in the z direction). According to industry standards for device packaging, thickness TE may correspond to the thickness requirement for coupling the external terminal formed by lead portion 3-0 to a printed circuit board. For example, for industry standard D2PAK, thickness TE may be approximately 0.5 mm. In an example embodiment, thickness TI of source lead extension 3-1 (including source contact lead region SL) may be the same as TE or less than TE (taking into account the reduction of mechanical stress at the interface between source contact lead region SL and semiconductor die during power cycling). In an example embodiment, thickness TI may be in the range of about 0.1 mm to about 0.4 mm (e.g., 0.125 mm), while TE is about 0.5 mm. More generally, in an example embodiment, the ratio of thickness TE to thickness T1 may be in the range of 0.2 to 1.0 (i.e., 20% to 100%). In example embodiments, substrate 100 may be coupled to a header portion (eg, header 110) above the substrate (eg, in the y-direction). Header 110 may be electrically connected to DAP 120 through the substrate and may be a drain or ground terminal of a semiconductor die in a package.

[0031] When manufacturing a stand-alone semiconductor device package according to the principles of the present disclosure, the lead frame structure may include a lead preform or clip (hereinafter referred to as a direct lead attachment clip or "DLA clip"), which includes leads that can be directly attached to the device contact pads. The leads may include dual-gauge leads. The DLA clip may include a collar (e.g., a copper (Cu) collar) that holds a single lead that is directly attached to the corresponding contact pads on the semiconductor die (e.g., source contact pads, gate contact pads, sense contact pads, and drain contact pads, etc.) and forms the corresponding external terminal leads of the package. The directly attached leads can be attached to the corresponding contact pads on the semiconductor die using Ag sinter. The directly attached leads can replace some or all of the aluminum wire bonds that can be used to connect the contact pads on the semiconductor die (e.g., source contact pads, gate contact pads, sense contact pads, and drain contact pads) to the corresponding external terminal leads of the package.

[0032] The foregoing principles of the present disclosure (e.g., using Ag sinter to attach the semiconductor die to the DAP, using a direct lead attach (DLA) process to form external terminals coupled to the device contact pads) can be used to manufacture any type of package. However, for the purpose of illustration, this document will focus on semiconductor device packages (e.g., discrete semiconductor device packages, Figure 6G ) in the context of Figures 1 to 6G Further discussing these principles, the semiconductor device package can be configured as, for example, a three-terminal D2PAK-3L or a seven-terminal D2PAK-7L type package.

[0033] The lead frame structure of the device package may include a DAP substrate (eg, substrate 100) and a direct lead attach (DLA) clip (eg, DLA clip 200, Figure 2 ) in the preformed leads.

[0034] Figure 2 An example direct lead attach clip (eg, DLA clip 200 ) is shown that includes preformed leads that can be directly attached to device contact pads of a semiconductor die in a package and form external terminals of the package.

[0035] The DLA clip 200 may include a plurality of metal strips or leads (e.g., lead 1, lead 2, lead 3, lead 4, lead 5, lead 6, and lead 7). An annular ring or collar 210 having, for example, a width CW (in the x-direction) and a height CH (in the y-direction) may hold portions (e.g., lead portion 1-0, lead portion 2-0, lead portion 3-0, lead portion 4-0, lead portion 5-0, lead portion 6-0, and lead portion 7-0, etc.) of the plurality of metal strips (e.g., leads 1-7). These lead portions may extend from a top portion CT of the collar 210 (in the y-direction) to a bottom portion CB of the collar 210 and may generally lie in a plane (e.g., an xy plane) of the collar 210. These lead portions may be precursors to external terminals (e.g., gate terminals, sense terminals, and source terminals) of a package using the DLA clip 200. In example embodiments, a lead portion (eg, lead portion 1-0) may have a width w (eg, in the x-direction) and a thickness TE (eg, in the z-direction). Figure 1 ).

[0036] In example embodiments, lead portions (e.g., lead portion 1-0, lead portion 2-0, lead portion 3-0, lead portion 4-0, lead portion 5-0, lead portion 6-0, lead portion 7-0, etc.) may be separated from adjacent lead portions by a gap (e.g., distance g) in the x-direction. Figure 2For example, lead portion 1.0 (extending in the y direction) is shown to be spaced apart from adjacent lead portion 2.0 in the x direction by a gap (e.g., distance g). Lead portion 1.0 (extending in the y direction) is also spaced apart from side CS of collar 210 in the x direction by a gap (e.g., distance g).

[0037] The leads (e.g., lead 1, lead 2, lead 3, lead 4, lead 5, lead 6, lead 7, etc.) in the DLA clip 200 may also include lead portions or extensions (e.g., gate lead extension 1-1, sense lead extension 2-1, and source lead extension 3-1) extending above the top CT of the collar 210. These extensions extending in three dimensions (e.g., x, y, and z) from above the top CT of the collar 210 may be located in regions (e.g., gate contact lead region GL, sense contact lead region SSL, sense contact lead region SSL) that may be coupled (e.g., via Ag sinter or other conductive material) to device contact pads (e.g., source contact pad, gate contact pad, and sense contact pad) on the semiconductor die. Figure 3B ) and the source contact lead region SL). In example embodiments, the source contact lead region SL may have a width W (eg, in the x-direction) and a thickness (eg, a thickness TI, in the z-direction, Figure 1 ).

[0038] In an example embodiment, the lead portions or extensions (e.g., gate lead extension 1-1, sense lead extension 2-1, and source lead extension 3-1) extending above the top portion CT of the collar 210 may at least initially extend a distance in the same direction (e.g., y direction) as the corresponding lead portions (e.g., lead portion 1-0, lead portion 2-0, lead portion 3-0) below the top portion CT of the collar 210. In some embodiments, the lead portions or extensions (e.g., lead portion 1-1, lead portion 2-1) may then change direction and zigzag in the x and z directions so that the contact lead regions (e.g., gate contact lead region GL, sense contact lead region SSL, source contact lead region SL) at the ends of the lead portions or extensions (e.g., lead portion 1-1, lead portion 2-1, lead portion 3-1) are substantially aligned with the contact lead regions GL, sense contact lead region SSL, source contact lead region SL, Figure 3B ) are aligned to attach to device contact pads present on the surface of the semiconductor die (e.g., source contact pad SP, sense contact pad SSP, and gate contact pad GP on semiconductor die 130, Fig.6D ).like Figure 2As shown, for example, the gate lead extension 1-1 may extend a distance Dy1 in the y direction above the collar 210, then extend a distance Dx in a zigzag direction to the right in the x direction, and then extend a distance Dy2 in the y direction to the end of the gate contact lead region GL. The step of the gate lead extension 1-1 in the z direction is Figure 2 is not visible in two dimensions, but is formed by the Figure 2 The width of the gate lead extension 1 - 1 is indicated by a pair of double lines Sz that are close to each other.

[0039] In example embodiments, some leads may share a common lead portion or extension. Figure 2 As shown in , a plurality of leads (eg, lead 3, lead 4, lead 5, lead 6, and lead 7) are connected to and share a common lead extension (ie, source lead extension 3-1).

[0040] The DLA clip 200 may be made from sheet metal (eg, copper) by cutting, stamping, or other material forming and removal processes.

[0041] FIG. 3A to FIG. 3C Various views of a package assembly 300 including a DLA clip 200 coupled to a substrate 100 are shown. Figure 3A 2 shows a top plan view of the package assembly 300, Figure 3B A side perspective view of the package assembly is shown, and Figure 3C A cross-sectional side view of the package assembly is schematically shown.

[0042] like FIG. 3A to FIG. 3C As shown, substrate 100, which may be made of a substrate made of metal (e.g., copper), includes a die attach pad (e.g., DAP 120) formed on a top surface S of the substrate. DAP 120 may, for example, have a rectangular area having a height ph (in the y direction) and a width pw (in the x direction). Substrate 100 may include a header portion (e.g., header 110) above DAP 120 (e.g., in the y direction). The header portion (e.g., header 110) may be electrically connected to DAP 120 through the substrate.

[0043] A semiconductor die (eg, semiconductor die 130) may be disposed on and attached to DAP 120. Semiconductor die 130 (eg, SiC MOSFET device) may be bonded to the DAP 120, for example, by a layer of Ag sinter (on FIG. 3A to FIG. 3C 1 (not visible in FIG. 1 ) is attached to DAP 120. Top surface SD of semiconductor die 130 may include FIG. 3A to FIG. 3C Device contact pads not visible in the image (e.g., source contact pads, sense contact pads, and gate contact pads, Fig.6D )).

[0044] In addition, the lead portions (e.g., gate lead extension 1-1, sense lead extension 2-2, and source lead extension 3-1) extending above the top portion CT of the collar 210 of the DLA clip 200 may be coupled to device contact pads (e.g., source contact pad, sense contact pad, and gate contact pad) of the semiconductor die 130. In an example embodiment, end regions (e.g., gate contact lead region GL, sense contact lead region (not shown), source contact lead region SL) of the gate lead extension 1-1, sense lead extension 2-1, and source lead extension 3-1 may be coupled (e.g., by Ag sinter or other conductive material) to corresponding device contact pads on the semiconductor die 130.

[0045] In an example embodiment, the width W of the source contact lead region SL in the DLA clip 200 may vary (during the manufacture of the DLA clip 200), for example, in proportion to the size of the target die (e.g., die 130). In an example embodiment, for a die width dw of about 5.2 mm, the width W of the source contact lead region SL may be equal to about 3.0 mm; for a die width dw of about 4.7 mm, the width W may be equal to about 2.5 mm; and for a die width dw of about 4.2 mm, the width W may be equal to about 2.0 mm.

[0046] In some embodiments, some of the lead portions in DLA clip 200 (e.g., lead portion 1-0, lead portion 2-0, lead portion 3-0, lead portion 4-0, lead portion 5-0, lead portion 6-0, and lead portion 7-0, etc.) can be redundant or repeated. For example, lead portion 1-0 and lead portion 2-0 can be used to form external terminals of the package for gate contact pads and sense contact pads on a semiconductor die. Lead portion 3-0 can be used to form external terminals for source contact pads on a semiconductor die. Lead portions 4-0 to 7-0 (connected to lead portion 3-1) can be repeated or redundant in at least the following sense: any of these lead portions can be used instead of lead portion 3-0 to form external terminals for source contact pads on a semiconductor die, such as in a three-terminal D2PAK-3L type package.

[0047] After the DLA clip 200 is coupled to the substrate 100 by sintering the leads with Ag to the corresponding device contact pads on the semiconductor die 130, the collar 210 can be removed (e.g., cut) from the DLA clip 200. In addition, redundant or duplicate leads or lead portions that are not needed to form external terminals of the device package can be removed from the DLA clip 200. For example, for a three-terminal D2PAK-3L type package, lead portions 1-0, lead portions 2-0, and lead portions 3-0 can be used as external terminals for the gate, sense, and source of the device. Lead portions 4-0 to 7-0 that are duplicates of lead portion 3-0 can be removed from the assembly at the same time as the collar 210 is removed.

[0048] Figure 3C A side view of the package assembly after removal of the collar 210 and the repeating lead portions 4 - 0 to 7 - 0 is schematically shown.

[0049] In an example embodiment, for an automated (or partially automated) assembly line configuration for a package (e.g., a device package), an array of substrates (e.g., substrate 100) and an array of DLA clips (e.g., DLA clip 200) may be provided on a wound substrate frame. The array of substrates and the array of DLA clips may be held in the wound substrate frame between a pair of spaced-apart flow channel strips having reference holes. The wound substrate frame including the array of substrates may be manufactured by electroplating copper traces and pads (on a PCB sheet).

[0050] Figure 4 An example rolled substrate frame 400 is shown that includes an array of substrates 100 (eg, array 40A) and an array of DLA clips 200 (eg, array 42A).

[0051] The substrate frame 400 may include spaced apart perforated runner strips. The runner strips may include reference holes 410 to help position and align the wound substrate frame 400 with, for example, assembly line processing tools (eg, singulation tools, die pick and place tools, material injection tools, etc.).

[0052] Figure 5 An example method 500 for fabricating a discrete semiconductor device package is shown.

[0053] Method 500 may include placing a semiconductor device die on a substrate (510), and attaching a second portion of a lead to a device contact pad on the semiconductor device die (520). The lead may be a dual gauge lead, wherein the thickness of the second portion of the lead is less than the thickness of the first portion of the lead.

[0054] The method 500 may further include encapsulating the semiconductor device die in a mold body, wherein first portions of the leads extend outside the mold body ( 530 ). The first portions of the leads extending outside the mold body may be formed as external terminals of a discrete semiconductor device package.

[0055] In an example implementation of method 500, disposing the semiconductor device die on the substrate 510 may include bonding the semiconductor device die to a die attach pad (DAP) on the substrate using an adhesive material (e.g., solder, solder bumps, solder paste, or adhesive paste) to bond the die to the DAP. In an example implementation, bonding the semiconductor device die to the die attach pad (DAP) on the substrate may include bonding the die to the DAP using a silver-based sinter.

[0056] Furthermore, attaching the second portion of the lead to the device contact pad on the semiconductor device die may include bonding the second portion of the lead to the device contact pad. In example embodiments, bonding the second portion of the lead to the device contact pad may include bonding the second portion of the lead to the device contact pad using an adhesive material (e.g., solder, solder bump, solder paste, or adhesive paste). In example embodiments, attaching the second portion of the lead to the device contact pad may include bonding the second portion of the lead to the device contact pad using a silver-based sinter.

[0057] In an example embodiment, the device contact pad is a source contact pad of a semiconductor device die.The source contact pad may have a width greater than 1.0 mm and a current carrying capacity greater than 200 amps.

[0058] In an example embodiment of method 500, the lead may be a first lead, and placing the semiconductor device die on the substrate 510 may include attaching a direct lead attach (DLA) clip to the semiconductor die. The DLA clip may include a plurality of leads including a first lead attached to an annular collar. Each of the plurality of leads may be a dual gauge lead, wherein a second portion of the lead has a thickness less than a thickness of the first portion of the lead. A first portion of the plurality of leads including a first portion of the first lead may extend between a top and a bottom of the collar. A second portion of the plurality of leads including a second portion of the first lead may extend above a top of the annular collar.

[0059] In an example embodiment, the plurality of leads attached to the annular collar may include up to seven leads (eg, Figure 2 In an example embodiment, some of the leads may share a common second lead portion or extension. Figure 2 As shown in , a plurality of leads (eg, lead 3, lead 4, lead 5, lead 6, and lead 7) are connected to and share a common second lead portion (ie, source lead extension 3-1).

[0060] In example embodiments, attaching the second portion of the lead to a device contact pad on a semiconductor device die may include attaching a second portion of a first lead of the plurality of leads to a first device contact pad, attaching a second portion of a second lead of the plurality of leads to a second device contact pad, and attaching a second portion of a third lead of the plurality of leads to a third device contact pad on the semiconductor die. Attaching the second portions of the first lead, the second lead, and the third lead to the respective device contact pads may include Ag-based sintering.

[0061] The method 500 may include encapsulating the semiconductor device die in a mold body 530 after attaching the first lead, the second lead, and the second portion of the third lead to the corresponding device contact pads. The method 500 may also include removing (e.g., cutting) the annular collar to individually separate the first portion of the leads attached to the annular collar. The method 500 may also include forming the first portion of the leads extending outside the mold body into an external terminal of the discrete semiconductor device package.

[0062] FIG. 6A to FIG. 6G Device packages (eg, discrete semiconductor device packages 600, 610, 620, 630, 640, 650, 660, 670, 680, 690, 700, 710, 720, 730, 740, 760, 770, 780, 790, 800, 810, 820, 830, 840, 850, 860, 870, 880, 890, 900, 910, 920, 930, 940, 960, 970, 980, 990, 1000, 1010, 1020, 1030, 1040, 1050, 1060, 1070, 1080, 1 Figure 6G ) view.

[0063] Fig. 6A A substrate 100 of a discrete semiconductor device package is shown in a first stage of construction. The substrate 100 includes a die attach pad (e.g., DAP 120) formed on a top surface S of the substrate. In example embodiments, the DAP 120 may be a Cu pad, an Al pad, or a metal layer of a direct bond metal (DBM) substrate.

[0064] Figure 6B The substrate 100 of the discrete semiconductor device package is shown in a second construction stage. At this stage, a layer of Ag sintering material (Ag sinter 131) is provided on the DAP 120. The Ag sintering material may be, for example, a nano-scale Ag particle paste.

[0065] Figure 6CThe substrate 100 of the discrete semiconductor device package is shown in a third construction stage. At this stage, a semiconductor device die (e.g., semiconductor die 130) is disposed on the AG sinter 131 and subjected to a low temperature sintering process. The low temperature sintering of the AG sinter 131 may bond the semiconductor die 130 to the DAP 120. In an example embodiment, the low temperature sintering may involve a sintering temperature, for example, in a range of about 200° C. to about 300° C. (e.g., 250° C.). The sintering process may cause the sintering material (e.g., Ag substance) to be completely diffused into the semiconductor die 130 and the DAP 120, so that the semiconductor die 130 is directly bonded to the DAP 120 without leaving a significant residual sintering material layer or intermediate component between the semiconductor die 130 and the DAP 120 (in other words, the semiconductor die 130 is directly in contact with or directly bonded to the DAP 120).

[0066] Fig.6D The substrate 100 of the discrete semiconductor device package is shown in a fourth construction stage. At this stage, a layer of Ag sintering material (Ag sinter 132) is disposed on the device contact pads (e.g., source contact pad SP, sense contact pad SSP, and gate contact pad GP) present on the surface of the semiconductor die 130. The Ag sintering material (e.g., Ag sinter 132) may be composed of a nano-scale Ag particle paste like the Ag sinter 131.

[0067] Fig. 6E 1 shows a substrate 100 of a discrete semiconductor device package in a fifth stage of construction. At this stage, a DLA clip (eg, DLA clip 200) is coupled to the substrate 100. The DLA clip 200 (eg, Figure 2 The dual gauge leads (e.g., lead 1, lead 2, lead 3, lead 4, lead 5, lead 6, lead 7, etc.) are held in a collar (e.g., collar 210) with lead portions or extensions (e.g., gate lead extension 1-1, sense lead extension 2-1, and source lead extension 3-1) extending above a top portion CT of collar 210. These extensions extending in three dimensions (e.g., x, y, and z) from above the top portion CT of collar 210 terminate at lead contact regions (e.g., gate contact lead region GL, sense contact lead region (not shown), source contact lead region SL) which are directly coupled to device contact pads (e.g., source contact pad SP, sense contact pad SSP, and gate contact pad GP) present on a surface of semiconductor die 130, for example, through Ag sinter 132. Fig.6DThe sintering process may cause the sintering material to completely diffuse into the lead contact regions and the device contact pads, so that the lead contact regions (e.g., the gate contact lead region GL, the sense contact lead region SSL, and the source contact lead region SL) are directly bonded to the device contact pads (e.g., the source contact pad SP, the sense contact pad SSP, and the gate contact pad GP, Fig.6D ) without leaving a significant residual sintered material layer or intermediate component between the lead contact area and the device contact pad (in other words, the lead directly contacts or is directly bonded to the device contact pad).

[0068] In the sixth construction stage, Fig. 6F As shown, the semiconductor die 130 sintered to the substrate by Ag and the portions of the leads extending from the DLA clip 200 may be encapsulated in a mold body 140 made of a molding compound. Some portions of the DLA clip 200 including the collar 210 holding the lead portions (e.g., lead portions (e.g., lead portion 1-0, lead portion 2-0, lead portion 3-0, lead portion 4-0, lead portion 5-0, lead portion 6-0, and lead portion 7-0, etc.) remain outside the mold body 140.

[0069] In the seventh construction stage, the collar 210 is removed (e.g., by singulation). In addition, portions of the leads that are not needed to form external terminals may also be removed. Figure 6G In the example shown, all seven lead portions (lead portion 1-0, lead portion 2-0, lead portion 3-0, lead portion 4-0, lead portion 5-0, lead portion 6-0, and lead portion 7-0) are retained. In addition, these lead portions can be bent (e.g., stamped) into a desired shape to form external terminals of the package. In an example embodiment, the package (e.g., semiconductor device package 600) may be of a type intended to be surface mounted on a circuit board, wherein the external terminals are shaped to lie flat on the surface of a circuit board (e.g., a PCB). Figure 6G In the example shown, the lead portions are bent so that end portions thereof lie flat in the xy plane along the bottom of the mold body 140 .

[0070] It should be understood that in the foregoing description, when an element such as a layer, a region, a substrate or a part is mentioned as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected to or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, the element shown as being directly on an element, directly connected, or directly coupled can be mentioned in this manner. The claims of the present application (if any) may be revised to narrate the exemplary relationships described in the specification or shown in the drawings.

[0071] As used in this specification and claims, singular forms may include plural forms unless the context indicates otherwise. Spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to encompass different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent may include lateral adjacent or horizontal adjacent.

[0072] Some embodiments may be implemented using various semiconductor processing and / or packaging technologies. Some embodiments may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0073] Although certain features of the described embodiments have been described as described herein, those skilled in the art will now appreciate that many modifications, alternatives, variations, and equivalents are contemplated. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A package (10), comprising: a semiconductor die (130) attached to a substrate (100); A mold body (140) encapsulating the semiconductor die; first portions of leads (1, 2, 3, 4, 5, 6 and 7), the first portions of the leads being directly bonded to contact pads (SP, SSP, GP) on the semiconductor die without intermediate components between the first portions of the leads and the contact pads; as well as The second portions of the leads extend outside the mold body to form external terminals of the package (lead portion 1-0, lead portion 2-0, and lead portion 3-0).

2. The package of claim 1 , wherein the lead is a dual gauge lead, wherein the first portion of the lead has a thickness perpendicular to the contact pad that is smaller than a thickness of the second portion of the lead extending outside the mold body. The package of claim 1 , wherein the first portion of the lead has a thickness less than 0.5 mm. 4 . The package of claim 1 , wherein the contact pad is a source pad contact pad of the semiconductor die, the source pad contact pad having a width greater than 1.0 mm and a current carrying capacity greater than 200 amps. The package of claim 1 , wherein the semiconductor die is attached to the substrate by a sintering process. 6 . The package of claim 1 , wherein the first portion of the lead is directly attached to the contact pad by a sintering process.

7. The package of claim 1 wherein the semiconductor die is a silicon carbide (SiC) power transistor.

8. A package (10), comprising: a semiconductor die (130) attached to a substrate (100); A mold body (140) encapsulating the semiconductor die; a first portion of a first lead (1), the first portion of the first lead being directly attached to a source contact pad (SP) on the semiconductor die, a second portion of the first lead extending outside the mold body to form an external source terminal (1-0) of the package, the first portion of the first lead being directly attached to the source contact pad without an intermediate component between the first portion of the first lead and the source contact pad; as well as A first portion of a second lead (2), the first portion of the second lead being directly attached to a gate contact pad (GP) on the semiconductor die, a second portion of the second lead extending outside the mold body to form an external gate terminal (2-0) of the package, the first portion of the second lead being directly attached to the gate contact pad, and no intermediate component between the first portion of the first lead and the source contact pad. 9 . The package of claim 8 , wherein the first portion of the first lead is directly attached to the source contact pad by a sintering process.

10. The package of claim 8, wherein the first lead is a dual-gauge lead, wherein the first portion of the lead has a thickness perpendicular to the source contact pad that is smaller than a thickness of the second portion of the first lead extending outside the mold body. The package of claim 10 , wherein the first portion of the first lead has a thickness less than 0.5 mm.

12. The package of claim 8, wherein the source pad contact pad has a width greater than 1.0 mm and a current carrying capacity greater than 200 amps.

13. The package of claim 8, wherein the semiconductor die is attached to the substrate by a sintering process.

14. The package of claim 8, wherein the semiconductor die is a silicon carbide (SiC) power transistor.

15. A method comprising: Disposing a semiconductor device die on a substrate (510); attaching a second portion of a lead directly to a device contact pad on the semiconductor device die without an intermediate component between the lead and the device contact pad, the lead being a double gauge lead, wherein the thickness of the second portion of the lead is less than the thickness of the first portion of the lead (520); as well as The semiconductor device die is encapsulated in a mold body, wherein the first portion of the lead extends outside the mold body (530).

16. The method of claim 15, wherein disposing the semiconductor device die on the substrate comprises: The semiconductor device die is bonded to a die attach pad DAP on the substrate using a sintering process to bond the semiconductor device die to the DAP.

17. The method of claim 15, wherein attaching the second portion of the lead to the device contact pad on the semiconductor device die comprises: The second portion of the lead is bonded to the device contact pad using a sintering process.

18. The method of claim 15, wherein the lead is a first lead, the device contact pad is a first device contact pad, and disposing the semiconductor device die on the substrate comprises: A direct lead attach (DLA) clip is attached to the semiconductor device die, the DLA clip comprising a plurality of leads, wherein a first portion of the plurality of leads comprises the first portion of the first lead extending between a top and a bottom of a collar, and a second portion of the plurality of leads comprises the second portion of the first lead extending above the top of the collar.

19. The method of claim 18, wherein attaching the second portion of the lead to the device contact pad on the semiconductor device die comprises: Attach the second portion of the first lead of the plurality of leads to the first device contact pad, attach the second portion of the second lead of the plurality of leads to a second device contact pad, and attach the second portion of the third lead of the plurality of leads to a third device contact pad on the semiconductor device die.

20. The method of claim 19, wherein attaching the second portion of a second lead of the plurality of leads to the second device contact pad and attaching the second portion of the third lead of the plurality of leads to the third device contact pad comprises: Use sintering process.

21. The method of claim 20, wherein the first device contact pad is a gate contact pad, the second device contact pad is a sense contact pad, and the third device contact pad is a source contact pad of the semiconductor device die.

22. The method of claim 18, wherein encapsulating the semiconductor device die in the mold body, wherein the second portion of the lead extends outside the mold body, comprises: The semiconductor device die is encapsulated in the mold body, wherein the collar of the DLA clip is retained outside the mold body.

23. The method according to claim 22, further comprising: The ferrule is removed from the DLA clip to individually separate the first portion of the lead attached to the ferrule.

24. The method according to claim 23, further comprising: The first portions of the plurality of leads are shaped to form external terminals of a device package.

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