Silicon carbide semiconductor device, power module device, power conversion device, and moving object

Abstract

The purpose of the present invention is to provide a technique capable of improving surge tolerance in a silicon carbide semiconductor device having a built-in SBD. A silicon carbide semiconductor device includes a semiconductor layer of a first conductivity type provided with an active region including a unit cell region including a Schottky barrier diode region and a MOSFET region, and a surge energization region. The surge energization region includes a Schottky barrier diode replacement region in which a first conductivity type of the Schottky barrier diode region is replaced by a second conductivity type. The area ratio of the Schottky barrier diode replacement region to the active region is 0.01% or more and is less than the area ratio of the Schottky barrier diode region to the active region when the Schottky barrier diode replacement region is not replaced.

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device, a power module device, a power conversion device, and a moving object. Background Art

[0002] The following problem is known: if a forward current, i.e., a bipolar current, continues to flow through a pn diode provided in a semiconductor layer of silicon carbide (SiC), crystal defects such as stacking defects are generated in the crystal, and the forward voltage is shifted. It is believed that the reason for this is that the recombination energy when the minority carriers injected through the pn diode recombine with the majority carriers starts from the basal plane dislocations existing in the semiconductor layer of silicon carbide, and crystal defects such as stacking defects, which are surface defects, are expanded. This crystal defect hinders the flow of current, so if the crystal defect expands, the current decreases, the forward voltage increases, and the reliability of the silicon carbide semiconductor device decreases.

[0003] This increase in forward voltage also occurs in vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) using silicon carbide. Vertical MOSFETs have a body diode between the source and drain that serves as a parasitic pn diode. If a forward current flows through the body diode, the reliability of the vertical MOSFET will be reduced in the same way as the pn diode. Therefore, when the body diode of SiC-MOSFET is used as the return diode of the MOSFET, the MOSFET characteristics may be reduced.

[0004] As a structure for solving the reliability problem caused by the forward current flowing through the parasitic pn diode, a structure is proposed in which a unipolar diode is built into a silicon carbide semiconductor device that is a unipolar transistor such as a MOSFET to serve as a return diode. For example, Patent Documents 1 and 2 propose a structure in which a Schottky barrier diode (SBD) that is a unipolar transistor is built into a unit cell of a MOSFET.

[0005] In a silicon carbide semiconductor device including a unipolar transistor having a built-in unipolar diode, a bipolar current of a body diode, that is, a parasitic pn diode can be reduced during a reflux operation, thereby suppressing degradation of characteristics of the transistor. Prior art literature Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2003-017701 Patent Document 2: International Publication No. 2014 / 038110 Summary of the invention Technical problem to be solved by the invention

[0007] However, the pn diode as a bipolar diode has a low resistance due to conductivity modulation caused by bipolar action, but the SBD as a unipolar diode has a high resistance. Therefore, the energy generated when the SBD is energized is higher than the energy generated when the body diode as a pn diode is energized.

[0008] As a result, in the silicon carbide semiconductor device having a built-in SBD as described above, when a surge current such as a fault current flows through the SBD, the energy density generated is high, and a large amount of heat is generated in the SBD. Therefore, there is a problem that the breakdown withstand capacity for the surge current, i.e., the surge withstand capacity, is reduced.

[0009] Therefore, the present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to provide a technology capable of improving surge tolerance in a silicon carbide semiconductor device having a built-in SBD. Technical means for solving technical problems

[0010] The silicon carbide semiconductor device involved in the present disclosure includes: a semiconductor layer of the first conductivity type, the semiconductor layer of the first conductivity type is provided with an active area including a unit cell area and a surge power-on area, the unit cell area includes a Schottky barrier diode area and a MOSFET area, the surge power-on area includes a Schottky barrier diode replacement area that replaces the first conductivity type of the Schottky barrier diode area with a second conductivity type, the area ratio of the Schottky barrier diode replacement area to the active area is greater than 0.01%, and is less than the area ratio of the Schottky barrier diode area to the active area when it is not replaced with the Schottky barrier diode replacement area. Effects of the Invention

[0011] According to the present disclosure, during a longer backflow action caused by a surge current such as a fault current, the action of the pn diode formed in the Schottky barrier diode replacement region is linked, and the body diode in the active region plane acts earlier than when the Schottky barrier diode replacement region is not replaced, thereby reducing the energy density generated and improving surge tolerance.

[0012] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a plan view showing the structure of the silicon carbide semiconductor device according to the first embodiment. Figure 2 This is a plan view showing the structure of the silicon carbide semiconductor device according to the first embodiment. Figure 3 1 is a schematic cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment. Figure 4 1 is a schematic plan view showing the structure of the silicon carbide semiconductor device according to the first embodiment. Figure 5 1 is a schematic plan view showing the structure of the silicon carbide semiconductor device according to the first embodiment. Figure 6 1 is a schematic cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment. Figure 7 This is a plan view showing the structure of the silicon carbide semiconductor device according to the first embodiment. Figure 8 1 is a schematic cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment. Fig. 9 1 is a schematic cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment. Fig.10 This is a schematic cross-sectional view for explaining the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Fig.11 This is a schematic cross-sectional view for explaining the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Fig.12 This is a schematic cross-sectional view for explaining the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Fig.13 This is a schematic cross-sectional view for explaining the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Fig.14 This is a schematic cross-sectional view for explaining the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Fig.15 This is a schematic cross-sectional view for explaining the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Fig.16 This is a schematic cross-sectional view for explaining the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Fig.17 This is a schematic cross-sectional view for explaining the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Fig.18 FIG. 1 is a diagram showing simulation results of the silicon carbide semiconductor device according to the first embodiment. Fig.19This is a diagram for explaining switching of energization in the silicon carbide semiconductor device according to the first embodiment. Fig. 20 This is a diagram for explaining switching of energization in the silicon carbide semiconductor device according to the first embodiment. Fig.21 1 is a schematic cross-sectional view showing the structure of a silicon carbide semiconductor device according to the second embodiment. Fig. 22 This is a plan view showing the structure of a silicon carbide semiconductor device according to the third embodiment. Fig.23 This is a plan view showing the structure of a silicon carbide semiconductor device according to the third embodiment. Fig.24 1 is a schematic cross-sectional view showing the structure of a silicon carbide semiconductor device according to a third embodiment. Fig.25 1 is a schematic cross-sectional view showing the structure of a silicon carbide semiconductor device according to a third embodiment. Fig.26 This is a schematic cross-sectional view for explaining a method for manufacturing a silicon carbide semiconductor device according to the third embodiment. Fig. 27 This is a schematic cross-sectional view for explaining a method for manufacturing a silicon carbide semiconductor device according to the third embodiment. Fig.28 This is a schematic cross-sectional view for explaining a method for manufacturing a silicon carbide semiconductor device according to the third embodiment. Fig.29 This is a schematic cross-sectional view for explaining a method for manufacturing a silicon carbide semiconductor device according to the third embodiment. Fig.30 This is a schematic cross-sectional view for explaining a method for manufacturing a silicon carbide semiconductor device according to the third embodiment. Fig.31 This is a schematic cross-sectional view for explaining a method for manufacturing a silicon carbide semiconductor device according to the third embodiment. Fig.32 This is a block diagram showing the configuration of a power module device according to the fourth embodiment. Fig.33 This is a block diagram showing the configuration of a power conversion device according to the fifth embodiment. Fig.34 This is a diagram showing the structure of a moving object according to the sixth embodiment. DETAILED DESCRIPTION

[0014] In the following description, n and p represent the conductivity type of the semiconductor. In the present disclosure, the first conductivity type is n-type and the second conductivity type is p-type for description, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0015] Hereinafter, the embodiments will be described with reference to the accompanying drawings. In addition, the accompanying drawings are schematically shown, and the relationship between the sizes and positions of the images shown in different drawings is not necessarily accurately recorded and can be changed appropriately. In addition, in the following description, the same structural elements are marked with the same reference numerals for illustration, and their names and functions are also set to be the same. Therefore, detailed descriptions of them are sometimes omitted.

[0016] Hereinafter, a case where the silicon carbide semiconductor device is a SiC-MOSFET having a built-in SBD will be described. Compared with silicon semiconductor devices, silicon carbide semiconductor devices can achieve stable operation at high temperatures and high voltages, and high switching speeds.

[0017] <Implementation method 1> Figure 1 This is a plan view of the structure of the silicon carbide semiconductor device 100 according to the first embodiment as viewed from the upper surface. The silicon carbide semiconductor device 100 according to the first embodiment is a planar silicon carbide semiconductor device. Figure 1 In the embodiment, a gate pad 81 is formed on a part of the upper surface of the silicon carbide semiconductor device 100 , and a source electrode 80 is formed adjacent thereto. In addition, a gate wiring 82 extending from the gate pad 81 is formed.

[0018] (1) Planar stripe structure Figure 2 1 is a plan view of the silicon carbide layer of the silicon carbide semiconductor device 100 according to the first embodiment as viewed from the upper surface. Figure 2 Equivalent to Figure 1 FIG. 1 is a plan view in which the source electrode 80, the gate pad 81, and the gate wiring 82 are omitted. The silicon carbide semiconductor device 100 includes an active region including a unit cell region and a surge current conducting region. Figure 2 In the present invention, the unit cell regions are arranged side by side in a stripe shape, and the unit cell regions include an SBD region (Schottky barrier diode region) and MOSFET regions arranged on both sides of the SBD region. The structure of the silicon carbide semiconductor device 100 having the unit cell regions is called a "stripe type" structure.

[0019] Figure 2In the figure, the unit cell region is repeatedly arranged in one direction in a plan view, and the unit cell region includes an n-type first separation region 21 roughly corresponding to the SBD region, and a p-type first well region 30 roughly corresponding to the MOSFET region. The region formed by combining the unit cell region of the MOSFET with a built-in SBD and the surge current conduction region described later is called an active region. The region that is the periphery of the active region and includes the region where the gate pad 81 is formed, where the p-type second well region 31 and the like are formed, is called a terminal region.

[0020] Figure 3 The unit cell region is viewed from the long side of the stripe. Figure 1 A schematic cross-sectional view showing a schematic structure from a source electrode 80 to a gate wiring 82 at the outer periphery of a silicon carbide semiconductor device 100.

[0021] Figure 3 In the silicon carbide semiconductor device 100 shown in FIG. 1 , a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of low-resistance n-type silicon carbide. In the first embodiment, the semiconductor layer having the active region is the drift layer 20 on the semiconductor substrate 10, but it may also be the semiconductor substrate 10. Figure 3 As shown in the cross-sectional view, in the case of Figure 1 A second well region 31 made of p-type silicon carbide is provided in the surface portion of the drift layer 20 at the position of the region of the gate wiring 82 described above.

[0022] exist Figure 1 The first well region 30 made of p-type silicon carbide is provided in the surface layer portion of the drift layer 20 in the active region, which is the region below the source electrode 80 described in the above. Figure 2 As shown, the first well region 30 is formed in a stripe shape in a plan view. One well region in which a plurality of first well regions 30 are connected to each other may be provided, or a plurality of separated first well regions 30 may be provided.

[0023] like Figure 3 As shown, in the surface layer portion of the first well region 30 , a source region 40 made of n-type silicon carbide is formed at a position a certain distance inward from the outer periphery of the first well region 30 .

[0024] In the surface layer of the first well region 30, a contact region 35 made of low-resistance p-type silicon carbide is formed on one end side of the source region 40. Between adjacent contact regions 35, a first separation region 21 made of silicon carbide and penetrating the first well region 30 is formed. Figure 2As shown, the first separation region 21 is formed in a stripe shape. The conductivity type of the first separation region 21 is the same n-type as the drift layer 20, and the n-type impurity concentration of the first separation region 21 can be the same as the n-type impurity concentration of the drift layer 20, or can be higher or lower than the n-type impurity concentration of the drift layer 20.

[0025] like Figure 3 As shown, a Schottky electrode 71 is formed on the surface side of the first isolation region 21. The Schottky electrode 71 is in a stripe shape in a plan view and is in Schottky connection with the first isolation region 21. The Schottky electrode 71 is preferably formed in a region including the corresponding first isolation region 21 in a plan view.

[0026] An ohmic electrode 70 is formed on the surface of the source region 40. A source electrode 80 connected to the ohmic electrode 70, the Schottky electrode 71 and the contact region 35 is formed thereon. The first well region 30 can easily exchange electrons and holes with the ohmic electrode 70 via the contact region 35 of low resistance.

[0027] A second separation region 22 made of n-type silicon carbide is formed in a region between adjacent first well regions 30, which is different from the first separation region 21. The conductivity type of the second separation region 22 is the same n-type as the drift layer 20, and the n-type impurity concentration of the second separation region 22 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20.

[0028] A gate insulating film 50 made of, for example, silicon oxide is selectively formed on the surfaces of the adjacent first well regions 30, the second isolation region 22 therebetween, and the source region 40 in the first well regions 30. A gate electrode 60 made of, for example, polysilicon is formed on the gate insulating film 50 at least on the upper side of the first well region 30. The surface portion of the first well region 30 that faces the gate electrode 60 via the gate insulating film 50 is referred to as a channel region.

[0029] A second well region 31 is formed outside the first well region 30 at the outermost periphery of the silicon carbide semiconductor device 100, and a third separation region 23 made of silicon carbide is formed between the first well region 30 and the second well region 31. The conductivity type of the third separation region 23 is the same n-type as that of the drift layer 20, and the n-type impurity concentration of the third separation region 23 can be the same as the n-type impurity concentration of the drift layer 20, or can be higher or lower than the n-type impurity concentration of the drift layer 20.

[0030] A gate insulating film 50 is selectively formed on the second well region 31 similarly to the first well region 30 , and a gate electrode 60 is formed on the gate insulating film 50 . The gate electrode 60 is electrically connected to the gate electrode 60 formed on the first well region 30 .

[0031] A silicon carbide conductive layer 45 made of silicon carbide is formed in a certain proportion of the upper layer of the second well region 31. The silicon carbide conductive layer 45 has a higher n-type impurity concentration and a lower resistance than the drift layer 20. The silicon carbide conductive layer 45 has a lower sheet resistance than the second well region 31, and forms a pn junction with the p-type second well region 31. The silicon carbide conductive layer 45 is formed, for example, in a width range of more than half of the width in the cross-sectional direction of the second well region 31. The portion formed by the silicon carbide conductive layer 45 having a width of more than half of the width in the cross-sectional direction of the second well region 31 does not need to be provided in all cross sections, and may be provided in a portion of the cross sections.

[0032] An interlayer insulating film 55 made of, for example, silicon carbide is formed between the gate electrode 60 and the source electrode 80. The gate electrode 60 and the gate wiring 82 above the second well region 31 are connected via a gate contact hole 95 formed in the interlayer insulating film 55. In addition, a JTE region 38 made of p-type silicon carbide is formed on the outer peripheral side of the second well region 31, that is, on the opposite side of the first well region 30. The impurity concentration of the JTE region 38 is lower than the impurity concentration of the second well region 31. An FLR (Field Limiting Ring) may be formed instead of the JTE region 38. In addition, a combination of the JTE region 38 and the FLR may be formed.

[0033] A field insulating film 51 or gate insulating film 50 having a greater film thickness than the gate insulating film 50 is formed on the second well region 31 and the silicon carbide conductive layer 45. An opening, i.e., a terminal region contact hole 91, is formed in a portion of the gate insulating film 50 or the field insulating film 51 on the surface of the silicon carbide conductive layer 45. The silicon carbide conductive layer 45 and the source electrode 80 are ohmically connected via the ohmic electrode 72 at the terminal portion below the terminal region contact hole 91.

[0034] The terminal region contact hole 91 penetrates the gate insulating film 50 or the field insulating film 51 and the interlayer insulating film 55, and makes the silicon carbide conductive layer 45 and the source electrode 80 ohmically connected, but the second well region 31 and the source electrode 80 may not be connected. In addition, the width of the silicon carbide conductive layer 45 is larger than the diameter or width of the terminal region contact hole 91. In the first embodiment, the second well region 31 is not directly ohmically connected to the source electrode 80.

[0035] In the active region, the ohmic electrode 70 , the Schottky electrode 71 , and the contact region 35 are connected to the source electrode 80 on the interlayer insulating film 55 via an active region contact hole 90 that penetrates the interlayer insulating film 55 and the gate insulating film 50 .

[0036] A drain electrode 84 is formed on the back surface side of the semiconductor substrate 10 .

[0037] When the plane orientation of the first main surface of the semiconductor substrate 10 is a (0001) plane having an offset angle in the <11-20> direction, the extension direction of the striped first well region 30 can be parallel to the deviation direction, i.e., the <11-20> direction, or can be parallel to a direction orthogonal to the deviation direction.

[0038] Figure 4 It is further schematically shown Figure 2 The active region 15 includes not only the above-mentioned unit cell region but also the surge current region 301 .

[0039] The surge current-carrying area 301 does not have the first separation area 21 connected to the Schottky electrode 71, and is defined as an area surrounded by the first separation area 21. The "surrounded" mentioned here is not necessarily limited to being surrounded by the continuous first separation area 21. Figure 2 As shown in the top view of , it also includes a plurality of first separation regions 21 separated from and periodically arranged at the ends of the stripes in the extension direction. That is, the surge current-carrying region 301 is an area in the active region 15 covered by the source electrode 80 that is adjacent to, and more preferably surrounded by, the first separation region 21 connected to the Schottky electrode 71 in a top view.

[0040] The area of ​​the surge current conduction region 301 is sufficiently small relative to the entire area of ​​the active region 15, and the active region 15 is provided in the surge current conduction region 301. In addition, the surge current conduction region 301 is covered by the source electrode 80 in the same manner as the unit cell region. From these points of view, the surge current conduction region 301 is clearly distinguished from the second well region 31 formed around the active region 15 on the lower side of the gate pad 81 and having a relatively wide area.

[0041] The surge current conducting region 301 is formed in at least one unit cell region in the chip. When formed in two or more unit cell regions, it is desirable that the surge current conducting region 301 is dispersedly formed in the chip in a plan view.

[0042] As described later, the surge current-carrying region 301 includes a Schottky barrier diode replacement region 302 in which the n-type of the SBD region in the unit cell region is replaced with the p-type. The p-type Schottky barrier diode replacement region 302 has the function of a pn diode in cooperation with the n-type drift layer 20. When the silicon carbide semiconductor device 100 is in a reflux operation with a sufficiently long energization time such as 1 to 10 msec, the body diode of the unit cell region operates in conjunction with the operation of the pn diode. The body diode mentioned here includes a parasitic pn diode as a reflux diode of the MOSFET.

[0043] In this embodiment 1, the area ratio of the p-type Schottky barrier diode replacement region 302 to the active region 15 when viewed from above is greater than 0.01%, and is smaller than the area ratio of the SBD region to the active region 15 when not replaced by the Schottky barrier diode replacement region 302, and is more preferably greater than 0.01% and less than 5%.

[0044] If the area ratio of the Schottky barrier diode replacement region 302 is equal to the area ratio of the SBD region when not replaced by the Schottky barrier diode replacement region 302, the SBD does not exist in the plane of the active region 15, and the function as a MOSFET with a built-in SBD is lost.

[0045] Furthermore, as the ratio of the Schottky barrier diode replacement region 302 in the plane decreases, the influence on the original electrical characteristics becomes smaller, and it is expected that the efficiency of power conversion will be improved (loss will be reduced).

[0046] In the silicon carbide semiconductor device 100 involved in the first embodiment, during the above-mentioned reflow action, the longer the power-on time is extended, the greater the area ratio of the body diode linkage action region, i.e., the body diode linkage action region 16, to the active region 15, and finally the body diode operates on the entire surface of the active region 15. Figure 5 : is a diagram showing an example of such a body diode interlocking operation region 16. The speed at which the body diode interlocking operation region 16 spreads to the entire surface of the active region 15 during the above-mentioned reflow operation is adjusted by adjusting the size and number of the surge current conducting regions 301.

[0047] Figure 6 This is a schematic cross-sectional view showing the schematic structure of the surge current conducting region 301 and the active region contact hole 90 as viewed from the long side direction of the stripe-shaped unit cell region.

[0048] Inside the surge current region 301, at the surface of the drift layer 20, one or more Schottky barrier diode replacement regions 302 made of p-type silicon carbide are formed. The Schottky barrier diode replacement region 302 is provided between the Schottky electrode 71 and the drift layer 20, so that the pn junction is located in the middle of the conduction path between the source electrode 80 and the drain electrode 84. That is, the Schottky electrode 71 is not connected to the n-type silicon carbide layer such as the first separation region 21 of the same n-type as the drift layer 20, and the Schottky electrode 71 and the drift layer 20 are separated by the Schottky barrier diode replacement region 302. In addition, "connected" here means a state in which the Schottky current can flow in the chip cross-sectional direction without passing through the pn junction in the middle.

[0049] In the present first embodiment, the Schottky barrier diode replacement region 302 is a p-type region that replaces the first separation region 21 sandwiched by the adjacent first well region 30. The Schottky barrier diode replacement region 302 is formed on the lower side of the periodically formed Schottky electrode 71. At this time, the first well region 30 adjacent to the Schottky barrier diode replacement region 302 becomes a p-type region. In such a layout, the total width of the Schottky barrier diode replacement region 302 and the adjacent first well region 30 is necessarily greater than the width of the first well region 30. The following examples illustrate two advantages of this layout.

[0050] As a first advantage, the gate electrode 60 and the active region contact hole 90 in the surge current region 301 can be formed at the same pitch as the surrounding region. As a result, the gate electrode 60 and the active region contact hole 90 can be arranged at equal intervals in all regions within the chip, thereby improving the uniformity of processing. In addition, at the end of the surge current region 301 in the extension direction of the stripe, the gate electrode 60 and the active region contact hole 90 do not need to be interrupted or bifurcated, thereby further improving the uniformity of processing.

[0051] As a second advantage, the gate electrode 60 can be formed to pass through the surge power-on area 301 when viewed from above. This brings about the effect that the propagation of the gate potential will not be interrupted by the surge power-on area 301. In particular, in the stripe-type structure, when the gate potential is interrupted by the surge power-on area 301, the gate potential cannot be propagated from this area first, and an area without MOSFET function will be generated, resulting in the disadvantage that the chip area cannot be effectively and flexibly used. The propagation of the gate potential will not be interrupted by the surge power-on area 301, thereby reducing this disadvantage. In addition, compared with the structure in which the gate electrode pattern is formed to bypass the surge power-on area 301, the propagation delay of the gate potential of this structure is smaller, and therefore, the following effects can be obtained: high-speed switching is achieved, or local concentration of the switching current is suppressed.

[0052] Here, the contact hole for the active region contact hole 90 formed on the upper side of the Schottky barrier diode replacement region 302 is referred to as the active region second contact hole 90B, and the other active region contact holes 90 are referred to as the active region first contact hole 90A. In the active region first contact hole 90A, the source electrode 80 is in contact with the source region 40 and the first isolation region 21, respectively, whereas the active region second contact hole 90B is in contact with the p-type Schottky barrier diode replacement region 302. Therefore, a pn diode formed by a pn junction between the Schottky barrier diode replacement region 302 and the drift layer 20 and through which current flows in the thickness direction of the chip is formed at a position separated from the SBD.

[0053] In the present first embodiment, in the surge current conduction region 301, the second separation region 22 is provided between two adjacent Schottky barrier diode replacement regions 302 or between the Schottky barrier diode replacement region 302 and the first well region 30. The source region 40 is formed on the inner side of the surface layer of the Schottky barrier diode replacement region 302 at a certain distance from the end thereof, and the gate insulating film 50 and the gate electrode 60 are formed in the region from the second separation region 22 to the source region 40. That is, in the present first embodiment, the same channel structure as the MOSFET region of the active region 15 is formed on the inner side of the Schottky barrier diode replacement region 302, and the surge current conduction region 301 also has the function of a MOSFET.

[0054] In the channel structure, the separation distance between the source region 40 and the second separation region 22 is called the channel length. The channel length formed in the surge power-on region 301 is preferably the same as or greater than the channel length of the MOSFET region formed in the active region 15. In addition, if the channel length formed in the surge power-on region 301 is too short, the current flows in the surge power-on region 301 at a lower gate voltage due to the short channel effect, resulting in a decrease in the threshold voltage of the entire chip, which is likely to cause malfunction of the element. On the other hand, if the channel length formed in the surge power-on region 301 is too long, the channel current in the surge power-on region 301 becomes smaller, and it is difficult to obtain the effect brought about by the channel current described later. For these reasons, the channel length formed in the surge power-on region 301 is preferably the same as the channel length of the MOSFET region formed in the active region 15.

[0055] For the same reason, the impurity concentration of the channel formed in the surge power supply region 301 is preferably the same as the impurity concentration of the channel region formed in the MOSFET region of the active region 15. In addition, the film thickness of the gate insulating film 50 in the surge power supply region 301 is preferably the same as the film thickness of the gate insulating film 50 in the MOSFET region of the active region 15. According to this structure, the gate insulation withstand voltage of the Schottky barrier diode replacement region 302 can be kept from being lowered and the channel current can be kept from being reduced relative to the MOSFET region.

[0056] (2) Planar lattice structure Figure 7 is a top view of another structure of the silicon carbide semiconductor device 100 according to the first embodiment as viewed from the top surface, corresponding to Figure 2 Figure 1. A top view of a . Figure 7In the silicon carbide semiconductor device 100 shown, unit cell regions including an SBD region and a MOSFET region surrounding the SBD region are repeatedly arranged in the vertical and horizontal directions in a plan view. The structure of the silicon carbide semiconductor device 100 having such unit cell regions is called a "lattice type" structure.

[0057] Figure 7 In the figure, the unit cell region is repeatedly arranged in the vertical and horizontal directions in a plan view, and the unit cell region includes an n-type first separation region 21 roughly corresponding to the SBD region, and a p-type first well region 30 roughly corresponding to the MOSFET region. The region formed by combining the unit cell region of the MOSFET with a built-in SBD and the surge current conduction region is called an active region. The region that is the periphery of the active region and includes the region where the gate pad 81 is formed, where the p-type second well region 31 and the like are formed, is called a terminal region.

[0058] Figure 8 It is shown from Figure 1 FIG. 1 is a cross-sectional view schematically showing a schematic structure of a gate wiring 82 extending from a source electrode 80 to the outer periphery of a silicon carbide semiconductor device 100 .

[0059] Figure 8 In the silicon carbide semiconductor device 100 shown in FIG. 1 , a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of n-type and low-resistance silicon carbide. Figure 8 As shown in the cross-sectional view, in the case of Figure 1 A second well region 31 made of p-type silicon carbide is provided in the surface portion of the drift layer 20 at the position of the region of the gate wiring 82 described above.

[0060] exist Figure 1 A plurality of first well regions 30 made of p-type silicon carbide are provided in the surface portion of the drift layer 20 in the active region, which is the region below the source electrode 80 described in the above description.

[0061] In the surface layer portion of the first well region 30 , a source region 40 made of n-type silicon carbide is formed at a position a certain distance inward from the outer periphery of the first well region 30 .

[0062] In the surface portion of the first well region 30, a contact region 35 made of low-resistance p-type silicon carbide is formed on one end side of the source region 40. Between adjacent contact regions 35, a first separation region 21 made of silicon carbide that penetrates the first well region 30 is formed. The conductivity type of the first separation region 21 is the same n-type as that of the drift layer 20, and the n-type impurity concentration of the first separation region 21 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20.

[0063] A Schottky electrode 71 is formed on the surface side of the first separation region 21 to make Schottky connection with the first separation region 21. The Schottky electrode 71 is preferably formed in a region including the corresponding first separation region 21 in a plan view.

[0064] An ohmic electrode 70 is formed on the surface of the source region 40. A source electrode 80 connected to the ohmic electrode 70, the Schottky electrode 71 and the contact region 35 is formed thereon. The first well region 30 can easily exchange electrons and holes with the ohmic electrode 70 via the contact region 35 of low resistance.

[0065] A second separation region 22 made of n-type silicon carbide is formed in a region between adjacent first well regions 30, which is different from the first separation region 21. The conductivity type of the second separation region 22 is the same n-type as the drift layer 20, and the n-type impurity concentration of the second separation region 22 may be the same as the n-type impurity concentration of the drift layer 20, or may be higher or lower than the n-type impurity concentration of the drift layer 20.

[0066] A gate insulating film 50 made of, for example, silicon oxide is selectively formed on the surfaces of the adjacent first well regions 30, the second isolation region 22 therebetween, and the source region 40 in the first well regions 30. A gate electrode 60 made of, for example, polysilicon is formed on the gate insulating film 50 at least on the upper side of the first well region 30. The surface portion of the first well region 30 that faces the gate electrode 60 via the gate insulating film 50 is referred to as a channel region.

[0067] A second well region 31 is formed outside the first well region 30 at the outermost periphery of the silicon carbide semiconductor device 100, and a third separation region 23 made of silicon carbide is formed between the first well region 30 and the second well region 31. The conductivity type of the third separation region 23 is the same n-type as that of the drift layer 20, and the n-type impurity concentration of the third separation region 23 can be the same as the n-type impurity concentration of the drift layer 20, or can be higher or lower than the n-type impurity concentration of the drift layer 20.

[0068] A gate insulating film 50 is selectively formed on the second well region 31 similarly to the first well region 30 , and a gate electrode 60 is formed on the gate insulating film 50 . The gate electrode 60 is electrically connected to the gate electrode 60 formed on the first well region 30 .

[0069] A silicon carbide conductive layer 45 made of silicon carbide is formed in a certain proportion of the upper layer of the second well region 31. The silicon carbide conductive layer 45 has a higher n-type impurity concentration and a lower resistance than the drift layer 20. The silicon carbide conductive layer 45 has a lower sheet resistance than the second well region 31, and forms a pn junction with the p-type second well region 31. The silicon carbide conductive layer 45 is formed, for example, to span a width of more than half of the width in the cross-sectional direction of the second well region 31. The portion where the silicon carbide conductive layer 45 is formed with a width of more than half of the width in the cross-sectional direction of the second well region 31 does not need to be provided in all cross sections, and may be provided in a portion of the cross sections.

[0070] An interlayer insulating film 55 made of, for example, silicon carbide is formed between the gate electrode 60 and the source electrode 80. The gate electrode 60 and the gate wiring 82 above the second well region 31 are connected via a gate contact hole 95 formed in the interlayer insulating film 55. In addition, a JTE region 38 made of p-type silicon carbide is formed on the outer peripheral side of the second well region 31, that is, on the opposite side of the first well region 30. The impurity concentration of the JTE region 38 is lower than the impurity concentration of the second well region 31. An FLR (Field Limiting Ring) may be formed instead of the JTE region 38. In addition, a combination of the JTE region 38 and the FLR may be formed.

[0071] A field insulating film 51 or gate insulating film 50 having a greater film thickness than the gate insulating film 50 is formed on the second well region 31 and the silicon carbide conductive layer 45. An opening, i.e., a terminal region contact hole 91, is formed in a portion of the gate insulating film 50 or the field insulating film 51 on the surface of the silicon carbide conductive layer 45. The silicon carbide conductive layer 45 and the source electrode 80 are ohmically connected via the ohmic electrode 72 at the terminal portion below the terminal region contact hole 91.

[0072] The terminal region contact hole 91 penetrates the gate insulating film 50 or the field insulating film 51 and the interlayer insulating film 55, and makes an ohmic connection between the silicon carbide conductive layer 45 and the source electrode 80, but it is not necessary to connect the second well region 31 and the source electrode 80. In addition, the width of the silicon carbide conductive layer 45 is larger than the diameter or width of the terminal region contact hole 91.

[0073] In the first embodiment, the second well region 31 is not directly ohmically connected to the source electrode 80 .

[0074] In the active region, the ohmic electrode 70 , the Schottky electrode 71 , and the contact region 35 are connected to the source electrode 80 on the interlayer insulating film 55 via an active region contact hole 90 that penetrates the interlayer insulating film 55 and the gate insulating film 50 .

[0075] A drain electrode 84 is formed on the back surface side of the semiconductor substrate 10 .

[0076] Fig. 9 3 is a cross-sectional view showing the schematic structure of the surge power supply area 301 and the active area contact hole 90. In this cross-sectional view, the structure of the surge power supply area 301 and the Schottky barrier diode replacement area 302 is similar to that of FIG. Figure 6 In addition, the area ratio of the Schottky barrier diode replacement region 302 to the active region 15 in a top view is also the same as that of the Schottky barrier diode replacement region 302. Figure 4 and Figure 5 Same as described.

[0077] (3) Supplementary explanation common to stripe type and lattice type In the region closest to the terminal region of the active region, a SBD high surface density structure such as a folded structure may be formed. In addition, in the region closest to the active region of the terminal region, a terminal SBD high surface density structure including a JBS forming a large number of SBDs may be formed. In addition, a sensing unit for sensing current may be provided inside the active region.

[0078] The concentration of the n-type impurity in the second separation region 22 can be set higher than the concentration of the n-type impurity in the drift layer 20. When the drift layer 20 and the second separation region 22 are formed in this way, the on-resistance can be reduced.

[0079] (4) Planar type manufacturing method Next, use Figure 10 to Figure 17 The method for manufacturing the planar silicon carbide semiconductor device 100 according to Embodiment 1 is described with reference to a schematic cross-sectional view of FIG. Hereinafter, the method for manufacturing the stripe-type silicon carbide semiconductor device 100 will be described, but the method for manufacturing the lattice-type silicon carbide semiconductor device 100 is also the same as the following.

[0080] First, a semiconductor substrate 10 is prepared. The semiconductor substrate 10 is a surface whose first main surface has an offset angle (0001) in the plane orientation and is composed of n-type low-resistance silicon carbide having a 4H polymorph. On the semiconductor substrate 10, a 1×10 15 Up to 1×10 17 cm -3 The drift layer 20 composed of silicon carbide having an n-type impurity concentration of, for example, 5 to 50 μm in thickness is epitaxially grown.

[0081] Next, an implantation mask is formed in a predetermined region on the surface of the drift layer 20 by means of a photoresist or the like, and ion implantation of p-type impurities, i.e., Al (aluminum), is performed. At this time, the depth of the Al ion implantation is set to be not more than the thickness of the drift layer 20, for example, about 0.5 to 3 μm. In addition, the impurity concentration of the ion-implanted Al is, for example, 1×10 17 Up to 1×10 19 cm -3 , which is higher than the impurity concentration of the drift layer 20. After that, the implantation mask is removed. The region after Al ion implantation in this step becomes the first well region 30 in the active region and becomes the second well region 31 in the terminal region.

[0082] Next, an implantation mask is formed in a predetermined region on the surface of the drift layer 20 by using a photoresist or the like, and ion implantation of Al, which is a p-type impurity, is performed. At this time, the depth of the Al ion implantation is set to be about 0.5 to 3 μm less than the thickness of the drift layer 20. In addition, the impurity concentration of the Al ion implantation is, for example, 1×10 17 Up to 1×10 19 cm -3 , which is higher than the impurity concentration of the drift layer 20. After that, the implantation mask is removed. The region after Al ion implantation in this process becomes the Schottky barrier diode replacement region 302.

[0083] A portion of the surface of the first well region 30 adjacent to the Schottky barrier diode replacement region 302 becomes a channel region. In order to set the threshold voltage of the first well region 30 adjacent to the Schottky barrier diode replacement region 302 to be greater than, preferably equal to, the threshold voltage of the MOSFET region, the p-type impurity concentration of the surface of the Schottky barrier diode replacement region 302 and the adjacent first well region 30 is set to be greater than, preferably equal to, the p-type impurity concentration of the surface of the first well region 30 of the MOSFET region. As one of the implementation methods, there is a method of performing an injection step of the Schottky barrier diode replacement region 302 and the adjacent first well region 30, and an injection step of the first well region 30 of the MOSFET region in the same process. According to this method, the p-type impurity concentrations of the surfaces of the Schottky barrier diode replacement region 302 and the first well region 30 can be made the same, and the number of processes can be reduced.

[0084] Next, an implantation mask is formed by photoresist or the like in a predetermined region on the surface of the drift layer 20 in the termination region, and ion implantation of Al, which is a p-type impurity, is performed. At this time, the depth of the Al ion implantation is set to be about 0.5 to 3 μm less than the thickness of the drift layer 20. In addition, the impurity concentration of Al after ion implantation is, for example, 1×10 16 Up to 1×10 18 cm -3, which is higher than the impurity concentration of the drift layer 20 and lower than the impurity concentration of the first well region 30 and the Schottky barrier diode replacement region 302. After that, the implantation mask is removed. The region after the Al ion implantation in this process becomes the JTE region 38. Similarly, in the predetermined region of the surface layer of the first well region 30 and the Schottky barrier diode replacement region 302, a higher impurity concentration than these regions, for example, 1×10 16 Up to 1×10 18 cm -3 Al is ion-implanted at an impurity concentration of , thereby forming a contact region 35 .

[0085] Next, an implantation mask is formed using a photoresist or the like to expose a predetermined portion of the inner side of the surface layer of the first well region 30 and the Schottky barrier diode replacement region 302, and ion implantation of n-type impurities, i.e., N (nitrogen), is performed. The ion implantation depth of N is set to be shallower than the thickness of the first well region 30. In addition, the impurity concentration of the ion implanted N is, for example, 1×10 18 Up to 1×10 21 cm -3 , which is higher than the p-type impurity concentration of the first well region 30 and the Schottky barrier diode replacement region 302. In this process, the region indicating n-type in the region implanted with N becomes the source region 40. The thickness of the source region 40 may be smaller than the thickness of the first well region 30.

[0086] Similarly, an implantation mask is formed by using a photoresist or the like to expose a predetermined portion inside the second well region 31 of the termination region, and ion implantation of N, which is an n-type impurity, is performed. The ion implantation depth of N is shallower than the thickness of the second well region 31. In addition, the impurity concentration of the implanted N is, for example, 1×10 18 Up to 1×10 21 cm -3 , which is higher than the p-type impurity concentration of the second well region 31. In this step, the region indicating n-type in the region implanted with N becomes the silicon carbide conductive layer 45. The thickness of the silicon carbide conductive layer 45 may be smaller than the thickness of the second well region 31.

[0087] The silicon carbide conductive layer 45 and the source region 40 may be formed in the same process, with the same thickness, and with the same impurity concentration, or may be formed in different processes, with different thicknesses, and with different impurity concentrations.

[0088] Next, the drift layer 20 is annealed at 1300 to 1900° C. for 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar) gas using a heat treatment apparatus. The ion-implanted N and Al are electrically activated by the annealing. Fig.10 and Fig.11 The process up to this stage is completed. Figure 3and Figure 6 Cross-sectional view of the same area.

[0089] Next, a field insulating film 51 made of silicon oxide is formed on the region other than the active region where the first well region 30 and the surge current conducting region 301 are formed, i.e., on the termination region, using CVD method and photolithography technology, etc. The film thickness of the field insulating film 51 is, for example, 0.5 to 2 μm, which is larger than the film thickness of the gate insulating film 50.

[0090] Next, the surface of the silicon carbide layer not covered by the field insulating film 51 is thermally oxidized to form a silicon oxide film of a desired thickness as the gate insulating film 50. Next, a polysilicon film having conductivity, for example, is formed on the gate insulating film 50 and the field insulating film 51 by a reduced pressure CVD method, and is patterned to form the gate electrode 60. Next, an interlayer insulating film 55 having a greater film thickness than the gate insulating film 50 and made of, for example, silicon oxide is formed by a reduced pressure CVD method. Fig.12 and Fig.13 The process up to this stage is completed. Figure 3 and Figure 6 Cross-sectional view of the same area.

[0091] Next, a portion of an active region contact hole 90 that penetrates the interlayer insulating film 55 and the gate insulating film 50 and reaches the contact region 35 and the source region 40 in the active region, and a terminal region contact hole 91 that reaches the silicon carbide conductive layer 45 in the terminal region are formed. However, in the remaining portion of the active region contact hole 90, that is, the portion where the Schottky electrode 71 is formed, the interlayer insulating film 55 and the gate insulating film 50 remain.

[0092] Next, a metal film mainly composed of Ni is formed on the surface of the silicon carbide layer exposed from a part of the active region contact hole 90 and the terminal region contact hole 91, for example, by sputtering, and then a heat treatment is performed at a temperature of 600 to 1100° C. Thus, the metal film mainly composed of Ni reacts with the silicon carbide layer to form a silicide layer between the metal film and the silicon carbide layer. Next, the remaining metal film other than the silicide layer is removed by wet etching. Thus, the remaining silicide layer becomes the ohmic electrode 70 and the ohmic electrode 72 of the terminal portion. Fig.14 and Fig.15 The process up to this stage is completed. Figure 3 and Figure 6 Cross-sectional view of the same area.

[0093] Next, a metal film mainly composed of Ni is formed on the back surface (second main surface) of the semiconductor substrate 10 and heat treated to form a back surface ohmic electrode, ie, a drain electrode 84 , on the back surface side of the semiconductor substrate 10 .

[0094] Next, a resist mask 99 is formed to remove the interlayer insulating film 55 and the gate insulating film 50 on the first isolation region 21 and the Schottky barrier diode replacement region 302, as well as the interlayer insulating film 55 at the position of the gate contact hole 95. As a method of removal, wet etching is used that does not damage the surface of the silicon carbide layer that becomes the Schottky interface. Fig.16 and Fig.17 The process up to this stage is completed. Figure 3 and Figure 6 Cross-sectional view of the same area.

[0095] Next, after removing the resist mask 99, a metal film to be a Schottky electrode is deposited by sputtering or the like. Then, using patterning based on photoresist or the like, a Schottky electrode 71 is formed on the first isolation region 21 in the active region contact hole 90 and the Schottky barrier diode replacement region 302. The material of the Schottky electrode 71 is, for example, Ti (titanium), Mo (molybdenum), or the like.

[0096] Next, a wiring metal such as Al is formed on the surface of the substrate that has been processed so far by sputtering or evaporation, and processed into a predetermined shape by photolithography technology, thereby forming an ohmic electrode 70 on the source side, an ohmic electrode 72 at the terminal, a source electrode 80 in contact with the Schottky electrode 71, and a gate pad 81 and a gate wiring 82 in contact with the gate electrode 60. As described above, the manufacturing Figure 3 and Figure 6 The silicon carbide semiconductor device 100 according to the first embodiment is shown.

[0097] (5) Action description Next, the operation of the silicon carbide semiconductor device 100 according to the first embodiment will be described. Here, a silicon carbide semiconductor device whose semiconductor material is 4H-type silicon carbide will be described as an example. In this case, the diffusion potential of the pn junction is about 2V.

[0098] The operation of the silicon carbide semiconductor device 100 according to the first embodiment will be briefly described by dividing it into four normal operation states and one abnormal state.

[0099] The first normal operation state is a state in which a voltage higher than that of the source electrode 80 is applied to the drain electrode 84, and a positive voltage higher than the threshold voltage is applied to the gate electrode 60, which is hereinafter referred to as the "on state". In this on state, an inversion channel is formed in the channel region, and a path for the flow of electrons as carriers is formed between the n-type source region 40 and the n-type second separation region 22. On the other hand, in the Schottky junction formed at the contact portion between the first separation region 21 and the Schottky electrode 71, an electric field in a direction in which current does not easily flow for the Schottky junction, that is, a reverse direction (reverse bias) is applied, so that current does not flow.

[0100] The electrons flowing from the source electrode 80 to the drain electrode 84 follow the electric field formed by the positive voltage applied to the drain electrode 84. Therefore, the electrons reach the drain electrode 84 from the source electrode 80 via the ohmic electrode 70, the source region 40, the channel region, the second separation region 22, the drift layer 20 and the semiconductor substrate 10. Therefore, by applying a positive voltage to the gate electrode 60, the on-current flows from the drain electrode 84 to the source electrode 80. At this time, the voltage applied between the source electrode 80 and the drain electrode 84 is called the on-voltage, and the value obtained by dividing the on-voltage by the density of the on-current is called the on-resistance. The on-resistance is equal to the sum of the resistances of the paths through which the above-mentioned electrons flow. The product of the on-resistance and the square of the on-current corresponds to the on-loss consumed when the MOSFET is powered on, so the on-resistance is preferably the lower one. In the first embodiment, the channel region is also formed in the surge power-on region 301. Therefore, the surge power-on region 301 also helps to reduce the on-resistance.

[0101] The second normal operation state is a state in which a voltage higher than the source electrode 80 is applied to the drain electrode 84 and a voltage less than the threshold is applied to the gate electrode 60, which is hereinafter referred to as the "off state". In this off state, there are no reverse carriers in the channel region, so the on-current does not flow, and the high voltage applied to the load in the on state is applied between the source electrode 80 and the drain electrode 84 of the MOSFET.

[0102] An electric field in the same direction as the "on state" is applied to the Schottky junction formed at the contact portion between the first separation region 21 and the Schottky electrode 71, so ideally no current flows. However, since a much higher electric field than the "on state" is applied, leakage current may occur. If the leakage current is large, the heat generation of the MOSFET increases, and the MOSFET and the module using the MOSFET may be thermally damaged. Therefore, in order to reduce the leakage current, it is preferable to suppress the electric field applied to the Schottky junction to a low level.

[0103] The third normal operation state is a state in which a voltage lower than that of the source electrode 80 is applied to the drain electrode 84, that is, a back electromotive force is applied to the MOSFET, and a voltage less than the threshold is applied to the gate electrode 60. In this state, the return current flows from the source electrode 80 to the drain electrode 84. Hereinafter, this state is referred to as the "asynchronous rectification state". In the asynchronous rectification state, in the active region outside the surge current-carrying region 301, a positive electric field (forward bias) is applied to the Schottky junction formed at the contact portion between the first separation region 21 and the Schottky electrode 71. Therefore, a unipolar current including an electron current flows from the Schottky electrode 71 to the n-type first separation region 21. That is, a unipolar current flows through the SBD including the Schottky electrode 71 and the first separation region 21. The return current component of the return diode is mainly a unipolar component.

[0104] In addition, the source electrode 80 and the first well region 30 are at the same potential via the ohmic electrode 70 on the source side. As a result, a forward bias is also applied to the pn junction between the p-type first well region 30 and the drift layer 20. However, the pn junction is formed in parallel with the above-mentioned Schottky junction, and when the off state is changed to the asynchronous rectification state, the Schottky junction with a lower threshold voltage is turned on before the pn junction, so the return current basically flows through the Schottky junction, and does not flow through the pn junction.

[0105] Even if the voltage applied between the source and the drain exceeds the diffusion potential of the pn junction, a voltage obtained by subtracting the voltage drop caused by the unipolar current of the SBD in the drift layer 20 from the voltage between the source and the drain is applied to the pn junction. Therefore, a high voltage between the source and the drain can be applied without the pn junction being turned on, and as a result, a high current can flow only by the unipolar current.

[0106] Therefore, by building in the SBD, in the asynchronous rectification state, it is possible to suppress the bipolar current, that is, the positive phase current, from flowing through the pn junction, that is, the body diode as a parasitic pn diode. If there is a starting point such as a basal plane dislocation in the pn junction through which the bipolar current flows, crystal defects such as stacking defects may expand due to the repetition of the asynchronous rectification state. Crystal defects such as stacking defects cut off the current flowing in the thickness direction of the chip, so the on-resistance increases, and it is possible to cause component failure due to thermal runaway. In the silicon carbide semiconductor device 100 involved in this embodiment 1, since the SBD is built in, it is possible to suppress the bipolar current from flowing through the pn junction during reflow, and the reliability of the silicon carbide semiconductor device 100 can be improved.

[0107] On the other hand, in the asynchronous rectification state, the first separation region 21 connected to the Schottky electrode 71 does not exist in the surge power supply region 301, so the unipolar current does not flow easily. The unipolar current flowing in the junction of the Schottky electrode 71 and the first separation region 21 formed around the surge power supply region 301 diffuses into the drift layer 20 in the chip plane direction, and the unipolar current also flows through the drift layer 20 in the surge power supply region 301 to a certain extent. However, its current density is smaller than that of the active region outside the surge power supply region 301, so in the pn junction of the surge power supply region 301, due to the lower source-drain voltage, the bipolar current flows more easily than the active region outside the surge power supply region 301.

[0108] If a bipolar current flows through the pn junction, a crystal defect such as a stacking defect may expand, but since the time of the sequence of the asynchronous rectification state is assumed to be a relatively short time of hundreds of nsec to several μsec, the expansion of crystal defects such as stacking defects is not easy to occur. In addition, in the present embodiment 1, the area ratio of the Schottky barrier diode replacement region 302 to the active region is greater than 0.01%, and is less than the area ratio of the SBD region to the active region 15 when it is not replaced by the Schottky barrier diode replacement region 302, and is more preferably greater than 0.01% and less than 5%, which is relatively small. Therefore, the possibility of reliability degradation caused by the expansion of crystal defects such as stacking defects can be reduced. In addition, if the area ratio is less than 5%, the impact on the electrical characteristics of the chip during normal operation can be almost ignored, so the degradation of electrical characteristics such as conduction loss caused by the surge power-on region 301 can be suppressed.

[0109] The fourth normal operation state is a state in which a voltage lower than that of the source electrode 80 is applied to the drain electrode 84, that is, a back electromotive force is applied to the MOSFET, and a voltage above the threshold voltage is applied to the gate electrode 60. In this state, the return current flows from the source electrode 80 to the drain electrode 84. Hereinafter, this state is referred to as the "synchronous rectification state". In the synchronous rectification state, in addition to the unipolar current flowing in the Schottky electrode 71, a unipolar current flowing in the channel also flows. In the present embodiment 1, the channel is formed not only in the MOSFET area, but also in the surge power-on area 301. Therefore, in the surge power-on area 301, although there is no junction between the Schottky electrode 71 and the first separation area 21, the channel current becomes a carrier of the unipolar current, which can suppress the conduction of the pn junction. As a result, the heat concentration in the surge power-on area 301 in the synchronous rectification state can be suppressed.

[0110] For example, in the inverter operation, the sequence of synchronous rectification states occupies about half of the carrier cycle, and its time is assumed to be relatively long, such as tens of μsec to several msec. This time is much longer than the asynchronous rectification state, which is assumed to be relatively short, such as hundreds of nsec to several μsec. If the current continues to flow through the pn diode for such a long time, it will cause local heating. The reason for this is explained below.

[0111] First, compared with unipolar current, bipolar current has the characteristics of causing conductivity modulation and reducing drift resistance. In the area where bipolar current flows, the resistance decreases, and more current flows compared to the area where only unipolar current flows. As a result, the temperature rises in the local area where the bipolar current flows, and the conductivity modulation becomes stronger, and positive feedback of current concentration begins to occur. As a result, local heating is generated in the surge power-on area 301 and the like, and reliability degradation such as cracks in the electrode joint and damage to the gate insulating film may occur. In contrast, in the present embodiment 1, the channel current flows through the surge power-on area 301 in the synchronous rectification state. Therefore, the action of the pn diode in the surge power-on area 301 can be suppressed, local heating can be avoided, and thus higher reliability can be obtained.

[0112] Finally, as an abnormal state, the state in which a surge current flows between the source and the drain is described. In this state, due to an inverter failure or the like, a current exceeding the rated current instantly flows from the source to the drain. In many of these cases, it is assumed that a shutdown signal is applied to the gate and the channel is not energized. At this time, the chip is required not to fail due to heat. The allowable current that does not cause a failure is called surge tolerance. In order to increase the allowable current, it is important to flow the surge current with a low resistance and reduce the heat generation of the chip. In addition, the abnormal state only occurs in very rare cases such as when an accident occurs, and the frequency of occurrence is low. Therefore, it is usually not necessary to consider the expansion of crystal defects such as stacking defects and the reliability degradation caused by the energization of the pn diode.

[0113] However, surge tolerance should be improved. From the viewpoint of improving surge tolerance, bipolar current that generates conductivity modulation is suitable for flowing surge current with low resistance compared to unipolar current. In the surge power-on region 301 involved in the present embodiment 1, there is no first separation region 21 connected to the Schottky electrode 71, so unipolar current is not easy to flow. Therefore, at the beginning of surge power-on, in the surge power-on region 301, the pn junction is turned on during the period when the current flowing in the region outside the surge power-on region 301 is low, and bipolar power-on begins. In this state, when the surge current transiently increases and reaches a large current exceeding the rated current, the bipolar current flowing from the surge power-on region 301 further increases, and the holes in the drift layer 20 diffuse toward the active region around the surge power-on region 301.

[0114] In the area that receives the diffusion of holes, the resistance of the drift layer 20 decreases, the unipolar current density increases, and the parasitic pn diode (i.e., body diode) of the MOSFET is turned on. Then, the holes diffuse to the drift layer 20 around this area, and the body diode is turned on in the adjacent active area. That is, when the surge current is energized, the surge energization area 301 becomes the starting point, and the surrounding body diodes chain react, and the body diodes operate one after another. Therefore, when the body diode is turned on in a wide range of the chip, the chip becomes a bipolar energization state, and the low resistance caused by the conductivity modulation reduces the generated energy, so that the heat generated when the chip current flows can be suppressed. That is, the allowable surge current can be increased, so the surge tolerance can be improved.

[0115] Thus, in the surge current region 301, not only can the current flowing in the surge current region 301 be increased, but also the characteristics can be changed in a wide range of the chip through a chain action. Therefore, it does not matter if the surge current region 301 occupies a small area ratio of the active region.

[0116] Fig.18 1 is a diagram showing the result of verifying the chain action of the pn diode from the Schottky barrier diode replacement region 302 having a width of 20 μm by TCAD (Technical CAD) simulation. Fig.18 The higher the density of the dotted shadows, the higher the hole concentration. This shows that as time passes, the body diode chain action region corresponding to the region with a higher hole concentration becomes wider due to the conductivity modulation of the bipolar current. As described above, the body diode chain action region is a region in which the parasitic pn diode, i.e., the body diode, of the MOSFET in the unit cell region is operated by chaining starting from the operation of the pn diode in the Schottky barrier diode replacement region 302.

[0117] It can be confirmed that after the pn diode of the surge power-on region 301 is activated by surge power-on, the hole density of the adjacent cell increases with time, the conductivity modulation is propagated by the action of the body diode as the pn diode, and the body diode chain action region becomes wider. By understanding the propagation speed of the pn diode action during surge power-on, that is, the chain action speed, it is possible to design the area ratio of the body diode chain action region to the active region when a surge power-on of more than 1 msec, which is generally assumed to be an abnormal state, occurs.

[0118] According to the first embodiment, as described above, the SBD conduction is switched to the body diode conduction earlier than when there is no surge conduction region 301. The body diode, which is a pn diode, becomes low resistance due to conductivity modulation of bipolar operation, so the energy density generated decreases at the same time when the body diode starts to conduct. As a result, heat generation during surge conduction is suppressed, and surge tolerance can be improved.

[0119] Fig.19 The graph shows the relationship between the maximum forward voltage VFmax and the applied current IFSM during the surge power-on test in the prototype silicon carbide semiconductor device. In the prototype silicon carbide semiconductor device, the area ratio of the p-type Schottky barrier diode replacement region 302 in the surge power-on region 301 to the active region 15 in a plan view is changed.

[0120] If the Fig.19 As shown in the figure, the SBD is energized in the low current region, and when a certain current flows, it switches to body diode energization, and the slope of the VI characteristic changes according to the resistance change. At this time, the earlier the switch to body diode energization is made, the lower the generated energy is, which is beneficial to surge tolerance. Fig.19 In the above, the area ratio of the Schottky barrier diode replacement region 302 in the active region 15 was changed from about 0.0197% to 0.1967% for evaluation. As a result, it was confirmed that the body diode operation start voltage was lowered as the area ratio was increased, and the switching to the body diode current was earlier.

[0121] Fig. 20 3 is a diagram showing the result of confirming the surge tolerance based on the result. The surge current applied to the silicon carbide semiconductor device gradually increased, and the measurement was performed until the silicon carbide semiconductor device broke down. As a result, it can be confirmed that the surge tolerance is improved in the structure with the Schottky barrier diode replacement region 302 compared to the structure without the Schottky barrier diode replacement region 302.

[0122] In addition, in the present first embodiment, at a position away from the junction of the Schottky electrode 71 and the first separation region 21, the Schottky barrier diode replacement region 302 is connected to the source electrode 80 via the active region second contact hole 90B. That is, in the surge current-carrying region 301, a pn diode is formed that penetrates the source and drain in the chip cross-sectional direction. This pn diode does not need to flow in the p-type layer with a high sheet resistance in the chip plane direction, so when the pn diode is turned on by the surge current, a large bipolar current can flow. Therefore, the Schottky barrier diode replacement region 302 can easily function as the starting point of the pn diode action.

[0123] Furthermore, in the first embodiment, since the unipolar transistor and the bipolar diode coexist in the active region of the same chip, the effective area of ​​the diode region can be reduced compared to the case where one of them is externally connected.

[0124] In order to further improve surge tolerance, it is desirable to evenly arrange a plurality of surge current conducting regions 301 over the entire surface of the active region so that the region where the pn diode operates in linkage with the surge current conducting region 301 is not biased toward the active region. This structure can disperse the heat generating parts.

[0125] <Implementation method 2> Fig.21 1 is a cross-sectional view showing a schematic structure of the surge current conducting region 301 and the active region contact hole 90 according to the second embodiment. Figure 6 As shown in FIG. 2 , a second separation region 22 is formed. In contrast, in the surge current supply region 301 according to the second embodiment, as shown in FIG. Fig.21 As shown, the second isolation region 22 is not formed. As an example of this layout method, in the surge current conducting region 301, the region including the first well region 30, the first isolation region 21, and the second isolation region 22 is all replaced with p-type.

[0126] According to this structure, there is no channel in the surge current region 301, so the surge current region 301 does not have the function of a MOSFET. Therefore, when the gate is turned on, the pn diode is also turned on first, and the operation of the pn diode is not likely to be chained around, so the surge tolerance can be improved.

[0127] <Variations of Implementation Examples 1 and 2> In the above description, the SBD region and the MOSFET region form an integrated unit cell structure, but the SBD and the MOSFET may be arranged in parallel within the unit cell formed in the active region.

[0128] <Implementation method 3> The silicon carbide semiconductor devices 100 according to the first and second embodiments are planar silicon carbide semiconductor devices. In contrast, the silicon carbide semiconductor device 100 according to the third embodiment is a trench silicon carbide semiconductor device.

[0129] (1) Groove type structure Fig. 22 is a plan view of the silicon carbide layer of the silicon carbide semiconductor device 100 according to the third embodiment as viewed from the upper surface, corresponding to Figure 2 A top view of the Fig. 22 In the silicon carbide semiconductor device 100 shown, in the active region, stripe-shaped gate trenches GT forming transistors and stripe-shaped Schottky trenches ST burying Schottky electrodes are alternately arranged in parallel with each other. A second well region 31 is formed in a terminal region around the active region.

[0130] Fig.231 is a plan view of an enlarged active region of the silicon carbide semiconductor device 100 according to the third embodiment. A first connection region 36 and a second connection region 37 composed of p-type silicon carbide formed at a certain interval along their extending directions are formed adjacently in the gate trench GT and the Schottky trench ST, respectively. In addition, in the surge power-on region 301, a p-type Schottky barrier diode replacement region 302 is formed adjacently in the Schottky trench ST. The region including the unit cell region and the surge power-on region 301 is referred to as an active region, and the unit cell region includes the Schottky trench ST roughly corresponding to the SBD region and the gate trench GT roughly corresponding to the MOSFET region.

[0131] In the terminal region of the silicon carbide semiconductor device 100 according to the third embodiment, the same structure as the planar silicon carbide semiconductor device 100 described in the first embodiment, etc., may be formed, or another structure matching the trench type may be formed. Hereinafter, only the active region of the silicon carbide semiconductor device 100 according to the third embodiment will be described.

[0132] Fig.24 It is a schematic diagram showing the Fig.23 Schematic cross-sectional view of a portion where the first connection region 36 and the second connection region 37 are not formed in the active region of the surge current conducting region 301. Fig.25 It is a schematic diagram showing the Fig.23 Schematic cross-sectional view of a portion where a first connection region 36 and a second connection region 37 are formed in an active region of a surge current conducting region 301 of an active region.

[0133] Figure 23 to Figure 25 In the silicon carbide semiconductor device 100 shown in FIG. 1 , a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of low-resistance n-type silicon carbide. In the third embodiment, the semiconductor layer having the active region is the drift layer 20 on the semiconductor substrate 10, but it may also be the semiconductor substrate 10. Fig.24 and Fig.25 As shown in the cross-sectional view of FIG. 1 , a first well region 30 made of p-type silicon carbide is formed in the surface layer portion of the drift layer 20 .

[0134] A source region 40 made of n-type silicon carbide is formed on a portion of the surface of the first well region 30 . A contact region 35 made of low-resistance p-type silicon carbide is formed adjacent to the source region 40 in the remaining surface of the first well region 30 .

[0135] In the active region, a gate trench GT is formed which penetrates the source region 40 and the first well region 30 and reaches the drift layer 20. In addition, a Schottky trench ST is formed which penetrates the source region 40 and the first well region 30 and reaches the drift layer 20 in other locations.

[0136] The gate trenches GT and the Schottky trenches ST are arranged alternately and in parallel with each other. The gate trenches GT and the Schottky trenches ST have the same depth as each other, but may have different depths. In addition, the gate trenches GT and the Schottky trenches ST may be formed with the same width, or the widths of the two may be different.

[0137] In the gate trench GT, a gate electrode 60 is formed via a gate insulating film 50 composed of, for example, silicon oxide. The gate electrode 60 is composed of, for example, low-resistance polysilicon with a high impurity concentration. On the gate electrode 60, an interlayer insulating film 55 composed of, for example, silicon oxide is formed. A Schottky electrode 71 and a source electrode 80 are formed in the Schottky trench ST, and the Schottky electrode 71 is formed to be in contact with the drift layer 20 and to be Schottky-connected to the drift layer 20.

[0138] A p-type first protection region 32 is formed in the drift layer 20 at the bottom of the gate trench GT. A p-type second protection region 33 is formed in the drift layer 20 at the bottom of the Schottky trench ST. The first protection region 32 and the second protection region 33 preferably have the same depth and the same impurity concentration.

[0139] like Fig.25 As shown, the first guard region 32 and the first well region 30 are connected via a p-type first connection region 36. In addition, the second guard region 33 and the first well region 30 are connected via a p-type second connection region 37.

[0140] An ohmic electrode 70 is formed on the surface of the source region 40. A source electrode 80 connected to the ohmic electrode 70, the Schottky electrode 71, and the contact region 35 is formed thereon. The first well region 30 can easily exchange electrons and holes with the ohmic electrode 70 via the low-resistance contact region 35. The source electrode 80 is also connected to the Schottky electrode 71 in the Schottky trench ST.

[0141] The region of the first well region 30 facing the gate electrode 60 via the gate insulating film 50 on the side surface of the gate trench GT where the gate electrode 60 is formed is referred to as a channel region. An SBD is formed at a portion where the Schottky electrode 71 and the drift layer 20 are in contact on the side surface of the Schottky trench ST.

[0142] A drain electrode 84 is formed on the back surface side of the semiconductor substrate 10 .

[0143] In addition, the second well region 31 of the terminal region may have the same depth and thickness as the first well region 30 of the active region. In addition, the second well region 31 of the terminal region may be formed to the depth of the bottom of the gate trench GT and the Schottky trench ST so as to have the same depth as the first protection region 32 and the second protection region 33 of the active region. In addition, a low-resistance n-type silicon carbide conductive layer 45 may be formed on the surface of the second well region 31. In addition, the second well region 31 may not be directly ohmically connected to the source electrode 80.

[0144] like Fig.24 As shown, in the third embodiment, the first separation region 21 corresponds to a region that is in contact with the side surface of the Schottky trench ST and is sandwiched between the first well region 30 and the second protection region 33 that are in contact with the Schottky trench ST. In addition, the second separation region 22 corresponds to a region that is in contact with the side surface of the gate trench GT and is sandwiched between the first well region 30 and the first protection region 32 that are in contact with the gate trench GT.

[0145] In the surge current conducting region 301, the first isolation region 21 is replaced by a p-type Schottky barrier diode replacement region 302 that is in contact with the side surface of the Schottky trench ST. Fig.24 and Fig.25 , for convenience, the boundary of the Schottky barrier diode replacement region 302 is indicated by a dotted line. The Schottky electrode 71 is not connected to the n-type silicon carbide layer such as the first separation region 21 of the same n-type as the drift layer 20, and the Schottky electrode 71 and the drift layer 20 are disconnected by the p-type Schottky barrier diode replacement region 302.

[0146] In addition, in the present embodiment 3, similarly to the embodiment 1, the area ratio of the Schottky barrier diode replacement region 302 to the active region 15 when viewed from above is greater than 0.01%, and is less than the area ratio of the SBD region to the active region 15 when not replaced by the Schottky barrier diode replacement region 302, and is more preferably greater than 0.01% and less than 5%.

[0147] (2) Groove type manufacturing method Next, use Figure 26 to Figure 31 The manufacturing method of the trench type silicon carbide semiconductor device 100 according to the third embodiment is described with reference to a schematic cross-sectional view of the active region of FIG. Here, the manufacturing method of the portion where the first connection region 36, the second connection region 37, and the Schottky barrier diode replacement region 302 are not formed is described, but since the portion where these regions are formed is roughly the same as the following, they are appropriately described without being shown in the figure.

[0148] First, a semiconductor substrate 10 is prepared. The semiconductor substrate 10 is a surface whose first main surface has an offset angle (0001) in the plane orientation and is composed of n-type and low-resistance silicon carbide having a 4H polymorph. On the semiconductor substrate 10, for example, 1×10 15 Up to 1×10 17 cm -3 The drift layer 20 composed of silicon carbide having an n-type impurity concentration of, for example, 5 to 50 μm in thickness is epitaxially grown.

[0149] Next, p-type impurities, i.e., Al, are ion-implanted into the surface of the drift layer 20. At this time, the depth of the Al ion implantation is set to be not more than the thickness of the drift layer 20, for example, about 0.5 to 3 μm. In addition, the impurity concentration of the ion-implanted Al is, for example, 1×10 17 Up to 1×10 19 cm -3 , which is higher than the impurity concentration of the drift layer 20. The region after Al ion implantation in this process becomes the first well region 30 in the active region and the second well region 31 in the terminal region. In addition, the first well region 30 can be formed on the drift layer 20 by epitaxy instead of ion implantation.

[0150] Next, in a predetermined region of the surface layer portion of the first well region 30, an impurity concentration higher than that of the first well region 30 is applied, for example, 1×10 16 Up to 1×10 18 cm -3 Al is ion-implanted at an impurity concentration of 100 to form a contact region 35. In addition, N, which is an n-type impurity, is ion-implanted in a predetermined region of the surface layer of the first well region 30. The ion-implanted depth of N is shallower than the thickness of the first well region 30. In addition, the impurity concentration of the ion-implanted N is, for example, 1×10 18 Up to 1×10 21 cm -3 , which is higher than the p-type impurity concentration of the first well region 30. In this step, the region showing n-type in the region into which N is implanted becomes the source region 40. Fig.26 This is a cross-sectional view of the active region after the process up to this stage is completed.

[0151] Next, one of the gate trench GT and the Schottky trench ST is formed in a source region 40 between adjacent contact regions 35. In addition, the gate trench GT and the Schottky trench ST are arranged alternately. At the bottom of each of the gate trench GT and the Schottky trench ST, p-type impurities, i.e., Al, are ion-implanted. Thus, a first protection region 32 is formed at the bottom of the gate trench GT, and a second protection region 33 is formed at the bottom of the Schottky trench ST. The impurity concentration of each of the first protection region 32 and the second protection region 33 is, for example, 1×1017 Up to 1×10 19 cm -3 .

[0152] The first connection region 36 and the second connection region 37 formed in the gate trench GT and the Schottky trench ST, respectively, are formed by, for example, implanting ions of p-type impurities such as Al obliquely from a direction perpendicular to the extending direction of each trench. The impurity concentration of each of the first connection region 36 and the second connection region 37 is, for example, 1×10 17 Up to 1×10 19 cm -3 .

[0153] The Schottky barrier diode replacement region 302 is formed by, for example, obliquely implanting p-type impurity ions such as Al from a direction perpendicular to the extension direction of the Schottky trench ST, similarly to the first connection region 36 and the second connection region 37. The impurity concentration of the Schottky barrier diode replacement region 302 is 1×10 17 Up to 1×10 19 cm -3 If the Schottky barrier diode replacement region 302 is formed simultaneously with at least one of the first connection region 36 and the second connection region 37 , the number of steps can be reduced.

[0154] Here, when the plane orientation of the first main surface of the semiconductor substrate 10 is a surface having an offset angle (0001) in the <11-20> direction, the extension direction of the gate trench GT and the Schottky trench ST in the active region can be parallel to the offset direction, i.e., the <11-20> direction. According to this structure, the Schottky trench ST and the trench sidewalls on both sides thereof are not affected by the offset direction of the semiconductor substrate 10, and thus the deviation of the barrier height of the Schottky interface of the Schottky trench ST can be reduced. In addition, the threshold voltage of the MOSFET of the gate trench GT is not affected by the offset direction of the semiconductor substrate 10, and thus the deviation of the threshold voltage of the MOSFET can be reduced.

[0155] Next, the drift layer 20 is annealed at 1300 to 1900° C. for 30 seconds to 1 hour in an inert gas atmosphere such as argon using a heat treatment apparatus. The ion-implanted N and Al are electrically activated by the annealing. Fig. 27 This is a cross-sectional view of the active region after the process up to this stage is completed.

[0156] Then, if Fig.28 As shown, the interior of Schottky trench ST is filled with a protective insulating film 52 made of silicon oxide.

[0157] Next, the silicon carbide surface not covered by the protective insulating film 52 is thermally oxidized to form a gate insulating film 50 of a desired thickness, for example, made of silicon oxide, in the gate trench GT. Next, on the gate insulating film 50, for example, a polysilicon film having conductivity is formed by a reduced pressure CVD method, and the polysilicon film is patterned to form a gate electrode 60. Next, on the gate electrode 60, an interlayer insulating film 55 having a greater film thickness than the gate insulating film 50, for example, made of silicon oxide, is formed by a reduced pressure CVD method. Next, the interlayer insulating film 55 and the gate insulating film 50 are selectively removed by wet etching to expose the contact region 35 and the source region 40 in the active region. Fig.29 This is a cross-sectional view of the active region after the process up to this stage is completed.

[0158] Next, a metal film mainly composed of Ni is formed on the surface of the silicon carbide layer of the exposed source region 40 and the contact region 35 by, for example, sputtering, and then a heat treatment is performed at a temperature of 600 to 1100° C. Thus, the metal film mainly composed of Ni reacts with the silicon carbide layer to form a silicide layer between the metal film and the silicon carbide layer. Next, the remaining metal film other than the silicide layer is removed by wet etching. Thus, the remaining silicide layer becomes the ohmic electrode 70. Fig.30 This is a cross-sectional view of the active region after the process up to this stage is completed.

[0159] Next, after the protective insulating film 52 in the Schottky trench ST is removed by hydrofluoric acid or the like, the Schottky electrode 71 is formed in the Schottky trench ST. The material of the Schottky electrode 71 is, for example, Ti, Mo or the like.

[0160] Next, a source electrode 80 mainly composed of Al is formed in contact with the Schottky electrode 71 and the ohmic electrode 70 . Fig.31 8 is a cross-sectional view of the active region after the steps up to this stage are completed. The gate pad 81 and the gate wiring 82 are formed in the same manner as the source electrode 80 . The gate pad 81 and the gate wiring 82 can be formed at the same time as the source electrode 80 .

[0161] Next, a metal film mainly composed of Ni is formed on the back surface of the semiconductor substrate 10 and heat-treated to form a back ohmic electrode, that is, a drain electrode 84, on the back surface side of the semiconductor substrate 10. Fig.24 A silicon carbide semiconductor device 100 according to the third embodiment is shown.

[0162] (3) Action description The operation and effects of the trench-type silicon carbide semiconductor device 100 according to the third embodiment are the same as those of the planar-type silicon carbide semiconductor device 100 according to the first and second embodiments, and thus detailed descriptions thereof will be omitted.

[0163] <Implementation method 4> Fig.32 1 is a block diagram schematically showing a configuration of a power module device 101 according to Embodiment 4. The power module device 101 includes a plurality of silicon carbide semiconductor devices 100 , each of which is the silicon carbide semiconductor device 100 according to any one of Embodiments 1 to 4.

[0164] This configuration can improve the surge tolerance of the power module device 101 when a surge current is applied. In addition, the power module device 101 can ensure a longer time from surge current detection to interruption, thereby increasing the freedom of design of a surge protection circuit (not shown) that operates when a surge current is applied.

[0165] In addition, in order to increase the current handled by the power module device 101, a plurality of silicon carbide semiconductor devices that perform the functions of a switching element and a return diode may be connected in parallel. The plurality of silicon carbide semiconductor devices may include a silicon carbide semiconductor device 100 having a surge power-carrying region 301 and a silicon carbide semiconductor device that does not have a surge power-carrying region 301. However, the plurality of silicon carbide semiconductor devices may include only the silicon carbide semiconductor device 100 so that when a surge current flows, the pn diode of a specific silicon carbide semiconductor device is turned on and the current is not concentrated on the silicon carbide semiconductor device.

[0166] <Implementation method 5> Fig.33 1 is a block diagram showing a power conversion device 501 according to Embodiment 5. The power conversion device 501 includes a control circuit 501a, a drive circuit 501b, and a main conversion circuit 501c equipped with a silicon carbide semiconductor device 100 according to any one of Embodiments 1 to 4. In addition, the main conversion circuit 501c may be equipped with a power module device 101 according to Embodiment 4 instead of the silicon carbide semiconductor device 100 according to any one of Embodiments 1 to 4.

[0167] The drive circuit 501b drives the silicon carbide semiconductor device 100 of the main conversion circuit 501c based on the control signal from the control circuit 501a. For example, when the return current flows through the return diode, that is, the parasitic pn diode of the silicon carbide semiconductor device 100, the drive circuit 501b turns on the gate of the MOSFET of the silicon carbide semiconductor device 100 except for a short dead time. According to this structure, the unipolar current through the channel can be energized, and the heat concentration in the surge energization area 301 can be avoided.

[0168] The main conversion circuit 501 c including the silicon carbide semiconductor device 100 converts the electric power from the power source 502 into electric power that can be used by the load 503 by driving the silicon carbide semiconductor device 100 based on the control signal.

[0169] According to the above structure, the surge tolerance of the power conversion device 501 when the surge current is applied can be improved. In addition, the time from surge current detection to cutoff can be ensured to be long in the power conversion device 501, so the design freedom of the surge protection circuit (not shown) that operates when the surge current is applied can be improved.

[0170] In the fifth embodiment, the silicon carbide semiconductor device 100 according to the first to fourth embodiments is used as a switching element of the main conversion circuit 501 c , so that a power conversion device 501 with low loss and high reliability of high-speed switching can be realized.

[0171] <Implementation method 6> Fig.34 This is a diagram showing a moving object 601 according to the sixth embodiment. Fig.34 In the example of , the mobile body 601 is a train, but the present invention is not limited thereto. The mobile body 601 is provided with the power conversion device 501 according to the fifth embodiment, and the power conversion device 501 generates the electric power required by the mobile body 601. According to this structure, the power conversion device used for the mobile body 601 can obtain the same effect as the power conversion device 501 according to the fifth embodiment.

[0172] <Supplementary explanation on Embodiments 1 to 6> The p-type impurity described above may be boron (B) or gallium (Ga), rather than aluminum (Al). The n-type impurity described above may be phosphorus (P) rather than nitrogen (N). The gate insulating film 50 described above does not necessarily have to be an oxide film such as SiO2, but may also be an insulating film other than an oxide film or a combination of an insulating film and an oxide film other than an oxide film. In addition, the gate insulating film 50 may be a deposited film composed of silicon oxide formed by a CVD method, etc., rather than silicon oxide after thermal oxidation of silicon carbide. In addition, in the above description, specific examples such as crystal structure, surface orientation of the main surface, offset angle and various injection conditions are used for illustration, but are not limited to these numerical ranges. In addition, the silicon carbide semiconductor device 100 can be configured to have a MOSFET with a super junction structure with a built-in SBD.

[0173] In addition, the embodiments and the modifications can be freely combined, and the embodiments and the modifications can be appropriately modified or omitted.

[0174] The above description is intended in all respects to be illustrative rather than restrictive, and it will be appreciated that numerous variations not shown here are conceivable. Description of symbols

[0175] 15 Active area 16 Body diode interlocking action area 20 Drift layer 100 Silicon carbide semiconductor device 101 Power module device 301 Surge Power Area 302 Schottky barrier diode replacement area 501 Power conversion device 551 Mobile body.

Claims

1. A silicon carbide semiconductor device, characterized in that: include: a semiconductor layer of a first conductivity type, the semiconductor layer of the first conductivity type having an active region including a unit cell region and a surge current conduction region, wherein the unit cell region includes a Schottky barrier diode region and a MOSFET region, The surge current conducting region includes a Schottky barrier diode replacement region in which the first conductivity type of the Schottky barrier diode region is replaced with a second conductivity type. The area ratio of the Schottky barrier diode replacement region to the active region is greater than 0.01% and is smaller than the area ratio of the Schottky barrier diode region to the active region when the Schottky barrier diode replacement region is not replaced.

2. The silicon carbide semiconductor device according to claim 1, wherein: The surge current conduction region has the function of a MOSFET.

3. The silicon carbide semiconductor device according to claim 1, wherein: The surge current conduction region does not have the function of a MOSFET.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein: The area ratio of the surge current conducting region to the active region is greater than or equal to 0.01% and less than or equal to 5%.

5. A power module device, characterized in that: include: A plurality of silicon carbide semiconductor devices, each of the plurality of silicon carbide semiconductor devices is the silicon carbide semiconductor device according to any one of claims 1 to 4.

6. A power conversion device, characterized in that: Electric power is converted using a power module device, the power module device including the silicon carbide semiconductor device according to any one of claims 1 to 4.

7. A mobile body, characterized in that: A power conversion device as claimed in claim 6 is provided.

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