PWM wave output self-detection circuit applied to airborne electromechanical management system

Abstract

The invention relates to a PWM wave output self-detection circuit applied to an airborne electromechanical management system, and belongs to the technical field of aviation airborne electromechanical management systems. According to the scheme of the invention, through the matching design of the triode driving circuit, the optical relay output circuit and the comparator circuit, the self-detection of the PWM wave output of the airborne electromechanical management system and the periodic monitoring of the PWM wave output are realized, the testability index of the product is improved, and the rapid fault positioning of the product outfield is greatly facilitated.

Description

Technical Field

[0001] The invention belongs to the technical field of aviation airborne electromechanical management systems, and in particular relates to a PWM wave output self-detection circuit applied to an airborne electromechanical management system. Background Art

[0002] As the functions and performance of airborne products become more and more complex, product fault detection becomes more difficult. In order to quickly locate product faults, quickly repair products and improve product reliability, airborne electromechanical systems have increasingly higher requirements for product testability. In the past, products usually did not implement self-detection of PWM wave output, making it difficult to quickly locate the source of the fault during field troubleshooting. To address the above issues, it is necessary to design a self-detection solution for the PWM wave output of the airborne electromechanical management system to achieve periodic monitoring of the PWM wave output. Summary of the invention

[0003] 1. Technical issues to be resolved

[0004] The technical problem to be solved by the present invention is: in an aviation airborne electromechanical management system, in view of the problem that previous products usually do not realize self-detection of PWM wave output, and it is difficult to quickly locate the source of the fault during field troubleshooting, a PWM wave output self-detection circuit applied to the airborne electromechanical management system is provided to realize periodic monitoring of the PWM wave output.

[0005] (II) Technical solution

[0006] In order to solve the above technical problems, the present invention provides a PWM wave output self-detection circuit applied to an airborne electromechanical management system, comprising a transistor drive circuit, a photorelay output circuit and a comparator circuit;

[0007] The transistor driving circuit includes: a field programmable logic gate array FPGA, a transistor V1; the output port I01 of the FPGA is connected to the base of V1, and the collector of V1 is connected to the first input terminal 3 pin of the photorelay V2 in the photorelay output circuit;

[0008] The field programmable logic gate array FPGA outputs a control signal. When the control signal is high and effective, the collector and emitter of the transistor V1 are turned on, driving the photorelay V2 in the photorelay output circuit to turn on and output a high effective signal of the PWM waveform. When the control signal is low and ineffective, the collector and emitter of the transistor V1 are turned off, thereby turning off the high effective signal of the PWM waveform output by the photorelay V2.

[0009] The photorelay output circuit includes: a photorelay V2; when the transistor drive circuit is turned on, the primary side of the photorelay V2 generates a current of about 15mA, the secondary side is turned on, and a high effective signal of a PWM waveform is output; when the transistor drive circuit is turned off, there is no current on the primary side, the secondary side of the photorelay V2 is turned off, and the high effective signal of the PWM waveform is turned off;

[0010] The comparator circuit includes a diode V4, resistors R5 and R6, and a comparator N1; the positive electrode of V4 is connected to the first output terminal of V2, namely, pins 6 and 7, and the negative electrode is connected to the first end of R5; the second end of R5 is connected to the first end of R6 and the inverting end of N1, and the inverting end of N1 is connected to the +2.5V reference voltage; the output end of N1 is connected to the input port I02 of the FPGA;

[0011] The PWM waveform output by the photorelay V2 is isolated by the diode V4, and then input into the voltage divider circuit composed of the resistors R5 and R6, and then converted into a suitable voltage and input into the inverting terminal of the comparator N1. The +2.5V reference voltage is input into the non-inverting terminal of the comparator N1. The voltages of the inverting terminal and the non-inverting terminal of the comparator N1 are compared. When the high effective signal of the PWM waveform is output, the output terminal of the comparator N1 outputs a low level after hysteresis comparison; when the high effective signal of the PWM waveform is cut off, the output terminal of the comparator N1 outputs a high level after hysteresis comparison. After the high and low levels of the output terminal of the comparator N1 enter the input port IO2 of the FPGA, the FPGA collects and calculates the period and duty cycle of the PWM waveform output, so as to realize the self-detection of the PWM wave output of the airborne electromechanical management system.

[0012] The invention also provides an aviation airborne electromechanical management system based on the circuit design.

[0013] (III) Beneficial effects

[0014] The solution of the present invention realizes self-detection of the PWM wave output of the airborne electromechanical management system and periodic monitoring of the PWM wave output through matching design of the transistor drive circuit, the photorelay output circuit and the comparator circuit, thereby improving the testability index of the product and greatly facilitating rapid fault location of the product in the field. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the circuit principle of the present invention. DETAILED DESCRIPTION

[0016] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0017] refer to Figure 1, the present invention provides a PWM wave output self-detection circuit applied to an airborne electromechanical management system, including a transistor drive circuit, a photorelay output circuit and a comparator circuit;

[0018] The transistor driving circuit includes: a field programmable logic gate array FPGA, a transistor V1; the output port I01 of the FPGA is connected to the base of V1, and the collector of V1 is connected to the first input terminal 3 pin of the photorelay V2 in the photorelay output circuit;

[0019] The field programmable logic gate array FPGA outputs a control signal. When the control signal is high and effective, the collector and emitter of the transistor V1 are turned on, driving the photorelay V2 in the photorelay output circuit to turn on and output a high-effective signal of the PWM waveform. When the control signal is low and invalid, the collector and emitter of the transistor V1 are turned off, thereby cutting off the high-effective signal of the PWM waveform output by the photorelay V2.

[0020] The photorelay output circuit includes: photorelay (photocoupler) V2;

[0021] When the transistor drive circuit is turned on, the primary side of the photorelay V2 generates a current of about 15mA, the secondary side is turned on, and a high effective signal of the PWM waveform is output. When the transistor drive circuit is turned off, there is no current on the primary side, the secondary side of the photorelay V2 is turned off, and the high effective signal of the PWM waveform is turned off.

[0022] The comparator circuit includes a diode V4, resistors R5 and R6, and a comparator N1; the positive electrode of V4 is connected to the first output terminal of V2, namely, pins 6 and 7, and the negative electrode is connected to the first end of R5; the second end of R5 is connected to the first end of R6 and the inverting end of N1, and the inverting end of N1 is connected to the +2.5V reference voltage; the output end of N1 is connected to the input port I02 of the FPGA;

[0023] The PWM waveform output by the photorelay V2 is isolated by the diode V4, and then input into the voltage divider circuit composed of the resistors R5 and R6, and then converted into a suitable voltage and input into the inverting terminal of the comparator N1. The +2.5V reference voltage is input into the non-inverting terminal of the comparator N1. The voltages of the inverting terminal and the non-inverting terminal of the comparator N1 are compared. When the high effective signal of the PWM waveform is output, the output terminal of the comparator N1 outputs a low level after hysteresis comparison; when the high effective signal of the PWM waveform is cut off, the output terminal of the comparator N1 outputs a high level after hysteresis comparison. After the high and low levels of the output terminal of the comparator N1 enter the input port IO2 of the FPGA, the FPGA collects and calculates the period and duty cycle of the PWM waveform output, so as to realize the self-detection of the PWM wave output of the airborne electromechanical management system.

[0024] A resistor R1 is also connected between the output port IO1 of the FPGA and the base of V1, and a capacitor C1 and a resistor R2 are also connected in parallel between the base and emitter of V1; resistors R3 and R4 are connected in series between the collector of V1 and the second input terminal 2 of V2, and a +5V power supply is connected between R3 and R4; the +2.5V reference voltage is connected to a resistor R7 and then input to the in-phase terminal of N1; a resistor R8 is also connected between the in-phase terminal and the output terminal of N1; V4 outputs a PWM wave PWM_OUT through a diode V3, and the positive pole of V4 is connected to the positive pole of V3; the output terminal of N1 is also connected to a pull-up resistor R9.

[0025] When the output port IO1 of the FPGA outputs a high level, the collector of pin 3 and the emitter of pin 2 of V1 are turned on. When the output port IO1 of the FPGA outputs a low level, the collector of pin 3 and the emitter of pin 2 of V1 are cut off. R1 can output a suitable current for the emitter of V1 to ensure that V1 works normally in the saturation area.

[0026] The function of C1 is to eliminate the glitches and jitters of the FPGA output port IO1 through filtering, and to prevent the 3-pin collector and 2-pin emitter of V1 from malfunctioning.

[0027] The function of R2 is to provide a pull-down resistor for the base of V1 to prevent V1 from being mistakenly turned on when the output port IO1 of the FPGA is in a high-impedance state.

[0028] When the collector of pin 3 and the emitter of pin 2 of V1 are turned on, pins 2 and 3 of V2 are turned on, and pins 6, 7 and pins 5, 8 are turned on, where pins 5, 8 are connected as the second output end of V2, and pins 6, 7 of V2 output DC28V; when the collector of pin 3 and the emitter of pin 2 of V1 are cut off, pins 2 and 3 of V2 are cut off, pins 6, 7 and pins 5, 8 are cut off, and pins 6 and 7 have no output. Different PWM waveforms are generated according to the output of different cycles and duty cycles.

[0029] The function of R3 is to provide a pull-up resistor for the collector of pin 3 of V1 to prevent pins 2 and 3 of V2 from being mistakenly turned on; the function of R4 is to output a suitable current between pins 2 and 3 of V2 to ensure that pins 2 and 3 of V2 work normally.

[0030] The PWM waveform output from pins 6 and 7 of V2 is input to the inverting terminal of N1 through V4, R5, and R6, and the +2.5V reference voltage is input to the non-inverting terminal of N1. When the PWM waveform output from pins 6 and 7 of V2 is DC28V, the voltage input to the inverting terminal of N1 is about (28-2) / 12*2=4.5V, which is greater than the reference voltage of 2.5V, and the output terminal of N1 outputs a low level. When the PWM waveform output from pins 6 and 7 of V2 is no output, the voltage input to the inverting terminal of N1 is about 0V, which is less than the reference voltage of 2.5V, and the output terminal of N1 outputs a high level. The output terminal of N1 converts the collected PWM waveform into a high and low level with a peak value of DC3.3V, and then inputs it to the input port IO2 of the FPGA. The FPGA calculates the input high and low level period and duty cycle, and then compares them with the calculated period and duty cycle of the PWM waveform. If the comparison results are consistent, it is considered that the PWM wave output self-detection is normal. If the comparison results are inconsistent, it is considered that the PWM wave output self-detection is abnormal.

[0031] Diodes V3 and V4 can prevent external current input. The role of R5 and R6 is to divide the PWM waveform DC28V to ensure that the voltage drop on R6, that is, the voltage input to the inverting terminal of comparator N1, is (28-2) / 12*2=4.5V; the role of R7 and R8 is the hysteresis function to prevent the output of comparator N1 from jittering; the role of R9 is to pull up the high-impedance state of the output of comparator N1 to DC3.3V.

[0032] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A PWM wave output self-detection circuit applied to an airborne electromechanical management system, characterized in that: It includes a transistor drive circuit, a photorelay output circuit and a comparator circuit; The transistor driving circuit includes: a field programmable logic gate array FPGA, a transistor V1; the output port I01 of the FPGA is connected to the base of V1, and the collector of V1 is connected to the first input terminal 3 pin of the photorelay V2 in the photorelay output circuit; The field programmable logic gate array FPGA outputs a control signal. When the control signal is high and effective, the collector and emitter of the transistor V1 are turned on, driving the photorelay V2 in the photorelay output circuit to turn on and output a high effective signal of the PWM waveform. When the control signal is low and ineffective, the collector and emitter of the transistor V1 are turned off, thereby turning off the high effective signal of the PWM waveform output by the photorelay V2. The photorelay output circuit includes: a photorelay V2; when the transistor drive circuit is turned on, the primary side of the photorelay V2 generates a current of about 15mA, the secondary side is turned on, and a high effective signal of a PWM waveform is output; when the transistor drive circuit is turned off, there is no current on the primary side, the secondary side of the photorelay V2 is turned off, and the high effective signal of the PWM waveform is turned off; The comparator circuit includes a diode V4, resistors R5 and R6, and a comparator N1; the positive electrode of V4 is connected to the first output terminal of V2, namely, pins 6 and 7, and the negative electrode is connected to the first end of R5; the second end of R5 is connected to the first end of R6 and the inverting end of N1, and the inverting end of N1 is connected to the +2.5V reference voltage; the output end of N1 is connected to the input port I02 of the FPGA; The PWM waveform output by the photorelay V2 is isolated by the diode V4, and then input into the voltage divider circuit composed of the resistors R5 and R6, and then converted into a suitable voltage and input into the inverting terminal of the comparator N1. The +2.5V reference voltage is input into the non-inverting terminal of the comparator N1. The voltages of the inverting terminal and the non-inverting terminal of the comparator N1 are compared. When the high effective signal of the PWM waveform is output, the output terminal of the comparator N1 outputs a low level after hysteresis comparison; when the high effective signal of the PWM waveform is cut off, the output terminal of the comparator N1 outputs a high level after hysteresis comparison. After the high and low levels of the output terminal of the comparator N1 enter the input port IO2 of the FPGA, the FPGA collects and calculates the period and duty cycle of the PWM waveform output, so as to realize the self-detection of the PWM wave output of the airborne electromechanical management system.

2. The circuit according to claim 1, characterized in that A resistor R1 is also connected between the FPGA output port IO1 and the base of V1. When the FPGA output port IO1 outputs a high level, the collector and emitter of V1 are turned on. When the FPGA output port IO1 outputs a low level, the collector and emitter of V1 are turned off. R1 can output a suitable current for the emitter of V1 to ensure that V1 works normally in the saturation area.

3. The circuit according to claim 1, characterized in that Capacitor C1 and resistor R2 are also connected in parallel between the base and emitter of V1. C1 can eliminate the burrs and jitters of the FPGA output port IO1 through filtering to prevent the collector and emitter of V1 from malfunctioning. R2 provides a pull-down resistor for the base of V1 to prevent V1 from being misconnected when the FPGA output port IO1 is in a high-impedance state.

4. The circuit according to claim 1, characterized in that Resistors R3 and R4 are connected in series between the collector of V1 and the second input terminal 2 of V2; when the collector of pin 3 of V1 and the emitter of pin 2 are turned on, pins 2 and 3 of V2 are turned on, and pins 6 and 7 and pins 5 and 8 are turned on, among which pins 5 and 8 are connected as the second output terminal of V2, and pins 6 and 7 of V2 output DC28V; When the collector of pin 3 and the emitter of pin 2 of V1 are cut off, pins 2 and 3 of V2 are cut off, pins 6, 7 and pins 5, 8 are cut off, and pins 6 and 7 have no output. Different PWM waveforms are generated according to the output of different cycles and duty cycles; R3 provides a pull-up resistor for the collector of pin 3 of V1 to prevent pins 2 and 3 of V2 from being mistakenly turned on; R4 outputs a suitable current between pins 2 and 3 of V2 to ensure that pins 2 and 3 of V2 work normally.

5. The circuit according to claim 1, characterized in that The PWM waveform output from pins 6 and 7 of V2 is input to the inverting terminal of N1 through V4, R5, and R6, and the +2.5V reference voltage is input to the non-inverting terminal of N1. When the PWM waveform output from pins 6 and 7 of V2 is DC28V, the voltage input to the inverting terminal of N1 is about (28-2) / 12*2=4.5V, which is greater than the reference voltage of 2.5V, and the output terminal of N1 outputs a low level. When the PWM waveform output from pins 6 and 7 of V2 is no output, the voltage input to the inverting terminal of N1 is about 0V, which is less than the reference voltage of 2.5V, and the output terminal of N1 outputs a high level. The output terminal of N1 converts the collected PWM waveform into a high and low level with a peak value of DC3.3V, and then inputs it to the input port IO2 of the FPGA. The FPGA calculates the input high and low level period and duty cycle, and then compares them with the calculated period and duty cycle of the PWM waveform. If the comparison results are consistent, it is considered that the PWM wave output self-detection is normal. If the comparison results are inconsistent, it is considered that the PWM wave output self-detection is abnormal.

6. The circuit according to claim 1, characterized in that A +5V power supply is connected between R3 and R4; a +2.5V reference voltage is connected to a resistor R7 and then input to the non-inverting terminal of N1; a resistor R8 is also connected between the non-inverting terminal and the output terminal of N1; R7 and R8 realize the hysteresis function to prevent N1 output jitter.

7. The circuit according to claim 1, characterized in that V4 outputs a PWM wave PWM_OUT through a diode V3. The anode of V4 is connected to the anode of V3. Diodes V3 and V4 can prevent external current input.

8. The circuit according to claim 5, characterized in that R5 and R6 can divide the PWM waveform DC28V to ensure that the voltage drop across R6, i.e. the voltage at the inverting end of the input comparator, is (28-2) / 12*2=4.5V.

9. The circuit according to claim 1, characterized in that The output end of N1 is also connected to a pull-up resistor R9, which can pull up the high-impedance state of N1 output to DC3.3V.

10. An aircraft-borne electromechanical management system based on the circuit design according to any one of claims 1 to 9.

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