A method and apparatus for internal harmonic analysis of a metering chip

Abstract

This invention relates to a method and apparatus for internal harmonic analysis of a metering chip, belonging to the field of power metering technology. The invention performs power frequency synchronization processing on the data, calculates the relative deviation value of the fundamental frequency and the standard frequency, processes the frequency deviation value of the current data based on the power frequency synchronization output skip flag of the previous data, determines the relationship between the processed frequency deviation value and 0.5 and -0.5, processes the deviation value accordingly, and then inputs the processing result into a polynomial with multiple filtering results from the current and previous data as coefficients for calculation to obtain the power frequency synchronization output data. This solves the problem of increased computational load caused by the inability to perform synchronous sampling due to fluctuations in the power grid frequency.

Description

Technical Field

[0001] This invention belongs to the field of electrical energy metering technology, specifically relating to a method and device for internal harmonic analysis of a metering chip. Background Technology

[0002] The widespread application of power electronic equipment and the increasing number of other nonlinear loads in power systems have led to the generation of a large number of high-order harmonics in the power grid, causing serious deterioration of power quality and endangering the normal operation of electrical equipment and power systems. High-precision analysis of harmonics can provide a basis for harmonic control in the power grid.

[0003] The Fast Fourier Transform (FFT) has become the primary method for harmonic analysis due to its ease of implementation in embedded digital signal processing systems. However, because the power grid frequency is not fixed and fluctuates within a range of 50±2.5Hz, it is difficult to achieve strictly synchronized sampling. Under asynchronous sampling conditions, when using FFT to analyze truncated data, long-range leakage occurs. In addition, when the frequency point to be analyzed is not on a discrete frequency point, the nearest discrete frequency point value is usually used as a substitute, resulting in short-range leakage (also known as the picket fence effect). To address the long-range leakage problem, windowing or zero-padding is usually used to improve it. Increasing the length of the truncated data can improve the picket fence effect, but both zero-padding and increasing the data length will increase the computational load. Summary of the Invention

[0004] The purpose of this invention is to provide a method and apparatus for internal harmonic analysis of a metering chip, in order to solve the problem of large computational load in harmonic analysis.

[0005] To address the aforementioned technical problems, this invention provides a method for harmonic analysis within a metering chip, comprising the following steps:

[0006] 1) If the power frequency synchronization method is used to perform harmonic analysis on the input discrete digital signal data, multiple filters with different filter coefficients are used to filter the input data to obtain multiple current data filtering results; the fundamental frequency is extracted, the relative deviation value of the fundamental frequency relative to the standard frequency is calculated, and the frequency deviation value of the current data is processed accordingly based on the power frequency synchronization skip flag of the previous data.

[0007] If the processed frequency deviation is greater than 0.5, then calculate the first deviation and the second deviation. The first deviation is the processed frequency deviation minus 1, and the second deviation is the first deviation plus the relative deviation. Substitute the first deviation into a polynomial with multiple filtering results of the previous data as coefficients for calculation, and the result is used as the power frequency synchronization output data. Substitute the second deviation into a polynomial with multiple filtering results of the current data as coefficients for calculation, and the result is used as the power frequency synchronization output data.

[0008] If the processed frequency deviation value is greater than or equal to -0.5 and less than or equal to 0.5, the second deviation value is the processed frequency deviation value; the second deviation value is substituted into the polynomial with the current data filtering result as the coefficient for calculation, and the calculation result is used as the power frequency synchronization output data;

[0009] While outputting the power frequency synchronous output data, update the power frequency synchronous output skip flag of the previous data, and use the filtering result of the current data as the filtering result of the previous data; reprocess the frequency deviation value of the current data according to the power frequency synchronous output skip flag of the previous data for iterative calculation; when the power frequency synchronous output data is a whole cycle length, output the data.

[0010] 2) Perform FFT calculation on the output data, and perform harmonic analysis based on the FFT calculation results.

[0011] Furthermore, if the processed frequency deviation value is less than -0.5, the processed frequency deviation value is incremented by 1 to become the frequency deviation value of the previous data, the power frequency synchronization output skip flag of the previous data is updated, the filtering result of the current data is used as the filtering result of the previous data, and if the current data is the first input data, the filtering result of the previous data is set to 0; the frequency deviation value of the current data is reprocessed according to the power frequency synchronization output skip flag of the previous data for iterative calculation.

[0012] Furthermore, if the processed frequency deviation value is less than -0.5, the power frequency synchronization output skip flag of the previous data is updated to 1; otherwise, the power frequency synchronization output skip flag of the previous data is updated to 0. The specific method for processing the frequency deviation value of the current data according to the power frequency synchronization output skip flag of the previous data is as follows: when the power frequency synchronization output skip flag of the previous data is 1, the frequency deviation value of the previous data is used as the frequency deviation value of the current data; when the power frequency synchronization output skip flag of the previous data is 0, the sum of the frequency deviation value of the previous data and the relative deviation value is used as the frequency deviation value of the current data.

[0013] Furthermore, the filter mentioned in step 1) is an FIR filter.

[0014] Furthermore, there are 5 different sets of filter coefficients.

[0015] Furthermore, if the harmonic analysis method of Rife-Vincent window interpolation FFT is used to perform harmonic analysis on the input discrete digital signal data, the input discrete digital signal data is de-DC processed to obtain de-DC data, the de-DC data is corrected and compensated to obtain corrected and compensated data, the corrected and compensated data is windowed and FFT calculated to obtain FFT output data, and the fundamental frequency interval is obtained from the maximum value and the position of the maximum value and the position of the second maximum value in the frequency domain data, and the frequency, amplitude and phase of the fundamental frequency are calculated. The frequency, amplitude and phase of each harmonic are calculated from the fundamental frequency.

[0016] Furthermore, the correction and compensation process includes bias correction, gain correction, and temperature compensation.

[0017] Furthermore, temperature compensation specifically involves using the temperature data provided by the temperature sensor of the metering chip, inputting the temperature data into a univariate quadratic compensation equation with set coefficient scaling parameters to calculate the total gain caused by the temperature deviation of each device at the current temperature, and then adding the total gain to the uncompensated data to obtain the temperature-compensated data.

[0018] Furthermore, the windowing process is performed using Lef-Vincent window interpolation.

[0019] Furthermore, the input discrete digital signal data is discrete digital signal data that has undergone downsampling and filtering processing.

[0020] To address the aforementioned technical problems, the present invention also provides a harmonic analysis device for an internal metering chip. The device includes a memory and a processor, as well as computer program instructions stored in the memory and running on the processor. The processor is used to execute the computer program instructions stored in the memory to implement the harmonic analysis method for the internal metering chip.

[0021] The beneficial effects of the above technical solution are as follows: This invention is an improved invention. By performing power frequency synchronization processing on the input discrete digital signal data, the relative deviation value of the fundamental frequency and the standard frequency is calculated. Based on the power frequency synchronization output skip flag of the previous data, the frequency deviation value of the current data is processed. The accuracy of the power frequency synchronization output data is determined based on the relationship between the processed frequency deviation value and 0.5 and -0.5. The deviation value is then processed, and the processing result is input into a polynomial with multiple filtering results of the current and previous data as coefficients for calculation to obtain the power frequency synchronization output data. This solves the problem of increased computational load caused by the inability to perform synchronous sampling due to fluctuations in the power grid frequency. Attached Figure Description

[0022] Figure 1 This is a flowchart of an embodiment of the metering chip internal harmonic analysis method of the present invention;

[0023] Figure 2 This is a flowchart of harmonic analysis based on Rife-Vincent window interpolation FFT, representing an embodiment of the internal harmonic analysis method for metering chips of the present invention.

[0024] Figure 3 This is a flowchart of a harmonic analysis method based on power frequency synchronous sampling, which is an embodiment of the internal harmonic analysis method of the metering chip of the present invention. Detailed Implementation

[0025] The focus of this invention is to provide a method for harmonic analysis inside a metering chip, characterized by the following steps:

[0026] 1) If the power frequency synchronization method is used to perform harmonic analysis on the input discrete digital signal data, multiple filters with different filter coefficients are used to filter the input data to obtain multiple current data filtering results; the fundamental frequency is extracted, the relative deviation value of the fundamental frequency relative to the standard frequency is calculated, and the frequency deviation value of the current data is processed accordingly based on the power frequency synchronization skip flag of the previous data.

[0027] If the processed frequency deviation is greater than 0.5, then calculate the first deviation and the second deviation. The first deviation is the processed frequency deviation minus 1, and the second deviation is the first deviation plus the relative deviation. Substitute the first deviation into a polynomial with multiple filtering results of the previous data as coefficients for calculation, and the result is used as the power frequency synchronization output data. Substitute the second deviation into a polynomial with multiple filtering results of the current data as coefficients for calculation, and the result is used as the power frequency synchronization output data.

[0028] If the processed frequency deviation value is greater than or equal to -0.5 and less than or equal to 0.5, the second deviation value is the processed frequency deviation value; the second deviation value is substituted into the polynomial with the current data filtering result as the coefficient for calculation, and the calculation result is used as the power frequency synchronization output data;

[0029] While outputting the power frequency synchronous output data, update the power frequency synchronous output skip flag of the previous data, and use the filtering result of the current data as the filtering result of the previous data; if the current data is the first input data, the filtering result of the previous data is set to 0; reprocess the frequency deviation value of the current data according to the power frequency synchronous output skip flag of the previous data for iterative calculation; when the power frequency synchronous output data is a whole cycle length, output the data.

[0030] 2) Perform FFT calculation on the output data, and perform harmonic analysis based on the FFT calculation results.

[0031] This invention performs power frequency synchronization processing on the data, calculates the relative deviation value of the fundamental frequency and the standard frequency, processes the frequency deviation value of the current data based on the power frequency synchronization output skip flag of the previous data, judges the relationship between the processed frequency deviation value and 0.5 and -0.5 and processes the deviation value, and then inputs the processing result into a polynomial with multiple filtering results of the current and previous data as coefficients for calculation to obtain the power frequency synchronization output data. This solves the problem of increased computational load caused by the inability to perform synchronous sampling due to power grid frequency fluctuations.

[0032] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0033] Example of a method for analyzing internal harmonics in a metering chip:

[0034] This embodiment of the method for harmonic analysis within a metering chip includes two methods: one is a harmonic analysis method based on Rife-Vincent window interpolation FFT, and the other is a harmonic analysis method based on power frequency synchronous sampling. Specifically, as follows... Figure 1 As shown.

[0035] First, the data is preprocessed, and the specific steps are as follows:

[0036] (1) Suppose that the discrete digital signal s after the ADC analog-to-digital conversion of the three-phase three-wire voltage and current is... in The input data is sampled and filtered to output full-wave sampled and filtered data of three-phase three-wire voltage and current with a sampling rate of 6.4KHz. These data are: A-phase full-wave voltage signal sampled and filtered data All_Ua_Decim, A-phase full-wave current signal sampled and filtered data All_Ia_Decim, B-phase full-wave voltage signal sampled and filtered data All_Ub_Decim, full-wave current signal sampled and filtered data All_Ib_Decim, B-phase full-wave current signal sampled and filtered data All_Ia_Decim, C-phase full-wave voltage signal sampled and filtered data All_Uc_Decim, C-phase full-wave current signal sampled and filtered data All_Ic_Decim, and N-phase full-wave current signal sampled and filtered data All_In_Decim.

[0037] (2) The A-phase full-wave voltage signal downsampled and filtered data All_Ua_Decim is processed to remove DC, and the output A-phase full-wave voltage signal removed DC data All_Ua_Dcrm is generated.

[0038] (3) The full-wave voltage signal of phase A to DC data All_Ua_Dcrm is biased and gained to output full-wave voltage signal correction data All_Ua_Calibra.

[0039] (4) The full-wave voltage signal correction data All_Ua_Calibra is then processed by automatic temperature compensation. The specific implementation method is as follows: the temperature data provided by the chip's temperature sensor module is compared with the coefficients of the user-fitted quadratic compensation equation. Configurable coefficient scaling parameters are set. The coefficient scaling parameters are determined based on the fixed bit width of the decimal part of the coefficients. The total gain caused by the temperature deviation of each device at the current temperature is automatically calculated. Then, the full-wave voltage signal correction data All_Ua_Calibra is added to this total gain for temperature compensation, and the A-phase full-wave voltage signal correction compensation output data All_Ua_Comp is output.

[0040] (5) Replace All_Ua_Decim with All_Ub_Decim and repeat steps 2 to 4 to obtain the B-phase full-wave voltage signal correction and compensation output data All_Ub_Comp.

[0041] (6) Replace All_Ua_Decim with All_Uc_Decim and repeat steps 2 to 4 to obtain the C-phase full-wave voltage signal correction and compensation output data All_Uc_Comp.

[0042] (7) Replace All_Ua_Decim with All_Ia_Decim and repeat steps 2 to 4 to obtain the A-phase full-wave current signal correction and compensation output data All_Ia_Comp.

[0043] (8) Replace All_Ua_Decim with All_Ib_Decim and repeat steps 2 to 4 to obtain the B-phase full-wave current signal correction and compensation output data All_Ib_Comp.

[0044] (9) Replace All_Ua_Decim with All_Ic_Decim and repeat steps 2 to 4 to obtain the C-phase full-wave current signal correction and compensation output data All_Ic_Comp.

[0045] When only harmonic amplitude, frequency, and phase analysis are required, the harmonic analysis method based on Rife-Vincent window interpolation FFT is selected, as follows: Figure 2 As shown.

[0046] (10) By using the correction and compensation output data as the input data for harmonic analysis, we can obtain the input data Har_Ua_In for phase A voltage harmonic analysis, Har_Ub_In for phase B voltage harmonic analysis, Har_Uc_In for phase C voltage harmonic analysis, Har_Ia_In for phase A current harmonic analysis, Har_Ib_In for phase B current harmonic analysis, and Har_Ic_In for phase C current harmonic analysis.

[0047] (11) The input data Har_Ua_In for phase A voltage harmonic analysis is first windowed using the Lef-Vincent window interpolation and then cached in RAM.

[0048] (12) When the accumulated cache reaches 1024 data, the data is read from RAM and output to FFT for calculation. 512 frequency domain data are output to RAM for caching.

[0049] (13) First, find the interval where the fundamental wave is located, that is, find the maximum value and the position of the maximum value in the 6th to 10th frequency domain data, then compare the size of the two values ​​to the left and right of the maximum value, select the second maximum value, and save the position of the second maximum value.

[0050] (14) Based on the found maximum value and the location of the maximum value, the second maximum value and the location of the second maximum value, the frequency, amplitude and phase of the fundamental wave are calculated.

[0051] (15) Based on the frequency Fund_Freq of the fundamental wave, calculate the approximate interval Har_Freq_Site of the second harmonic. Then, find the maximum value and the position of the maximum value in the frequency domain data of the interval Har_Freq_Site-1 to Har_Freq_Site+1. Then compare the two values ​​to the left and right of the maximum value, select the second maximum value, and save the position of the second maximum value.

[0052] (16) Based on the found maximum value and the location of the maximum value, the second maximum value and the location of the second maximum value, the frequency, amplitude and phase of the second harmonic are calculated.

[0053] (17) Repeat steps 15 to 16 to calculate the frequency, amplitude and phase of the 3rd to 63rd harmonics of phase A voltage.

[0054] (18) Replace Har_Ua_In with Har_Ub_In, repeat steps 11 to 17, and calculate the frequency, amplitude, and phase of the 1st to 63rd harmonics of phase B voltage.

[0055] (19) Replace Har_Ua_In with Har_Uc_In, repeat steps 11 to 17, and calculate the frequency, amplitude, and phase of the 1st to 63rd harmonics of the C-phase voltage.

[0056] (20) Replace Har_Ua_In with Har_Ia_In, repeat steps 11 to 17, and calculate the frequency, amplitude and phase of the 1st to 63rd harmonics of the A-phase current.

[0057] (21) Replace Har_Ua_In with Har_Ib_In, repeat steps 11 to 17, and calculate the frequency, amplitude, and phase of the 1st to 63rd harmonics of the B-phase current.

[0058] (22) Replace Har_Ua_In with Har_Ic_In, repeat steps 11 to 17, and calculate the frequency, amplitude and phase of the 1st to 63rd harmonics of the C-phase current.

[0059] (23) After calculating the frequency, amplitude and phase of the 1st to 63rd harmonics of the A / B / C voltage and A / B / C current, a completion interrupt is issued to notify the software that it can read the frequency, amplitude and phase of the 1st to 63rd harmonics for the next step of analysis.

[0060] (24) Repeat steps 11 to 23 to continuously update the latest harmonic analysis results.

[0061] When the output data requires harmonic amplitude, frequency, phase, three-phase imbalance, and topology identification analysis, a harmonic analysis method based on power frequency synchronous sampling is selected, specifically as follows: Figure 3 As shown.

[0062] (25) Perform power frequency synchronization processing on the full-wave downsampled filtered data; the specific method of power frequency synchronization processing is to design a fourth-order multiphase polynomial interpolation filter to perform FIR filtering on the full-wave downsampled filtered data. A 38th-order FIR filter is used, with a total of 5 sets of FIR filter coefficients, which can obtain 5 filter results. The 5 filter results are used as the coefficients of the polynomial. At the same time, the deviation between the signal frequency and the standard frequency is substituted into the polynomial to obtain the synchronously sampled data.

[0063] The specific filtering process is as follows:

[0064] The sampling frequency of the signal is Fs. After interpolation by 32 times, the sampling frequency is 32*Fs. Based on the sampling frequency of 32*Fs, a prototype filter is designed, resulting in a total of 32*38 coefficients.

[0065] The 32*38 coefficients are grouped according to the polyphase interpolation filter format. Coefficients 1-32 form the first filter group (fir_filter1), coefficients 33-64 form the second filter group (fir_filter2), and so on, resulting in 38 groups of filter coefficients. Each column represents a group of filter coefficients, leading to the following polynomial matrix equation:

[0066]

[0067] Then, curve fitting is performed on each group of coefficients. The fitted polynomial equations are of order 5, resulting in 38 groups of order 5 polynomial matrix equations as follows:

[0068]

[0069] The calculation process for power frequency synchronization output is as follows:

[0070]

[0071] In the formula, sync_out(n) is the power frequency synchronous output, n is the nth sampling output point, k is the filter order, and b m,k Let b′ be the matrix equation consisting of the filter coefficients. m,k Let d(n) be the matrix equation after fitting the filter coefficients, where d(n) represents the nth power frequency synchronous input data and Δf represents the frequency deviation value.

[0072] We can filter the input data sequentially by treating each row of the polynomial matrix equation as a set of filters. For each input data, we can obtain 5 filtering results: c1(n), c2(n), ..., c5(n). Then, by substituting the obtained frequency deviation values ​​into the calculation formula, we can obtain the output data of power frequency synchronization.

[0073] (26) First, use 5 sets of FIR filter coefficients to perform FIR filtering on the current input data of the A-phase voltage signal All_Ua_Decim, and obtain 5 filtering results of the current data from cur_filter_out0 to cur_filter_out4.

[0074] (27) Calculate the fundamental frequency of the data based on the phase A voltage signal. The fundamental frequency can be obtained by using algorithms such as zero crossing. Calculate the relative deviation value delta of the fundamental frequency relative to the standard frequency.

[0075] (28) If the current data is the first input data, the filtering result of the previous data is set to 0; determine whether the power frequency synchronization output skip flag of the previous data is 1. If yes, assign the frequency deviation value pre_offset of the previous data to the frequency deviation value cur_offset of the current data; otherwise, add the relative deviation value delta to the frequency deviation value pre_offset of the previous data and assign it to the frequency deviation value cur_offset of the current data. A positive frequency deviation value indicates that the sampling point position based on the standard frequency is lagging behind the sampling point position based on the fundamental frequency; a negative frequency deviation value indicates that the sampling point position based on the standard frequency is ahead of the sampling point position based on the fundamental frequency. A flag of 0 indicates that the previous data underwent power frequency synchronization processing.

[0076] (29) If the absolute value of the frequency deviation is greater than 0.5, the accuracy of the calculation result is relatively poor. Therefore, we need to convert the absolute value of the frequency deviation to less than 0.5 before performing the calculation to obtain the power frequency synchronization output data. If the processed frequency deviation is less than -0.5, the accuracy of the data output by using the current data for power frequency synchronization processing is poor, and there is currently no power frequency synchronization output data.

[0077] The frequency deviation value cur_offset of the current data is determined. If cur_offset is less than -0.5, the current data's frequency deviation value cur_offset is incremented by 1 and assigned to the previous data's frequency deviation value pre_offset. The previous data's power frequency synchronization output skip flag is set to 1, and then the process jumps to step 34. Otherwise, the process jumps to step 30. A flag of 1 indicates that the previous data did not undergo power frequency synchronization processing. When the previous data did not undergo power frequency synchronization processing, it means that the data output using the previous data for synchronization has relatively poor accuracy. Power frequency synchronization processing needs to be performed on the next data. The data output using the next data (i.e., the current data) for power frequency synchronization processing has higher accuracy, so the frequency deviation value of the previous data needs to be assigned to the current data's frequency deviation value.

[0078] (30) If the frequency deviation value cur_offset of the current data is greater than 0.5, then the frequency deviation value cur_offset of the current data is reduced by 1 and assigned to the deviation offset1. The relative deviation value delta is added to the deviation offset1 and assigned to the deviation offset2. If the frequency deviation value of the current data is greater than 0.5, it means that the frequency deviation value of the current data is obtained by adding 1 to the deviation value of the previous data. To calculate the power frequency synchronization output data of the previous data, the frequency deviation of the current data needs to be reduced by 1. At the same time, the 5 filtering results of the previous data are used as the coefficients of the polynomial to calculate the power frequency synchronization result of the previous data. Jump to step 32.

[0079] (31) If the frequency deviation value cur_offset of the previous data is greater than -0.5 but less than 0.5, then the frequency deviation value cur_offset of the previous data is assigned to the deviation offset2; the frequency deviation value of the current data is between -0.5 and 0.5, which means that the accuracy of using the current data to calculate the power frequency synchronous output data is relatively high, so the five filtering results of the current data are used as the coefficients of the polynomial; skip to step 33.

[0080] (32) Take the five filtering results of the previous data, pre_filter_out0~pre_filter_out4, as the coefficients of the polynomial, substitute the deviation offset1 into the polynomial, calculate the result as the power frequency synchronous output data, and cache the data.

[0081] (33) The five filtering results of the current data, cur_filter_out0 to cur_filter_out4, are used as coefficients of a polynomial. The deviation offset2 is substituted into the polynomial, and the calculation result is used as the power frequency synchronization output data. The data is then cached. Meanwhile, since the output data of the power frequency synchronization processing using the current data has high precision, the power frequency synchronization output data calculated in step 32 is used as the power frequency synchronization data of the previous data, and the power frequency synchronization output skip flag of the previous data is set to 0.

[0082] (34) Update the five filtering results pre_filter_out0~pre_filter_out4 of the previous data, assign the five filtering results cur_filter_out0~cur_filter_out4 of the current data to the five filtering results pre_filter_out0~pre_filter_out4 of the previous data, and jump to step 26.

[0083] (35) Replace All_Ua_Decim with All_Ub_Decim, repeat steps 26 to 34, perform power frequency synchronization processing on the B phase voltage signal to obtain the power frequency synchronization output data of the B phase voltage signal, and cache the data.

[0084] (36) Replace All_Ua_Decim with All_Uc_Decim, repeat steps 26 to 34, perform power frequency synchronization processing on the C-phase voltage signal, obtain the power frequency synchronization output data of the C-phase voltage signal, and cache the data.

[0085] (37) Replace All_Ua_Decim with All_Ia_Decim, repeat steps 26 to 34, perform power frequency synchronization processing on the A-phase current signal, obtain the power frequency synchronization output data of the A-phase current signal, and cache the data.

[0086] (38) Replace All_Ua_Decim with All_Ib_Decim, repeat steps 26 to 34, perform power frequency synchronization processing on the B-phase current signal, obtain the power frequency synchronization output data of the B-phase current signal, and cache the data.

[0087] (39) Replace All_Ua_Decim with All_Ic_Decim, repeat steps 26 to 34, perform power frequency synchronization processing on the C-phase current signal, obtain the power frequency synchronization output data of the C-phase current signal, and cache the data.

[0088] (40) After buffering the power frequency synchronous output data for one full cycle, perform FFT calculations on the power frequency synchronous output data of phase A voltage, phase B voltage, phase C voltage, phase A current, phase B current, and phase C current signals in sequence.

[0089] (41) After the calculation is completed, the software can read the FFT calculation results for further harmonic analysis.

[0090] (42) The software can also read the power frequency synchronous output data of three-phase three-wire voltage and current, and perform more performance index analysis, such as three-phase unbalance and topology identification.

[0091] (43) Depending on the actual needs, if only the amplitude, frequency and phase of the harmonics need to be analyzed, then Method 1 can be selected. Compared with Method 2, Method 1 is faster to calculate and easier to use. The software only needs to wait for the harmonic analysis to complete the interruption before it can read the amplitude, frequency and phase of the harmonics. The software does not need to participate in the calculation. If the user also needs to analyze other performance indicators, such as three-phase imbalance, topology identification, etc., then Method 2 can be selected. Compared with Method 1, Method 2 is more flexible. The user can analyze more performance indicators by reading the power frequency synchronization data.

[0092] Example of a harmonic analysis device inside a metering chip:

[0093] This invention also provides a harmonic analysis device for an internal metering chip. The device includes a memory and a processor, as well as a computer program stored in the memory and running on the processor. The processor executes the computer program instructions stored in the memory to implement the internal harmonic analysis method for the metering chip. The specific details of the internal harmonic analysis method for the metering chip have been described in detail in the embodiments of the internal harmonic analysis method for the metering chip, and will not be repeated here. The processor can be a microprocessor (MCU), a programmable logic device (FPGA), or other processing devices, and the memory can be a portable hard drive, a read-only memory (ROM), a random access memory (RAM), or other storage devices.

[0094] Specific implementation methods have been given above, but the present invention is not limited to the described implementation methods. The basic idea of ​​the present invention lies in the above basic scheme. For those skilled in the art, designing various modified models, formulas, and parameters based on the teachings of the present invention does not require creative effort. Changes, modifications, substitutions, and variations made to the implementation methods without departing from the principles and spirit of the present invention still fall within the protection scope of the present invention.

Claims

1. A method for analyzing internal harmonics of a metering chip, characterized in that, Includes the following steps: 1) Harmonic analysis of the input discrete digital signal data is performed using the following power frequency synchronization method: The input data is filtered using multiple filters with different filter coefficients to obtain multiple current data filtering results; the fundamental frequency is extracted, the relative deviation of the fundamental frequency from the standard frequency is calculated, and the frequency deviation of the current data is processed accordingly based on the skip flag of the previous data's power frequency synchronization output. If the processed frequency deviation is greater than 0.5, then calculate the first deviation and the second deviation. The first deviation is the processed frequency deviation minus 1, and the second deviation is the first deviation plus the relative deviation. The first deviation value is substituted into a polynomial with multiple filtering results of the previous data as coefficients for calculation, and the calculation result is used as the power frequency synchronization output data. The second deviation value is substituted into a polynomial with multiple filtering results of the current data as coefficients for calculation, and the calculation result is used as the power frequency synchronization output data. If the processed frequency deviation value is greater than or equal to -0.5 and less than or equal to 0.5, the second deviation value is the processed frequency deviation value; the second deviation value is substituted into the polynomial with the current data filtering result as the coefficient for calculation, and the calculation result is used as the power frequency synchronization output data; If the processed frequency deviation value is less than -0.5, then the processed frequency deviation value is incremented by 1 as the frequency deviation value of the previous data, the power frequency synchronization output skip flag of the previous data is updated, the filtering result of the current data is used as the filtering result of the previous data, and the frequency deviation value of the current data is reprocessed according to the power frequency synchronization output skip flag of the previous data for iterative calculation. While outputting the power frequency synchronous output data, update the power frequency synchronous output skip flag of the previous data, use the filtering result of the current data as the filtering result of the previous data, and if the current data is the first input data, set the filtering result of the previous data to 0; reprocess the frequency deviation value of the current data according to the power frequency synchronous output skip flag of the previous data for iterative calculation; when the power frequency synchronous output data is a whole cycle length, output the data. 2) Perform FFT calculation on the output data, and perform harmonic analysis based on the FFT calculation results.

2. The method for analyzing internal harmonics of a metering chip according to claim 1, characterized in that, If the processed frequency deviation value is less than -0.5, update the power frequency synchronization output skip flag of the previous data to 1; otherwise, update the power frequency synchronization output skip flag of the previous data to 0. The specific method for processing the frequency deviation value of the current data according to the power frequency synchronization output skip flag of the previous data is as follows: when the power frequency synchronization output skip flag of the previous data is 1, the frequency deviation value of the previous data is used as the frequency deviation value of the current data; when the power frequency synchronization output skip flag of the previous data is 0, the sum of the frequency deviation value of the previous data and the relative deviation value is used as the frequency deviation value of the current data.

3. The method for analyzing internal harmonics of a metering chip according to claim 1, characterized in that, The filter mentioned in step 1) is an FIR filter.

4. The method for analyzing internal harmonics of a metering chip according to claim 3, characterized in that, The multiple sets of different filter coefficients are 5 sets of different filter coefficients.

5. A harmonic analysis device for an internal metering chip, characterized in that, The device includes a memory and a processor, as well as computer program instructions stored in the memory and running on the processor, the processor being used to execute the computer program instructions stored in the memory to implement the internal harmonic analysis method of the metering chip as described in any one of claims 1 to 4.

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