Method and system for testing reliability of connection for pins
By combining the methods of conductivity testing and data transmission testing, the connection reliability of the pins is comprehensively measured, and the problem of relying solely on conductivity testing in the prior art has been solved, achieving a more accurate and reliable detection effect.
Patent Information
- Application Number
- CN202411786802.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-06
- Publication Date
- 2025-03-07
AI Technical Summary
When determining the reliability of pin connections, the prior art only relies on conductivity testing, and lacks a comprehensive measurement of multiple testing methods, resulting in low detection accuracy.
By combining conductivity testing and data transmission testing, the reference chip and the chip to be tested are selected, and the excellent values of conductivity and data transmission are obtained, based on these values, the performance judgment values of the reference chip pins are obtained, and the connection reliability of the chip pins to be tested is determined.
It realizes a comprehensive measurement and accurate judgment of pin connection reliability, and improves the accuracy and reliability of detection.
Smart Images
Figure CN119575135A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of pin testing, and in particular relates to a method and a system for testing the connection reliability of a pin. Background Art
[0002] Pins refer to the wiring that leads from the internal circuit of the integrated circuit to the peripheral circuit. These pins constitute the interface of the chip and are used to realize functions such as signal input, output, and control. The pins are connected to the pads on the printed circuit board through soldering to form solder joints to realize the connection between the chip and the external circuit. At present, with the increasing number of chip functions and applications, the number of chip pins is also increasing. Testing the reliability of chip pin connections is very important for chip applications.
[0003] However, in the prior art, whether the pin connection is reliable is usually determined by conductivity. Although the connection reliability of the pin can be determined to a certain extent, it does not combine multiple test methods to comprehensively measure the connection reliability of the pin, making its detection accuracy relatively low; To this end, the present invention provides a method and system for testing the connection reliability of pins. Summary of the invention
[0004] The purpose of the present invention is to provide a method and system for testing the reliability of pin connections to solve the problems raised in the above background technology.
[0005] In order to achieve the above object, the present invention adopts the following technical solutions: A method for testing the reliability of connection of a pin, the specific testing method is as follows: Step S1, selecting a reference chip and a chip to be tested and placing them in a pin conductivity test unit, testing the conductivity of the pins, and obtaining an excellent conductivity value of the pins of the chip to be tested; Step S2, placing the chip to be tested and the reference chip in a signal transmission test unit, performing a data transmission test on the pins, and obtaining an excellent data transmission value of the pins of the chip to be tested; Step S3, obtaining a performance determination value of a reference chip pin based on the excellent conductivity value and the excellent data transmission value; Step S4, determining the connection reliability of the pins of the chip to be tested according to the performance determination value.
[0006] Furthermore, the step S1 includes the following sub-steps: Step S101, the switch K1 and the switch K2 are in a closed state, and the output voltage is gradually increased over time; Step S102, at the same time, the sampling circuit collects a first reference current value of a reference chip pin and collects a first test current value of a chip pin to be tested; Step S103, comparing and analyzing the first reference current value and the first test current value, and the first reference voltage value and the first test voltage value; Step S104, if the absolute value of the current difference between the first reference current value and the first test current value is less than the current threshold, and the absolute value of the voltage difference between the first reference voltage value and the first test voltage value is less than the voltage threshold, then proceed to the next step; If the absolute value of the current difference between the first reference current value and the first test current value is greater than or equal to the current threshold or the absolute value of the voltage difference between the first reference voltage value and the first test voltage value is greater than or equal to the voltage threshold, it is considered that the conductivity of the chip pin under test is abnormal.
[0007] Furthermore, the step S1 includes the following sub-steps: Step S105, when the switch K1 is closed and the switch K2 is open, the output voltage is also gradually increased over time, and the sampling circuit collects the second reference voltage value and the second reference current value of the reference chip pin; Step S106, when the switch K1 is opened and the switch K2 is closed, the voltage output by the control power supply gradually increases with time, and the sampling circuit collects the second test voltage value and the second test current value of the pin of the chip to be tested; Step S107, generating a voltage-current relationship curve diagram according to the second reference voltage value and the second reference current value of the reference chip pin and the second test voltage value and the second test current value of the chip pin to be tested; Step S108, the resistivity ρ1 of the reference chip pin and the resistivity ρ2 of the chip pin to be tested are calculated by a formula, and the calculation formula is as follows: ρ1=(U / I)*(A / L), where U is the second reference voltage value, I is the second reference current value, A is the cross-sectional area of the reference chip pin, and L is the length of the reference chip pin. Similarly, the resistivity ρ2 of the chip pin to be tested can be obtained; The conductivity DDP1 of the reference chip pin and the conductivity DDP2 of the chip pin to be tested are calculated by the formula. The calculation formula is as follows: DDP1=1 / ρ1, and similarly, the conductivity DDP2 of the chip pin to be tested can be obtained; Step S109, if the absolute value of the conductivity difference between the reference chip pin and the chip pin to be tested is greater than the conductivity threshold, the excellent conductivity value of the chip pin to be tested is a second excellent conductivity value; If the absolute value of the conductivity difference between the reference chip pin and the chip pin to be tested is less than or equal to the conductivity threshold, the excellent conductivity value of the chip pin to be tested is the first excellent conductivity value; wherein the first excellent conductivity value is greater than the second excellent conductivity value.
[0008] Furthermore, the first reference voltage value and the first reference current value are the voltage value and the current value of the reference chip pin when the switch K1 and the switch K2 are both in the closed state; The second reference voltage value and the second reference current value are the voltage value and the current value of the reference chip pin when the switch K1 is closed and the switch K2 is open; The first test voltage value and the first test current value are the voltage value and current value of the pin of the chip to be tested when the switch K1 and the switch K2 are both closed; The second test voltage value and the second test current value are the voltage value and the current value of the pin of the chip to be tested when the switch K1 is opened and the switch K2 is closed.
[0009] Furthermore, the step S2 includes the following sub-steps: Step S201, the signal generator generates a pseudo-random binary sequence, records the total number of binary digits of the pseudo-random binary sequence, and sends the pseudo-random binary sequence to the signal transmission test unit; Step S202, the signal transmission test unit writes a pseudo-random binary sequence into the chip to be tested and the reference chip respectively; Step S203, the data receiver receives the reference transmission data transmitted via the reference chip pin and the transmission data to be tested transmitted via the pin of the chip to be tested; Step S204, comparing the reference transmission data and the transmission data to be tested with the pseudo-random binary sequence bit by bit, and recording the binary reference bit error number in the reference transmission data and the binary test bit error number in the transmission data to be tested; Step S205, the bit error rate generated by the pseudo-random binary sequence transmitted through the reference chip and the chip to be tested is calculated by a formula, and the calculation formula is as follows: The bit error rate of the reference transmission data = the number of binary reference bit errors / the total number of binary digits of the pseudo-random binary sequence * 100%. The bit error rate of the test data can be calculated in the same way; Step S206, if the bit error rate of the transmission data to be tested is greater than the bit error rate of the reference transmission data, it is considered that the data transmission of the chip pin to be tested is unreliable, and an excellent data transmission value of the chip pin to be tested is generated as a second excellent data transmission value; If the bit error rate of the transmission data to be tested is less than or equal to the bit error rate of the reference transmission data, the data transmission of the chip pin to be tested is considered to be stable and reliable, and an excellent data transmission value of the chip pin to be tested is generated as a first excellent data transmission value; wherein the first excellent data transmission value is greater than the second excellent data transmission value.
[0010] Furthermore, the step S202 includes the following sub-steps: Step T1, the seventh pins of the chip under test and the reference chip are grounded respectively, and then a pseudo-random binary sequence is obtained, and the pseudo-random binary sequence is written into each address of the entire memory space of the chip under test and the reference chip respectively; Step T2, the 7th pins of the chip under test and the reference chip are connected to the positive power supply respectively, data is read from each address in the memory space corresponding to the chip under test to obtain the transmission data under test, and data is read from each address in the memory space corresponding to the reference chip to obtain the reference transmission data.
[0011] Furthermore, the step S3 includes the following sub-steps: Step S31, obtaining the conductivity excellence value GD and the data transmission excellence value GC of the reference chip pin; Step S32, the connection reliability value GK of the reference chip pin is calculated by a formula, and the formula is as follows: GK=GD*α+GC*λ; Step S33, repeatedly executing the above steps S1 to S3 for multiple times, to obtain the connection reliability value of the reference chip pin during multiple tests; Step S34, traverse and compare to obtain the minimum value among the connection reliability values, and use the minimum value of the connection reliability values as the performance judgment value of the reference chip pin.
[0012] Furthermore, α is a conductivity weight determined by the conductivity of the chip pin. If the conductivity of the chip pin is less than or equal to X1, the value of α is α1. If the conductivity of the chip pin is greater than X1 and less than X2, the value of α is α2. If the conductivity of the chip pin is greater than or equal to X2, the value of α is α3, wherein X1 and X2 are standard pin conductivity, X1<X2, 0<α1<α2<α3; λ is the transmission weight determined by the bit error rate of the chip pin. If the bit error rate of the chip pin is less than or equal to Y1, the value of λ is λ1. If the bit error rate of the chip pin is greater than Y1 and less than Y2, the value of λ is λ2. If the bit error rate of the chip pin is less than or equal to Y2, the value of λ is λ3. Y1 and Y2 are standard pin bit error rates, Y1<Y2, 0<λ3<λ2<λ1.
[0013] Furthermore, the step S4 includes the following sub-steps: Step S41, according to step S34, obtaining the minimum value of the connection reliability values corresponding to the reference chip pins, and taking the minimum value of the connection reliability values corresponding to the reference chip pins as the performance determination threshold; Step S42, if the performance judgment value of the chip pin under test is greater than or equal to the performance judgment threshold of the reference chip pin, it is determined that the connection of the chip pin under test is reliable; Step S43: If the performance judgment value of the pin of the chip to be tested is less than the performance judgment threshold of the pin of the reference chip, it is determined that the connection of the pin of the chip to be tested is unreliable.
[0014] The present invention also provides a pin connection reliability testing system, comprising: The conductive test module is used to select a reference chip and a chip to be tested and place them in a pin conductivity test unit to test the conductivity of the pins and obtain the excellent conductivity value of the pins of the chip to be tested; The transmission test module is used to place the chip under test and the reference chip in the signal transmission test unit, perform data transmission test on the pins, and obtain the data transmission excellent value of the pins of the chip under test; A calculation module, which obtains the performance judgment value of the reference chip pin based on the excellent conductivity value and the excellent data transmission value analysis; The determination module is used to determine the connection reliability of the chip pins to be tested according to the performance determination value.
[0015] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: The present invention first selects a reference chip and a chip to be tested and places them in a pin conductivity test unit, tests the conductivity of the pins, and obtains the excellent conductivity value of the pins of the chip to be tested. Then, the chip to be tested and the reference chip are placed in a signal transmission test unit, and a data transmission test is performed on the pins to obtain the excellent data transmission value of the pins of the chip to be tested. Therefore, the performance judgment value of the reference chip pin can be obtained based on the excellent conductivity value and the excellent data transmission value analysis, and finally the connection reliability of the pins of the chip to be tested is judged according to the performance judgment value. The present invention realizes comprehensive measurement and accurate judgment of the connection reliability of the pins based on the conductivity test and the transmission test. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to facilitate understanding by those skilled in the art, the present invention is further described below with reference to the accompanying drawings.
[0017] Figure 1 is a flow chart of the method of the present invention; Figure 2 This is a flow chart of the conductive test of the chip pins in the present invention; Figure 3 A line graph showing voltage changes of the power supply output in the present invention; Figure 4 A curve diagram showing the relationship between voltage and current of the chip pins in the present invention; Figure 5 It is a transmission test flow chart of the chip pins in the present invention; Figure 6 It is a chip pin structure diagram of the present invention; Figure 7 It is the overall system block diagram of the present invention. DETAILED DESCRIPTION
[0018] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0019] Example 1: Please refer to Figure 1-Figure 6 As shown, the technical solution provided by the present invention is: a method for testing the reliability of connection of pins. In this embodiment, a normal reference chip with the same model as the chip to be tested is selected as a test reference, and the reference chip pins are tested under the same test conditions as the test pins of the chip to be tested. The test method includes the following specific steps: Step S1, selecting a reference chip and a chip to be tested and placing them in a pin conductivity test unit, testing the conductivity of the pins, and obtaining an excellent conductivity value of the pins of the chip to be tested; like Figure 2 As shown, the power supply provides a variable voltage to the pin conductivity test unit, and the voltage gradually increases with time; the pin conductivity test unit is used to test the conductivity of the reference chip pin, the switch K1 is connected to the reference chip, the switch K2 is connected to the chip to be tested, the switch K1 and the switch K2 are controlled to close the circuits of the corresponding reference chip and the chip to be tested, and the sampling circuit is used to sample and collect the first reference voltage value and the first reference current value corresponding to the reference chip pin, and collect the first test voltage value and the first test current value corresponding to the chip pin to be tested; the switch K1 is controlled to close the circuit of the corresponding reference chip and the switch K2 is controlled to disconnect the circuit of the corresponding chip to be tested, and the sampling circuit is used to sample and collect the second reference voltage value and the second reference current value corresponding to the reference chip pin; the switch K1 is controlled to disconnect the circuit of the corresponding reference chip and the switch K2 is controlled to close the circuit of the corresponding chip to be tested, and the sampling circuit is used to sample and collect the second test voltage value and the second test current value corresponding to the chip pin to be tested; the data analysis module combines the reference voltage value, the reference current value, the test voltage value and the test current value to analyze and obtain the excellent conductivity value of the chip pin to be tested; It should be specifically explained that the first reference voltage value and the first reference current value are the voltage value and the current value of the reference chip pin when the switch K1 and the switch K2 are both closed, and the second reference voltage value and the second reference current value are the voltage value and the current value of the reference chip pin when the switch K1 is closed and the switch K2 is open; the first test voltage value and the first test current value are the voltage value and the current value of the chip pin to be tested when the switch K1 and the switch K2 are both closed, and the second test voltage value and the second test current value are the voltage value and the current value of the chip pin to be tested when the switch K1 is open and the switch K2 is closed; In this embodiment, step S1 includes the following sub-steps: Step S101, the switch K1 and the switch K2 are in a closed state, and the output voltage is gradually increased over time; Step S102, at the same time, the sampling circuit collects a first reference current value of a reference chip pin and collects a first test current value of a chip pin to be tested; It should be specifically noted that when the reference chip pin and the chip pin under test are subjected to different voltage changes, the corresponding current will also change accordingly; Step S103, comparing and analyzing the first reference current value and the first test current value, and the first reference voltage value and the first test voltage value; Step S104, if the absolute value of the current difference between the first reference current value and the first test current value is less than the current threshold, and the absolute value of the voltage difference between the first reference voltage value and the first test voltage value is less than the voltage threshold, then proceed to the next step; If the absolute value of the current difference between the first reference current value and the first test current value is greater than or equal to the current threshold or the absolute value of the voltage difference between the first reference voltage value and the first test voltage value is greater than or equal to the voltage threshold, it is considered that the conductivity of the chip pin to be tested is abnormal; Step S105, when the switch K1 is closed and the switch K2 is open, the output voltage is also gradually increased over time, and the sampling circuit collects the second reference voltage value and the second reference current value of the reference chip pin; Step S106, when the switch K1 is opened and the switch K2 is closed, the voltage output by the control power supply gradually increases with time, and the sampling circuit collects the second test voltage value and the second test current value of the pin of the chip to be tested; It should be specifically noted that when the switch K1 is closed and the switch K2 is open, and when the switch K1 is open and the switch K2 is closed, the voltage change of the power supply output is the same. Figure 3 The figure shows the variation of the voltage output by the power supply over time, which ensures that the test environment of the reference chip and the chip under test is consistent, and thus accurately determines the conductivity value of the pin of the chip under test; Step S107, generating a voltage-current relationship curve diagram according to the second reference voltage value and the second reference current value of the reference chip pin and the second test voltage value and the second test current value of the chip pin to be tested; like Figure 4The figure shows a voltage-current relationship curve diagram, in which the conductivity of the reference chip pin and the chip pin to be tested is tested under the same variable voltage and current environment. By comparing the voltage-current relationship curve of the reference chip pin, the second reference current value is 0mA when the variable voltage is between 0V and 0.5V, and the second reference current value gradually increases after 0.5V, indicating that the on-voltage of the reference chip pin is 0.5V, until the variable voltage is 1.9V, when the second reference current value is 1.5mA, it is a stable state; the voltage-current relationship curve of the chip pin to be tested, after the second test voltage value is 0.5V, the second test current value does not increase significantly with the increase of the second test voltage value, and under the same variable voltage, the second reference current value and the second test current value differ greatly, indicating that the voltage-current relationship curve of the chip pin to be tested does not match the voltage-current relationship curve of the reference chip pin, and further indicating that the conductivity of the chip pin to be tested is extremely weak; Step S108, the resistivity ρ1 of the reference chip pin and the resistivity ρ2 of the chip pin to be tested are calculated by a formula, and the calculation formula is as follows: ρ1=(U / I)*(A / L), where U is the second reference voltage value, I is the second reference current value, A is the cross-sectional area of the reference chip pin, and L is the length of the reference chip pin. Similarly, the resistivity ρ2 of the chip pin to be tested can be obtained; The conductivity DDP1 of the reference chip pin and the conductivity DDP2 of the chip pin to be tested are calculated by the formula. The calculation formula is as follows: DDP1=1 / ρ1, and similarly, the conductivity DDP2 of the chip pin to be tested can be obtained; Step S109, if the absolute value of the conductivity difference between the reference chip pin and the chip pin to be tested is greater than the conductivity threshold, the excellent conductivity value of the chip pin to be tested is a second excellent conductivity value; If the absolute value of the conductivity difference between the reference chip pin and the chip pin to be tested is less than or equal to the conductivity threshold, the excellent conductivity value of the chip pin to be tested is the first excellent conductivity value; It should be specifically stated that the greater the excellent conductivity value is, the better the conductivity of the pin is, and the first excellent conductivity value is greater than the second excellent conductivity value.
[0020] Step S2, placing the chip to be tested and the reference chip in a signal transmission test unit, performing a data transmission test on the pins, and obtaining an excellent data transmission value of the pins of the chip to be tested; Among them, the data transmission test is used to test the accuracy and integrity of the data signal transmitted by the pin; like Figure 5As shown, the signal generator generates a stable pseudo-random binary sequence, and the pseudo-random binary sequence is used as a data signal source for data transmission testing; the signal transmission test unit is used to test the integrity and accuracy of data signal transmission of the reference chip pin to obtain reference transmission data, which is the pseudo-random binary sequence received by the reference chip, and at the same time, the integrity and accuracy of data signal transmission of the chip pin to be tested are tested to obtain the transmission data to be tested, which is the pseudo-random binary sequence received by the chip to be tested; the data receiver is used to receive the reference transmission data and the transmission data to be tested transmitted by the signal transmission test unit; the data analysis module analyzes the reference transmission data and the transmission data to be tested to obtain the data transmission excellence value of the chip pin to be tested; like Figure 6 As shown, Figure 6 The pin structure diagram of the chip, where pins 1, 2, and 3 are three address lines, used to determine the hardware address of the chip, pins 8 and 4 are positive and negative power supplies respectively, pin 5 SDA is serial data input / output, data is transmitted bidirectionally serially through the SDA pin, pin 6 SCL is the serial clock, SDA and SCL are open-drain terminals, in order to ensure data transmission and reception in actual applications, a 5.1kΩ resistor pull-up is required between the positive power supply, and pin 7 is the WP write protection terminal. When grounded, the chip is allowed to perform read and write operations, and when connected to the positive power supply, only read operations are allowed on the device; In this embodiment, step S2 includes the following sub-steps: Step S201, the signal generator generates a pseudo-random binary sequence, records the total number of binary digits of the pseudo-random binary sequence, and sends the pseudo-random binary sequence to the signal transmission test unit; Step S202, the signal transmission test unit writes a pseudo-random binary sequence into the chip to be tested and the reference chip respectively; The step S202 includes the following sub-steps: Step T1, the seventh pins of the chip under test and the reference chip are grounded respectively, and then a pseudo-random binary sequence is obtained, and the pseudo-random binary sequence is written into each address of the entire memory space of the chip under test and the reference chip respectively; Step T2, the 7th pins of the chip to be tested and the reference chip are connected to the positive power supply respectively, and data is read from each address in the memory space corresponding to the chip to be tested to obtain the transmission data to be tested, and data is read from each address in the memory space corresponding to the reference chip to obtain the reference transmission data; Step S203, the data receiver receives the reference transmission data transmitted via the reference chip pin and the transmission data to be tested transmitted via the pin of the chip to be tested; Step S204, comparing the reference transmission data and the transmission data to be tested with the pseudo-random binary sequence bit by bit, and recording the binary reference bit error number in the reference transmission data and the binary test bit error number in the transmission data to be tested; In this example, the pseudo-random binary sequence is 11000110, the reference transmission data is 11000111, the transmission data to be tested is 00111011, the reference transmission data is compared with the pseudo-random binary sequence to obtain a binary reference bit error number of 1, and the transmission data to be tested is compared with the pseudo-random binary sequence to obtain a binary test bit error number of 7; Step S205, the bit error rate generated by the pseudo-random binary sequence transmitted through the reference chip and the chip to be tested is calculated by a formula, and the calculation formula is as follows: The bit error rate of the reference transmission data = the number of binary reference bit errors / the total number of binary digits of the pseudo-random binary sequence * 100%. The bit error rate of the test data can be calculated in the same way; Step S206, if the bit error rate of the transmission data to be tested is greater than the bit error rate of the reference transmission data, it is considered that the data transmission of the chip pin to be tested is unreliable, and an excellent data transmission value of the chip pin to be tested is generated as a second excellent data transmission value; If the bit error rate of the transmission data to be tested is less than or equal to the bit error rate of the reference transmission data, the data transmission of the pin of the chip to be tested is considered to be stable and reliable, and an excellent data transmission value of the pin of the chip to be tested is generated as a first excellent data transmission value; It should be specifically noted that the first data transmission excellence value is greater than the second data transmission excellence value.
[0021] Step S3, obtaining a performance determination value of a reference chip pin based on the excellent conductivity value and the excellent data transmission value; In this embodiment, step S3 includes the following sub-steps: Step S31, obtaining the conductivity excellence value GD and the data transmission excellence value GC of the reference chip pin; Step S32, the connection reliability value GK of the reference chip pin is calculated by a formula, and the formula is as follows: GK=GD*α+GC*λ; Wherein, α is the conduction weight determined by the conductivity of the chip pin. If the conductivity of the chip pin is less than or equal to X1, the value of α is α1. If the conductivity of the chip pin is greater than X1 and less than X2, the value of α is α2. If the conductivity of the chip pin is greater than or equal to X2, the value of α is α3. X1 and X2 are standard pin conductivity, X1<X2, 0<α1<α2<α3; λ is the transmission weight determined by the bit error rate of the chip pin. If the bit error rate of the chip pin is less than or equal to Y1, the value of λ is λ1. If the bit error rate of the chip pin is greater than Y1 and less than Y2, the value of λ is λ2. If the bit error rate of the chip pin is less than or equal to Y2, the value of λ is λ3. Y1 and Y2 are standard pin bit error rates, Y1<Y2, 0<λ3<λ2<λ1; Step S33, repeatedly executing the above steps S1 to S3 for multiple times, to obtain the connection reliability value of the reference chip pin during multiple tests; Step S34, traverse and compare to obtain the minimum value among the connection reliability values, and use the minimum value of the connection reliability values as the performance determination value of the reference chip pin.
[0022] Step S4, determining the connection reliability of the chip pin to be tested according to the performance determination value, specifically as follows: Step S41, according to step S34, obtaining the minimum value of the connection reliability values corresponding to the reference chip pins, and taking the minimum value of the connection reliability values corresponding to the reference chip pins as the performance determination threshold; Step S42, if the performance judgment value of the chip pin under test is greater than or equal to the performance judgment threshold of the reference chip pin, it is determined that the connection of the chip pin under test is reliable; Step S43, if the performance judgment value of the chip pin to be tested is less than the performance judgment threshold of the reference chip pin, it is determined that the connection of the chip pin to be tested is unreliable; In this application, if corresponding calculation formulas appear, the above calculation formulas are all dimensionless and take their numerical calculations. The weight coefficients, proportional coefficients and other coefficients in the formulas are set to a result value obtained by quantifying each parameter. The size of the weight coefficient and the proportional coefficient can be determined as long as it does not affect the proportional relationship between the parameter and the result value.
[0023] Embodiment 2: As a further solution of Embodiment 1, step S2 may further include the following sub-steps: Step P1, using a temperature control device to set an initial test temperature; Step P2, testing the stability of writing and reading data of the reference chip under the initial test temperature environment; The step P2 comprises the following sub-steps: Step P201, predefine a segment of data with a size of mKB as a test data block, where m is a positive integer; Step P202, sequentially write the test data blocks into the memory space corresponding to the reference chip, and record the start time t1 and the completion time t2 of the write operation; Step P3, reading the test data block in the memory of the reference chip, and recording the start time t3 and the completion time t4 of the reading operation; Step P4, calculating the first reference writing speed V1 and the first reference reading speed V2 of the reference chip by formula, the formula is as follows: V1=m / (t2-t1)*1024; V2=m / (t4-t3)*1024; Step P5, replacing the reference chip with the chip to be tested, and executing steps P1 to P4 to obtain a second write speed V3 and a second read speed V4 of the chip to be tested by calculation; Step P6, gradually increase the test temperature, and repeat steps P1-P5; Step P7, if the second test write speed is greater than or equal to the first reference write speed and the second test read speed is greater than or equal to the first reference read speed, it is considered that the pin data transmission of the chip under test is stable and reliable under different temperature environments; otherwise, it is considered that the pin data transmission of the chip under test fluctuates and is unreliable under different temperature environments.
[0024] Embodiment 3: Figure 7 As shown, based on another concept of the same invention, a pin connection reliability testing system is now proposed, comprising: The conductive test module is used to select a reference chip and a chip to be tested and place them in a pin conductivity test unit to test the conductivity of the pins and obtain the excellent conductivity value of the pins of the chip to be tested; The transmission test module is used to place the chip under test and the reference chip in the signal transmission test unit, perform data transmission test on the pins, and obtain the data transmission excellent value of the pins of the chip under test; A calculation module, which obtains the performance judgment value of the reference chip pin based on the excellent conductivity value and the excellent data transmission value analysis; The determination module is used to determine the connection reliability of the chip pins to be tested according to the performance determination value.
[0025] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to only specific implementation methods. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A method for testing the connection reliability of a pin, characterized in that: The test method is as follows: Step S1, selecting a reference chip and a chip to be tested and placing them in a pin conductivity test unit, testing the conductivity of the pins, and obtaining an excellent conductivity value of the pins of the chip to be tested; Step S2, placing the chip to be tested and the reference chip in a signal transmission test unit, performing a data transmission test on the pins, and obtaining an excellent data transmission value of the pins of the chip to be tested; Step S3, obtaining a performance determination value of a reference chip pin based on the excellent conductivity value and the excellent data transmission value; Step S4, determining the connection reliability of the pins of the chip to be tested according to the performance determination value.
2. A method for testing the connection reliability of a pin according to claim 1, characterized in that: The step S1 includes the following sub-steps: Step S101, the switch K1 and the switch K2 are in a closed state, and the output voltage is gradually increased over time; Step S102, at the same time, the sampling circuit collects a first reference current value of a reference chip pin and collects a first test current value of a chip pin to be tested; Step S103, comparing and analyzing the first reference current value and the first test current value, and the first reference voltage value and the first test voltage value; Step S104, if the absolute value of the current difference between the first reference current value and the first test current value is less than the current threshold, and the absolute value of the voltage difference between the first reference voltage value and the first test voltage value is less than the voltage threshold, then proceed to the next step; If the absolute value of the current difference between the first reference current value and the first test current value is greater than or equal to the current threshold or the absolute value of the voltage difference between the first reference voltage value and the first test voltage value is greater than or equal to the voltage threshold, it is considered that the conductivity of the chip pin under test is abnormal.
3. A method for testing the connection reliability of a pin according to claim 2, characterized in that: The step S1 includes the following sub-steps: Step S105, when the switch K1 is closed and the switch K2 is open, the output voltage is also gradually increased over time, and the sampling circuit collects the second reference voltage value and the second reference current value of the reference chip pin; Step S106, when the switch K1 is opened and the switch K2 is closed, the voltage output by the control power supply gradually increases with time, and the sampling circuit collects the second test voltage value and the second test current value of the pin of the chip to be tested; Step S107, generating a voltage-current relationship curve diagram according to the second reference voltage value and the second reference current value of the reference chip pin and the second test voltage value and the second test current value of the chip pin to be tested; Step S108, the resistivity ρ1 of the reference chip pin and the resistivity ρ2 of the chip pin to be tested are calculated by a formula, and the calculation formula is as follows: ρ1=(U / I)*(A / L), where U is the second reference voltage value, I is the second reference current value, A is the cross-sectional area of the reference chip pin, and L is the length of the reference chip pin. Similarly, the resistivity ρ2 of the chip pin to be tested can be obtained; The conductivity DDP1 of the reference chip pin and the conductivity DDP2 of the chip pin to be tested are calculated by the formula. The calculation formula is as follows: DDP1=1 / ρ1, and similarly, the conductivity DDP2 of the chip pin to be tested can be obtained; Step S109, if the absolute value of the conductivity difference between the reference chip pin and the chip pin to be tested is greater than the conductivity threshold, the excellent conductivity value of the chip pin to be tested is a second excellent conductivity value; If the absolute value of the conductivity difference between the reference chip pin and the chip pin to be tested is less than or equal to the conductivity threshold, the excellent conductivity value of the chip pin to be tested is the first excellent conductivity value; wherein the first excellent conductivity value is greater than the second excellent conductivity value.
4. A method for testing the connection reliability of a pin according to claim 3, characterized in that: The first reference voltage value and the first reference current value are the voltage value and the current value of the reference chip pin when the switch K1 and the switch K2 are both closed; The second reference voltage value and the second reference current value are the voltage value and the current value of the reference chip pin when the switch K1 is closed and the switch K2 is open; The first test voltage value and the first test current value are the voltage value and current value of the pin of the chip to be tested when the switch K1 and the switch K2 are both closed; The second test voltage value and the second test current value are the voltage value and the current value of the pin of the chip to be tested when the switch K1 is opened and the switch K2 is closed.
5. A method for testing the connection reliability of a pin according to claim 3, characterized in that: The step S2 includes the following sub-steps: Step S201, the signal generator generates a pseudo-random binary sequence, records the total number of binary digits of the pseudo-random binary sequence, and sends the pseudo-random binary sequence to the signal transmission test unit; Step S202, the signal transmission test unit writes a pseudo-random binary sequence into the chip to be tested and the reference chip respectively; Step S203, the data receiver receives the reference transmission data transmitted via the reference chip pin and the transmission data to be tested transmitted via the pin of the chip to be tested; Step S204, comparing the reference transmission data and the transmission data to be tested with the pseudo-random binary sequence bit by bit, and recording the binary reference bit error number in the reference transmission data and the binary test bit error number in the transmission data to be tested; Step S205, the bit error rate generated by the pseudo-random binary sequence transmitted through the reference chip and the chip to be tested is calculated by a formula, and the calculation formula is as follows: The bit error rate of the reference transmission data = the number of binary reference bit errors / the total number of binary digits of the pseudo-random binary sequence * 100%. The bit error rate of the test data can be calculated in the same way; Step S206, if the bit error rate of the transmission data to be tested is greater than the bit error rate of the reference transmission data, it is considered that the data transmission of the chip pin to be tested is unreliable, and an excellent data transmission value of the chip pin to be tested is generated as a second excellent data transmission value; If the bit error rate of the transmission data to be tested is less than or equal to the bit error rate of the reference transmission data, the data transmission of the chip pin to be tested is considered to be stable and reliable, and an excellent data transmission value of the chip pin to be tested is generated as a first excellent data transmission value; wherein the first excellent data transmission value is greater than the second excellent data transmission value.
6. A method for testing the connection reliability of a pin according to claim 5, characterized in that: The step S202 includes the following sub-steps: Step T1, the seventh pins of the chip under test and the reference chip are grounded respectively, and then a pseudo-random binary sequence is obtained, and the pseudo-random binary sequence is written into each address of the entire memory space of the chip under test and the reference chip respectively; Step T2, the 7th pins of the chip under test and the reference chip are connected to the positive power supply respectively, data is read from each address in the memory space corresponding to the chip under test to obtain the transmission data under test, and data is read from each address in the memory space corresponding to the reference chip to obtain the reference transmission data.
7. A method for testing the connection reliability of a pin according to claim 6, characterized in that: The step S3 includes the following sub-steps: Step S31, obtaining the conductivity excellence value GD and the data transmission excellence value GC of the reference chip pin; Step S32, the connection reliability value GK of the reference chip pin is calculated by a formula, and the formula is as follows: GK=GD*α+GC*λ; Step S33, repeatedly executing the above steps S1 to S3 for multiple times, to obtain the connection reliability value of the reference chip pin during multiple tests; Step S34, traverse and compare to obtain the minimum value among the connection reliability values, and use the minimum value of the connection reliability values as the performance judgment value of the reference chip pin.
8. A method for testing the connection reliability of a pin according to claim 7, characterized in that: α is the conductivity weight determined by the conductivity of the chip pin. If the conductivity of the chip pin is less than or equal to X1, the value of α is α1. If the conductivity of the chip pin is greater than X1 and less than X2, the value of α is α2. If the conductivity of the chip pin is greater than or equal to X2, the value of α is α3, where X1 and X2 are standard pin conductivity, X1<X2, 0<α1<α2<α3; λ is the transmission weight determined by the bit error rate of the chip pin. If the bit error rate of the chip pin is less than or equal to Y1, the value of λ is λ1. If the bit error rate of the chip pin is greater than Y1 and less than Y2, the value of λ is λ2. If the bit error rate of the chip pin is less than or equal to Y2, the value of λ is λ3. Y1 and Y2 are standard pin bit error rates, Y1<Y2, 0<λ3<λ2<λ1.
9. A method for testing the connection reliability of a pin according to claim 7, characterized in that: The step S4 includes the following sub-steps: Step S41, according to step S34, obtaining the minimum value of the connection reliability values corresponding to the reference chip pins, and taking the minimum value of the connection reliability values corresponding to the reference chip pins as the performance determination threshold; Step S42, if the performance judgment value of the chip pin under test is greater than or equal to the performance judgment threshold of the reference chip pin, it is determined that the connection of the chip pin under test is reliable; Step S43: If the performance judgment value of the pin of the chip to be tested is less than the performance judgment threshold of the pin of the reference chip, it is determined that the connection of the pin of the chip to be tested is unreliable.
10. A pin connection reliability testing system, characterized in that: In combination with a method for testing the connection reliability of a pin according to any one of claims 1 to 9, the method comprises: The conductive test module is used to select a reference chip and a chip to be tested and place them in a pin conductivity test unit to test the conductivity of the pins and obtain the excellent conductivity value of the pins of the chip to be tested; The transmission test module is used to place the chip under test and the reference chip in the signal transmission test unit, perform data transmission test on the pins, and obtain the data transmission excellent value of the pins of the chip under test; A calculation module, which obtains the performance judgment value of the reference chip pin based on the excellent conductivity value and the excellent data transmission value analysis; The determination module is used to determine the connection reliability of the chip pins to be tested according to the performance determination value.