Multi-channel data acquisition device, method and radar system

Abstract

The present invention discloses a multi-channel data acquisition device, method and radar system, wherein the device comprises M analog acquisition channels, N AD chips, FPGA, clock module and DDR; each analog acquisition channel is used to convert a single-ended analog signal into a differential analog signal; each AD chip is used to convert the differential analog signal into a digital signal; the FPGA is used to synchronously capture the digital signals output by multiple AD chips; each digital signal is subjected to time-frequency conversion to obtain a corresponding frequency domain signal; each frequency domain signal is subjected to filtering processing; the filtered signal is stored and uploaded; the clock module is used to provide a reference clock for the entire device; and the DDR is used to cache the data processed by the FPGA. The present invention solves the problem that the time domain filtering method is complex in calculation and difficult to control the frequency response.

Description

Technical Field

[0001] The present invention belongs to the technical field of radar data acquisition, and in particular relates to a multi-channel data acquisition device, method and radar system. Background Art

[0002] Due to interference, noise and propagation energy loss in the radar detection process, the echo signal received by the antenna is very weak. In order to better acquire and process the echo signal, the received signal needs to be amplified and filtered first.

[0003] At present, most of the filtering processing of phased array radar is for time domain filtering scheme, which is complex to calculate, difficult to control frequency response, and has low effect in radar system. At the same time, the number of channels of current analog signal acquisition modules is usually 1 to 8. The signal acquisition of more channels has problems such as processor resource occupation, signal interference and acquisition performance that cannot meet the standards. Summary of the invention

[0004] The object of the present invention is to provide a multi-channel data acquisition device, method and radar system to solve at least one of the problems of complex calculation and difficulty in controlling frequency response of traditional time domain filtering schemes, and signal interference and poor acquisition performance in multi-channel signal acquisition.

[0005] The present invention solves the above technical problems through the following technical solutions: a multi-channel data acquisition device, comprising M analog acquisition channels, N AD chips, FPGA, clock module and DDR; m analog acquisition channels correspond to one AD chip, 1≤m<M, N≤M; the output end of each analog acquisition channel is connected to the input end of the corresponding AD chip, the output end of each AD chip is connected to the FPGA, and the clock module and DDR are connected to the FPGA;

[0006] Each of the analog acquisition channels is used to convert a single-ended analog signal into a differential analog signal;

[0007] Each of the AD chips is used to convert the differential analog signal into a digital signal;

[0008] The FPGA is used to synchronously capture the digital signals output by multiple AD chips; perform time-frequency conversion on each of the digital signals to obtain a corresponding frequency domain signal; perform filtering on each of the frequency domain signals; and store and upload the filtered signals;

[0009] The clock module is used to provide a reference clock for the entire device; the DDR is used to cache data processed by the FPGA;

[0010] The FPGA is used to filter each of the frequency domain signals using a filter; when designing the filter, an optimization algorithm is used to optimize the actual frequency response of the filter, and the frequency domain signal and its weight coefficient and the penalty factor of the filter sampling point number are added to the optimization function.

[0011] Furthermore, each of the analog acquisition channels includes an LC filter, an ESD protection circuit, a single-ended to differential circuit, and a filtering circuit which are connected in sequence.

[0012] Furthermore, the single-ended to differential circuit adopts a balun module.

[0013] Furthermore, a first isolation wall is provided between two adjacent analog acquisition channels; the m analog acquisition channels and their corresponding AD chips are located in the same isolation cavity; and a second isolation wall is provided between the N AD chips and the FPGA.

[0014] Furthermore, the filter is a FIR filter, and the design process of the FIR filter includes:

[0015] The frequency response function of the FIR filter is constructed, and its specific expression is:

[0016] ;

[0017] in, represents the actual frequency response of the FIR filter, represents the number of filter sampling points, k represents the sampling point sequence number, represents the time domain impulse response function of the FIR filter, Indicates frequency;

[0018] The optimization function is constructed according to the frequency response function of the FIR filter, and its specific expression is:

[0019] ;

[0020] ;

[0021] in, represents the minimum mean square error, represents the weight coefficient, represents the ideal frequency response, represents the frequency domain signal, represents the penalty factor, represents the cut-off frequency; BW represents the signal bandwidth;

[0022] An optimization algorithm is used to solve the optimization function to obtain an optimal actual frequency response of the filter, and then filtering is performed according to the optimal actual frequency response of the filter.

[0023] Based on the same concept, the present invention also provides a radar system, which includes the multi-channel data acquisition device as described above.

[0024] Based on the same concept, the present invention also provides a multi-channel data acquisition method, comprising:

[0025] Convert the single-ended analog signal input to each analog acquisition channel into a differential analog signal;

[0026] converting each of the differential analog signals into a digital signal;

[0027] Synchronously capture all digital signals, and perform time-frequency conversion on each of the digital signals to obtain corresponding frequency domain signals;

[0028] Performing filtering processing on each of the frequency domain signals;

[0029] Store and upload the filtered signal;

[0030] In which, a filter is used to filter each of the frequency domain signals; when designing the filter, an optimization algorithm is used to optimize the actual frequency response of the filter, and the frequency domain signal and its weight coefficient and the penalty factor of the filter sampling point number are added to the optimization function.

[0031] Furthermore, before data collection, the collection method also includes multi-channel synchronous debugging, specifically including:

[0032] Inputting the first test data into each analog acquisition channel, and converting the input first test data into first differential test data through each analog acquisition channel;

[0033] Determine a differential symbol according to each of the first differential test data, and then determine a differential symbol change position;

[0034] Determine the zero crossing point of each first differential test data at the same clock rising edge according to the differential sign change position of each first differential test data;

[0035] Determine whether the data center points of each analog acquisition channel are aligned according to the zero crossing point of each first differential test data; if yes, determine the data center points of each analog acquisition channel; if not, adjust the time delay of each analog acquisition channel to align the data center points of each analog acquisition channel;

[0036] Inputting the second test data into each analog acquisition channel, and converting the input second test data into second differential test data through each analog acquisition channel;

[0037] Reading the digital data result of each second differential test data;

[0038] According to the digital data results, it is determined whether the data of each analog acquisition channel is aligned. If so, each analog acquisition channel realizes clock synchronization; if not, the delay of each analog acquisition channel is adjusted in bytes to align the data of each analog acquisition channel.

[0039] Furthermore, a radix-4 FFT algorithm is used to perform time-frequency conversion on each of the digital signals.

[0040] Furthermore, the filter is a FIR filter, and the design process of the FIR filter includes:

[0041] The frequency response function of the FIR filter is constructed, and its specific expression is:

[0042] ;

[0043] in, represents the actual frequency response of the FIR filter, represents the number of filter sampling points, k represents the sampling point sequence number, represents the time domain impulse response function of the FIR filter, Indicates frequency;

[0044] The optimization function is constructed according to the frequency response function of the FIR filter, and its specific expression is:

[0045] ;

[0046] ;

[0047] in, represents the minimum mean square error, represents the weight coefficient, represents the ideal frequency response, represents the frequency domain signal, represents the penalty factor, represents the cut-off frequency; BW represents the signal bandwidth;

[0048] An optimization algorithm is used to solve the optimization function to obtain an optimal actual frequency response of the filter, and then filtering is performed according to the optimal actual frequency response of the filter.

[0049] Beneficial Effects

[0050] Compared with the prior art, the advantages of the present invention are:

[0051] The present invention converts multi-channel digital signals from the time domain to the frequency domain, and then accurately filters the frequency domain signals, thereby reducing the computational complexity of the filtering process, improving the filtering process efficiency and filtering accuracy, and solving the problems of complex calculations and difficulty in controlling frequency response in the time domain filtering method. The present invention uses an optimization algorithm to optimize the actual frequency response of the filter based on the filter input frequency domain signal, thereby further improving the filtering accuracy and realizing adaptive optimization of the filter design.

[0052] The present invention designs each analog acquisition channel, and ensures the accuracy of analog signal acquisition of each channel through a high-order LC filter circuit, an ESD protection circuit, a single-ended to differential circuit and a filter circuit; an isolation wall is designed between each analog acquisition channel, m analog acquisition channels and their corresponding AD chips are located in the same isolation cavity, and an isolation wall is provided between the AD chip and the FPGA, which reduces the mutual influence between the channels, avoids interference between signals within the board, avoids interference caused by clutter and harmonics generated by an external harsh environment and aliasing when acquiring signals at a low sampling rate, and greatly improves the acquisition performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only one embodiment of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 is a structural schematic diagram of a multi-channel data acquisition device in an embodiment of the present invention;

[0055] Figure 2 is a schematic diagram of the structure of a single analog acquisition channel in an embodiment of the present invention;

[0056] Figure 3 is a schematic diagram of the isolated cavity structure in an embodiment of the present invention;

[0057] Figure 4 is a schematic diagram of the structure of a clock module in an embodiment of the present invention;

[0058] Figure 5 is a signal curve of a traditional time domain filtering solution in an embodiment of the present invention;

[0059] Figure 6 is a signal curve of a multi-channel data acquisition device in an embodiment of the present invention;

[0060] Figure 7 is the frequency domain waveform of the channel itself and its adjacent channels in the traditional time domain filtering solution in the embodiment of the present invention;

[0061] Figure 8is the frequency domain waveform of the channel itself and its adjacent channels of the multi-channel data acquisition device in the embodiment of the present invention;

[0062] Fig. 9 is a flow chart of a multi-channel data acquisition method in an embodiment of the present invention;

[0063] Fig.10 It is a flow chart of multi-channel synchronous debugging in an embodiment of the present invention.

[0064] Explanation of the accompanying drawings: 1-first isolation wall, 2-AD chip, 3-isolation cavity, 4-FPGA, 5-second isolation wall. DETAILED DESCRIPTION

[0065] The following is a clear and complete description of the technical solutions in the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0067] Example 1

[0068] like Figure 1 As shown, a multi-channel data acquisition device provided by an embodiment of the present invention includes M analog acquisition channels, N AD chips (i.e., analog-to-digital conversion chips), FPGA (i.e., field programmable gate array), clock module, and DDR (i.e., double-speed memory); m analog acquisition channels correspond to one AD chip, 1≤m<M, N≤M; the output end of each analog acquisition channel is connected to the input end of the corresponding AD chip, the output end of each AD chip is connected to the FPGA, and the clock module and DDR are connected to the FPGA. Taking 32 channels as an example, every 4 analog acquisition channels correspond to one AD chip, then M=32, m=4, and N=8.

[0069] Each analog acquisition channel is used to convert the input single-ended analog signal into a differential analog signal. Figure 2 As shown, each analog acquisition channel includes a high-order LC filter, an ESD protection circuit, a single-ended to differential circuit, and a filter circuit connected in sequence. In this embodiment, the single-ended to differential circuit uses a balun module to convert the single-ended analog signal into a differential analog signal; the filter circuit uses a capacitor to filter out differential and common mode interference. The accuracy of signal acquisition is ensured by configuring peripheral circuits such as a high-order LC filter, a single-ended to differential circuit, and a filter circuit.

[0070] In order to avoid mutual influence between the analog acquisition channels, Figure 3 As shown, a first isolation wall 1 is provided between two adjacent analog acquisition channels; in order to avoid interference between signals in the PCB board, the four analog acquisition channels and their corresponding AD chips 2 are located in the same isolation cavity 3, and a second isolation wall 5 is provided between the eight AD chips 2 and the FPGA 4. At the same time, isolation is provided between the power supply side and the analog side, and between the analog side and the digital side. The PCB isolation design, the isolation cavity structure design, etc. are combined to avoid interference caused by clutter and harmonics generated by the harsh external environment and aliasing when acquiring signals at a low sampling rate, thereby improving signal acquisition performance and reducing interference.

[0071] Each AD chip is used to convert the differential analog signal input by the corresponding analog acquisition channel into a digital signal. FPGA is used to synchronously capture the digital signals output by multiple AD chips; perform time-frequency conversion on each digital signal to obtain the corresponding frequency domain signal; filter each frequency domain signal; store and upload the filtered signal. FPGA caches the filtered signal in DDR; when FPGA receives the trigger signal, it uploads the data cached in DDR to the host computer, and finally the host computer processes the received data to obtain the distance, speed and direction of the radar target.

[0072] The simultaneous input of multi-channel signals will cause mutual interference between the filtering circuit and the single-ended to differential circuit. At the same time, the signals between the links will also interfere with each other. The filtering of time domain data has the problems of complex calculation and difficulty in controlling the frequency response, and the effect in the radar system is relatively low. The present invention utilizes the parallel computing capability of FPGA to convert the time domain signal into the frequency domain signal, and then filters the frequency domain signal, which reduces the calculation complexity of the filtering process and improves the filtering process efficiency and filtering accuracy.

[0073] In this embodiment, FPGA uses the Radix-4 FFT algorithm (Radix-4 FFT, Fast Fourier Transform of Radix 4) to perform time-frequency conversion on each digital signal to obtain the corresponding frequency domain signal. The radar system needs to analyze the frequency domain and calculate the position and speed of different scenes according to the various parameters of the frequency domain change process. The present invention chooses to implement FFT in FPGA. On the one hand, it is convenient for the host computer to analyze the data in real time. On the other hand, it directly filters according to the frequency domain signal, and can adjust the actual frequency response of the filter in real time. Compared with the filtering of the time domain signal, it is more accurate and flexible. In the application scenario of multi-channel synchronous acquisition, the traditional FFT algorithm consumes too much computing resources. Radix-4 FFT is a divide-and-conquer algorithm, which can greatly reduce the amount of calculation by decomposing the discrete Fourier transform (DFT) of multiple points into multiple smaller DFTs. Implementing the Radix-4 FFT algorithm on FPGA can make full use of the parallel computing power of the hardware, schedule and process multiple computing units at the same time, maximize throughput, and is more suitable for situations with high frequency response requirements.

[0074] The designed FIR filter (Finite Impulse Response, finite unit impulse response filter) is used to filter each frequency domain signal. In a specific embodiment of the present invention, the design process of the FIR filter is as follows:

[0075] Constructing the time domain relationship of the FIR filter:

[0076] (1)

[0077] in, Represents a time domain signal and impulse response function The convolution result is represents the time domain signal, represents the number of filter sampling points, represents the time variable, k represents the sampling point number, Represents the time domain impulse response function of the filter. Since the convolution in the time domain is equivalent to the product in the frequency domain obtained after Fourier transform, according to formula (1), we can get:

[0078] (2)

[0079] in, represents the signal after filtering, represents the frequency domain signal, The actual frequency response of the filter. The time domain impulse response function The Fourier transform expression is:

[0080] (3)

[0081] To filter the frequency domain signal, there is no need to consider the filter model in the time domain. Make adjustments.

[0082] The purpose of filtering frequency domain signals is to make the obtained frequency response closer to the ideal frequency response. Therefore, the present invention controls the error between the actual frequency response and the ideal frequency response by minimizing the mean square error (MSE). At the same time, in order to adjust the filter's response to input spurious in non-ideal conditions, the frequency domain signal is added to the optimization function. and its weight coefficient , so the specific expression of the optimization function is:

[0083] (4)

[0084] (5)

[0085] in, represents the minimum mean square error, represents the ideal frequency response, represents the penalty factor, represents the cutoff frequency, and BW represents the signal bandwidth. Considering the number of filter sampling points The increase in will directly increase the computational complexity, and in theory The larger the value, the better the filter effect. Therefore, the present invention increases the number of filter sampling points in the optimization function. The penalty factor , to avoid overly complex calculations.

[0086] An optimization algorithm is used to solve the optimization function (i.e., formula (2)) to obtain the optimal actual frequency response of the filter, and then the FIR filter is designed based on the optimal actual frequency response of the filter. In this embodiment, the Seagull optimization algorithm is used to solve the optimal actual frequency response of the filter. The Seagull optimization algorithm solves the optimal solution by combining local search and global search, which can not only explore the global solution, but also make fine adjustments in the local area. This means that when designing a frequency domain filter, the Seagull optimization algorithm can not only find the global optimal solution, but also refine the solution after finding a good local area, thereby improving the accuracy of the filter design. The Seagull optimization algorithm converges quickly and can find the optimal solution with limited computing resources. Compared with other heuristic algorithms, the Seagull optimization algorithm has fewer parameter settings, which reduces the computational complexity and improves efficiency. In the Seagull optimization algorithm, the position update formula is:

[0087] (6)

[0088] in, represents the parameter vector of the i-th seagull at the t+1th iteration, represents the parameter vector of the i-th seagull at the t-th iteration, represents the current optimal solution (i.e. the actual frequency response of the current optimal filter), represents the local optimal position, , Respectively represent the weights of global variables and local variables, that is, the step size. Usually the weight of the global variable Less than the local variable weight .

[0089] The present invention combines time-frequency domain conversion and filter design algorithm to realize adaptive filtering inside FPGA, and optimizes the actual frequency response of the filter through the Seagull optimization algorithm, ensuring that the actual frequency response of the acquisition can reach the optimal value. Compared with other optimization algorithms, the Seagull optimization algorithm can better reflect the global situation by changing the weights of global variables and local variables, avoiding falling into the local optimum.

[0090] The clock module is used to provide reference clock for the entire device. Figure 4 As shown, the clock module includes a first clock buffer, a second clock buffer, a third clock buffer, an external reference clock and an internal reference clock; the second clock buffer is connected to the radar adapter card through the first clock buffer, the second clock buffer is also connected to the external reference clock through the third clock buffer, and the internal reference clock is connected to the second clock buffer. The model selected for the first clock buffer and the third clock buffer is SI53340, the external reference clock uses a 156.25MHz crystal oscillator, and the internal reference clock uses a 10MHz crystal oscillator. The radar adapter card provides a 10MHz external reference clock, and the 10MHz external reference clock is divided into the clock required by the FPGA and the clock of the second clock buffer through the first clock buffer to ensure that the clock of the entire device is synchronized with the external clock. The third clock buffer divides out a 10MHz channel as a reserve, which is compared with the clock of the entire device to ensure that the clock output by the second clock buffer is consistent with the external clock. Figure 4In the figure, SYNC represents the synchronization clock, which is used for AD data synchronous acquisition; Fs represents the sampling clock, which is used to provide the sampling clock for the AD chip. The sampling clock Fs is also supplied to the FPGA so that the FPGA can monitor the sampling clock Fs; VCXO represents the voltage-controlled crystal oscillator, which generates an 80MHz clock source through the voltage-controlled crystal oscillator VCXO; tune represents the feedback adjustment signal, and the voltage value of tune can adjust the output frequency of the voltage-controlled crystal oscillator VCXO to make it stably output 80MHz; GTX_CLK represents the source clock provided by the second clock buffer to the third clock buffer. The MGTREFCLK0 and MGTREFCLK1 generated by the third clock buffer are used to provide the clock for the MGT (high-speed serial transceiver module) in the FPGA, and FPGA_CLK is used to provide the internal clock for the FPGA.

[0091] The multi-channel data acquisition device of the present invention also includes a communication module, which specifically includes communication interfaces such as Gigabit Ethernet, optical modules and 10 Gigabit electrical ports, which can ensure that the collected data is effectively reported to the host computer; at the same time, the acquisition device is also provided with an overvoltage and overcurrent protection circuit and a temperature and humidity detection circuit, which monitors the temperature and humidity information of the device in real time through the temperature and humidity detection circuit, and monitors the current and voltage information of each chip of the device in real time through the overvoltage and overcurrent protection circuit, and reports it to the state control module of the radar, so as to monitor the information of the acquisition device in real time, and ensure that after the radar system is installed, the user can grasp the status information of the acquisition device in real time.

[0092] In order to illustrate the effectiveness of the device of the present invention, the present invention is compared with the traditional time domain filtering scheme. Figure 5 and Figure 6 The signal curve after traditional time domain filtering and the signal curve after frequency domain filtering of the present invention are respectively shown. Figure 5 , input 391MHz signal to channel 8 (corresponding to Figure 5 IN_8V curve in the figure), channel 1 (corresponding to Figure 5 T_1V curve in) and channel 16 (corresponding to Figure 5 There is obvious interference in the T_16V curve in the figure, and the interference intensity reaches -50dB. V represents the horizontal polarization channel. Figure 6 , input 391MHZ signal to channel 13 (corresponding to Figure 6 13_H curve in the figure), channel 11 (corresponding to Figure 6 11_H curve in the figure) and channel 16 (corresponding to Figure 6 The interference of the 16_H curve in the figure is basically filtered out, and the channel isolation is higher than 80dB. H represents the vertical polarization channel. Figure 7 and Figure 8 The conventional time domain filtering scheme and the frequency domain filtering scheme of the present invention are shown respectively. Figure 7 and Figure 8It can be seen that the signal harmonics of the traditional time domain filtering solution are significantly higher than those of the present invention, and there is obvious interference between adjacent channels. It can be seen that the present invention has good interference filtering performance and high channel isolation.

[0093] The acquisition device of the present invention is used to perform high-precision synchronous acquisition of 32 channels of signals above 300M at a sampling rate of 120MHZ. By analyzing the quality of the acquired signals, it is obtained that ENOB (effective number of bits)>10.5, SNR (signal-to-noise ratio)>65, DBFS (signal strength)>80, SFDR (spurious-free dynamic range)>80. After experimental verification, after using the acquisition device of the present invention, the isolation between adjacent channels is>70dB, and there is basically no influence between adjacent channels. The present invention can realize the synchronous acquisition and reporting of signals of 32 channels, and at the same time realize clock synchronization with the external module to realize real-time data reporting.

[0094] Example 2

[0095] like Figure 7 As shown, a multi-channel data acquisition method provided by an embodiment of the present invention includes the following steps:

[0096] Step 1: Convert the input single-ended analog signal into a differential analog signal through the analog acquisition channel;

[0097] Step 2: Convert the input differential analog signal into a digital signal through the AD chip;

[0098] Step 3: FPGA synchronously captures the digital signals input by all AD chips, and performs time-frequency conversion on each digital signal to obtain the corresponding frequency domain signal;

[0099] Step 4: FPGA performs filtering on each frequency domain signal;

[0100] Step 5: FPGA stores and uploads the filtered signal.

[0101] In a specific implementation of the present invention, FPGA uses a radix 4 FFT algorithm to perform time-frequency conversion on each digital signal to obtain a corresponding frequency domain signal; and uses a designed FIR filter to filter each frequency domain signal. The design process of the FIR filter includes:

[0102] In order to achieve filtering of frequency domain signals, it is necessary to convert the time domain impulse response of the filter into an actual frequency response. Therefore, the frequency response function of the FIR filter is constructed based on discrete Fourier transform, and its specific expression is shown in formula (3) in Example 1 of the present application.

[0103] The purpose of filtering the frequency domain signal is to make the obtained frequency response closer to the ideal frequency response. Therefore, the present invention controls the error between the actual frequency response and the ideal frequency response by minimizing the mean square error (MSE). The specific expressions of the optimization function designed in this way are shown in Formula (4) and Formula (5) in Example 1 of the present application.

[0104] An optimization algorithm is used to solve the optimization function to obtain the optimal actual frequency response of the filter, and then the FIR filter is designed according to the optimal actual frequency response of the filter. In this embodiment, the Seagull optimization algorithm is used to solve the optimal actual frequency response of the filter. The Seagull optimization algorithm solves the optimal solution by combining local search and global search, which can not only explore the global solution, but also make fine adjustments in the local area. This means that when designing a frequency domain filter, the Seagull optimization algorithm can not only find the global optimal solution, but also refine the solution after finding a good local area, thereby improving the accuracy of the filter design. The Seagull optimization algorithm converges quickly and can find the optimal solution under limited computing resources. Compared with other heuristic algorithms, the Seagull optimization algorithm has fewer parameter settings, which reduces the computational complexity and improves efficiency.

[0105] In order to achieve synchronous acquisition of each analog acquisition channel, a shared clock source solution is used. This solution is divided into two parts: data center alignment and data alignment. Before data acquisition, each channel is first synchronized and debugged to achieve data center alignment and data alignment. Figure 8 As shown, the specific implementation process includes:

[0106] Step S1: inputting first test data into each analog acquisition channel, and converting the input first test data into first differential test data through each analog acquisition channel.

[0107] In this embodiment, the first test data is data that continuously switches between 0 and 1, such as 01010101….

[0108] Step S2: Determine the differential sign according to each first differential test data, and then determine the position where the differential sign changes.

[0109] The differential signal is the result signal obtained by performing a differential operation on two signals. One of the two signals is a positive polarity signal and the other is a negative polarity signal. When the positive polarity signal is greater than the negative polarity signal, the differential sign is positive; when the positive polarity signal is less than the negative polarity signal, the differential sign is negative. The position where the differential sign changes can be determined by continuously analyzing the differential signs of each first differential test data at the same clock rising edge.

[0110] Step S3: determining the zero crossing point of each first differential test data at the same clock rising edge according to the differential symbol change position of each first differential test data.

[0111] Step S4: judging whether the data center points of each analog acquisition channel are aligned according to the zero crossing points of each first differential test data; if so, determining the data center points of each analog acquisition channel; if not, adjusting the delay of each analog acquisition channel to align the data center points of each analog acquisition channel.

[0112] On the same clock rising edge, continuously analyze the first differential test data. If the single-channel state is unstable and jumps between 0 and 1, it indicates that the point is at the zero crossing point. If the single-channel state is stable, it indicates that there is an offset in the channel. By setting the delay, the data center points of all analog acquisition channels are aligned to ensure data synchronization of all acquisition channels.

[0113] Step S5: input the second test data into each analog acquisition channel, and convert the input second test data into second differential test data through each analog acquisition channel.

[0114] Step S6: Read the digital data result of the second differential test data.

[0115] Step S7: Determine whether the data of each analog acquisition channel is aligned according to each digital data result. If so, each analog acquisition channel implements clock synchronization; if not, adjust the delay of each analog acquisition channel in bytes to align the data of each analog acquisition channel.

[0116] Data alignment is performed on the basis of data center point alignment. Since data center point alignment has been achieved, data alignment only considers whether the first byte is synchronized. For example, the second test data is 123456, and the results may be 234561, 561234, etc. The channels corresponding to the inconsistent results are offset by bytes so that the results of all channels are 123456, so that data alignment of all channels can be achieved, thereby ensuring that FPGA synchronously captures the signals of all channels.

[0117] In some specific embodiments of the present invention, the multi-channel data acquisition method in Example 2 of the present application can be combined with the features of the multi-channel data acquisition device in Example 1 of the present application, which will not be repeated here.

[0118] What is disclosed above is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or modifications within the technical scope disclosed in the present invention, which should be covered within the protection scope of the present invention.

Claims

1. A multi-channel data acquisition device, comprising M analog acquisition channels, N AD chips, FPGA, clock module and DDR; m analog acquisition channels correspond to one AD chip, 1≤m<M, N≤M; the output end of each analog acquisition channel is connected to the input end of the corresponding AD chip, the output end of each AD chip is connected to the FPGA, and the clock module and DDR are connected to the FPGA; characterized in that: Each of the analog acquisition channels is used to convert a single-ended analog signal into a differential analog signal; Each of the AD chips is used to convert the differential analog signal into a digital signal; The FPGA is used to synchronously capture the digital signals output by multiple AD chips; perform time-frequency conversion on each of the digital signals to obtain a corresponding frequency domain signal; and perform filtering processing on each of the frequency domain signals; Store and upload the filtered signal; The clock module is used to provide a reference clock for the entire device; the DDR is used to cache data processed by the FPGA; The FPGA is used to filter each of the frequency domain signals using a filter; when designing the filter, an optimization algorithm is used to optimize the actual frequency response of the filter, and the frequency domain signal and its weight coefficient and the penalty factor of the number of filter sampling points are added to the optimization function; wherein the expression of the optimization function is: ； ； in, represents the minimum mean square error, represents the weight coefficient, represents the actual frequency response of the filter, Indicates frequency, represents the ideal frequency response, represents the frequency domain signal, represents the penalty factor, represents the number of filter sampling points, represents the cutoff frequency; BW represents the signal bandwidth.

2. The multi-channel data acquisition device according to claim 1, characterized in that: Each of the analog acquisition channels includes an LC filter, an ESD protection circuit, a single-ended to differential circuit, and a filter circuit which are connected in sequence.

3. The multi-channel data acquisition device according to claim 2, characterized in that: The single-ended to differential circuit adopts a balun module.

4. The multi-channel data acquisition device according to claim 1, characterized in that: A first isolation wall is provided between two adjacent analog acquisition channels; the m analog acquisition channels and their corresponding AD chips are located in the same isolation cavity; and a second isolation wall is provided between the N AD chips and the FPGA.

5. The multi-channel data acquisition device according to any one of claims 1 to 4, characterized in that: The filter is a FIR filter, and the design process of the FIR filter includes: The frequency response function of the FIR filter is constructed, and its specific expression is: ； Where k represents the sampling point number, represents the time domain impulse response function of the FIR filter; Constructing an optimization function according to the frequency response function of the FIR filter; An optimization algorithm is used to solve the optimization function to obtain an optimal actual frequency response of the filter, and then filtering is performed according to the optimal actual frequency response of the filter.

6. A radar system, characterized in that: The radar system comprises a multi-channel data acquisition device as described in any one of claims 1 to 5.

7. A multi-channel data acquisition method, characterized in that: The collection method comprises: Convert the single-ended analog signal input to each analog acquisition channel into a differential analog signal; converting each of the differential analog signals into a digital signal; Synchronously capture all digital signals, and perform time-frequency conversion on each of the digital signals to obtain corresponding frequency domain signals; Performing filtering processing on each of the frequency domain signals; Store and upload the filtered signal; Wherein, a filter is used to filter each of the frequency domain signals; when designing the filter, an optimization algorithm is used to optimize the actual frequency response of the filter, and the frequency domain signal and its weight coefficient and the penalty factor of the number of filter sampling points are added to the optimization function; wherein the expression of the optimization function is: ； ； in, represents the minimum mean square error, represents the weight coefficient, represents the actual frequency response of the filter, Indicates frequency, represents the ideal frequency response, represents the frequency domain signal, represents the penalty factor, represents the number of filter sampling points, represents the cutoff frequency; BW represents the signal bandwidth.

8. The multi-channel data acquisition method according to claim 7, characterized in that: Before data collection, the collection method also includes multi-channel synchronous debugging, specifically including: Inputting the first test data into each analog acquisition channel, and converting the input first test data into first differential test data through each analog acquisition channel; Determine a differential symbol according to each of the first differential test data, and then determine a differential symbol change position; Determine the zero crossing point of each first differential test data at the same clock rising edge according to the differential sign change position of each first differential test data; Determine whether the data center points of each analog acquisition channel are aligned according to the zero crossing point of each first differential test data; if yes, determine the data center points of each analog acquisition channel; if not, adjust the time delay of each analog acquisition channel to align the data center points of each analog acquisition channel; Inputting the second test data into each analog acquisition channel, and converting the input second test data into second differential test data through each analog acquisition channel; Reading the digital data result of each second differential test data; According to the digital data results, it is determined whether the data of each analog acquisition channel is aligned. If so, each analog acquisition channel realizes clock synchronization; if not, the delay of each analog acquisition channel is adjusted in bytes to align the data of each analog acquisition channel.

9. The multi-channel data acquisition method according to claim 7, characterized in that: A radix-4 FFT algorithm is used to perform time-frequency conversion on each of the digital signals.

10. The multi-channel data acquisition method according to any one of claims 7 to 9, characterized in that: The filter is a FIR filter, and the design process of the FIR filter includes: The frequency response function of the FIR filter is constructed, and its specific expression is: ； Where k represents the sampling point number, represents the time domain impulse response function of the FIR filter; Constructing an optimization function according to the frequency response function of the FIR filter; An optimization algorithm is used to solve the optimization function to obtain an optimal actual frequency response of the filter, and then filtering is performed according to the optimal actual frequency response of the filter.

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