Memory controller and data input / output method thereof

Abstract

The invention relates to a memory controller and a data input / output method thereof. The memory controller may include: a shared memory configured to store data; a hardware group configured to generate entry data including result data of an operation corresponding to the command, and output an interrupt signal generated in response to storage of the entry data; and a processor group configured to receive the entry data from the shared memory, where the processor group includes: an interface converter configured to manage first index information of the entry data in response to the interrupt signal, and generate a first address of the entry data based on the first index information; and a data transmitter configured to receive entry data through a first interface using a data input / output scheme set by firmware based on the first address, and transmit the received entry data to the processor through a second interface using a fixed data input / output scheme.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0118233, filed on September 6, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a memory controller, and more particularly, to a memory controller and a data input / output method thereof. Background Art

[0004] A memory system is a device that stores data according to a request from a host device such as a computer or a smart phone. The memory device may include a memory device that stores data and a memory controller that controls the memory device. The memory device may be a volatile memory device or a nonvolatile memory device.

[0005] A volatile memory device is a memory device that stores data only when power is supplied and loses the stored data when power supply is interrupted. The volatile memory device may be a static random access memory (SRAM), a dynamic random access memory (DRAM), or the like.

[0006] A nonvolatile memory device is a memory device that retains stored data even when power supply is interrupted. A nonvolatile memory device may be a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, or the like.

[0007] Data stored in the memory device can be transferred to and processed by the core unit. The core unit can input and output data through the interface. The data input / output performance may vary depending on the interface. In order to meet the required data input / output performance, it may be necessary to use a suitable interface. Summary of the invention

[0008] Various embodiments of the present disclosure relate to a memory controller having improved data input / output performance, and a method of transmitting data to a processor through a plurality of interfaces.

[0009] An embodiment of the present disclosure may provide a memory controller. The memory controller may include: a shared memory configured to temporarily store data; a hardware group configured to generate entry data including result data of an operation corresponding to a received command, and output an interrupt signal generated in response to the entry data being stored in the shared memory; and a processor group configured to receive the entry data from the shared memory, wherein the processor group includes: an interface converter configured to manage first index information of the entry data stored in the shared memory in response to the interrupt signal, and generate a first address of the entry data based on the first index information; and a data transmitter configured to receive the entry data through a first interface based on the first address, and transmit the received entry data to the processor through a second interface, wherein the first interface uses a data input / output scheme set by firmware, and the second interface uses a fixed data input / output scheme.

[0010] Embodiments of the present disclosure may provide a method for operating a memory controller. The method may include: storing entry data including result data of an operation corresponding to a command in a shared memory; generating an interrupt signal in response to the storage of the entry data; generating a first address indicating a location where the entry data is stored in the shared memory based on first index information stored in a processor group in response to the interrupt signal; receiving the entry data based on the first address by using a first interface of a data input / output scheme set by firmware; and transmitting the received entry data to the processor by using a second interface of a fixed data input / output scheme.

[0011] An embodiment of the present disclosure may provide a memory controller. The memory controller may include: a shared memory configured to temporarily store data; a data generation group configured to generate entry data to be transmitted to a processor and store the entry data in the shared memory; and a data processing group configured to receive the entry data stored in the shared memory by using a first interface of a data input / output scheme set by firmware, and transmit the entry data to the processor by using a second interface of a fixed data input / output scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram illustrating a memory device including a memory controller according to an embodiment of the present disclosure.

[0013] Figure 2 is a diagram illustrating a memory controller for transmitting entry data stored in a shared memory to a processor according to an embodiment of the present disclosure.

[0014] Figure 3 is a flowchart for describing a method of transmitting entry data to a processor according to an embodiment of the present disclosure.

[0015] Figure 4 is a diagram illustrating a data processing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification are provided as examples to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in this specification.

[0017] Figure 1 is a diagram illustrating a memory device 50 including a memory controller 100 according to an embodiment of the present disclosure.

[0018] Reference Figure 1 , the storage device 50 may include a memory device 60 and a memory controller 100 that controls the operation of the memory device 60. The storage device 50 may be a device that stores data according to a request of a host device 400 such as a solid state drive (SSD), a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a television (TV), a tablet PC, or an in-vehicle infotainment system.

[0019] The memory device 60 may store data. The memory device 60 may operate in response to the control of the memory controller 100. The memory device 60 may include a memory cell array including a plurality of memory cells storing data.

[0020] The memory device 60 may receive a command and an address from the memory controller 100 and may access a region selected by the address in the memory cell array. The memory device 60 may perform an operation indicated by the command on the region selected by the address.

[0021] The memory controller 100 may control the operation of the memory device 50. The memory controller 100 may control the memory device 60 to perform a program operation, a read operation, or an erase operation according to a request from a host device.

[0022] In an embodiment of the present disclosure, the memory controller 100 may include a data generation group 110, a shared memory 120, and a data processing group 130. The data generation group 110, the shared memory 120, and the data processing group 130 may transmit data through a bus 140. In an embodiment of the present disclosure, the shared memory 120 may be a static random access memory (SRAM). The time required to input / output data in the shared memory 120 may be shorter than the time required for the processor to process the data. The time required to input / output data in the SRAM may be shorter than the time required for the processor to process the data. In an embodiment of the present disclosure, the bus 140 may be a path for transmitting data, and may be a multi-channel bus. In a multi-channel bus, each channel may operate independently, and therefore each data transfer rate may be maintained even when the data transfer rate varies from device to device.

[0023] The data generation group 110 may be a module that generates data to be transmitted to the processor. The module may include a logic circuit that processes commands received from an external system. The power, clock signal, etc. applied to the module may be shared by the components included in the module.

[0024] In an embodiment of the present disclosure, the data generation group 110 may be a hardware group that generates data including a result of performing an operation in response to a received command, or a processor group including another processor. The data generated by the data generation group 110 may be entry data. For example, the data generation group 110 may generate entry data indicating read data or read failure in response to receiving a read command.

[0025] The shared memory 120 may temporarily store data received through the bus. The shared memory 120 may store entry data generated by the data generation group 110 and may transfer the stored entry data to the data processing group 130.

[0026] The data processing group 130 may receive entry data from the shared memory 120 through the first interface. The first interface may be an interface in which a data input / output scheme may be set by firmware. During a boot operation of the storage device 50, the firmware may set the first interface to a data input / output scheme changed by a user.

[0027] The data processing group 130 can transmit the received entry data to the processor through the second interface. The second interface can be an interface using a fixed data input / output scheme and cannot be changed. In an embodiment of the present disclosure, the processor can be included in the data processing group 130 or can be located outside the data processing group 130. The data processing group including the processor can be designated as a processor group.

[0028] In an embodiment of the present disclosure, the data input / output speed of the second interface can be higher than the data input / output speed of the first interface. Since the data input / output scheme of the first interface can be changed, the first interface can realize flexible data processing. The data processing group 130 can transmit the entry data received through the first interface to the processor through the second interface, thereby improving the data input / output speed while flexibly processing the data.

[0029] Figure 2 is a diagram illustrating a memory controller for transmitting entry data stored in a shared memory to a processor according to an embodiment of the present disclosure.

[0030] Reference Figure 2 , it can be shown that the process of transferring the entry data stored in the shared memory 220 to the processor 234. Figure 2 In FIG. 2 , the data generation group is a hardware group 210 that generates data by receiving a command, and the data processing group is a processor group 230 including a processor 234. Figure 2 In the example, the entry data is stored at index #1 in the entry table 221 of the shared memory 220. The maximum index value in the entry table 221 may be 3.

[0031] The hardware group 210 may generate entry data including result data of the operation corresponding to the received command. The hardware group 210 may store the generated entry data in the shared memory 220. In an embodiment of the present disclosure, the process of storing the generated entry data in the shared memory 220 may be regarded as data update.

[0032] The hardware group 210 may include a second memory 211, in which index information and a phase bit indicating a state of entry data are stored. The index information stored in the second memory 211 may be second index information. The second index information may include a header index value and a footer index value. The phase bit stored in the second memory 211 may be a second phase bit.

[0033] The hardware group 210 may manage the second index information of the entry data in response to the generation of the entry data. The hardware group 210 may increase the suffix index value of the second index information by 1 in response to the generation of the entry data. The hardware group 210 may generate a second address indicating a location in the shared memory 220 where the entry data is to be stored based on the suffix index value of the second index information.

[0034] The hardware group 210 may initialize the tail index value and change the second phase bit in response to the tail index value of the second index information exceeding the preset maximum value. The maximum value may be preset according to the size of the queue set by the firmware. For example, a case where entry data is generated when the preset maximum value is 3 and the tail index value of the second index information is 3 is shown. Since the tail index value of the second index information increases by 1 and exceeds the maximum value 3, the hardware group 210 may initialize the tail index value of the second index information to 0 and change the value of the second phase bit. In an embodiment of the present disclosure, the second phase bit may be located at the most significant bit (MSB) of the entry data. The hardware group 210 may store the entry data in the shared memory 220 according to the generated second address. The hardware group 210 may generate an interrupt signal in response to the entry data being stored in the shared memory 220. The hardware group 210 may transmit the generated interrupt signal to the processor group 230. Here, the transmitted interrupt signal may include information indicating that the entry data has been stored in the shared memory 220.

[0035] The processor complex 230 may include an interface converter 231, a data transmitter 232, a first memory 233, and a processor 234. The processor complex 230 may receive entry data from the shared memory 220.

[0036] The interface converter 231 may manage first index information of entry data stored in the shared memory 220 in response to the interrupt signal. The first memory 233 may store the first index information and a first phase bit indicating a state of the first interface.

[0037] The interface converter 231 may increase the tail index value of the first index information by 1. The interface converter 231 may generate a first address of the entry data based on a value of the header index value of the first index information increased by 1. The first address may be transmitted to the data transmitter 232.

[0038] In an embodiment of the present disclosure, the interface converter 231 may increase the tail index value and the header index value of the first index information by 1 each in response to receiving an interrupt signal, or may increase the header index value of the first index information by 1 after transmitting the entry data to the processor 234 .

[0039] The interface converter 231 may update the first phase bit in response to the header index value of the first index information reaching a maximum value. The maximum value may be determined according to the size of the queue set by the firmware. For example, the maximum value may be 3. When the header index value of the first index information is 0, the first phase bit may be kept unchanged. When the header index value of the first index information is 3, the first phase bit may be changed.

[0040] The first address may be an address indicating a location where the entry data is stored in the shared memory 220. The first address and the second address may match each other to indicate the same location in the shared memory 220.

[0041] The data transmitter 232 may receive the entry data based on the first address by using a first interface of a data input / output scheme that may be set by firmware. In an embodiment of the present disclosure, the first interface may be a software queue, which is a flexible interface. The software queue may be an interface that allows a user to set the size of a queue for storing entry data.

[0042] The data transmitter 232 may store the received entry data in a buffer memory. The buffer memory may be an SRAM included in the data transmitter 232. The data transmitter 232 may determine whether the entry data is received based on the first phase bit and the second phase bit included in the entry data. The second phase bit may be set by the hardware group 210.

[0043] In an embodiment of the present disclosure, the data transmitter 232 may store the entry data in the buffer memory in response to the values ​​of the first phase bit and the second phase bit being different from each other. The initial values ​​of the first phase bit and the second phase bit may be set to different values. The first phase bit and the second phase bit may be used to verify the reliability of the entry data.

[0044] The value of the first phase bit and the value of the second phase bit may indicate whether the data has been updated. For example, when the preset maximum value is 3 and the suffix index value of the second index information is 3, the hardware group 210 may change the value of the second phase bit in response to the generation of the entry data. Before the update of the entry data is completed in the state where the value of the second phase bit is changed, the value of the first phase bit may be kept unchanged, and therefore the values ​​of the first phase bit and the second phase bit being equal to each other may indicate that the data update is not completed. Similarly, the value of the first phase bit and the value of the second phase bit being different from each other may indicate that the data update is completed.

[0045] After the hardware group 210 causes an interrupt, the value of the first phase bit and the value of the second phase bit being equal to each other for a certain period of time or longer may indicate a data transmission error. The data transmission error may mean that the entry data is not stored in the shared memory 220 until a certain time has passed after the entry data is generated.

[0046] The data transmitter 232 can transmit the received entry data to the processor through a second interface using a fixed data input / output scheme. In an embodiment of the present disclosure, the second interface can be a first-in first-out (FIFO) (or first-in first-out) interface, which is a static interface. The FIFO interface can be an interface connected in an end-to-end manner, where the transmitting end and the receiving end are directly connected to each other. The data transmitter 232 can be directly connected to the processor 234 to send / receive data. Since the second interface does not manage the address of the data, the second interface can perform data input / output operations at a higher speed than the speed of the first interface.

[0047] The data transmitter 232 may output a result signal indicating the result of transmitting the entry data through the second interface to the interface converter 231. The interface converter 231 may update the tail index value of the first index information and the header index value of the second index information based on the received result signal. The interface converter 231 may increase the tail index value of the first index information and the header index value of the second index information by 1 in response to the entry data being transmitted to the processor 234. In an embodiment of the present disclosure, the interface converter 231 may increase the header index values ​​of the first index information and the second index information by 1 based on increasing only the tail index value of the first index information in response to receiving an interrupt signal.

[0048] exist Figure 2 , the header index value and the footer index value of the first index information are 0, the header index value and the footer index value of the second index information are 0, the value of the first phase bit is 0, and the value of the second phase bit is 1. It can be explained that in the index table 221 stored in the shared memory 220, data up to index #0 is stored, and the entry data generated by the hardware group 210 is stored at index #1. Figure 2 Table 240 may show an embodiment in which header index values, footer index values, and phase bits stored in the first memory 233 and the second memory 211 are changed according to the transmission of entry data. Table 240 only shows an embodiment in which the index values ​​are changed, and the index values ​​may be changed in various ways.

[0049] The hardware group 210 may increase the suffix index value of the second index information by 1 in response to the generation of the entry data. Since the suffix index value does not exceed the maximum value, the value of the second phase bit may be kept unchanged. The hardware group 210 may calculate the second address based on the base address of the shared memory 220, the offset address of the first interface, the size of the entry data, and the increased suffix index value. In an embodiment of the present disclosure, the second address may be a value obtained by multiplying the size of the entry data by the suffix index value and adding the base address of the shared memory 220, the offset address of the first interface, and the product value.

[0050] The hardware group 210 may store the entry data in the shared memory 220 based on the second address, and may transmit the interrupt signal to the processor group 230. In response to receiving the interrupt signal, the interface converter 231 may increase the header index value of the first index information by 1. That is, in response to the entry data being stored in the shared memory 220, the header index value of the first index information and the footer index value of the second index information may each increase by 1, and the remaining values ​​may remain unchanged.

[0051] The interface converter 231 may generate a first address based on the header index value of the increased first index information. The data transmitter 232 may receive the entry data stored in the shared memory 220 based on the first address. The data transmitter 232 may store the received entry data in the buffer memory. The interface converter 231 may compare the second phase bit included in the entry data with the first phase bit, and the data transmitter 232 may transmit the entry data to the processor 234 through the second interface in response to the values ​​of the second phase bit and the first phase bit being different from each other.

[0052] The data transmitter 232 may check the available space of the second interface based on the size of the entry data stored in the buffer memory. The data transmitter 232 may store the entry data in the available space in response to the size of the available space of the second interface being equal to or greater than the size of the entry data. The entry data stored in the available space may be transmitted to the processor 234.

[0053] The processor 234 may be an operation unit that processes entry data. The processor 234 may include an event table that stores input / output data history. The processor 234 may read entry data received through the event table.

[0054] The data transmitter 232 may generate a result signal indicating a result of transmitting the entry data, and may output the generated result signal to the interface converter 231. The interface converter 231 may increase the tail index value of the first index information and the header index value of the second index information by 1 respectively. When the entry data is generated and transmitted to the processor 234, the header index value and the tail index value of the first index information may each be increased by 1, and the header index value and the tail index value of the second index information may each be increased by 1 compared to the value before the entry data is transmitted. Since the increased index value does not exceed the maximum value, the phase bit may be kept unchanged. The initial values ​​of the first phase bit and the second phase bit may be set to different values.

[0055] In an embodiment of the present disclosure, the hardware group 210 may change the interrupt signal from a low level to a high level in response to the entry data being stored in the shared memory 220, and may maintain the interrupt signal until the hardware group 210 enters an idle state. Because the hardware group 210 has no waiting time for transmitting the interrupt signal, the time required for the hardware group 210 to store the entry data in the shared memory 220 may be shortened. The processor group 230 may periodically check whether the value of the phase bit included in the entry data changes in response to the interrupt signal being maintained at a high level. Even if the interrupt signal becomes a low level, the processor group 230 may receive the entry data from the shared memory 220 in response to the header index value and the footer index value of the first index information being different from each other. Because the header index value of the first index information is changed in response to the entry data being transmitted to the processor, the header index value and the footer index value of the first index information may be equal to each other. The processor group 230 may check the completion of data transmission and terminate the operation in response to the interrupt signal becoming a low level and the header index value and the footer index value of the first index information being equal to each other.

[0056] Figure 3 is a flowchart for describing a method of transmitting entry data to a processor according to an embodiment of the present disclosure.

[0057] Reference Figure 3 , the entry data can be temporarily stored in the shared memory and can be transmitted to the processor through the first interface and the second interface. The first interface has the advantage of high compatibility because the data input / output scheme can be changed, while the second interface has the advantage of high data input / output speed. The present disclosure can transmit the entry data through the first interface and the second interface, thereby improving the data transmission rate while maintaining the data transmission compatibility.

[0058] In operation S310, the hardware group may generate entry data including result data of an operation corresponding to the command. The entry data may refer to data transmitted from the hardware group to the processor through an interface.

[0059] In operation S320, the hardware group may generate a second address indicating a location in the shared memory where the entry data is to be stored based on the second index information stored in the second memory. The hardware group may update the second index information in response to the generation of the entry data. The second address may be generated based on a suffix index value of the updated second index information.

[0060] In operation S330 , the hardware group may store the entry data in the shared memory based on the second address.

[0061] In operation S340, the hardware group may generate an interrupt signal indicating that the entry data has been stored in the shared memory. The hardware group may output the interrupt signal to the processor group in response to the entry data being stored in the shared memory.

[0062] In operation S350, the interface converter may update the first index information in response to receiving the interrupt signal. The interface converter may increase the tail index value of the first index information by 1, and may generate a first address indicating a location in the shared memory where the entry data is stored based on a value that is 1 incremented by the header index value of the first index information. The first address may match the second address to indicate the same location in the shared memory. The interface converter may output the first address to the data transmitter.

[0063] In operation S360, the data transmitter may receive entry data from the shared memory through the first interface based on the first address. The first interface may be an interface in which a data input / output scheme may be set by firmware during a boot operation. The data transmitter may verify the reliability of the received entry data by comparing a second phase bit included in the received entry data with a first phase bit stored in the processor group. The data transmitter may store the received entry data in a buffer memory.

[0064] In an embodiment of the present disclosure, since the initial values ​​of the first phase bit and the second phase bit are set to different values, the fact that the values ​​of the first phase bit and the second phase bit do not remain different may indicate that a data transmission error has occurred. For example, when erroneous entry data is received or when the index information and the phase bit are erroneously updated, the values ​​of the first phase bit and the second phase bit may be equal to each other.

[0065] In operation S370, the data transmitter may transmit the entry data stored in the buffer memory to the processor through the second interface. The data transmitter may check the available space in the second interface before transmitting the entry data. The data transmitter may store the entry data in the available space of the second interface in response to the size of the available space of the second interface being equal to or greater than the size of the entry data. The data transmitter may output a result signal indicating the result of transmitting the entry data to the available space of the second interface to the interface converter.

[0066] In operation S380, the interface converter may additionally update the first index information and the second index information based on the result signal. The interface converter may increase the tail index value of the first index information and the head index value of the second index information by 1 each in response to the entry data being transmitted to the processor.

[0067] Figure 4 2 is a diagram showing a data processing system 2000 according to an embodiment of the present disclosure. Figure 4, the data processing system 2000 may include a host device 2100 and a solid state drive (SSD) 2200 .

[0068] The SSD 2200 may include a controller 2210 , a buffer memory device 2220 , nonvolatile memories 2231 to 223 n , a power supply 2240 , a signal connector 2250 , and a power connector 2260 .

[0069] The buffer memory device 2220 may temporarily store data to be stored in the nonvolatile memories 2231 to 223n. In addition, the buffer memory device 2220 may temporarily store data read from the nonvolatile memories 2231 to 223n. Under the control of the controller 2210, the data temporarily stored in the buffer memory device 2220 may be transmitted to the host device 2100 or the nonvolatile memories 2231 to 223n.

[0070] The nonvolatile memories 2231 to 223n may be used as storage media of the SSD 2200. The nonvolatile memories 2231 to 223n may be connected to the controller 2210 through a plurality of channels CH1 to CHn, respectively. One or more nonvolatile memories may be connected to one channel. The nonvolatile memories connected to one channel may be connected to the same signal bus and the same data bus.

[0071] The controller 2210 may control the operation of the SSD 2200. In an embodiment of the present disclosure, the controller 2210 may transmit entry data including the result of executing a command to the processor. The controller 2210 may generate a first address indicating a location in the shared memory where the entry data is stored based on the index information. The controller 2210 may receive the entry data through a first interface based on the first address, and store the received entry data in a buffer memory, and the data input / output scheme of the first interface may be set by firmware. The controller 2210 may transmit the entry data stored in the buffer memory to the processor through a second interface, and the data input / output scheme of the second interface is preset (i.e., fixed).

[0072] The power supply 2240 may provide the power PWR received through the power connector 2260 to the SSD 2200. The power supply 2240 may include an auxiliary power supply 2241. When a sudden power failure occurs, the auxiliary power supply 2241 may supply power so that the SSD 2200 is normally shut down. The auxiliary power supply 2241 may include a large-capacity capacitor capable of charging the power PWR.

[0073] The controller 2210 may exchange a signal SGL with the host device 2100 through the signal connector 2250. Here, the signal SGL may include a command, an address, data, etc. The signal connector 2250 may be implemented as various types of connectors according to an interface scheme of the host device 2100 and the SSD 2200.

[0074] According to an embodiment of the present disclosure, a memory controller and a data transfer method are provided, which are capable of improving data input / output performance by transferring data through an interface supporting different input / output schemes.

[0075] The scope of the present disclosure is defined by the appended claims rather than the detailed description, and all modifications or changes derived from the meaning and scope of the claims and their equivalents should be interpreted as falling within the scope of the present disclosure. Furthermore, the embodiments may be combined to form additional embodiments.

Claims

1. A memory controller, comprising: Shared memory, temporarily storing data; a hardware group that generates entry data including result data of an operation corresponding to the received command, and outputs an interrupt signal generated in response to the entry data being stored in the shared memory; as well as A processor group receives the entry data from the shared memory, The processor group includes: an interface converter that manages first index information of entry data stored in the shared memory in response to the interrupt signal and generates a first address of the entry data based on the first index information; as well as A data transmitter receives the entry data through a first interface based on the first address and transmits the received entry data to a processor through a second interface, wherein the first interface uses a data input / output scheme set by firmware and the second interface uses a fixed data input / output scheme.

2. The memory controller according to claim 1, wherein: The hardware group manages second index information of the entry data in response to generation of the entry data, and stores the entry data in the shared memory according to a second address generated based on the second index information, and The first address and the second address match each other and are information indicating a location in the shared memory where the entry data is stored.

3. The memory controller according to claim 2, wherein: The interface converter updates a header index value of the first index information and generates the first address based on the header index value.

4. The memory controller according to claim 3, wherein: When the header index value exceeds a maximum value, the interface converter updates a first phase bit indicating a state of the first interface, and The maximum value is determined according to the size of the queue set by the firmware.

5. The memory controller according to claim 4, wherein: The data transmitter determines whether the entry data is received based on the first phase bit and a second phase bit included in the entry data, and The second phase bit is set by the hardware group.

6. The memory controller according to claim 5, wherein: When the values ​​of the first phase bit and the second phase bit are different from each other, the data transmitter stores the entry data in a buffer memory.

7. The memory controller according to claim 5, wherein: The hardware group updates a suffix index value of the second index information, generates a second address based on the suffix index value, and updates the second phase bit when the suffix index value reaches a maximum value.

8. The memory controller according to claim 2, wherein: The data transmitter outputs a result signal indicating a result of transmitting the entry data through the second interface to the interface converter, and The second interface is an interface directly coupling the processor to the data transmitter.

9. The memory controller according to claim 8, wherein: The interface converter updates a tail index value of the first index information and a header index value of the second index information based on the result signal.

10. A method of operating a memory controller, the method comprising: storing in the shared memory entry data including result data of the operation corresponding to the command; generating an interrupt signal in response to storing of the entry data; In response to the interrupt signal, generating a first address indicating a location in the shared memory where the entry data is stored based on first index information stored in the processor group; receiving the entry data through a first interface using a data input / output scheme set by firmware based on the first address; as well as The received entry data is transmitted to the processor through the second interface using a fixed data input / output scheme.

11. The method according to claim 10, wherein: Storing the entry data includes: generating the entry data; In response to the generation of the entry data, updating second index information included in a data generation group that generates the entry data; and A second address matching the first address is generated based on the second index information.

12. The method according to claim 11, wherein: Generating the first address includes: updating the first index information; and A first phase bit indicating a state of the first interface is updated based on the first index information.

13. The method according to claim 12, wherein: Receiving the entry data comprises: comparing the first phase bit with a second phase bit included in the entry data; and In response to determining that the first phase bit is different from the second phase bit, the entry data is stored in a buffer memory.

14. The method according to claim 13, wherein: The entry data received by the transmission includes: checking available space in the second interface based on the size of the entry data stored in the buffer memory; In response to determining that the size of the available space is equal to or greater than the size of the entry data, storing the entry data in the available space; transmitting the entry data stored in the available space to the processor; generating a result signal indicating a result of transferring the entry data in the available space; and The first index information and the second index information are updated based on the result signal.

15. A memory controller comprising: Shared memory, temporarily storing data; a data generation group, generating entry data to be transmitted to the processor, and storing the entry data in the shared memory; A data processing group receives entry data stored in the shared memory through a first interface and transmits the entry data to the processor through a second interface, wherein the first interface uses a data input / output scheme set by firmware and the second interface uses a fixed data input / output scheme.

16. The memory controller according to claim 15, wherein: The size of the queue of the first interface storing the entry data is flexible, and The second interface is connected to the processor in a first-in-first-out (FIFO) manner.

17. The memory controller according to claim 15, wherein: The data processing group includes a first memory storing first index information for generating a first address indicating a location in the shared memory where the entry data is stored, and storing a first phase bit indicating a state of the entry data received through the first interface, and The data generation group includes a second memory, which stores second index information and a second phase bit, wherein the second index information is used to generate a second address indicating a location where the entry data is stored in the shared memory, and the second phase bit indicates a state of the entry data stored in the shared memory.

18. The memory controller according to claim 17, wherein: The data generation group updates the second index information in response to generation of the entry data, generates the second address based on the updated second index information, and outputs an interrupt signal generated in response to storage of the entry data at the second address to the data processing group, and The data processing group updates the first index information in response to receiving the interrupt signal, generates the first address based on the updated first index information, and receives the entry data from the shared memory based on the first address.

19. The memory controller according to claim 17, wherein: The data processing group determines whether the entry data is received based on the first phase bit and the second phase bit.

20. The memory controller according to claim 18, wherein: The data processing group additionally updates the first index information and the second index information based on a result of transmitting the entry data.

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