Compilation system to ensure numerical accuracy for hybrid accelerator cluster computing

Abstract

The present invention discloses a compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing, comprising an operator identifier, a calculation scheduler, a result comparator, a precision controller and a compiler. By strictly following the IEEE 754 standard and accurately scheduling hardware resources, a balance between high precision and high performance of numerical computing is achieved, thereby effectively reducing the accumulation of numerical errors and improving the consistency and reliability of computing results.

Description

Technical Field

[0001] The present invention relates to the field of cluster computing, and in particular to a compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing. Background Art

[0002] With the rapid development of high-performance computing technology, heterogeneous computing architecture has become the current mainstream trend. Hybrid accelerator clusters (such as the combination of CPU and GPU, CPU and FPGA and other hardware accelerators) are widely used in scientific computing, artificial intelligence, engineering simulation and other fields. Their powerful parallel computing capabilities can greatly improve computing efficiency. However, in complex computing tasks, numerical accuracy issues have gradually become an important factor affecting the reliability of hybrid accelerator cluster computing results.

[0003] (1) Precision challenges of floating-point operations

[0004] Floating point numbers are a common data representation method in scientific computing and high-performance computing, following the single-precision (32-bit) and double-precision (64-bit) formats defined by the IEEE 754 standard. However, due to differences in hardware platform support for floating-point operations, numerical errors may gradually accumulate during the calculation process, resulting in inconsistent results. For example, GPU hardware usually has FMA (Fused Multiply-Add) operations, which improves calculation accuracy through a single rounding step, while hardware platforms such as CPUs may not have this function, resulting in further expansion of numerical errors.

[0005] (2) Operation scheduling issues in hybrid accelerated computing

[0006] In a hybrid accelerator cluster, different hardware supports the IEEE 754 standard to different degrees. For example, some hardware may only support single-precision floating-point operations, while some tasks require double-precision operations to ensure numerical accuracy. If the scheduling is unreasonable, tasks may be assigned to inappropriate computing nodes, causing calculation errors and even wrong calculation results.

[0007] (3) Comparison of calculation results and accuracy verification

[0008] In a heterogeneous computing environment, due to the computing characteristics of different hardware, there may be slight differences in the calculation results of hardware accelerators such as CPU and GPU. This difference comes from the different implementations of floating-point operations by hardware, especially in terms of rounding mode, floating-point data format conversion, and operation order. How to effectively compare calculation results and detect and control numerical errors is an important challenge facing current technology.

[0009] (4) Impact of compiler optimization on accuracy

[0010] The compiler's handling of floating-point operations during code generation and optimization affects the final calculation accuracy. For example, the compiler may enable FMA operations by default or adjust the order of operations, thereby changing the rounding process and result accuracy. In addition, different compiler options (such as controlling the precision mode, disabling FMA, etc.) have a direct impact on the balance between calculation performance and numerical accuracy.

[0011] In summary, the existing technology in hybrid accelerator cluster computing generally has problems such as insufficient numerical accuracy, unreasonable operation scheduling, inconsistent calculation results, etc., which seriously affect the reliability of high-performance computing tasks. Therefore, there is an urgent need for a compilation system that can guarantee the numerical accuracy of hybrid accelerator clusters to improve the consistency and reliability of calculation results and meet the actual needs of high-precision computing. Summary of the invention

[0012] In view of the shortcomings of the prior art, the present invention proposes a compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing. By setting functional modules such as operator identifier, operation scheduler, result comparator, precision controller and compiler, and by strictly following the IEEE 754 standard and accurately scheduling hardware resources, a balance between high precision and high performance of numerical calculation is achieved, thereby effectively reducing the accumulation of numerical errors and improving the consistency and reliability of calculation results.

[0013] The purpose of the present invention is achieved through the following technical solutions:

[0014] A compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing, including an operator identifier, a calculation scheduler, a result comparator, a precision controller and a compiler;

[0015] The operator identifier is used to extract all floating-point operators from the input computing task, determine and mark the computing accuracy of each operator through static analysis technology; and check whether each floating-point operator meets the accuracy requirements and computing rules specified in the standard according to the IEEE 754 standard, and feed back the identification results to the computing scheduler;

[0016] The operation scheduler schedules the computing task to the most matching computing node for execution according to the accuracy requirement of the computing task identified by the operator identifier, as well as the hardware accuracy, computing power, and load of the computing node, and schedules the computing task to the CPU for synchronous execution once; the operation scheduler is also used to receive the calculation result error of the same computing task on the computing node and the CPU fed back by the result comparator, and decide whether to reschedule the computing task or adjust the calculation accuracy;

[0017] The result comparator compares the calculation results of the computing node and the CPU for the same computing task, and evaluates the size of the error according to the ULP error value in the IEEE 754 standard; if the error exceeds the specified range, it is considered that there is a significant difference in the calculation result, and the error is fed back to the operation scheduler; at the same time, the error result of each comparison is recorded for subsequent analysis and optimization reference;

[0018] The precision controller is used to declare single-precision point and double-precision point data types in C language, and defaults the rounding mode in the single-precision point and double-precision point data types to the nearest even rounding mode; the precision controller also defines a fused multiplication-addition operation for a computing task including a multiplication-addition operation;

[0019] The functions related to precision control in the compiler are implemented based on the IEEE 754 standard. The compiler provides FMA operation options for users, and enables or disables compiler flags related to IEEE 754 operations according to the precision requirements of the operation operators.

[0020] Furthermore, the error result of each comparison of the same computing task recorded by the result comparator specifically includes the error range, computing node and task type.

[0021] Furthermore, the matching principle when the operation scheduler schedules the computing task to the most matching computing node for execution is: first select the computing node that can meet the accuracy required by the computing task, and then select the node with stronger computing power and lower load among the computing nodes that meet the accuracy requirements.

[0022] Furthermore, the operation scheduler receives the same computing task fed back by the result comparator and calculates the result error on the computing node and the CPU. When the error exceeds a predetermined ULP threshold, the computing task is rescheduled; when the error is within a predetermined ULP threshold but still exceeds the accuracy requirement, the calculation accuracy is adjusted.

[0023] Furthermore, the hybrid acceleration card includes a GPU, an NPU and a CPU.

[0024] Furthermore, the floating-point operation operators include addition, subtraction, multiplication, division, square root and multiply-add operations.

[0025] Furthermore, the precision controller is also configured to automatically select a suitable rounding mode according to the precision requirements of the computing task, and dynamically check the calculation precision of each stage during the task execution process to ensure that the result of each step meets the set precision requirements.

[0026] Furthermore, the compiler is also configured to optimize the generation of floating-point operation instructions according to the performance requirements of the computing task, so as to improve the computing efficiency while ensuring the accuracy.

[0027] Furthermore, the operation scheduler is also configured to dynamically adjust the task allocation strategy according to the real-time computing node load conditions to balance the system load and improve the overall computing efficiency.

[0028] Furthermore, the result comparator is also used to generate a detailed error report, record the error range, computing node information and task type of each comparison, and provide an error trend analysis function to support subsequent system optimization.

[0029] The beneficial effects of the present invention are as follows:

[0030] (1) The present invention can effectively reduce the numerical errors in the calculation of the hybrid accelerator card, ensure that the calculation results comply with the IEEE754 standard, and guarantee the accuracy and consistency of the numerical calculation.

[0031] (2) The present invention dynamically allocates tasks to hardware nodes that support high-precision computing through a computing scheduler, thereby solving the problem of unreasonable task scheduling and avoiding the loss of precision caused by hardware differences.

[0032] (3) The present invention realizes real-time comparison of CPU and accelerator card calculation results through a result comparator, timely discovers numerical errors and corrects them, and effectively ensures the reliability of high-performance computing tasks.

[0033] (4) The present invention provides FMA enable and disable options through the compiler, so that users can flexibly choose between calculation accuracy and performance according to their needs, adapting to the accuracy requirements of different application scenarios.

[0034] (5) The present invention can be widely used in fields that require high numerical accuracy, such as scientific computing, high-performance computing, machine learning, and engineering simulation, and has a wide range of applications and high adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the structure of a compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing provided by an embodiment of the present invention.

[0036] Figure 2 A schematic diagram of an operator identification process performed by an operator identifier provided by an embodiment of the present invention.

[0037] Figure 3 A schematic diagram of a process of task scheduling by a computing scheduler provided in an embodiment of the present invention.

[0038] Figure 4 A schematic diagram of a process of comparing results performed by a result comparator provided in an embodiment of the present invention.

[0039] Figure 5A schematic diagram of a process of precision control performed by a precision controller provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The present invention will be described in detail below based on the accompanying drawings and preferred embodiments, and the purpose and effects of the present invention will become more clear. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0041] like Figure 1 As shown, the compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing provided by the embodiment of the present invention includes an operator identifier, an operation scheduler, a result comparator, a precision controller and a compiler. Each module optimizes the execution efficiency of the task and the utilization of computing resources while ensuring numerical accuracy.

[0042] 1. Operator Identifier

[0043] The main function of the operator identifier is to identify and analyze the floating-point operators in the calculation task and determine whether these floating-point operators meet the requirements of the IEEE 754 standard. Figure 2 The specific implementation steps of the operator identifier are as follows:

[0044] (1) Operator extraction and classification: The operator identifier first extracts all floating-point operators from the input computing task. These operators include but are not limited to addition, subtraction, multiplication, division, square root, and more complex multiplication-addition (FMA) operations.

[0045] (2) Precision judgment: The operator identifier uses static analysis technology to judge the precision requirements of the operator. If the operator belongs to single-precision operation (i.e. float type), the corresponding precision will be marked; if it belongs to double-precision operation (i.e. double type), it will also be marked and recorded.

[0046] (3) Standard compliance verification: The operator identifier checks whether each floating-point operator meets the accuracy requirements and calculation rules specified in the IEEE 754 standard. For example, if an operator uses an operation form or data format that is not supported by the IEEE 754 standard (such as not properly rounding floating-point numbers), the operator identifier will record and mark it as an operator that does not meet the standard.

[0047] (4) Output and feedback: After identification and judgment are completed, the operator identifier feeds back the results to the operation scheduler for the reasonable scheduling of subsequent tasks.

[0048] 2. Computation Scheduler

[0049] The task of the operation scheduler is to schedule the computing tasks to the most matching computing nodes for execution according to the hardware accuracy, computing power, load of the computing nodes, and the accuracy requirements of the computing tasks output by the operator identifier, such as Figure 3 The specific implementation steps are as follows:

[0050] (1) Task allocation strategy: The computation scheduler selects appropriate hardware to perform computations based on the accuracy requirements of the computational tasks and the computing power of the hardware nodes. For example, if a task requires double-precision floating-point operations and the GPU does not support it, the task will be assigned to the CPU node; if the GPU supports double precision, the task will be scheduled to the GPU first.

[0051] (2) Load balancing and resource optimization: In hybrid accelerator cluster computing, the computation scheduler must not only allocate tasks based on accuracy requirements, but also consider the load of hardware resources. For example, when multiple tasks can be executed in parallel, the computation scheduler is also configured to dynamically adjust the task allocation strategy based on the real-time computing node load to balance the system load and improve the overall computing efficiency.

[0052] (3) Task scheduling and precision matching: The operation scheduler matches the appropriate hardware precision based on the output of the operator identifier. For example, when it is found that the floating-point operation operator in the computing task belongs to single precision, the scheduler can assign the task to a GPU or accelerator card that only supports single-precision floating-point operations; when higher precision is required in the task, hardware that supports double precision can be selected. The operation scheduler is also used to calculate the result error of the same computing task on the computing node and CPU for the feedback from the result comparator, and decide whether to reschedule the computing task or adjust the computing precision: when the error exceeds the predetermined ULP threshold, the computing task is rescheduled; when the error is within the predetermined ULP threshold but still exceeds the precision requirement, the computing precision is adjusted.

[0053] (4) Scheduling result output: The operation scheduler finally outputs the scheduling result to the matching computing node to ensure that the task is executed on the appropriate computing node. The specific matching principle is: give priority to computing nodes that can meet the accuracy required by the computing task, and select nodes with stronger computing power and lower load among the computing nodes that meet the accuracy requirements.

[0054] 3. Result Comparator

[0055] The result comparator is an important module to ensure the calculation accuracy. It is responsible for comparing the calculation results of the CPU and hardware acceleration card (such as GPU, FPGA, etc.) for the same calculation task and detecting the numerical errors in the calculation results. Figure 4 As shown, the specific implementation steps are as follows:

[0056] (1) Receiving calculation results: The result comparator receives the calculation results of the same calculation task from the CPU and the accelerator card. These results are usually generated by different hardware executing the same task under the same input conditions.

[0057] (2) Error detection and evaluation: The result comparator compares the differences in the calculation results generated after different hardware performs the same task, and evaluates the size of the error based on the ULP error value (unit last position) in the IEEE 754 standard. If the error exceeds the set range, it is considered that there is a significant difference in the calculation result.

[0058] (3) Error feedback and adjustment: If the error of the calculation result exceeds the set range, the result comparator will feed back the result to the operation scheduler so that the operation scheduler can make further adjustments.

[0059] (4) Error reporting and recording: The result comparator also records the error results of each comparison, including error range, computing nodes, task type and other information, for reference in subsequent analysis and optimization.

[0060] 4. Precision controller

[0061] The precision controller uses the unified data format defined by the IEEE 754 standard to ensure the consistency of precision control during task execution, such as Figure 5 As shown in the figure, the functions of the precision controller include:

[0062] (1) Unified data format: The precision controller uses the data format defined by the IEEE 754 standard for unified management. During the entire calculation process, the precision controller uses the float (single precision) and double (double precision) data types in the C language to declare variables and performs corresponding precision control according to the precision requirements of different tasks.

[0063] (2) Rounding mode selection: The precision controller selects the appropriate rounding mode to control the floating-point precision during the calculation process according to the precision requirements of the calculation task. The default is to use the nearest even rounding mode (Round to Nearest Even) of the IEEE 754 standard, which improves the calculation precision through a single rounding step during the floating-point operation.

[0064] (3) Enabling FMA operations: For computing tasks that include multiply-add operations, the precision controller enables hardware-supported Fused Multiply-Add (FMA) operations. FMA operations allow multiplication and addition to be completed in a single operation, thereby reducing rounding errors and being more accurate than traditional step-by-step calculations.

[0065] (4) Accuracy verification and correction: The accuracy controller dynamically checks the calculation accuracy of each stage during the task execution to ensure that the results of each step meet the set accuracy requirements. If an accuracy problem is found, it will be fed back to the operation scheduler, which will correct it or reschedule the calculation task.

[0066] 5. Compiler

[0067] The compiler is an important optimization tool of the present invention. It optimizes the execution efficiency of tasks through precision control options and ensures high-precision execution of floating-point operations. The specific implementation steps are as follows:

[0068] (1) The compiler provides users with a range of options to control precision, allowing users to adjust according to specific needs to find the best balance between performance and precision. The following are some key options and their functions:

[0069] Enable or disable FMA operation: Enable FMA to reduce intermediate rounding errors and improve calculation accuracy by fusing multiplication and addition operations. However, this may affect performance on some hardware; Disable FMA. In the case of performance priority, you can choose to disable FMA and decompose it into separate multiplication and addition operations to improve execution speed.

[0070] Floating point precision setting: Users can choose single precision (32-bit), double precision (64-bit), or higher precision to meet different precision requirements. Higher precision consumes more resources but provides better accuracy.

[0071] Rounding mode selection: Provides multiple rounding modes, such as round to nearest value, round to zero, round up, and round down, to meet different computing needs, especially in iterative calculations.

[0072] Optimization level control: Different optimization levels may affect the calculation order and results. Higher optimization levels may introduce approximations or reorder operations, thus affecting accuracy. Users can select the appropriate optimization level according to their needs.

[0073] Enabling and disabling specific optimizations: Users can control whether to enable certain optimizations, such as loop unrolling or strength reduction, which may affect the accuracy of calculations.

[0074] Precision model specification: Users can choose a strict IEEE 754 compliance mode to ensure consistency, or choose to relax compliance to allow more aggressive optimizations.

[0075] Floating-point exception handling: Provides options to enable or disable the capture of floating-point exceptions (such as overflow, underflow, etc.), affecting the precision error handling method at runtime.

[0076] SIMD instruction usage control: Users can control the extent to which SIMD instructions are used, which can speed up computations but may require data alignment and affect precision.

[0077] These options can be set via compiler flags or configuration files. For example, disabling FMA operations may be achieved through a specific compiler flag. Users should choose the appropriate options based on their specific application needs to achieve the best balance between performance and accuracy.

[0078] When choosing these options, the user needs to consider how they affect each other. For example, choosing a higher precision setting may override some optimizations that assume lower precision. Also, disabling FMA may result in more operations on some hardware, thus affecting performance, but may be more flexible in terms of compatibility.

[0079] In short, these options provided by the compiler provide users with great flexibility, enabling them to adjust the compilation strategy according to specific needs in different application scenarios to obtain the best performance and precision.

[0080] (2) Operation order optimization: The compiler reduces redundant calculations and multiple rounding operations by optimizing the order of floating-point operations and instruction generation, thereby further improving the calculation accuracy. During the compilation process, optimizing the order of floating-point operations and instruction generation is a key step to improve the calculation accuracy. The following is a specific method used in the present invention:

[0081] ①Algebraic transformation:

[0082] The compiler minimizes rounding errors by reorganizing mathematical expressions. For example, it uses associativity to group operations together to reduce the accumulation of errors. This transformation ensures that the error of intermediate results is reduced without changing the result of the calculation.

[0083] ② Operational fusion:

[0084] The compiler implements a fused multiply-add (FMA) operation that combines multiplication and addition into a single step, thereby reducing rounding steps and errors. This optimization is particularly effective on hardware that supports FMA instructions.

[0085] ③Instruction Scheduling:

[0086] The compiler arranges the execution order of instructions to fully utilize the processor's pipeline and parallel execution capabilities. By optimizing the instruction sequence, it ensures that the operation maintains high precision while improving execution efficiency.

[0087] ④Redundant calculation elimination:

[0088] The compiler identifies and eliminates redundant computations, and reduces the number of rounding operations by reusing intermediate results. For example, if a subexpression is evaluated multiple times with the same input, the compiler optimizes it to evaluate it only once and reuse the result.

[0089] ⑤Hardware perception:

[0090] The compiler generates instructions based on the specific capabilities of the target hardware, ensuring optimal accuracy and performance on different hardware platforms. This includes taking advantage of the hardware's floating point unit features and instruction set extensions.

[0091] ⑥Compiler options:

[0092] Providing user-controllable compiler flags and options allows users to make trade-offs between performance and accuracy, and enable or disable certain optimizations based on specific needs.

[0093] These optimizations are implemented during the optimization phase of the compiler and work in conjunction with other optimization steps to ensure that the correctness and performance of the code are maintained while improving accuracy. The compiler uses verification mechanisms to ensure that the optimized code is consistent with the original code in numerical results or within an acceptable error range.

[0094] Through the above method, the compiler significantly improves the accuracy of floating-point calculations, reduces rounding errors, and thus improves the reliability of overall calculations.

[0095] (3) Compilation result feedback: The compiler will provide optimization suggestions based on the actual running results of the task, such as adjusting the use of FMA operations or adjusting the calculation accuracy based on the error of the calculation results.

[0096] ①The error exceeds the predetermined range

[0097] Example: In a computing task, the result comparator detects that the error between the computing node and the CPU exceeds a predetermined range.

[0098] Optimization suggestions: The compiler may suggest disabling FMA operations to reduce errors, although this may affect performance, or suggest using higher precision data types to improve the accuracy of the results.

[0099] ②The error is within the acceptable range but the performance is low

[0100] Example: The error of the calculation result is within an acceptable range, but the task execution performance is low.

[0101] Optimization suggestions: The compiler can suggest enabling more FMA operations, or adjusting rounding modes, to improve performance while maintaining precision.

[0102] ③The order of operations leads to error accumulation

[0103] Example: Due to the problem of operation order, the errors of intermediate results accumulate too large.

[0104] Optimization suggestions: The compiler can suggest rearranging the order of operations or using higher precision data types in key steps to reduce errors.

[0105] ④Error accumulation in the cycle

[0106] Example: In certain loops, repeated floating-point operations cause errors to accumulate.

[0107] Optimization suggestions: The compiler can suggest combining these operations or using error compensation techniques to reduce the accumulated error.

[0108] ⑤Task scheduling leads to inconsistent accuracy

[0109] Example: In parallel computing, a task is assigned to multiple computing nodes for execution, but due to inconsistent computing accuracy between nodes, there is a large error in the final result.

[0110] Optimization suggestions: The compiler can suggest rescheduling tasks so that tasks with the same precision requirements are assigned to computing nodes with the same precision, thereby reducing errors.

[0111] ⑥ Error under specific input conditions

[0112] Example: A computing task is prone to large errors under certain specific inputs.

[0113] Optimization suggestions: The compiler can suggest adjusting compilation options for these input conditions, such as enabling stricter precision control or choosing a different floating-point operation mode.

[0114] (4) Support for multi-platform compilation: The compiler of the present invention supports compilation for multiple platforms (such as x86, ARM, GPU, etc.) and can generate efficient code suitable for the platform according to the hardware characteristics of different platforms.

[0115] The compiler supports multi-platform compilation, including x86, ARM, and GPU, etc., and generates efficient code by identifying and utilizing the hardware characteristics of each platform. The following are detailed supplements and improvements:

[0116] ① Platform identification and feature utilization:

[0117] x86 platform: The compiler uses the AVX-512 instruction set to optimize floating-point operations and improve parallel processing capabilities.

[0118] ARM platform: Use NEON instructions to accelerate vector operations and adapt to the pipeline characteristics of the ARM architecture.

[0119] GPU platform: Generate CUDA or OpenCL code to fully utilize the parallel computing resources of GPU.

[0120] ②Memory hierarchy optimization:

[0121] x86 platform: Optimize cache line usage and reduce cache misses.

[0122] GPU platform: Efficiently manage global memory and shared memory to reduce memory access latency.

[0123] ③Numerical accuracy consistency:

[0124] Ensuring compliance with the IEEE 754 standard on different platforms may require adjusting rounding modes or the way floating-point exceptions are handled.

[0125] ④Platform specific optimization options:

[0126] Provides options for users to adjust the optimization strategy based on application requirements, such as selecting a higher optimization level in performance-critical scenarios or a conservative strategy in accuracy-critical scenarios.

[0127] ⑤ Platform difference processing:

[0128] Handle instruction set differences and register number differences to ensure that the code runs correctly on each platform.

[0129] ⑥Testing and verification mechanism:

[0130] Ensure that the generated code is not only efficient on all platforms, but also produces consistent results and meets expectations.

[0131] Through the above measures, the compiler can generate efficient and consistent code on multiple platforms to meet the needs of different applications.

[0132] Those skilled in the art can understand that the above are only preferred examples of the invention and are not intended to limit the invention. Although the invention is described in detail with reference to the above examples, those skilled in the art can still modify the technical solutions recorded in the above examples or replace some of the technical features therein with equivalents. Any modification, equivalent replacement, etc. made within the spirit and principle of the invention shall be included in the protection scope of the invention.

Claims

1. A compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing, characterized in that: It includes operator identifier, operation scheduler, result comparator, precision controller and compiler; The operator identifier is used to extract all floating-point operators from the input computing task, determine and mark the computing accuracy of each operator through static analysis technology; and check whether each floating-point operator meets the accuracy requirements and computing rules specified in the standard according to the IEEE 754 standard, and feed back the identification results to the computing scheduler; The operation scheduler schedules the computing task to the most matching computing node for execution according to the accuracy requirement of the computing task identified by the operator identifier, as well as the hardware accuracy, computing power, and load of the computing node, and schedules the computing task to the CPU for synchronous execution once; the operation scheduler is also used to receive the calculation result error of the same computing task on the computing node and the CPU fed back by the result comparator, and decide whether to reschedule the computing task or adjust the calculation accuracy; The result comparator compares the calculation results of the computing node and the CPU for the same computing task, and evaluates the size of the error according to the ULP error value in the IEEE 754 standard; if the error exceeds the specified range, it is considered that there is a significant difference in the calculation result, and the error is fed back to the operation scheduler; at the same time, the error result of each comparison is recorded for subsequent analysis and optimization reference; The precision controller is used to declare single-precision point and double-precision point data types in C language, and defaults the rounding mode in the single-precision point and double-precision point data types to the nearest even rounding mode; the precision controller also defines a fused multiplication-addition operation for a computing task including a multiplication-addition operation; The functions related to precision control in the compiler are implemented based on the IEEE 754 standard. The compiler provides FMA operation options for users, and enables or disables compiler flags related to IEEE 754 operations according to the precision requirements of the operation operators.

2. The compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing according to claim 1, characterized in that: The error result of each comparison of the same computing task recorded by the result comparator specifically includes the error range, computing node and task type.

3. The compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing according to claim 1, characterized in that: The matching principle of the operation scheduler when scheduling the computing task to the most matching computing node for execution is: first select the computing node that can meet the accuracy required by the computing task, and then select the node with stronger computing power and lower load among the computing nodes that meet the accuracy requirements.

4. The compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing according to claim 1, characterized in that: The operation scheduler receives the same computing task fed back by the result comparator and calculates the result error on the computing node and the CPU. When the error exceeds a predetermined ULP threshold, the computing task is rescheduled; when the error is within a predetermined ULP threshold but still exceeds the accuracy requirement, the calculation accuracy is adjusted.

5. The compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing according to claim 1, characterized in that: The hybrid acceleration card includes a GPU, an NPU and a CPU.

6. The compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing according to claim 1, characterized in that: The floating point operators include addition, subtraction, multiplication, division, square root and multiply-add operations.

7. The compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing according to claim 1, characterized in that: The precision controller is also configured to automatically select an appropriate rounding mode according to the precision requirements of the computing task, and dynamically check the calculation precision of each stage during the task execution to ensure that the result of each step meets the set precision requirements.

8. The compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing according to claim 1, characterized in that: The compiler is also configured to optimize the generation of floating-point operation instructions according to the performance requirements of the computing task, so as to improve the computing efficiency while ensuring the accuracy.

9. The compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing according to claim 1, characterized in that: The operation scheduler is also configured to dynamically adjust the task allocation strategy according to the real-time computing node load conditions to balance the system load and improve the overall computing efficiency.

10. The compilation system for ensuring numerical accuracy for hybrid accelerator card cluster computing according to claim 1, characterized in that: The result comparator is also used to generate a detailed error report, record the error range, computing node information and task type of each comparison, and provide an error trend analysis function to support subsequent system optimization.

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