Port management method based on connector and related equipment

Abstract

The port management method based on the connector comprises the steps that component access is identified, a transmission interface is provided through the connector, a component requirement is obtained, the component requirement is used for indicating the attribute of a port needed by the component, and the port mode of the port connected with the connector is matched with the component according to the component requirement. Therefore, the defects that the port signal definition of the same connector cannot be adaptively and flexibly configured, the connector can only be suitable for one high-speed signal type and supports the same type of components are overcome, the flexibility of the port is effectively improved, the purpose that the same port supports more components is achieved, and the configuration flexibility of the whole machine is improved.

Description

[0001] This application is a divisional application. The application number of the original application is 202210188357.1, and the original application date is February 28, 2022. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a connector-based port management method, a base board, a main board, and a computing device. Background Art

[0003] Since the 1980s, Microsoft and Intel have formed the Wintel Alliance to promote the development of the personal computer (PC) industry. The two companies have worked closely in the PC industry to drive faster development of the computing industry and gradually affect other computing devices such as servers. Computing devices such as servers have many application scenarios, many configuration types, and relatively high reliability requirements. At the same time, computing devices such as servers have a huge commercial volume and are the focus of open industry ecosystem construction.

[0004] The technical threshold for the development of traditional server motherboards is high. In addition to the central processing unit (CPU), it also includes bus fan-out, power fan-out, maintenance management and other functions. The CPU-related circuits on these motherboards are all from the reference design provided by the CPU manufacturer, and the reference designs provided by different CPU manufacturers are completely different, which requires a lot of resources and time to develop and design the motherboard. In order to meet the needs of rapid updates and replacements of computing products such as servers, whole machine manufacturers need to invest more energy in differentiated innovation, but they can often only focus on low-level hardware specification competition. This can neither meet the diverse scenarios and computing power needs of customers, nor force whole machine manufacturers to fall into inefficient homogeneous competition. With the trend of computing power diversity, more processor manufacturers have emerged and launched more processor products with different architectures, and the functions of various processors have been increasingly enhanced. For example, the ports of some processors can be flexibly configured with multiple protocols. Specifically, the processor port can support high-speed serial computer expansion bus standard peripheral component interconnect express (PCIe), serial attached small computer system interface (Serial Attached Small Computer System Interface, SAS), serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) or Ethernet (Ethernet, ETH) and other protocol types.

[0005] In order to meet the application scenarios, configuration types or reliability requirements of computing devices such as servers, the motherboards of computing devices such as servers can also be connected to components. The motherboard and components can be interconnected through connectors and cables. For example, when the component is a high-speed component, the motherboard and the high-speed component can be interconnected at high speed through high-speed connectors and high-speed cables.

[0006] However, the port definitions on the connectors in the motherboard are usually fixed, so the motherboard is usually used to connect components of the same type, such as components that support PCIe. This limits the application scenarios of the motherboard and is not conducive to flexible and differentiated configuration of the entire machine. Summary of the invention

[0007] The present application provides a connector-based port management method, which uses the transmission interface provided by the connector to obtain requirements, and adapts the port mode of the port connected by the connector to the component according to the component requirements, so as to solve the problem that the interface signal definition of the same connector cannot be adaptively and flexibly configured, can only be applied to one type of high-speed signal, and supports the same type of components, effectively improves the flexibility of the port, enables the same port to support more components, and improves the configuration flexibility of the whole machine. The present application also provides a basic board, component, mainboard, computing device, computer-readable storage medium, and computer program product corresponding to the above method.

[0008] In the first aspect, an embodiment of the present application provides a connector-based port management method. The method is proposed on the basis of a new server architecture. The new server architecture refers to a peer-to-peer interconnection architecture, in which the traditional motherboard is split into a basic board and an expansion board, and the basic board cooperates with the expansion board to support the specifications and forms of the motherboard required for different scenarios. In the new server architecture, the basic board is connected to the component communication through PCIe, memory interconnection or a unified bus, and is connected to the expansion board through a management interface. Among them, a component is a general term for a class of devices or equipment. For example, a component may include components with different functions such as a storage component, an input and output component, an acceleration component, a memory expansion component, a heat dissipation component, a computing component, and a management component.

[0009] The method can be performed by a basic board. Specifically, the basic board identifies component access, obtains component requirements through the transmission interface provided by the connector, and the component requirements are used to indicate the properties of the port required by the component. Then, the basic board can adapt the port mode of the port connected to the connector to the component according to the component requirements.

[0010] In this method, the basic board uses the transmission interface provided by the connector to obtain component requirements, and adapts the port mode of the port connected to the connector to the component according to the component requirements, so as to solve the problem that the port signal definition of the same connector cannot be adaptively and flexibly configured, and can only be applicable to one high-speed signal type and support the same type of components. It effectively improves the flexibility of the port, enables the same port to support more components, and improves the competitiveness of the basic board and the configuration flexibility of the whole machine.

[0011] In some possible implementations, before obtaining the component requirements through the transmission interface provided by the connector, the base board may also obtain the component type of the component, and then configure the sideband signal corresponding to the component according to the component type, wherein the sideband signal includes the transmission interface.

[0012] In this method, the base board identifies the component type, adaptively configures the sideband signal according to the component type, and then transmits the component requirements according to the transmission interface in the sideband signal, and implements port adaptation based on the component requirements. In this way, the base board can support different components based on the same connector.

[0013] In some possible implementations, the component requirements include one or more of port type, link bit width, port maximum rate, channel order flip capability, signal polarity flip capability, and hot plug capability. The method implements adaptive configuration of port type, channel order flip, polarity flip, and hot plug through the component requirements transmitted by the component.

[0014] In some possible implementations, the connector is provided with a first pin for transmitting a component type. The first pin may be a plurality of pins among the pins for transmitting sideband signals, for example, three fixed pins among the pins for transmitting sideband signals. Accordingly, the base board may sample the first pin of the connector to obtain the component type of the component. The base board includes a controller, and the controller has a component type identification circuit. The base board may sample the first pin of the connector through the controller, and then use the component type identification circuit in the controller to identify the signal of the first pin, thereby obtaining the component type of the component.

[0015] In some possible implementations, the component type is identified by the high and low levels of the first pin. Specifically, the component type can be represented by a component type identification code, and the component type identification code can be identified by the high and low levels of the first pin, so that the basic board can quickly identify the component type of the component based on the first pin, and then configure the sideband signal based on the component type, and based on the component requirements transmitted by the transmission interface in the sideband signal, quickly configure the port mode of the port, thereby improving the adaptation efficiency.

[0016] In some possible implementations, the connector is provided with a second pin for transmitting component requirements. The second pin may be a plurality of pins among the pins for transmitting sideband signals, for example, may be a plurality of fixed pins among the pins for transmitting sideband signals except the first pin. Accordingly, the base board may sample the second pin of the connector to obtain the component requirements transmitted by the component through the transmission interface.

[0017] In some possible implementations, the component has a reporting function. The component can actively report the component requirements, and the basic board can receive the component requirements reported by the component through the transmission interface provided by the connector, thereby realizing port mode adaptation and further realizing the expansion of different types of components. In this way, a basic board can flexibly support more complete machine configurations, improve the reuse of the basic board, and reduce development costs.

[0018] In some possible implementations, the base board may also first send a request to the component, and then the base board may receive the component requirements returned by the component in response to the request through the transmission interface provided by the connector, thereby achieving port adaptation.

[0019] In some possible implementations, the transmission interface is a single-line transmission interface. The single-line transmission interface uses a single-line transmission communication protocol. The protocol is specifically a private communication protocol, and the protocol layer may use a Hisport interface protocol. The method uses a single-line transmission communication protocol to transmit component requirements, which can save pins and reserve more pins for other sideband signals.

[0020] In some possible implementations, the component type is generated by a component type identification code implementation circuit in the component. The component type identification code implementation circuit can generate a corresponding component type identification code by controlling a pull-up resistor and a pull-down resistor, and then transmit the component type identification code to the basic board, so that the basic board can adaptively configure the sideband signal according to the component type identification code.

[0021] In some possible implementations, the method is performed by a basic board. In this way, the basic board can extend different types of components through a connector, meet business needs, and avoid restrictions on application scenarios.

[0022] In some possible implementations, the components include one or more of a storage component, an input / output IO component, an acceleration component, and a memory expansion component. In this way, the basic board can expand components with corresponding functions according to business needs.

[0023] In a second aspect, an embodiment of the present application provides a connector-based port management method. The method is executed by a component. The method includes:

[0024] Access the basic board;

[0025] The component requirements are provided to the base board through a transmission interface provided by the connector, so that the base board adapts the port mode of the port to the component according to the component requirements.

[0026] In some possible implementations, before providing component requirements to the base board, the method further includes:

[0027] The component type is provided to the base board through the connector, so that the base board configures a sideband signal corresponding to the component according to the component type, and the sideband signal includes the transmission interface.

[0028] In some possible implementations, the transmission interface provided by the connector provides the component requirements to the base board, including:

[0029] The component requirements are reported to the base board through the transmission interface provided by the connector.

[0030] In some possible implementations, the transmission interface provided by the connector provides the component requirements to the base board, including:

[0031] In response to the request of the base board, the component requirements are returned to the base board through the transmission interface.

[0032] In some possible implementations, the component requirements include one or more of port type, link bit width, port maximum rate, channel order flipping capability, signal polarity flipping capability, and hot plug capability.

[0033] In a third aspect, the present application provides a basic board, wherein the basic board includes a processor and a connector, wherein the processor has a port, and the basic board is used to execute the method described in any one of the implementations of the first aspect of the present application to manage the port of the processor based on the connector.

[0034] In some possible implementations, the processor is a central processing unit, which encapsulates a main processor and a coprocessor. The coprocessor is used to obtain component requirements through a transmission interface provided by the connector. The component requirements are used to indicate the properties of the port required by the component, and the component requirements are passed to the main processor. The main processor is used to adapt the port mode of the port connected to the connector to the component according to the component requirements.

[0035] In some possible implementations, the base board also includes a controller, which is used to obtain component requirements through a transmission interface provided by the connector, the component requirements are used to indicate properties of the port required by the component, and pass the component requirements to the processor, which is used to adapt the port mode of the port connected to the connector to the component.

[0036] In some possible implementations, the controller includes one or more of a microcontroller unit MCU, a complex programmable logic device CPLD, and a field programmable gate array FPGA.

[0037] In a fourth aspect, the present application provides a component, including a memory and a connector, and configured to execute the method described in any one of the implementations of the second aspect of the present application, so as to manage the port of the processor based on the connector.

[0038] In a fifth aspect, the present application provides a motherboard. The motherboard includes a base board and a component, and when the component is connected to the base board, the base board is used to execute the method described in any one of the implementations of the first aspect of the present application to manage the ports of the processor in the base board based on the connector.

[0039] In a sixth aspect, the present application provides a computing device, wherein the computing device comprises a base board, and the base board is used to execute the method as described in any one of the implementation modes of the first aspect of the present application, so as to manage the ports of the processor in the base board based on the connector.

[0040] In a seventh aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, wherein the instructions instruct a computing device to execute the method described in any one of the implementations of the first aspect or the second aspect.

[0041] In an eighth aspect, the present application provides a computer program product comprising instructions, which, when executed on a computing device, enables the computing device to execute the method described in any one of the implementations of the first or second aspect above.

[0042] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical method of the embodiments of the present application, the drawings required for use in the embodiments are briefly introduced below.

[0044] Figure 1 A schematic diagram of the structure of a mainboard provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of the structure of a mainboard provided in an embodiment of the present application;

[0046] Figure 3 A flowchart of a connector-based port management method provided in an embodiment of the present application;

[0047] Figure 4 A schematic diagram of a stable access detection provided in an embodiment of the present application;

[0048] Figure 5 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] To facilitate understanding, the technical terms involved in this application are first introduced.

[0050] The new server architecture, also referred to as the new architecture, is a peer-to-peer interconnected architecture. In this architecture, the traditional motherboard is first split into the basic computing unit (BCU) and the extension unit (EXU), and the basic board is combined with the extension board to support the specifications and forms of the motherboard required for different scenarios.

[0051] The basic board includes a CPU, double data rate (DDR) and related power supplies, providing general computing capabilities and peripheral storage, input / output (IO), acceleration and other expansion interfaces. The basic board supports Optionally, the base board supports heterogeneous processors, that is, the base board can support different types of processors, for example, the base board supports CPU, and any processor or any combination thereof, such as application-specific integrated circuit (ASIC), programmable logic device (PLD), complex programmable logical device (CPLD), field-programmable gate array (FPGA), generic array logic (GAL), system on chip (SoC), software-defined infrastructure (SDI) chip, artificial intelligence (AI) chip, etc.

[0052] The expansion board includes a baseboard management controller (BMC) chip and a management system, a bridge chip (for example, the platform controller hub (PCH) of Intel system), which is a management extension of the base board. As the management center of the entire system, it provides management functions such as equipment, security, energy efficiency, and reliability. Among them, BMC can also be called a baseboard management controller.

[0053] In the new architecture, the base board is connected to the components through PCIe, Compute Express Link (CXL), or unified bus (UB or Ubus), and is connected to the expansion board through the management interface. The management interface can transmit management signals, power timing control signals, and IO expansion interface signals. In specific implementations, the specific connection methods of the above-mentioned base board and components, and the basic board and expansion board include: a soft connection method using a cable to achieve the above-mentioned connection, or a hard connection method using a connector to achieve the above-mentioned connection.

[0054] Furthermore, a component is a general term for a type of device or equipment. Components include storage components (STorage Unit, STU), IO components (Input Output Unit, IOU), acceleration components (ACceleration Unit, ACU), memory expansion components (Memory Expansion Unit, MEU), heat dissipation components, computing components, management components, etc. according to their functions.

[0055] Among them, storage components include hard disk backplanes, etc., which are used to expand system storage and support multiple media and forms such as hard disk drive (HDD) / solid-state drive (SSD) / non-volatile memory express (NVMe) / storage class memory (SCM).

[0056] IO components include Riser and other components to expand the system IO and support PCIe standard cards and Open Compute Project (OCP) cards.

[0057] Acceleration components include standard card-type acceleration cards, in-module acceleration modules, etc., providing system acceleration component expansion and interconnection functions.

[0058] Memory expansion components include carrier boards, memory expansion chips, dual in-line memory modules (DIMMs), SCM media, etc., which provide the system with the function of expanding memory bandwidth and content capacity.

[0059] The heat dissipation component is used to dissipate heat from a computing device or hardware in the computing device, including a combination of several heat dissipation methods such as air cooling, liquid cooling, or a combination of the two. It should be understood that the structure, type, and number of the heat dissipation components do not constitute a limitation on the technical solution to be protected by this application.

[0060] Computing components, such as central processing unit (CPU), memory, etc., provide general computing capabilities.

[0061] Management components, baseboard management controllers, etc. provide device management devices.

[0062] This application proposes a port management solution based on connector adaptation on the basis of a new server architecture, and uses the transmission interface provided by the connector to obtain component requirements, which are used to indicate the properties of the port required by the component (for the sake of ease of description, the following text uses high-speed components as examples). According to the component requirements, the port mode of the port connected by the connector is adapted to the high-speed component (such as the above-mentioned storage components, IO components, acceleration components, memory expansion components and other high-speed components) to solve the problem that the interface signal definition of the same connector cannot be adaptively and flexibly configured, and can only be applicable to one type of high-speed signal and support the same type of high-speed components. The flexibility of the port is effectively improved, and the same port can support more high-speed components, thereby improving the competitiveness of the basic board and the configuration flexibility of the entire machine.

[0063] In order to make the technical solution of the present application clearer and easier to understand, the technical solution provided by the present application is described in detail below with reference to the accompanying drawings.

[0064] First, see Figure 1 The mainboard 10 includes a base board 100 and a peripheral high-speed component 200. The high-speed component 200 is connected to the base board 100, for example, the high-speed component 200 can be connected to the base board 100 by plugging. The mainboard 10 also includes an expansion board ( Figure 1 (not shown in the figure), the expansion board provides management functions and power supply for the basic board 100 and the extended high-speed component 200.

[0065] The base board 100 includes a processor 102, a controller 104 and a connector 106. The processor 102 may be a CPU. The controller 104 may be one or more of a microcontroller unit (MCU), a complex programmable logic device (CPLD), and a field programmable gate array (FPGA). The connector 106 is used to connect peripheral high-speed components 200. In some embodiments, the connector 106 may be a high-speed connector, such as a unified bus connector (UBC) or a unified bus connector-DoubleDensity (UBC-DD) with double density. The base board 100 may include one or more connectors 106, and a plurality of connectors 106 may be used to connect different types of high-speed components 200 (e.g., a high-speed component 200 supporting PCIe, a high-speed component 200 supporting ETH).

[0066] The high-speed component 200 includes a memory 202 and a connector 204. The memory 202 is used to store the component requirements of the high-speed component. The component requirements include the properties of the port required by the component. In some embodiments, the properties of the port include one or more of the port type, link width, port maximum rate, channel sequence (lane) flip capability, signal polarity flip capability, and hot plug capability. The connector 204 is used to dock with the base board 100. Specifically, the connector 204 is connected to the connector 106 in the base board 100, so as to achieve docking with the base board 100.

[0067] The component requirements stored in the memory 202 can be transmitted to the basic board 100 through the connector 204, so that the basic board 100 adapts the port mode of the port connected to the connector 106 to the high-speed component 200 according to the component requirements. The port mode refers to a mode divided based on the attributes of the port. When the port is in different port modes, the attributes of the port are usually different.

[0068] It should be noted that the high-speed component 200 can actively report the component requirements, or can respond to the request of the basic board 100 (for example, a read request) and return the component requirements to the basic board 100. In some embodiments, the high-speed component 200 can also include a component requirement reporting module 206, which is connected to the memory 202 and the connector 204 respectively. The component requirement reporting module 206 reads the component requirements stored in the memory 202, and transmits the component requirements to the basic board 100 through the transmission interface provided by the connector 204.

[0069] The component requirement reporting module 206 may be implemented by an MCU, a CPLD or an FPGA. The MCU, the CPLD or the FPGA may include a built-in memory, such as an on-chip read-only memory (ROM). The component requirements may also be stored in the built-in memory, and the component requirement reporting module 206 may read the component requirements from the built-in memory, and then report the component requirements to the basic board 100. In some embodiments, the component requirements may also be stored in an independent memory, such as the above-mentioned memory 202, and the component requirement reporting module 206 may read the component requirements from the independent memory, and then report the component requirements to the basic board 100. In other embodiments, when the basic board 100 obtains the component requirements by active reading, the component requirements may be read directly from an independent memory, such as the memory 204.

[0070] Further, the high-speed component 200 may also include a component type identification code implementation circuit 208. The component type identification code implementation circuit 208 is used to generate a component type, which can be characterized by a component type identification code. In some embodiments, the component type identification code can be 101, 110, 011, 010, etc. Based on this, the component type can be identified by the high and low levels of several pins of the connector 204 (for ease of description, it can be referred to as the first pin). The component type identification code implementation circuit 208 can transmit the component type (for example, the component type identification code) to the basic board 100 through the connector 204, so that the basic board 100 configures the sideband signal corresponding to the high-speed component 200 according to the component type. The sideband signal includes a transmission interface, which is used to transmit component requirements.

[0071] The embodiment of the present application designs the port definition on the connector 106 so that the same connector 106 can adaptively configure the high-speed signal type and sideband signal definition according to the type of the connected high-speed component 200, thereby greatly improving the flexibility and applicability of the connector 106.

[0072] For ease of understanding, the interface pin layout (pin map) of the connector 106 is described below by taking a widely used 74-pin high-speed connector (eg, a 74-pin slimline high-speed connector) as an example.

[0073] The 74-pin high-speed connector has 74 pins, including 8 pairs (i.e. 16) of pins for transmitting high-speed signals (such as high-speed port data receiving signals and high-speed port data sending signals), 20 pins for transmitting sideband signals (usually low-speed sideband signals, also referred to as low-speed signals), and some pins for transmitting ground signals, as shown below:

[0074] Table 1 Example of interface pin map for 74-pin high-speed connector

[0075]

[0076]

[0077] When the connector is used for different ports (different IO ports of the CPU) and connects different types of high-speed components 200, different port definitions are required. For this purpose, the sideband signals in the connector can be multiplexed. When the high-speed signals are used as PCIe, SAS / SATA or ETH network ports, the sideband signals can be given different signal definitions to meet the needs of different high-speed components 200. The details are as follows:

[0078] Table 2 Sideband signal multiplexing relationship

[0079]

[0080]

[0081]

[0082] In order to transmit different types of high-speed signals, such as PCIe-type high-speed signals and ETH-type high-speed signals, the embodiment of the present application selects different types of pins in the pins used by the connector 106 for transmitting sideband signals to define the transmission interface. Among them, different types of pins can also be selected from the pins used by the connector 106 for transmitting sideband signals to transmit component types. For ease of distinction, the embodiment of the present application refers to the pin used to transmit the component type as the first pin, and the pin used to transmit the component requirement as the second pin.

[0083] In some embodiments, the first pin may be A8, A26, and B10, as shown below:

[0084] Table 3 Definition of the first pin

[0085]

[0086] The three (low-speed) sideband signals P0_SB_7A, P0_SB_7B, and P0_SB_2A can be used as component type (BP_type) detection signals. The BP_type detection signal is used as an indication signal from the component to the BCU. The signal is pulled up on the BCU and enters the CPLD. It is left floating or pulled down on the high-speed component 200. Different BP_type combinations can distinguish the type of high-speed component 200 connected to the connector (such as UBC or UBC-DD), thereby distinguishing the purpose of other sideband signals within the CPLD logic.

[0087] Specifically, the high-speed component 200 can indicate the component type of the high-speed component 200 through BP_TYPE[2:0], as shown in the following table:

[0088] Table 4 Component type identification code

[0089]

[0090] It should be noted that BP_type[0] can also be used as a stable insertion detection signal of the high-speed component 200. The detection principle is described in detail below.

[0091] The basic board 100 can use CPLD (or other controllers, such as FPGA, MCU) to sample BP_TYPE[2:0], and adaptively configure the remaining sideband signals (specifically the transmission interface in the sideband signal) according to the component type obtained by the sampling, as shown below:

[0092] Table 5 Definition of transmission interface

[0093]

[0094]

[0095] Among them, P0_SB_3A is defined as GND, which serves as the reference GND of the high-speed homologous clock. P0_SB_2B is defined as Vstby_3v3, which serves as the 3.3V standby power supply provided by the base board 100 side to the high-speed component 200 side. In order to protect the cable and connector 106, the base board 100 side can provide overcurrent protection function for the P0_SB_2B power supply. P0_SB_3B is defined as not connected (notconnect, NC). Since the P0_SB_2B pin at the opposite end of the connector 106 has been defined as a power supply, in order to prevent the interconnection of the connector 106 on the base board 100 side from causing a power short circuit, P0_SB_3B is directly left floating. P0_SB_A+ / P0_SB_A- and P0_SB_B+ / P0_SB_B-, these two groups of signals are defined as clocks of the same source as the high-speed signal, which are used for high-speed port synchronization.

[0096] P0_SB_6B is defined as a transmission interface, also known as the cable detection signal TOPOLOGY_DET. The transmission interface may be a single-line transmission interface, which is used for the high-speed component 200 to report the component requirements of the peripheral high-speed component 200 to the base board 100. The component requirements may include one or more of the port type, link bit width, port maximum rate, channel sequence flip capability, signal polarity flip capability, and hot plug capability. The channel sequence flip capability is used to identify whether the connector 106 supports the channel sequence flip capability, the signal polarity flip capability is used to identify whether the connector 106 supports the signal polarity flip, and the hot plug capability is used to identify whether the connector 106 supports hot plugging.

[0097] Regarding the multiplexed sideband signals, the signal transmission and analysis processes are described below according to the different high-speed components 200 connected.

[0098] When the connected high-speed component 200 is a SAS / SATA hard disk backplane, the high-speed component 200 transmits BP_type[2:0]=000 to the BCU. According to the BP_type, the BCU external high-speed interface can provide two sets of SGPIO signals for hard disk lighting, and add a cable detection signal for high-speed cable use. The signal definition is compatible with the signal definition in the Universal Backplane Management (UBM) protocol standard.

[0099] When the connected high-speed component 200 is an Nvme hard disk backplane, the high-speed component 200 is passed to the BCU module BP_type[2:0]=011. According to the BP_type, the BCU external high-speed interface can provide two sets of HP_I2C signals for hard disk hot-swap operations, and provide two I2C reset signals, two PCIe reset signals, and a CHANGE_DET# interrupt signal. The signal definition is compatible with the signal definition in the UBM protocol standard.

[0100] When the connected high-speed component 200 is an OCP network card / Raid card / BBU module, the high-speed component 200 is passed to BCUBP_type[2:0]=100. According to the BP_type, the BCU external high-speed interface can provide a set of BMC_I2C signals for out-of-band management system component management, a set of CPU_I2C for in-band CPU component management, and two PCIe platform reset signals, a PCIe_PWRBRK# signal, a PCIe_WAKE# signal, and a device in-position indication signal. The signal definition is compatible with the signal definition in the OCP standard protocol.

[0101] When the connected high-speed component 200 is a CPU direct-output NIC network card, the high-speed component 200 is transmitted to BCU BP_type[2:0]=101. According to the BP_type, the BCU external high-speed interface can provide a group of BMC_I2C signals for out-of-band management system component management, a group of CPU_I2C for in-band CPU component management, a group of MDIO for in-band CPU component management, and an I2C reset signal, a device presence indication signal and a reserved signal.

[0102] When the connected high-speed component 200 is a Riser module, the high-speed component 200 is passed to the BCU module BP_type[2:0]=110. According to the BP_type, the BCU can provide a set of BMC_I2C signals on the external high-speed interface for out-of-band management system component management, and is equipped with a PCIe platform reset signal, a PCIe_PWRBRK# signal, a PCIe_WAKE# signal, a JTAG_TRST / AC_LOSS signal, a PCIe_CLKREQ# signal, and two reserved signals. The signal definition is compatible with the signal definition in the PCI Express Card Electromechanical Specification standard protocol.

[0103] Among them, the SPGIO signal is used for the hard disk lighting control on the high-speed component 200, and the signal definition complies with the SFF-8485 protocol standard. The HP_I2C signal is used for the hot-swappable device control on the high-speed component 200, and the signal definition complies with the I2C standard definition. BMC_I2C signal: used for out-of-band management control on the high-speed component 200, and the signal definition complies with the I2C standard definition. CPU_I2C signal: used for the in-band CPU to manage the high-speed component 200, and the signal definition complies with the I2C standard definition. MDIO signal: used for the in-band CPU to manage the NIC card type high-speed component 200, and the signal definition complies with the standard definition of MDIO in 802.3clause22. CHANGE_DET signal: used for the high-speed component 200 to report interrupts to the BCU, and the signal definition complies with the definition of CHANGE_DET in the SFF-TA-1005Specification for UBM. The PCIe_PWRBRK / PCIe_WAKE / PCIe_RST / PCIe_CLKREQ / JTAG_TRST signals are used for PCIe standard device control on the high-speed component 200, and the signal definition complies with the signal definition in the PCI Express Card Electromechanical Specification standard protocol.

[0104] In some possible implementations, the component requirements are stored in the memory 202 of the high-speed component 200. The memory 202 may be an independent memory. When the high-speed component 200 includes the component requirement reporting module 208, the memory 202 may also be a built-in memory of the component requirement reporting module 208. The memory 202 may be an electrically erasable programmable read-only memory (EEPROM) or a mask-programmed read-only memory (MROM). The component requirement reporting module 208 in the peripheral high-speed component 200 (including but not limited to the use of CPLD logic implementation) can read the component requirements in the memory 202 and transmit them to the controller 104 (including but not limited to the use of CPLD logic implementation) through the transmission interface provided by the connector 106. The controller 104 parses the component requirements and transmits the parsed component requirements to the processor 102. The processor 102 adapts the port mode of the port to the high-speed component 200 in the startup phase, thereby realizing the adaptive configuration of the port.

[0105] Among them, the transmission interface can use a single-line transmission communication protocol. The protocol is specifically a private communication protocol, and the protocol layer can adopt the Hisport interface protocol. Among them, the single-line transmission communication protocol defines the bus signal frequency, the verification method, and the maximum amount of data transmitted in a single time. In this example, the bus signal frequency can be 250 kilohertz (Khz), the verification method is a standard cyclic redundancy check (CRC), and the maximum amount of data transmitted in a single time can be 32 bytes (bytes, B).

[0106] The 32-byte data and 1-byte CRC content transmitted by the transmission interface are defined as follows:

[0107] Table 6 Transmission interface transmission content

[0108]

[0109]

[0110] In the above content, the content related to the port mode configuration includes component type, port information and parameters (port attributes). Among them, port information is used to identify the type of port, and parameters are used to define the attributes of the port. For details, please refer to the following table:

[0111] Table 7 Port information and parameter definitions

[0112]

[0113]

[0114] Among them, parameter BYTE1 (also called parameter 1) defines the link width, as shown in the following table:

[0115] Table 8 Definition of parameter BYTE1

[0116] Byte number bit stream Information content Parameter 1 0000_0000 default value Parameter 1 0000_0001 x16 Parameter 1 0000_0010 x8 Parameter 1 0000_0011 x4x4 Parameter 1 0000_0100 x2x2x2x2 Parameter 1 0000_0101 x4x2x2 Parameter 1 0000_0110 x2x2x4

[0117] Bits [7:4] of parameter BYTE2 (also called parameter 2) define the maximum port rate, as shown in the following table:

[0118] Table 9 Definition of bit [7:4] of parameter BYTE2

[0119] Byte number bit stream Information content Parameter 2 0000 none Parameter 2 0001 GEN1 Parameter 2 0010 GEN2 Parameter 2 0011 GEN3 Parameter 2 0100 GEN4 Parameter 2 0101 GEN5 Parameter 2 0110 ……

[0120] Bit [3] and bit [2] of parameter BYTE2 (also called parameter 2) define the hot-plug capability and lane flip capability of the port, respectively. For details, see the following table:

[0121] Table 10 Definition of the bits [3] of parameter BYTE2

[0122]

[0123] Table 11 Definition of the bits [2] of parameter BYTE2

[0124] Byte number bit stream Information content Parameter 2 0 No flip Parameter 2 1 Flip

[0125] Bits [1:0] of parameter BYTE2 are reserved bits and can be used to define other properties of the port.

[0126] Parameter BYTE3 (also called parameter 3) and parameter BYTE4 (also called parameter 4) are used to define polarity flip, where parameter 3 is used to define polarity flip RX, and parameter 4 is used to define polarity flip TX. As shown in the following table:

[0127] Table 12 Definition of parameter BYTE3

[0128] Byte number bit stream Information content Parameter 3 0000_0000 None / default not flip Parameter 3 0000_0001 Indicates that lane 0 polarity is flipped Parameter 3 0000_0010 Indicates that lane1 polarity is flipped …and so on Indicates lane polarity reversal

[0129] Table 13 Definition of parameter BYTE4

[0130] Byte number bit stream Information content Parameter 4 0000_0000 None / default not flip Parameter 4 0000_0001 Indicates that lane 0 polarity is flipped Parameter 4 0000_0010 Indicates that lane 1 polarity is flipped …and so on Indicates that lane n polarity is flipped

[0131] like Figure 1As shown, when the connector 106 transmits the component requirements including the port type, the maximum port rate, the lane sequence flipping capability, the polarity flipping capability, and the hot plug capability to the controller 104 through the above pins, and the controller 104 transmits the component requirements to the processor 102, the processor 102 can implement port mode adaptation. Accordingly, the processor 102 can receive the corresponding type of high-speed signal transmitted by the high-speed component 200 through the connector 106, rather than being limited to a fixed type of high-speed signal.

[0132] In some possible implementations, such as Figure 2 As shown, the processor 102 of the basic board 100 may be encapsulated with a main processor 1024 and a coprocessor 1022, and the coprocessor 1022 is used to assist the main processor 1024 in the processor 102 to complete processing tasks that it cannot perform or performs inefficiently or effectively. When the processor 102 is encapsulated with a coprocessor 1022, the coprocessor 1022 may sample the first pin of the connector 106 to obtain the component type, and configure the sideband signal corresponding to the high-speed component 200 according to the component type. Then the coprocessor 1022 obtains the component requirement of the high-speed component 200 through the transmission interface in the sideband signal. The coprocessor 1022 may pass the component requirement to the main processor 1024, and the main processor 1024 adapts the port mode of the port of the processor 102 to the high-speed component 200 based on the component requirement. In other words, in Figure 2 In the example of FIG. 1 , the function of the controller 104 may be implemented by the coprocessor 1022 , and the basic board 100 may not include the controller 104 .

[0133] Next, the process of the connector-based port management method according to the embodiment of the present application will be described in detail with reference to the accompanying drawings.

[0134] See also Figure 3 A flow chart of a connector-based port management method is shown, the method comprising:

[0135] S302: The base board 100 recognizes that the high-speed component 200 is connected.

[0136] The high-speed component 200 is specifically a component used to expand the function of the basic board 100. The high-speed component 200 usually has a higher IO rate. Based on the different expanded functions, the component 200 may include one or more of a storage component, an IO component, an acceleration component, and a memory expansion component.

[0137] In this embodiment, the high-speed components 200 can be divided into different types according to the supported protocol types. For example, the high-speed components 200 can include different types such as PCIe components, ETH components, SAS components, and SATA components.

[0138] The high-speed component 200 can be connected to the base plate 100 to expand the function of the base plate 100. There are multiple ways of connection. In some embodiments, the high-speed component 200 can be connected to the base plate 100 by insertion. In other embodiments, the high-speed component 200 can be connected to the base plate 100 by snap-fitting.

[0139] The base board 100 identifies whether a high-speed component 200 is connected. For example, when the high-speed component 200 is connected to the base board 100 by plugging, the base board 100 can identify whether a high-speed component 200 is connected by detecting a presence signal or the like. When it is identified that a high-speed component 200 is connected, the base board 100 can execute a subsequent process.

[0140] S304: The base board 100 identifies whether the high-speed component 200 is stably connected. If yes, S306 is executed, and if no, S314 is executed.

[0141] Taking into account the situation that the high-speed component 200 may have unstable access, for example, when the high-speed component 200 is inserted into the base board 100, the high-speed component 200 may be inserted unstably, resulting in intermittent connection between the high-speed component 200 and the base board 100. Therefore, the base board 100 can also identify whether the high-speed component 200 is stably connected.

[0142] For example, the basic board 100 can detect the presence signal of the connector 204 in the high-speed component 200 to identify whether the high-speed component 200 is stably connected. When the high-speed component 200 is not stably connected, the basic board 100 can execute S314 to issue an alarm to remind the user to reconnect the high-speed component. When the high-speed component 200 is stably connected, S306 can be executed to start port management based on the connector 106.

[0143] See also Figure 4 As shown in the stable access detection principle diagram, the controller 104 in the basic board 100, such as a CPLD, can be designed with an output pin A and an input pin B. When the CPLD logic starts to perform BP_type tri-state detection, the A pin is first output to a high impedance state. If the B pin detects a high level, it means that the high-speed component 200 is in place and BP_type[0]=1; if the B pin detects a low level, a high level is output to the A pin, and the B pin level is detected again. If the B pin is still at a low level, it means that the high-speed component 200 is in place and BP_type[0]=0; if the B pin detects a high level, it means that the high-speed component 200 is not in place. The basic board 100 continuously detects whether the high-speed component 200 is in place through the CPLD, for example, by detecting whether the high-speed component 100 is in place in N consecutive cycles, it can be realized to detect whether the high-speed component 200 is stably connected.

[0144] It should be noted that the method of the embodiment of the present application may not execute the above S304 . For example, the basic board 100 may also directly execute S306 to execute the port management method based on the connector 106 .

[0145] S306 : The base board 100 samples the first pin of the connector 106 to obtain the component type of the high-speed component 200 .

[0146] Specifically, the connector 106 is provided with a first pin for transmitting the component type of the high-speed component. For example, the 74-pin connector 106 is provided with pins with pin numbers A8, A26, and B10 for transmitting the component type of the high-speed component. The base board 100 can sample the above-mentioned first pin of the connector 106 to obtain the component type identification code of the high-speed component 200, and the component type identification code is used to identify the component type of the high-speed component 200.

[0147] In some possible implementations, the basic board 100 includes a controller 104, and the basic board 100 can sample the first pin through the controller 104 to obtain the component type of the high-speed component 200. The controller 104 has a component type identification circuit, and the controller 104 can sample the first pin, and identify the signal of the first pin based on the component type identification circuit, thereby obtaining the component type. In other possible implementations, when the processor 102 of the basic board 100 is packaged with a coprocessor 1022, the basic board 100 can sample the first pin through the coprocessor 1022 to obtain the component type of the high-speed component.

[0148] S308: The base board 100 configures the sideband signal corresponding to the high-speed component 200 according to the component type.

[0149] In some possible implementations, the base board 100 includes a controller 104 having a sideband signal configuration implementation circuit. The base board 100 can configure the sideband signal corresponding to the high-speed component 200 through the sideband signal configuration implementation circuit.

[0150] In some other possible implementations, the processor 102 of the basic board 100 is encapsulated with a coprocessor 1022, and the coprocessor 1022 can configure the sideband signal corresponding to the high-speed component according to the component type, thereby realizing adaptive configuration of the sideband signal.

[0151] It should be noted that the method of the embodiment of the present application may not execute the above S306 to S308. For example, the base board 100 may directly execute S310.

[0152] S310 : The high-speed component 200 reports the component requirement of the high-speed component 200 through the transmission interface provided by the second pin of the connector 106 .

[0153] The second pin of the connector 106 is used to transmit the component requirements of the high-speed component 200. Specifically, the second pin is defined with a transmission interface, and the high-speed component 200 can actively report the component requirements through the transmission interface.

[0154] The component requirements include one or more of port type, link width, port maximum rate, channel order flip capability, signal polarity flip capability, and hot plug capability. Referring to Table 6, the component requirements can be represented by 32 bytes of content.

[0155] It should be noted that S310 is only one implementation method of the basic board 100 obtaining the component requirements transmitted by the high-speed component 200 in the embodiment of the present application. In other possible implementation methods of the embodiment of the present application, the basic board 100 may also obtain the component requirements in other ways. For example, the basic board 100 may send a read request to the high-speed component 200, and the high-speed component 200 responds to the read request and receives the component requirements returned by the high-speed component 200 through the transmission interface provided by the connector 106.

[0156] S312: The base board 100 adapts the port mode of the port connected to the connector 106 to the high-speed component 200 according to the component requirements.

[0157] Specifically, the processor 102 of the basic board 100 has a port, and the port has multiple port modes. Different port modes correspond to different port properties. For example, in one port mode, the port type may be a PCIe type; for another example, in another port mode, the port type may be a SAS. The basic board 100 can adapt the port mode of the port to the high-speed component 200 according to the component requirements, thereby configuring the port of the processor 102 as a high-speed port required by the high-speed component 200, thereby achieving port mode adaptation.

[0158] S314: The basic board 100 reports an unstable access alarm.

[0159] The unstable access alarm is used to warn the user that the high-speed component 200 is not stably connected to the basic board 100. Among them, the unstable access alarm can be implemented in multiple forms. In some embodiments, the basic board 100 can play an alarm sound to warn, or present an alarm message through an alarm interface.

[0160] It should be noted that the above S314 is an optional step of the embodiment of the present application, and the method of the embodiment of the present application may not execute the above S314.

[0161] Based on the above description, an embodiment of the present application provides a port management method based on the connector 106. In this method, the basic board 100 can adapt the port mode of the port to the high-speed component 200 based on the transmission interface and transmission component requirements defined by the connector 106, thereby achieving port mode adaptation and then high-speed signal adaptation. The high-speed signal definition in the port definition on the connector 106 can be adaptive according to the component type. When the port supports multiple port modes, one connector 106 can be used to transmit different types of high-speed signals, thereby making full use of the flexible and configurable characteristics of the port, which is conducive to flexible and differentiated configuration of the whole machine.

[0162] The above embodiments describe port management based on a 74-pin high-speed connector such as UBC. In some possible implementations, the base board 100 can also manage ports based on a 184-pin high-speed connector such as UBC-DD. UBC-DD includes X16 high-speed signals, some out-of-band low-speed signals, and power signals, supports 150W power supply capacity, and can support up to 2 75W PCIe standard cards. The details are as follows:

[0163] Table 14 Example of interface pin map for 184-pin high-speed connector

[0164]

[0165]

[0166]

[0167]

[0168]

[0169] Among them, the multiplexing relationship of the low-speed management control signal (sideband signal) can refer to the definition of the multiplexing relationship in the 74-pin high-speed connector, which will not be repeated here.

[0170] Based on the above method and base board 100 provided in the embodiment of the present application, the embodiment of the present application further provides a main board 10. Figure 1 or Figure 2 The mainboard 10 shown in the figure comprises a base board 100 and a high-speed component 200. The mainboard 10 also comprises an expansion board (not shown in the figure).

[0171] The high-speed component 200 is connected to the base board 100, and the base board 100 and the high-speed component 200 cooperate to execute Figure 3 The method of the illustrated embodiment adapts the port mode of the port of the processor 102 in the base board 100 to the high-speed component 200 .

[0172] Furthermore, the embodiment of the present application also provides a computing device. In some embodiments, the computing device may be a server, such as a rack-mounted server. In other embodiments, the computing device may also be a terminal.

[0173] Figure 5 A schematic diagram of the structure of a computing device is provided, such as Figure 5 As shown, the computing device 50 includes a base board 100 and a high-speed component 200. In some embodiments, the base board 100 includes a processor 102, a controller 104, and a connector 106. In other embodiments, the processor 102 may be encapsulated with a main processor and a coprocessor. In this case, the function of the controller 104 may be implemented by the coprocessor, and the base board 100 may not include the controller 104. The high-speed component 200 includes a memory 202 and a connector 204. The high-speed component 200 is connected to the base board 100.

[0174] The processor 102 may be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP). In some embodiments, the processor 102 may also include a coprocessor.

[0175] The controller 104 may be one or more of a microcontroller unit MCU, a field programmable gate array FPGA, or a complex programmable logic device CPLD.

[0176] The connector 106 may be a high-speed connector, such as UBC or UBC-DD. In some embodiments, the connector 106 may also be a common connector (e.g., a low-speed connector). Similarly, the connector 204 of the high-speed component 200 may be a high-speed connector or a common connector (e.g., a low-speed connector). The connector 204 of the high-speed component 200 is connected to the connector 106 of the base board 100, thereby enabling the high-speed component 200 to be connected to the base board 100.

[0177] The base board 100 recognizes the access of the high-speed component 200, obtains the component requirements transmitted by the high-speed component 200 through the transmission interface provided by the connector 106, and adapts the port mode of the port connected to the connector 106 to the high-speed component 200 according to the component requirements.

[0178] The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be stored by a computing device or a data storage device such as a data center that contains one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk). The computer-readable storage medium includes instructions that instruct the computing device to execute the above-mentioned connector-based port management method.

[0179] The embodiment of the present application also provides a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computing device or data center to another website site, computing device or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer program product can be a software installation package. In the case where any of the aforementioned connector-based port management methods is required, the computer program product can be downloaded and executed on a computing device.

[0180] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

Claims

1. A connector-based port management method, characterized in that: The method is performed by a component, comprising: After the component is connected, the component requirements are provided to the controller through the transmission interface provided by the connector. The component requirements indicate the properties of the port required by the component, so that the controller can adapt the port mode of the port connected to the connector to the component according to the component requirements.

2. The method according to claim 1, characterized in that Before providing the component requirement to the controller through the transmission interface provided by the connector, the method further includes: The component type of the component is provided to the controller so that the controller configures a sideband signal corresponding to the component according to the component type, wherein the sideband signal includes the transmission interface.

3. The method according to claim 1 or 2, characterized in that: The port attributes required by the component include one or more of port type, link bit width, port maximum rate, channel sequence flipping capability, signal polarity flipping capability, and hot plug capability.

4. The method according to claim 2, characterized in that: The component type of the component is provided to the controller via the first pin of the connector.

5. The method according to claim 4, characterized in that The component type is identified by the high and low levels of the first pin.

6. The method according to any one of claims 1 to 5, characterized in that: Component requirements are provided to the controller via the second pin interface of the connector.

7. The method according to any one of claims 1 to 6, characterized in that: Providing component requirements to the controller through the transmission interface provided by the connector includes: The component requirements of the component are reported through the transmission interface provided by the connector.

8. The method according to any one of claims 1 to 6, characterized in that: The obtaining component requirements through the transmission interface provided by the connector includes: receiving a request sent by the controller, the request instructing the component to return a component requirement of the component; Based on the request, the component requirement is returned through the transmission interface provided by the connector.

9. The method according to any one of claims 1 to 6, characterized in that: The transmission interface is a single-line transmission interface.

10. The method according to any one of claims 1 to 7, characterized in that: The component type is generated by a component type identification code implementation circuit in the component.

11. The method according to any one of claims 1 to 10, characterized in that: The components include one or more of a storage component, an input / output (IO) component, an acceleration component, and a memory expansion component.

12. A motherboard, characterized in that: The mainboard includes a base board and a component. When the component is connected to the base board, the method according to any one of claims 1 to 11 is performed.

13. A computing device, characterized in that: The computing device includes the motherboard of claim 12.

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