PCIe equipment detection method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of computers, and provides a PCIe equipment detection method and device, electronic equipment and a storage medium. The method comprises the steps that in response to starting of a detection function, a first linked list is established according to PCIe equipment expected to be detected, and information of each piece of equipment expected to be detected is stored in a node, corresponding to the equipment, in the first linked list; determining a PCIe link between each device expected to be detected and the central processing unit, determining all PCIe devices on the PCIe link as detection related devices, and clearing errors of the detection related devices; and creating a detection thread, starting the detection thread, sequentially detecting whether each device recorded in the first linked list has an error or not by the detection thread, and recording the detected error information to a node corresponding to the device in the first linked list. According to the method, the requirements of PCIe equipment error detection on the PCIe equipment capability and the developer capability can be reduced, so that the PCIe equipment error detection cost is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a PCIe device detection method, device, electronic device and storage medium. Background Art

[0002] Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus used to connect major hardware devices on the motherboard, such as graphics processing units (GPUs), memory, network cards, etc. These hardware devices connected via PCIe are also called PCIe devices.

[0003] PCIe devices may generate errors. PCIe device errors need to be analyzed by the Central Processing Unit (CPU), so the CPU needs to obtain the error information of the PCIe device. The existing method is that the PCIe device actively reports error information, so the PCIe device must have an error reporting function, which places high requirements on PCIe devices and increases the error detection cost of PCIe devices. In addition, it is necessary to enable interrupts through the advanced error reporting (AER) service of the system firmware and operating system to notify the CPU. Enabling interrupts needs to be adapted to the CPU architecture, which requires very high capabilities of developers, further increasing the error detection cost of PCIe devices.

[0004] Based on this, how to reduce the requirements of PCIe device error detection on the capabilities of PCIe devices and the capabilities of developers, and reduce the cost of PCIe device error detection, has become a research hotspot in this field. Summary of the invention

[0005] In view of this, the present disclosure proposes a PCIe device detection method, apparatus, electronic device and storage medium. The PCIe device detection method of the present disclosure can reduce the requirements of PCIe device error detection on the capabilities of PCIe devices and developer capabilities, thereby reducing the cost of PCIe device error detection.

[0006] According to one aspect of the present disclosure, a PCIe device detection method is provided, the method being used to detect errors of PCIe devices in a system, the method comprising: in response to a PCIe device detection function being turned on, establishing a first linked list according to PCIe devices expected to be detected, the first linked list comprising a plurality of nodes, information of each PCIe device expected to be detected being stored in a node corresponding to the device in the first linked list; determining a PCIe link between each PCIe device expected to be detected and a central processing unit, determining all PCIe devices on the PCIe link as detection-related devices, and clearing errors of the detection-related devices; creating a detection thread and starting the detection thread, the detection thread sequentially detecting whether an error occurs in each PCIe device recorded in the first linked list, and recording the detected error information in a node corresponding to the PCIe device in the first linked list.

[0007] In a possible implementation, the detection thread further detects the link status of each PCIe link where the PCIe device recorded in the first linked list is located in sequence, and records the detected link status into a node corresponding to the PCIe device in the first linked list.

[0008] In a possible implementation, the detection thread detects in turn whether an error occurs in each PCIe device recorded in the first linked list, and records the detected error information in the node corresponding to the PCIe device in the first linked list, including: when the detection thread detects whether an error occurs in any PCIe device recorded in the first linked list, the detection thread reads the device identifier of the PCIe device from the node corresponding to the PCIe device in the first linked list, and accesses the correctable error status register and the uncorrectable error status register of the PCIe device according to the read device identifier; when a correctable error exists in the correctable error status register, the error information of the correctable error is read and recorded in the node corresponding to the PCIe device in the first linked list; when an uncorrectable error exists in the uncorrectable error status register, the error information of the uncorrectable error is read and recorded in the node corresponding to the PCIe device in the first linked list; and continues to detect whether an error occurs in the next PCIe device recorded in the first linked list.

[0009] In a possible implementation, the error information of the correctable error includes the error type, error mask, and error number statistics, and the error information of the uncorrectable error includes the error type, error mask, error level, Header log, and error number statistics.

[0010] In a possible implementation, the detection thread also detects the link status of the PCIe link where each PCIe device recorded in the first linked list is located in turn, and records the detected link status into the node corresponding to the PCIe device in the first linked list, including: when the detection thread detects the link status of the PCIe link where any PCIe device recorded in the first linked list is located, reads the device identification of the PCIe device from the node corresponding to the PCIe device in the first linked list, accesses the PCIe device according to the read device identification, reads the maximum transmission width and maximum transmission rate of the PCIe device, and the actual transmission width and actual transmission rate of the PCIe device; finds the opposite device of the PCIe link where the PCIe device is located according to the read device identification, accesses the opposite device, and reads the maximum transmission width and maximum transmission rate of the opposite device. rate; calculating the maximum transmission width and maximum transmission rate of the PCIe link where the PCIe device is located according to the maximum transmission width and maximum transmission rate of the PCIe device and the maximum transmission width and maximum transmission rate of the opposite device; judging whether the link state of the PCIe link where the PCIe device is located meets expectations according to the actual transmission width and actual transmission rate of the PCIe device and the maximum transmission width and maximum transmission rate of the PCIe link where the PCIe device is located; when the link state of the PCIe link where the PCIe device is located does not meet expectations, recording the actual transmission width and actual transmission rate of the PCIe device as the link state of the PCIe link where the PCIe device is located in the first linked list at the node corresponding to the PCIe device; and continuing to detect the link state of the PCIe link where the next PCIe device recorded in the first linked list is located.

[0011] In one possible implementation, the central processing unit also runs an information collection script. After the detection thread is created, the method also includes: creating an interactive node, the interactive node supports interaction between user state and kernel state; in response to the information collection function being turned on, executing the information collection script, so that the interactive node obtains the error information of each PCIe device in the first linked list, the link status of the PCIe link where the PCIe device is located, and obtains the system information and system logs stored in the system in the user state; in response to the PCIe device detection function being turned off, deregistering the interactive node.

[0012] In a possible implementation, when any detection-related device has a downlink port error interception function and an error reporting function, the method further includes: before clearing the error of the detection-related device, turning off the downlink port error interception function and the error reporting function of the detection-related device.

[0013] In one possible implementation, the method further includes: before shutting down the downstream port error interception function and the error reporting function of the detection-related device, saving the status of the registers related to error detection on each PCIe device expected to be detected in a first file; in response to the PCIe device detection function being shut down, restoring the status of the registers related to error detection on each PCIe device expected to be detected to the status before shutting down the downstream port error interception function and the error reporting function of the detection-related device according to the first file.

[0014] According to another aspect of the present disclosure, a PCIe device detection device is provided, the device is used to detect errors of PCIe devices in a system, the device comprising: an establishment module, for establishing a first linked list according to the PCIe devices expected to be detected in response to the PCIe device detection function being turned on, the first linked list comprising a plurality of nodes, information of each PCIe device expected to be detected is stored in the node corresponding to the device in the first linked list; a first determination module, for determining a PCIe link between each PCIe device expected to be detected and a central processor, determining all PCIe devices on the PCIe link as detection-related devices, and clearing errors of the detection-related devices; a detection module, for creating a detection thread and starting the detection thread, the detection thread sequentially detecting whether an error occurs in each PCIe device recorded in the first linked list, and recording the detected error information in the node corresponding to the PCIe device in the first linked list.

[0015] In a possible implementation, the detection thread further detects the link status of each PCIe link where the PCIe device recorded in the first linked list is located in sequence, and records the detected link status into a node corresponding to the PCIe device in the first linked list.

[0016] In a possible implementation, the detection thread detects in turn whether an error occurs in each PCIe device recorded in the first linked list, and records the detected error information in the node corresponding to the PCIe device in the first linked list, including: when the detection thread detects whether an error occurs in any PCIe device recorded in the first linked list, the detection thread reads the device identifier of the PCIe device from the node corresponding to the PCIe device in the first linked list, and accesses the correctable error status register and the uncorrectable error status register of the PCIe device according to the read device identifier; when a correctable error exists in the correctable error status register, the error information of the correctable error is read and recorded in the node corresponding to the PCIe device in the first linked list; when an uncorrectable error exists in the uncorrectable error status register, the error information of the uncorrectable error is read and recorded in the node corresponding to the PCIe device in the first linked list; and continues to detect whether an error occurs in the next PCIe device recorded in the first linked list.

[0017] In a possible implementation, the error information of the correctable error includes the error type, error mask, and error number statistics, and the error information of the uncorrectable error includes the error type, error mask, error level, Header log, and error number statistics.

[0018] In a possible implementation, the detection thread also detects the link status of the PCIe link where each PCIe device recorded in the first linked list is located in turn, and records the detected link status into the node corresponding to the PCIe device in the first linked list, including: when the detection thread detects the link status of the PCIe link where any PCIe device recorded in the first linked list is located, reads the device identification of the PCIe device from the node corresponding to the PCIe device in the first linked list, accesses the PCIe device according to the read device identification, reads the maximum transmission width and maximum transmission rate of the PCIe device, and the actual transmission width and actual transmission rate of the PCIe device; finds the opposite device of the PCIe link where the PCIe device is located according to the read device identification, accesses the opposite device, and reads the maximum transmission width and maximum transmission rate of the opposite device. rate; calculating the maximum transmission width and maximum transmission rate of the PCIe link where the PCIe device is located according to the maximum transmission width and maximum transmission rate of the PCIe device and the maximum transmission width and maximum transmission rate of the opposite device; judging whether the link state of the PCIe link where the PCIe device is located meets expectations according to the actual transmission width and actual transmission rate of the PCIe device and the maximum transmission width and maximum transmission rate of the PCIe link where the PCIe device is located; when the link state of the PCIe link where the PCIe device is located does not meet expectations, recording the actual transmission width and actual transmission rate of the PCIe device as the link state of the PCIe link where the PCIe device is located in the first linked list at the node corresponding to the PCIe device; and continuing to detect the link state of the PCIe link where the next PCIe device recorded in the first linked list is located.

[0019] In one possible implementation, the central processing unit also runs an information collection script, and the device also includes: a creation module, used to create an interactive node after creating a detection thread, and the interactive node supports interaction between user state and kernel state; an execution module, used to execute the information collection script in response to the information collection function being turned on, so that the interactive node obtains the error information of each PCIe device in the first linked list, the link status of the PCIe link where the PCIe device is located, and obtains the system information and system logs stored in the system in the user state; a deregistration module, used to deregister the interactive node in response to the PCIe device detection function being turned off.

[0020] In a possible implementation, the device also includes: a shutdown module, which is used to shut down the downstream port error interception function and error reporting function of any detection-related device before clearing the error of the detection-related device when the detection-related device has the downstream port error interception function and error reporting function.

[0021] In one possible implementation, the device also includes: a saving module, which is used to save the status of registers related to error detection on each PCIe device expected to be detected in a first file before turning off the downstream port error interception function and error reporting function of the detection-related device; and a recovery module, which is used to restore the status of registers related to error detection on each PCIe device expected to be detected to the status before turning off the downstream port error interception function and error reporting function of the detection-related device in response to the PCIe device detection function being turned off, according to the first file.

[0022] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0023] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored, wherein the computer program instructions implement the above method when executed by a processor.

[0024] According to another aspect of the present disclosure, a computer program product is provided, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0025] According to the PCIe device detection method of the embodiment of the present disclosure, when the PCIe device detection function is turned on, a first linked list is established according to the PCIe device expected to be detected, the first linked list includes multiple nodes, and the information of each PCIe device expected to be detected is stored in the node corresponding to the device in the first linked list, so that the first linked list has the ability to store the error information of the PCIe device; by determining the PCIe link between each PCIe device expected to be detected and the central processor, all PCIe devices on the PCIe link are determined as detection-related devices, and the errors of the detection-related devices are cleared, so that the accuracy of error detection can be guaranteed; by creating a detection thread and starting the detection thread, the detection thread sequentially detects whether each PCIe device recorded in the first linked list has an error, and records the detected error information to the node corresponding to the PCIe device in the first linked list, so that the first linked list can realize the statistics of error information. The method does not require the PCIe device to have an error reporting function, which can reduce the requirements of the PCIe device error detection on the ability of the PCIe device, which not only reduces the PCIe device detection cost, but also can realize the error detection of the PCIe device without the error reporting function, and improves the error detection capability. This method does not require enabling interrupts, so there is no need to adapt to different CPU architectures. It does not rely on the support of system firmware and operating coefficient services, greatly reduces the requirements on developer capabilities, and further reduces the cost of PCIe device detection.

[0026] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0028] Figure 1 Shows how error messages are routed in the local mode of the operating system.

[0029] Figure 2 An exemplary application scenario of the PCIe device detection method according to an embodiment of the present disclosure is shown.

[0030] Figure 3 A schematic diagram showing the process of a PCIe device detection method according to an embodiment of the present disclosure.

[0031] Figure 4 A schematic diagram showing an error detection process of a detection thread according to an embodiment of the present disclosure.

[0032] Figure 5 A schematic diagram showing the process of a PCIe device detection method according to an embodiment of the present disclosure.

[0033] Figure 6 A schematic diagram showing a link status detection process of a detection thread according to an embodiment of the present disclosure is shown.

[0034] Figure 7 A schematic diagram showing the functions of an information collection script according to an embodiment of the present disclosure.

[0035] Figure 8 A schematic diagram showing the structure of a PCIe device detection apparatus according to an embodiment of the present disclosure.

[0036] Fig. 9 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0037] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0038] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0039] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0040] The following introduces the existing PCIe device error detection solution.

[0041] Existing PCIe device error detection relies on PCIe error interrupt reporting, which is mainly divided into two types: Firmware First Model and OS Native Model.

[0042] The error detection process in firmware priority mode is as follows:

[0043] 1. System firmware registers an error handler.

[0044] 2. The PCIe device generates an error, which is reported to the CPU through the System Management Interruption (SMI). The CPU calls the error handler to collect error information.

[0045] 3. Clear the error of PCIe device.

[0046] 4. The system firmware generates a non-maskable interrupt (NMI) or a system control interrupt (SCI) to notify the operating system (OS), which can then process the error information.

[0047] The error detection process of the local mode of the operating system is that the PCIe device generates an error and routes the error information to the root port of the root complex through the PCIe link. The root port generates a message signal interrupt (MSI) and reports it to the CPU, triggering the interrupt service function of the AER service. The AER service traverses the PCIe device to obtain the error information of the PCIe device that generated the error.

[0048] Figure 1 Shows how error messages are routed in the local mode of the operating system.

[0049] like Figure 1 As shown, GPU1, GPU2 and PCIe switch are all PCIe devices, P1 and P2 are root ports of the root complex of the CPU, P3 and P5 are ports of the PCIe switch, P4 is a port of GPU1, and P6 is a port of GPU2. Port P1 is connected to port P3 via PCIe link L1, port P2 is connected to port P4 via PCIe link L2, and port P5 is connected to port P6 via PCIe link L3.

[0050] Assuming that the PCIe device generating the error is GPU2, the error information may be generated by GPU2, transmitted to the root complex via PCIe links L3 and L1, and then the root complex reports the interrupt to the CPU.

[0051] Whether it is firmware priority mode or operating system local mode, PCIe devices are required to actively report error information. Therefore, PCIe devices must have an error reporting function, which places high requirements on PCIe devices and increases the error detection cost of PCIe devices. In addition, the firmware priority mode requires the system firmware to enable interrupts to notify the CPU, and the operating system local mode requires the AER service to enable interrupts to notify the CPU. Enabling interrupts requires adaptation to the CPU architecture, which requires very high capabilities of developers, further increasing the error detection cost of PCIe devices. In addition, after the CPU receives an interrupt, it needs to find the corresponding error information in the log to analyze the cause of the error. Since the log only records error information and does not classify and organize errors, in order to achieve error statistics, it is usually necessary to find more information from the log, which increases the time cost.

[0052] The PCIe link status detection process in the prior art is similar to the error detection process, except that the PCIe link status detection relies on the Link Bandwidth Management and Link Autonomous Bandwidth Status interrupts to be reported to the CPU, and the CPU uses the corresponding interrupt processing function to obtain the link status of the PCIe link, including the transmission rate and transmission width of the current PCIe device.

[0053] Therefore, the link status detection of the prior art requires that the PCIe device has the link bandwidth notification capability (LinkBandwidth Notification Capability), which has high requirements for the PCIe device and increases the cost of PCIe link status detection. It is also necessary to enable interrupts through system firmware or through hot plug (Hotplug) service to notify the CPU, and the corresponding interrupt service function needs to be registered. Enabling interrupts requires adaptation to the CPU architecture, which requires very high capabilities of developers, which further increases the cost of PCIe device link status detection. In addition, the prior art can only obtain the transmission rate and transmission width of the current PCIe device, and cannot provide information about the devices at both ends of the PCIe link, and cannot provide statistical functions and historical records. If information is found from the log for statistics, it will increase the time cost.

[0054] In view of this, the present disclosure proposes a PCIe device detection method, apparatus, electronic device and storage medium. The PCIe device detection method of the present disclosure can reduce the requirements of PCIe device error detection on the capabilities of PCIe devices and developer capabilities, thereby reducing the cost of PCIe device error detection.

[0055] Furthermore, the method can also realize PCIe link status detection, and reduce the requirements of PCIe link status detection on the capabilities of PCIe devices and the capabilities of developers, thereby reducing the cost of PCIe link status detection.

[0056] Furthermore, the method can also realize one-click information collection through scripts, eliminating the need for manual log collection and reducing labor costs.

[0057] Figure 2 An exemplary application scenario of the PCIe device detection method according to an embodiment of the present disclosure is shown.

[0058] like Figure 2 As shown, the PCIe device detection method of the embodiment of the present disclosure can be executed by a CPU in a system. The system can be a terminal device or a server including a CPU and multiple PCIe devices.

[0059] exist Figure 2 In the example, GPU1, GPU2 and PCIe switch are all PCIe devices, P1 and P2 are root ports of the root complex of the CPU, P3 and P5 are ports of the PCIe switch, P4 is a port of GPU1, and P6 is a port of GPU2. Port P1 is connected to port P3 via PCIe link L1, port P2 is connected to port P4 via PCIe link L2, and port P5 is connected to port P6 via PCIe link L3. Those skilled in the art should understand that in actual applications, the system may include more or fewer PCIe devices, and the present disclosure does not limit the type and quantity of PCIe devices included in the system.

[0060] Any PCIe device can be used as a PCIe device to be detected. The CPU executes the PCIe device detection method. When the PCIe device detection function is turned on, the PCIe device to be detected can be directly accessed to obtain the error information stored in a specific register on the PCIe device (such as the correctable error status register and the uncorrectable error status register described below), and record it in a linked list (such as the first linked list described below). Furthermore, the transmission width, transmission rate and other information of the PCIe device can also be obtained, and based on this, the link status of the PCIe link where the PCIe device is located is determined, and the link status is also recorded in the linked list.

[0061] When the information collection function is enabled, the CPU can collect error information, link status, system information, and system logs with one click, and store them in categories for later use.

[0062] Those skilled in the art will understand that Figure 2In the example, the CPU that executes the PCIe device detection method can communicate with the PCIe device via the PCIe method. In actual applications, the CPU that executes the PCIe device detection method can also communicate with the PCIe device via other methods other than the PCIe method. The present disclosure does not limit whether the CPU that executes the PCIe device detection method must communicate with the PCIe device via the PCIe method.

[0063] Figure 3 A schematic diagram showing the process of a PCIe device detection method according to an embodiment of the present disclosure.

[0064] like Figure 3 As shown, in a possible implementation, the method is used to detect an error of a PCIe device in a system, and the method includes:

[0065] Step S31, in response to the PCIe device detection function being turned on, a first linked list is established according to the PCIe devices to be detected, the first linked list comprising a plurality of nodes, and information of each PCIe device to be detected is stored in a node corresponding to the device in the first linked list;

[0066] Step S32, determining a PCIe link between each PCIe device to be detected and the central processor, determining all PCIe devices on the PCIe link as detection-related devices, and clearing errors of the detection-related devices;

[0067] Step S33, creating and starting a detection thread, the detection thread sequentially detects whether an error occurs in each PCIe device recorded in the first linked list, and records the detected error information into a node corresponding to the PCIe device in the first linked list.

[0068] For example, the CPU may run a PCIe device detection tool, which may be in software form. The tool may be started and closed by a user operation, and when the tool is started, the PCIe device detection function is turned on, and when the tool is closed, the PCIe device detection function is turned off.

[0069] In response to the PCIe device detection function being enabled, the CPU may execute step S31 to establish a first linked list according to the PCIe devices to be detected. The first linked list may include multiple nodes, and information of each PCIe device to be detected is stored in the node corresponding to the device in the first linked list.

[0070] The CPU can establish the first linked list in a variety of ways. In one example, the CPU can traverse the PCIe devices in the system and add the information of each PCIe device to the second linked list. The second linked list can include multiple nodes, and the information of each PCIe device in the system is stored in the node corresponding to the device in the second linked list. The user can pre-store the identifier of the PCIe device to be detected in a configuration file visible to the CPU. The CPU can determine the identifier of the PCIe device to be detected by reading the configuration file, and according to the read identifier, find the information of the PCIe device including the same identifier from the second linked list, that is, the information of the PCIe device to be detected, and add the information of the PCIe device to be detected to the first linked list.

[0071] Among them, the information of the PCIe device may include the inherent properties of the PCIe device, the error information of the PCIe device, the link status of the PCIe link where the PCIe device is located, etc. The inherent properties of the PCIe device include the identification of the PCIe device. The error information of the PCIe device includes the error type, error mask, error number statistics, and optionally, may also include error level, Headerlog (transaction header indicating errors), etc. The link status of the PCIe link where the PCIe device is located may include the actual transmission rate, actual transmission width, maximum transmission rate, maximum transmission width, etc. of the PCIe device. The embodiments of the present disclosure do not limit the specific content included in the information of the PCIe device. In this case, the information stored in the linked list is more complete.

[0072] In another example, the CPU can determine the identifier of the PCIe device to be detected by reading a configuration file, and traverse the PCIe devices in the system. When the identifier of the current PCIe device is the same as the identifier of the PCIe device to be detected, it is determined that the current PCIe device is the PCIe device to be detected, and the information of the current PCIe device is added to the first linked list. In this case, the linked list occupies fewer resources.

[0073] Those skilled in the art should understand that as long as a first linked list including multiple nodes can be established so that the information of each PCIe device to be detected is stored in the node corresponding to the device in the first linked list, the embodiments of the present disclosure do not limit the specific method of establishing the first linked list.

[0074] After establishing the first linked list, the CPU may execute step S32 to determine the PCIe link between each PCIe device to be detected and the CPU. The CPU may determine all PCIe devices on the PCIe link as detection-related devices, and clear the errors of the detection-related devices to avoid the historical errors of the detection-related devices from affecting the error detection results of the PCIe devices.

[0075] by Figure 2 For example, the CPU can enumerate PCIe devices through the root complex and determine the topological connection relationship of the PCIe devices. Enumerating PCIe devices and determining the topological connection relationship of PCIe devices can be implemented based on existing technologies and will not be described in detail here. Assuming that GPU2 is the PCIe device to be detected, the CPU can determine that the PCIe link between GPU2 and the CPU can include PCIe link L1 and PCIe link L3 based on the topological connection relationship of the PCIe devices. The PCIe devices on PCIe link L1 include a PCIe switch, and the PCIe devices on PCIe link L3 include a PCIe switch and GPU2, so the PCIe switch and GPU2 can be determined as detection-related devices. The CPU can send an indication to the detection-related device to clear the error. After receiving the indication to clear the error, the detection-related device can clear the error in the register for storing errors included in itself.

[0076] After the errors of the relevant devices are detected and cleared, the CPU can execute step S33, create a detection thread and start the detection thread. The detection thread is also run by the CPU, and the detection thread can detect whether an error occurs in each PCIe device recorded in the first linked list in turn. When an error is detected in the current PCIe device, the detection thread can record the detected error information to the node corresponding to the current PCIe device in the first linked list, and continue to detect whether an error occurs in the next PCIe device recorded in the first linked list, until the errors of each PCIe device recorded in the first linked list are detected. In this case, the error information of all PCIe devices expected to be detected will be recorded in the first linked list, and the error information of the PCIe device can be obtained by directly querying the first linked list for analyzing the cause of the error in the PCIe device, without the need for each PCIe device to actively report the error information or generate an interrupt.

[0077] In order to ensure the accuracy of detection, multiple rounds of error detection can be performed on the PCIe devices in the first linked list. After each round of error detection is completed, the next round of error detection can be started after a period of time. First, it can avoid the detection thread occupying the CPU all the time, and second, it can avoid some frequent errors in a short period of time from affecting the accuracy of error detection.

[0078] According to the PCIe device detection method of the embodiment of the present disclosure, when the PCIe device detection function is turned on, a first linked list is established according to the PCIe device expected to be detected, the first linked list includes multiple nodes, and the information of each PCIe device expected to be detected is stored in the node corresponding to the device in the first linked list, so that the first linked list has the ability to store the error information of the PCIe device; by determining the PCIe link between each PCIe device expected to be detected and the central processor, all PCIe devices on the PCIe link are determined as detection-related devices, and the errors of the detection-related devices are cleared, so that the accuracy of error detection can be guaranteed; by creating a detection thread and starting the detection thread, the detection thread sequentially detects whether each PCIe device recorded in the first linked list has an error, and records the detected error information to the node corresponding to the PCIe device in the first linked list, so that the first linked list can realize the statistics of error information. The method does not require the PCIe device to have an error reporting function, which can reduce the requirements of the PCIe device error detection on the ability of the PCIe device, which not only reduces the PCIe device detection cost, but also can realize the error detection of the PCIe device without the error reporting function, and improves the error detection capability. This method does not require enabling interrupts, so there is no need to adapt to different CPU architectures. It does not rely on the support of system firmware and operating coefficient services, greatly reduces the requirements on developer capabilities, and further reduces the cost of PCIe device detection.

[0079] The following describes an exemplary method for a detection thread to detect whether an error occurs in a PCIe device. Figure 4 A schematic diagram showing an error detection process of a detection thread according to an embodiment of the present disclosure.

[0080] like Figure 4 As shown, in a possible implementation, the detection thread detects in turn whether an error occurs in each PCIe device recorded in the first linked list, and records the detected error information into a node corresponding to the PCIe device in the first linked list, including:

[0081] When the detection thread detects whether any PCIe device recorded in the first linked list has an error, steps S41-S44 are executed:

[0082] Step S41, reading a device identification of the PCIe device from a node corresponding to the PCIe device in the first linked list, and accessing a correctable error status register and an uncorrectable error status register of the PCIe device according to the read device identification;

[0083] Step S42, when a correctable error exists in the correctable error status register, reading error information of the correctable error and recording it into a node corresponding to the PCIe device in the first linked list;

[0084] Step S43, when there is an uncorrectable error in the uncorrectable error status register, reading error information of the uncorrectable error and recording it in a node corresponding to the PCIe device in the first linked list;

[0085] Step S44, continue to detect whether the next PCIe device recorded in the first linked list has an error.

[0086] For example, registers related to error detection on a PCIe device may include a correctable error status register (Correctable Error Status Register), an uncorrectable error status register (Uncorrectable Error Status Register), a correctable error mask register (Correctable Error Mask Register, CEMR), an uncorrectable error mask register (Uncorrectable Error Mask Register, UEMR), an uncorrectable error level register (Uncorrectable Error Severity Register, UESR), an advanced error capability and control register (Advanced Error Capabilities and Control Register, AER), a Header Log Register (Header Log Register), etc.

[0087] The correctable error status register can store correctable errors and corresponding error types. Correctable errors refer to errors that can be automatically recognized and corrected by hardware. Correctable errors can include multiple error types, for example, Receiver Error Status (indicating a receiver error), Bad TLP Status (indicating that the transaction layer data packet (TLP) is damaged), Bad DLLP Status (indicating that the data link layer data packet DLLP is damaged), REPLAY_NUM Rollover Status (indicating that the retransmission counter overflows), Replay Timer Timeout Status (indicating that the retransmission timer has timed out), etc. The error types included in the correctable errors shown above are only examples, and the present disclosure does not limit the error types of correctable errors.

[0088] The uncorrectable error status register can store uncorrectable errors and corresponding error types. Uncorrectable errors refer to errors that cannot be automatically corrected. Uncorrectable errors can include multiple error types, for example, Data Link Protocol Error Status (indicating a data link protocol error), Surprise Down Error Status (indicating an unexpected link disconnection), Poisoned TLP Received (indicating that the received TLP is poisoned), Flow Control Protocol Error Status (indicating a flow control protocol error), Completion Timeout Status (indicating completion timeout), Completer Abort Status (indicating completer abort), Unexpected Completion Status (indicating unexpected completion), Receiver Overflow Status (indicating receiver overflow), Malformed TLP Status (indicating TLP malformation), ECRC Error Status (indicating an end-to-end cyclic redundancy check ECRC error), Unsupported Request Error Status (indicating an unsupported request error), ACS Violation Status (indicating an access control service ACS violation), Uncorrectable Internal Error Status (indicating an uncorrectable internal error), etc. The error types included in the uncorrectable errors shown above are only examples, and the present disclosure does not limit the error types of uncorrectable errors.

[0089] The correctable error mask register can be used to store a mask of a correctable error, which can indicate whether to shield the reporting of the corresponding correctable error when the error is detected. The uncorrectable error mask register can be used to store a mask of an uncorrectable error, which can indicate whether to shield the reporting of the corresponding uncorrectable error when the error is detected.

[0090] The uncorrectable error level register can be used to store the error level (severity) of the uncorrectable error. The error level of the uncorrectable error can be preset, and the uncorrectable error can be divided into fatal error and non-fatal error according to the error level. For example, the unsupported request error status and the completion timeout status can be non-fatal errors among the uncorrectable errors. If the error level is not set, these two error types may be identified as Advisory Non-Fatal Error Status in subsequent analysis, while Advisory Non-Fatal Error Status is a correctable error. Therefore, after setting the error level, the correctable error and the uncorrectable error can be distinguished by whether there is an error level to avoid errors in the record.

[0091] The advanced error capability and control register can be used to record whether the PCIe device has a downstream port error interception (Downstream Port Containment, DPC) function and an error reporting function, and whether the downstream port error interception function and the error reporting function are enabled.

[0092] The Header log register can be used to store the packet header of the TLP in which the error occurred. This information can be used for error analysis and debugging.

[0093] For the detection thread, when it is detected whether an error occurs in any PCIe device recorded in the first linked list, the device identification of the PCIe device can be read from the node corresponding to the PCIe device in the first linked list, and the correctable error status register and uncorrectable error status register of the PCIe device can be accessed according to the read device identification.

[0094] When there is a correctable error in the correctable error status register, the error information of the correctable error can be read, the error information can be printed, and recorded in the node corresponding to the PCIe device in the first linked list. When there is an uncorrectable error in the uncorrectable error status register, the error information of the uncorrectable error can be read, the error information can be printed, and recorded in the node corresponding to the PCIe device in the first linked list. In any node of the first linked list, the error information of the correctable error and the error information of the uncorrectable error can be recorded separately. The error information of the correctable error can be read from the register related to the correctable error (for example, the correctable error status register, the correctable error mask register, etc.). The error information of the uncorrectable error can be read from the register related to the uncorrectable error (for example, the uncorrectable error status register, the uncorrectable error mask register, the uncorrectable error level register, the Header log register, etc.). Exemplary contents of the error information of the correctable error and the error information of the uncorrectable error are given later.

[0095] After the error record of the current PCIe device is completed, the same method may be used to continue detecting whether the next PCIe device recorded in the first linked list has an error.

[0096] In a possible implementation, the error information of the correctable error includes the error type, error mask, and error number statistics, and the error information of the uncorrectable error includes the error type, error mask, error level, Header log, and error number statistics.

[0097] For example, the error information of the correctable error may include the error type read from the correctable error status register and the error mask read from the correctable error mask register. According to the number of error masks, the number of errors can be determined as the error number statistics of the correctable errors. The error type of the correctable error can refer to the example given above. Optionally, it can also include the identification of the PCIe device that generated the error, etc. It should be understood by those skilled in the art that as long as it is information related to the correctable error, it can be used as the error information of the correctable error, and the present disclosure does not limit the specific content included in the error information of the correctable error.

[0098] The error information of the uncorrectable error may include the error type read from the uncorrectable error status register, the error mask read from the uncorrectable error mask register, the error level read from the uncorrectable error level register, and the header log read from the header log register. The error type, error mask, error level, and header log of the uncorrectable error have been described above and will not be repeated here.

[0099] Optionally, the error information of the uncorrectable error may also include an identifier of the PCIe device that generates the error, etc. Those skilled in the art should understand that any information related to the uncorrectable error can be used as the error information of the uncorrectable error, and the present disclosure does not limit the specific content of the error information of the uncorrectable error.

[0100] In a possible implementation manner, when any detection-related device has a downstream port error interception function and an error reporting function, the method further includes:

[0101] Before clearing the error of the detection-related device, disable the downlink port error interception function and error reporting function of the detection-related device.

[0102] For example, if the PCIe device has the Downstream Port Containment (DPC) function and the error reporting (error report) function, then the PCIe device may automatically report the error, which conflicts with the work of the detection thread. In this case, before clearing the error of the detection-related device, you can first query whether the detection-related device has the downstream port error interception function and the error reporting function. When any detection-related device has the downstream port error interception function and the error reporting function, turn off the downstream port error interception function and the error reporting function of the detection-related device. For detection-related devices that do not have the downstream port error interception function and the error reporting function, no additional processing is required.

[0103] In this way, the accuracy of the error information recorded in the first linked list can be guaranteed.

[0104] In a possible implementation, the method further includes:

[0105] Before disabling the downstream port error interception function and the error reporting function of the detection-related device, the state of the register related to the error detection on each PCIe device to be detected is saved in the first file;

[0106] In response to the PCIe device detection function being turned off, according to the first file, the state of the registers related to error detection on each PCIe device expected to be detected is restored to the state before the downstream port error interception function and error reporting function of the detection-related device are turned off.

[0107] For example, in some application scenarios, the user may hope that after the PCIe device detection function is turned off, the state of the registers related to error detection on the PCIe device is consistent with that before the PCIe device detection function is turned on. Examples of registers related to error detection on the PCIe device have been described above and will not be repeated here. Since turning off the downstream port error interception function and the error reporting function of the detection-related device will change the state of the above registers, the state of the registers related to error detection on each PCIe device expected to be detected can be saved in the first file before turning off the downstream port error interception function and the error reporting function of the detection-related device. After the PCIe device detection function is turned off, according to the first file, the state of the registers related to error detection on each PCIe device expected to be detected can be restored to the state before turning off the downstream port error interception function and the error reporting function of the detection-related device. In this case, after the PCIe device detection function is turned off, the state of the registers related to error detection on the PCIe device is consistent with that before the PCIe device detection function is turned on.

[0108] Optionally, the state of the registers related to error detection on each PCIe device expected to be detected can be first saved in the first file, and when the current PCIe device is used as a detection-related device, it is determined whether the current PCIe device has the downstream port error interception function and the error reporting function according to the state of the advanced error capability and the control register. When it is determined that the current PCIe device has the downstream port error interception function and the error reporting function, it can also be further determined whether the downstream port error interception function and the error reporting function are turned on according to the state of the advanced error capability and the control register. When the current PCIe device has the downstream port error interception function and the error reporting function, and the corresponding function is turned on, the downstream port error interception function and the error reporting function of the current PCIe device are turned off. In this case, before the detection thread is started, it is sufficient to traverse the PCIe devices in the system once, which can reduce the data access cost.

[0109] The PCIe device detection method disclosed in the present invention can also implement link status detection of the PCIe link where the PCIe device is located. Figure 5 A schematic diagram showing the process of a PCIe device detection method according to an embodiment of the present disclosure.

[0110] like Figure 5 As shown, in a possible implementation, the detection thread also detects the link status of the PCIe link where each PCIe device recorded in the first linked list is located in turn, and records the detected link status into the node corresponding to the PCIe device in the first linked list.

[0111] For example, in addition to recording the error information of the PCIe device, the first linked list may also record the link status of the PCIe link where the PCIe device is located. The detection thread may detect the link status of the PCIe link where each PCIe device recorded in the first linked list is located in turn, and record the detected link status to the node corresponding to the PCIe device in the first linked list. The detection thread may start the error detection and link status of the next PCIe device after completing the error detection and link status detection of one PCIe device. In another example, the detection thread may perform error detection and link status detection of the PCIe device separately, start the error detection of the next PCIe device after the error detection of the current PCIe device is completed, and start the link status detection of the next PCIe device after the link status detection of the current PCIe device is completed. The disclosed embodiments do not limit the order of error detection and link status detection.

[0112] A PCIe device may belong to multiple PCIe links. Figure 2 For example, the PCIe switch belongs to PCIe link L1 and PCIe link L3. If the PCIe switch is used as the PCIe device to be detected, the link status of PCIe link L1 and PCIe link L3 need to be detected. Since PCIe link L3 also includes GPU2, the link status of PCIe link L3 may have been detected when detecting the link status of the link where GPU2 is located. In this case, in order to avoid repeated detection, before detecting the link status of any PCIe link, it is possible to query whether the first linked list has stored the link status of the PCIe link. If the first linked list has stored the link status of the PCIe link, it is not necessary to detect the link status of the PCIe link again. If the first linked list does not store the link status of the PCIe link, then detect the link status of the PCIe link. After the link status of all PCIe links where a certain PCIe device is located has been detected and stored in the first linked list, start detecting the link status of the PCIe link where the next PCIe device is located.

[0113] An exemplary method for a detection thread to detect the link status of a PCIe link is described below. Figure 6 A schematic diagram showing a link status detection process of a detection thread according to an embodiment of the present disclosure is shown.

[0114] like Figure 6 As shown, in a possible implementation, the detection thread further detects the link status of each PCIe link where the PCIe device recorded in the first linked list is located in turn, and records the detected link status into the node corresponding to the PCIe device in the first linked list, including:

[0115] When the detection thread detects the link status of the PCIe link where any PCIe device recorded in the first linked list is located,

[0116] Step S61, reading a device identification of the PCIe device from a node corresponding to the PCIe device in the first linked list, accessing the PCIe device according to the read device identification, and reading a maximum transmission width and a maximum transmission rate of the PCIe device, as well as an actual transmission width and an actual transmission rate of the PCIe device;

[0117] Step S62, finding the peer device of the PCIe link where the PCIe device is located according to the read device identifier, accessing the peer device, and reading the maximum transmission width and maximum transmission rate of the peer device;

[0118] Step S63, calculating the maximum transmission width and maximum transmission rate of the PCIe link where the PCIe device is located according to the maximum transmission width and maximum transmission rate of the PCIe device and the maximum transmission width and maximum transmission rate of the peer device;

[0119] Step S64, judging whether the link state of the PCIe link where the PCIe device is located meets expectations according to the actual transmission width and actual transmission rate of the PCIe device and the maximum transmission width and maximum transmission rate of the PCIe link where the PCIe device is located;

[0120] Step S65, when the link status of the PCIe link where the PCIe device is located does not meet expectations, the actual transmission width and the actual transmission rate of the PCIe device are recorded as the link status of the PCIe link where the PCIe device is located in the node corresponding to the PCIe device in the first linked list;

[0121] Step S66, continue to detect the link status of the PCIe link where the next PCIe device recorded in the first linked list is located.

[0122] For example, when the detection thread detects the link status of the PCIe link where any PCIe device recorded in the first linked list is located, it can first read the device identifier of the PCIe device to be detected from the node corresponding to the PCIe device in the first linked list, access the PCIe device to be detected according to the read device identifier, and read the maximum transmission width and maximum transmission rate of the PCIe device to be detected, as well as the actual transmission width and actual transmission rate of the PCIe device to be detected.

[0123] The PCIe device to be detected may include at least one port, and at least one PCIe link (i.e., the PCIe link where the PCIe device is located) is connected through the at least one port. When detecting the link status of the PCIe link where the PCIe device to be detected is located, the PCIe link that has not been detected can be first determined as the PCIe link to be detected, and the link status of the PCIe link to be detected can be detected in turn. Therefore, when accessing the PCIe device to be detected, it is only necessary to read the maximum transmission width, maximum transmission rate, actual transmission width, and actual transmission rate of the port on the PCIe device to be detected that is connected to the PCIe link to be detected.

[0124] by Figure 2 For example, assuming that PCIe link L3 is an undetected PCIe link, when detecting the link status of the PCIe link where GPU2 is located, the maximum transmission width, maximum transmission rate, actual transmission width, and actual transmission rate of port P6 can be read.

[0125] Assuming that PCIe links L1 and L3 are undetected PCIe links, when detecting the link status of the PCIe link where the PCIe switch is located, the maximum transmission width, maximum transmission rate, actual transmission width, and actual transmission rate of ports P3 and P5 can be read respectively.

[0126] The detection thread can find out the opposite device of the PCIe link where the PCIe device to be detected is located according to the read device identifier, access the opposite device, and read the maximum transmission width and maximum transmission rate of the opposite device. Among them, finding out the opposite device of the PCIe link where the PCIe device to be detected is located can be for each PCIe link to be detected where the PCIe device to be detected is located, find out the opposite device of the PCIe device to be detected in the PCIe link.

[0127] The peer device may also be connected to multiple PCIe links through multiple ports, so reading the maximum transmission width and maximum transmission rate of the peer device may be reading the maximum transmission width and maximum transmission rate of the port on the peer device connected to the PCIe link to be detected.

[0128] by Figure 2 For example, assuming that PCIe link L3 is an undetected PCIe link, when detecting the link status of the PCIe link where GPU2 is located, the peer device accessed for PCIe link L3 can be a PCIe switch, and the maximum transmission width and maximum transmission rate of port P5 are read.

[0129] Assuming that PCIe links L1 and L3 are undetected PCIe links, when detecting the link status of the PCIe link where the PCIe switch is located, the peer device accessed for PCIe link L3 may be GPU2, and the maximum transmission width and maximum transmission rate of port P6 are read. The peer device accessed for PCIe link L1 may be the root complex of the CPU, and the maximum transmission width and maximum transmission rate of port P1 are read.

[0130] The detection thread can calculate the maximum transmission width and maximum transmission rate of the PCIe link where the PCIe device to be detected is located according to the maximum transmission width and maximum transmission rate of the PCIe device to be detected, as well as the maximum transmission width and maximum transmission rate of the opposite device. Wherein, for each PCIe link to be detected connected to the PCIe device to be detected, the maximum transmission width and maximum transmission rate of the PCIe link can be calculated according to the maximum transmission width and maximum transmission rate of the port of the PCIe device to be detected connected to the PCIe link, as well as the maximum transmission width and maximum transmission rate of the port of the opposite device connected to the PCIe link, and the maximum transmission width of the PCIe link is equal to the smaller of the maximum transmission width of the port of the PCIe device to be detected connected to the PCIe link and the maximum transmission width of the port of the opposite device connected to the PCIe link, and the maximum transmission rate of the PCIe link is equal to the smaller of the maximum transmission rate of the port of the PCIe device to be detected connected to the PCIe link and the maximum transmission rate of the port of the opposite device connected to the PCIe link.

[0131] by Figure 2 For example, assuming that PCIe link L3 is an undetected PCIe link, when detecting the link status of the PCIe link where GPU2 is located, the maximum transmission width and maximum transmission rate of PCIe link L3 can be calculated, and the maximum transmission width of PCIe link L3 can be equal to the smaller of the maximum transmission width of port P5 and the maximum transmission width of port P6, and the maximum transmission rate of PCIe link L3 can be equal to the smaller of the maximum transmission rate of port P5 and the maximum transmission rate of port P6.

[0132] Assuming that PCIe links L1 and L3 are undetected PCIe links, when detecting the link status of the PCIe link where the PCIe switch is located, the maximum transmission width and maximum transmission rate of PCIe links L1 and L3 can be calculated. Among them, the maximum transmission width of PCIe link L1 can be equal to the smaller of the maximum transmission width of port P1 and the maximum transmission width of port P3, and the maximum transmission rate of PCIe link L1 can be equal to the smaller of the maximum transmission rate of port P1 and the maximum transmission rate of port P3. The maximum transmission width of PCIe link L3 can be equal to the smaller of the maximum transmission width of port P5 and the maximum transmission width of port P6, and the maximum transmission rate of PCIe link L3 can be equal to the smaller of the maximum transmission rate of port P5 and the maximum transmission rate of port P6.

[0133] The user can pre-set a proportionality coefficient. When the ratio of the actual transmission width of the PCIe link to the maximum transmission width is greater than the proportionality coefficient and the ratio of the actual transmission rate of the PCIe link to the maximum transmission rate is also greater than the proportionality coefficient, it is considered that the link state of the PCIe link has reached the expectation. It should be understood that the actual transmission width and actual transmission rate of the PCIe device to be detected are the actual transmission width and actual transmission rate of the PCIe link where the PCIe device to be detected is located. The detection thread can judge whether the link state of the PCIe link where the PCIe device to be detected is located has reached the expectation based on the actual transmission width and actual transmission rate of the PCIe device to be detected, and the maximum transmission width and maximum transmission rate of the PCIe link where the PCIe device to be detected is located. Among them, it can be judged whether the link state of the PCIe link to be detected is reached according to the maximum transmission width and maximum transmission rate of the port of the PCIe device to be detected connected to any PCIe link to be detected, and the actual transmission width and actual transmission rate of the port of the PCIe device to be detected connected to the PCIe link to be detected.

[0134] by Figure 2 For example, assuming that PCIe link L3 is an undetected PCIe link, when detecting the link status of the PCIe link where GPU2 is located, it can be determined whether the link status of PCIe link L3 meets expectations based on the actual transmission rate and actual transmission width of port P6 of GPU2 and the maximum transmission rate and maximum transmission width of PCIe link L3.

[0135] Assuming that PCIe links L1 and L3 are undetected PCIe links, when detecting the link status of the PCIe link where the PCIe switch is located, it can be determined whether the link status of PCIe link L1 meets expectations based on the actual transmission rate and actual transmission width of port P3 of the PCIe switch, and the maximum transmission rate and maximum transmission width of PCIe link L1. It can be determined whether the link status of PCIe link L3 meets expectations based on the actual transmission rate and actual transmission width of port P5 of the PCIe switch, and the maximum transmission rate and maximum transmission width of PCIe link L3.

[0136] When the link status of the PCIe link where the PCIe device is located does not meet expectations, the detection thread can record the actual transmission width and actual transmission rate of the PCIe device to be detected as the link status of the PCIe link where the PCIe device to be detected is located in the node corresponding to the PCIe device to be detected in the first linked list. If the PCIe device to be detected has multiple ports connected to multiple PCIe links, when recording the link status of the PCIe link, the identifier of the PCIe link can also be recorded accordingly, so that the link status of a specific PCIe link can be accurately read from the first linked list.

[0137] Furthermore, the number of times the link status of the PCIe link where the PCIe device to be detected is located fails to reach the expected state can also be recorded at the node corresponding to the PCIe device to be detected in the first linked list, so that the user can quickly find which PCIe links have worse link status. The PCIe link that fails to reach the expected state more times has worse link status.

[0138] After the link status of all PCIe links of the PCIe device to be detected is detected, the link status of the PCIe link of the next PCIe device recorded in the first linked list can continue to be detected until the link status of the PCIe links of all PCIe devices recorded in the first linked list is detected.

[0139] In this way, the PCIe device detection method of the embodiment of the present disclosure can also realize PCIe link status detection, and reduce the requirements of PCIe link status detection on the capabilities of PCIe devices and developer capabilities, thereby reducing the cost of PCIe link status detection.

[0140] In a possible implementation, the central processor further runs an information collection script, and after creating a detection thread, the method further includes:

[0141] Create interactive nodes, which support interaction between user mode and kernel mode;

[0142] In response to the information collection function being turned on, executing the information collection script, so that the interactive node obtains error information of each PCIe device in the first linked list, the link status of the PCIe link where the PCIe device is located, and obtains system information and system logs stored in the system in the user mode;

[0143] In response to the PCIe device detection function being turned off, the interactive node is deregistered.

[0144] For example, under the premise that the PCIe device detection function is enabled, you can use the information collection script to realize one-click collection of error information, link status, system information, and system logs. The above information needs to be obtained in user mode and transmitted to kernel mode. Therefore, after creating the detection thread, you can also create an interactive node and allocate certain resources to the interactive node, so that the interactive node can be used to store error information, link status, system information, system logs, and support interaction between user mode and kernel mode.

[0145] When the user wants to collect error information, link status, system information, and system logs, the information collection function can be enabled. In response to the information collection function being enabled, the CPU can execute an information collection script. Figure 7 A schematic diagram showing the functions of an information collection script according to an embodiment of the present disclosure.

[0146] like Figure 7 As shown, after the information collection script starts executing, the interactive node can be entered, and the interactive node can obtain the error information of each PCIe device in the first linked list, the link status of the PCIe link where the PCIe device is located, and the system information and system logs stored in the system in the user state.

[0147] Among them, the system information may include PCIe information, interrupt information, CPU information, input and output interface information (ioport), input and output memory space (iomem), operating system version, command line (cmdline) configuration, memory information (meminfo), direct memory interface (Direct Memory Interface, DMI) (basic input and output system, system, motherboard, processor, memory, cache), etc. The system log may include kern.log files and syslog files, etc. The embodiments of the present disclosure do not limit the specific content of the collected system information and the file format of the collected system log.

[0148] Furthermore, the collected information can be classified, packaged and stored on the interactive node to facilitate information retrieval.

[0149] When the PCIe device detection function is turned off, the CPU can deregister the interactive node, and the resources allocated to the interactive node and the resources occupied by the first linked list are released. When the PCIe device detection function is turned on again, the interactive node can be recreated.

[0150] In this way, the PCIe device detection method disclosed in the present invention can also realize one-click information collection through scripts, without the need for manual log collection, thereby reducing labor costs.

[0151] The present disclosure also provides a PCIe device detection device, Figure 8 A schematic diagram showing the structure of a PCIe device detection apparatus according to an embodiment of the present disclosure.

[0152] like Figure 8 As shown, in a possible implementation, the device is used to detect an error of a PCIe device in a system, and the device includes:

[0153] An establishing module 81 is used for establishing a first linked list according to the PCIe devices expected to be detected in response to the PCIe device detection function being turned on, wherein the first linked list includes a plurality of nodes, and information of each PCIe device expected to be detected is stored in a node corresponding to the device in the first linked list;

[0154] A first determination module 82 is used to determine a PCIe link between each PCIe device to be detected and the central processor, determine all PCIe devices on the PCIe link as detection-related devices, and clear errors of the detection-related devices;

[0155] The detection module 83 is used to create a detection thread and start the detection thread. The detection thread detects whether each PCIe device recorded in the first linked list has an error in turn, and records the detected error information to the node corresponding to the PCIe device in the first linked list.

[0156] In a possible implementation, the detection thread further detects the link status of each PCIe link where the PCIe device recorded in the first linked list is located in sequence, and records the detected link status into a node corresponding to the PCIe device in the first linked list.

[0157] In a possible implementation, the detection thread detects in turn whether an error occurs in each PCIe device recorded in the first linked list, and records the detected error information in the node corresponding to the PCIe device in the first linked list, including: when the detection thread detects whether an error occurs in any PCIe device recorded in the first linked list, the detection thread reads the device identifier of the PCIe device from the node corresponding to the PCIe device in the first linked list, and accesses the correctable error status register and the uncorrectable error status register of the PCIe device according to the read device identifier; when a correctable error exists in the correctable error status register, the error information of the correctable error is read and recorded in the node corresponding to the PCIe device in the first linked list; when an uncorrectable error exists in the uncorrectable error status register, the error information of the uncorrectable error is read and recorded in the node corresponding to the PCIe device in the first linked list; and continues to detect whether an error occurs in the next PCIe device recorded in the first linked list.

[0158] In a possible implementation, the error information of the correctable error includes the error type, error mask, and error number statistics, and the error information of the uncorrectable error includes the error type, error mask, error level, Header log, and error number statistics.

[0159] In a possible implementation, the detection thread also detects the link status of the PCIe link where each PCIe device recorded in the first linked list is located in turn, and records the detected link status into the node corresponding to the PCIe device in the first linked list, including: when the detection thread detects the link status of the PCIe link where any PCIe device recorded in the first linked list is located, reads the device identification of the PCIe device from the node corresponding to the PCIe device in the first linked list, accesses the PCIe device according to the read device identification, reads the maximum transmission width and maximum transmission rate of the PCIe device, and the actual transmission width and actual transmission rate of the PCIe device; finds the opposite device of the PCIe link where the PCIe device is located according to the read device identification, accesses the opposite device, and reads the maximum transmission width and maximum transmission rate of the opposite device. rate; calculating the maximum transmission width and maximum transmission rate of the PCIe link where the PCIe device is located according to the maximum transmission width and maximum transmission rate of the PCIe device and the maximum transmission width and maximum transmission rate of the opposite device; judging whether the link state of the PCIe link where the PCIe device is located meets expectations according to the actual transmission width and actual transmission rate of the PCIe device and the maximum transmission width and maximum transmission rate of the PCIe link where the PCIe device is located; when the link state of the PCIe link where the PCIe device is located does not meet expectations, recording the actual transmission width and actual transmission rate of the PCIe device as the link state of the PCIe link where the PCIe device is located in the first linked list at the node corresponding to the PCIe device; and continuing to detect the link state of the PCIe link where the next PCIe device recorded in the first linked list is located.

[0160] In one possible implementation, the central processing unit also runs an information collection script, and the device also includes: a creation module, used to create an interactive node after creating a detection thread, and the interactive node supports interaction between user state and kernel state; an execution module, used to execute the information collection script in response to the information collection function being turned on, so that the interactive node obtains the error information of each PCIe device in the first linked list, the link status of the PCIe link where the PCIe device is located, and obtains the system information and system logs stored in the system in the user state; a deregistration module, used to deregister the interactive node in response to the PCIe device detection function being turned off.

[0161] In a possible implementation, the device also includes: a shutdown module, which is used to shut down the downstream port error interception function and error reporting function of any detection-related device before clearing the error of the detection-related device when the detection-related device has the downstream port error interception function and error reporting function.

[0162] In one possible implementation, the device also includes: a saving module, which is used to save the status of registers related to error detection on each PCIe device expected to be detected in a first file before turning off the downstream port error interception function and error reporting function of the detection-related device; and a recovery module, which is used to restore the status of registers related to error detection on each PCIe device expected to be detected to the status before turning off the downstream port error interception function and error reporting function of the detection-related device in response to the PCIe device detection function being turned off, according to the first file.

[0163] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0164] The embodiment of the present disclosure also provides a computer-readable storage medium on which computer program instructions are stored, and the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0165] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0166] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0167] Fig. 9 1 is a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 may be provided as a server or a terminal device. Fig. 9 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0168] The electronic device 1900 may also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958 (I / O interface). The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as Windows Server 2003. TM , Mac OS X TM , Unix TM ,Linux TM , FreeBSD TM or similar.

[0169] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions, which can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0170] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0171] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0172] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0173] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0174] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0175] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0176] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0177] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0178] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A PCIe device detection method, characterized in that: The method is used to detect an error of a PCIe device in a system, and the method comprises: In response to the PCIe device detection function being turned on, a first linked list is established according to the PCIe devices expected to be detected, the first linked list comprising a plurality of nodes, and information of each PCIe device expected to be detected is stored in a node corresponding to the device in the first linked list; Determine a PCIe link between each PCIe device to be detected and the central processor, determine all PCIe devices on the PCIe link as detection-related devices, and clear errors of the detection-related devices; A detection thread is created and started, wherein the detection thread detects in turn whether each PCIe device recorded in the first linked list has an error, and records the detected error information into a node in the first linked list corresponding to the PCIe device.

2. The method according to claim 1, characterized in that The detection thread also detects the link status of each PCIe link where the PCIe device recorded in the first linked list is located in turn, and records the detected link status into a node in the first linked list corresponding to the PCIe device.

3. The method according to claim 1, characterized in that The detection thread detects in sequence whether each PCIe device recorded in the first linked list has an error, and records the detected error information into a node corresponding to the PCIe device in the first linked list, including: When the detection thread detects whether any PCIe device recorded in the first linked list has an error, Reading a device identification of the PCIe device from a node corresponding to the PCIe device in the first linked list, and accessing a correctable error status register and an uncorrectable error status register of the PCIe device according to the read device identification; When a correctable error exists in the correctable error status register, error information of the correctable error is read and recorded in a node corresponding to the PCIe device in the first linked list; When an uncorrectable error exists in the uncorrectable error status register, error information of the uncorrectable error is read and recorded in a node corresponding to the PCIe device in the first linked list; Continue to detect whether the next PCIe device recorded in the first linked list has an error.

4. The method according to claim 3, characterized in that: The error information of correctable errors includes error type, error mask, and error count. The error information of uncorrectable errors includes error type, error mask, error level, Header log, and error count.

5. The method according to claim 2, characterized in that: The detection thread further detects the link status of each PCIe link where the PCIe device recorded in the first linked list is located in turn, and records the detected link status into a node corresponding to the PCIe device in the first linked list, including: When the detection thread detects the link status of the PCIe link where any PCIe device recorded in the first linked list is located, Reading a device identification of the PCIe device from a node corresponding to the PCIe device in the first linked list, accessing the PCIe device according to the read device identification, and reading a maximum transmission width and a maximum transmission rate of the PCIe device, as well as an actual transmission width and an actual transmission rate of the PCIe device; Find out the peer device of the PCIe link where the PCIe device is located according to the read device identification, access the peer device, and read the maximum transmission width and maximum transmission rate of the peer device; Calculate the maximum transmission width and maximum transmission rate of the PCIe link where the PCIe device is located according to the maximum transmission width and maximum transmission rate of the PCIe device and the maximum transmission width and maximum transmission rate of the opposite device; According to the actual transmission width and the actual transmission rate of the PCIe device and the maximum transmission width and the maximum transmission rate of the PCIe link where the PCIe device is located, determining whether the link state of the PCIe link where the PCIe device is located meets expectations; When the link state of the PCIe link where the PCIe device is located does not meet expectations, recording the actual transmission width and the actual transmission rate of the PCIe device as the link state of the PCIe link where the PCIe device is located in the node corresponding to the PCIe device in the first linked list; Continue to detect the link status of the PCIe link where the next PCIe device recorded in the first linked list is located.

6. The method according to claim 2, characterized in that The central processor also runs an information collection script. After the detection thread is created, the method further includes: Creating an interactive node, wherein the interactive node supports interaction between user state and kernel state; In response to the information collection function being turned on, the information collection script is executed, so that the interactive node obtains error information of each PCIe device in the first linked list, the link status of the PCIe link where the PCIe device is located, and obtains system information and system logs stored in the system in a user state; In response to the PCIe device detection function being turned off, the interactive node is deregistered.

7. The method according to claim 1 or 2, characterized in that: When any detection-related device has a downlink port error interception function and an error reporting function, the method further includes: Before clearing the error of the detection-related device, the downlink port error interception function and the error reporting function of the detection-related device are disabled.

8. The method according to claim 7, characterized in that The method further comprises: Before disabling the downstream port error interception function and the error reporting function of the detection-related device, the state of the register related to the error detection on each PCIe device to be detected is saved in the first file; In response to the PCIe device detection function being turned off, according to the first file, the state of the registers related to error detection on each PCIe device expected to be detected is restored to a state in which the downstream port error interception function and the error reporting function of the detection-related device are turned off.

9. A PCIe device detection device, characterized in that: The device is used to detect errors of PCIe devices in a system, and the device comprises: An establishing module, configured to establish a first linked list according to the PCIe devices expected to be detected in response to the PCIe device detection function being enabled, wherein the first linked list includes a plurality of nodes, and information of each PCIe device expected to be detected is stored in a node corresponding to the device in the first linked list; A first determination module is used to determine a PCIe link between each PCIe device to be detected and the central processor, determine all PCIe devices on the PCIe link as detection-related devices, and clear errors of the detection-related devices; The detection module is used to create a detection thread and start the detection thread. The detection thread detects whether an error occurs in each PCIe device recorded in the first linked list in turn, and records the detected error information to the node corresponding to the PCIe device in the first linked list.

10. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to implement the method described in any one of claims 1 to 8 when executing the instructions stored in the memory.

11. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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