Memory management method and memory controller

Abstract

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring a first bad block; the working mode of the first bad block is adjusted from a first storage mode to a second storage mode to obtain a second bad block, and the first storage capacity of each first storage unit of the first bad block in the first storage mode is larger than the second storage capacity of each second storage unit of the second bad block in the second storage mode; if the detection result of the second bad block is qualified, taking the second bad block as an adjusted block and recording; and according to the preset storage capacity and the respective storage capacity of the plurality of recorded adjusted blocks, obtaining a plurality of target adjusted blocks from the plurality of adjusted blocks, and combining the plurality of target adjusted blocks into a virtual standby block to be included in the standby area. By means of the method, the storage units which cannot work normally in the original working mode but can still be used after degradation can be fully utilized, and the service life of the storage device is effectively prolonged.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a memory management method and a memory controller. Background Art

[0002] Non-volatile memory refers to computer memory in which the stored data does not disappear when the current is cut off. It has the advantages of non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Common non-volatile memory is a memory configured with NAND Flash (such as a solid-state drive), which has the characteristics of high read and write speed and does not require a mechanical structure to access data.

[0004] In NAND Flash storage technology, as the use time of NAND Flash increases, the storage unit will gradually degrade, resulting in an increase in the number of bad blocks. Specifically, after the storage unit is frequently erased and written, its read voltage will be offset, which will eventually lead to the inability to read the data correctly. Therefore, it is necessary to record or verify the number of program / erase cycles (P / E cycles) or error correction code bits (ECC bits) of the block. When the recorded P / Ecycle of the block exceeds the threshold or the number of ECC bits exceeds the threshold, the corresponding block will be determined as a bad block.

[0005] In the prior art, when a bad block is detected, a spare block is usually taken from the over-provisioning space (OP space) to replace the bad block. However, since the number of spare blocks in the OP space is limited, when the number of bad blocks gradually increases, the spare blocks will gradually be exhausted. Once the spare blocks are exhausted, the available capacity of the storage device will be reduced, thereby affecting the service life of the storage device. Summary of the invention

[0006] In view of the above problems, the present disclosure provides a memory management method and a memory controller, which adjust the working mode of bad blocks and reuse the bad blocks that can still be used after adjustment as spare resources, thereby improving the utilization efficiency of spare resources. The technical solution of the present disclosure is not only applicable to TLC (Triple-Level Cell) type storage cells, but also to other types of multi-level storage cells such as MLC (Multi-Level Cell) or QLC (Quad-Level Cell).

[0007] One or more embodiments of the present disclosure provide a memory management method, which is applicable to a storage device equipped with a rewritable non-volatile memory module. The method includes: obtaining a first bad block; determining whether the working mode of the first bad block can be adjusted; if the working mode of the first bad block can be adjusted, then: adjusting the working mode of the first bad block from the first storage mode to the second storage mode to obtain a second bad block, wherein the first storage capacity of each first storage unit of the first bad block in the first storage mode is greater than the second storage capacity of each second storage unit of the second bad block in the second storage mode; detecting the second bad block in the second storage mode; if the detection result of the second bad block is qualified, treating the second bad block as an adjusted block and recording the adjusted block; according to the preset storage capacity and the storage capacity of each of the recorded multiple adjusted blocks, obtaining multiple target adjusted blocks from the multiple adjusted blocks, combining the multiple target adjusted blocks into a virtual spare block and incorporating it into the spare area of ​​the rewritable non-volatile memory module, wherein the storage capacity of the virtual spare block is equal to the preset storage capacity.

[0008] In one or more embodiments of the present disclosure, the step of obtaining the first bad block includes: detecting whether the physical block in the data area of ​​the rewritable non-volatile memory module meets the bad block judgment standard; and if the physical block in the data area meets the bad block judgment standard, judging the physical block to be the first bad block.

[0009] In one or more embodiments of the present disclosure, before adjusting the working mode of the first bad block from the first storage mode to the second storage mode, the method also includes: obtaining a first spare block or a first virtual spare block from the spare area as a first data block; and moving the data in the first bad block to the first data block, and incorporating the first data block into the data area of ​​the rewritable non-volatile memory module.

[0010] In one or more embodiments of the present disclosure, the step of obtaining the multiple target adjusted blocks from the multiple adjusted blocks according to the preset storage capacity and the respective storage capacities of the multiple recorded adjusted blocks, and combining the multiple target adjusted blocks into the virtual spare block and incorporating them into the spare area of ​​the rewritable non-volatile memory module includes: selecting the multiple target adjusted blocks from the multiple recorded adjusted blocks based on the preset storage capacity and the respective storage capacities of the multiple recorded adjusted blocks so that the total storage capacity of the multiple target adjusted blocks is equal to the preset storage capacity; combining the multiple target adjusted blocks into the virtual spare block; and incorporating the virtual spare block into the spare area, and establishing a mapping relationship between the virtual spare block and the multiple target adjusted blocks.

[0011] In one or more embodiments of the present disclosure, the step of determining whether the working mode of the first bad block can be adjusted includes: determining whether the working mode of the first bad block is the lowest storage mode; if the working mode of the first bad block is not the lowest storage mode, determining that the working mode of the first bad block can be adjusted; if the working mode of the first bad block is the lowest storage mode, determining that the working mode of the first bad block cannot be adjusted.

[0012] In one or more embodiments of the present disclosure, if the working mode of the first bad block cannot be adjusted, the method further includes: recording physical addresses of multiple qualified physical pages in the first bad block as a spare page group corresponding to the first bad block.

[0013] In one or more embodiments of the present disclosure, the method further includes: selecting multiple target spare page groups from the multiple spare page groups according to the preset storage capacity and the respective storage capacities of the multiple recorded spare page groups, so that the total storage capacity of the multiple target spare page groups is equal to the preset storage capacity; and combining the multiple target spare page groups into another virtual spare block and incorporating it into the spare area of ​​the rewritable non-volatile memory module, and establishing a mapping relationship between the other virtual spare block and the multiple target spare page groups.

[0014] In one or more embodiments of the present disclosure, the step of determining whether the working mode of the first bad block can be adjusted includes: detecting each physical page within the first bad block to obtain a plurality of qualified physical pages; if the total storage capacity of the second bad block adjusted to the second storage mode is less than the total storage capacity of the plurality of qualified physical pages of the first bad block, determining that the working mode of the first bad block cannot be adjusted, and recording the physical addresses of the plurality of qualified physical pages as a spare page group corresponding to the first bad block; and if the total storage capacity of the second bad block adjusted to the second storage mode is not less than the total storage capacity of the plurality of qualified physical pages of the first bad block, determining that the working mode of the first bad block can be adjusted.

[0015] In one or more embodiments of the present disclosure, the step of detecting the second bad block in the second storage mode includes: writing detection data to the second bad block, and reading the detection data from the second bad block; if the reading result of the detection data is successful, determining that the detection result of the second bad block is qualified; and if the reading result of the detection data is unsuccessful, determining that the detection result of the second bad block is unqualified.

[0016] In one or more embodiments of the present disclosure, the method further includes: if the detection result of the second bad block in the second storage mode is unqualified and the working mode of the second bad block can be adjusted, then: adjusting the working mode of the second bad block from the second storage mode to the third storage mode to obtain a third bad block, wherein the second storage capacity of each second storage unit of the second bad block in the second storage mode is greater than the third storage capacity of each third storage unit of the third bad block in the third storage mode; and if the detection result of the third bad block is qualified, recording the third bad block as another adjusted block.

[0017] One or more embodiments of the present disclosure provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit for electrically connecting to the rewritable non-volatile memory module; a data management circuit for electrically connecting to a connection interface circuit of the storage device for receiving data and commands from a host system via the connection interface circuit; a buffer memory for caching data; and a processor for electrically connecting to the memory interface control circuit, the data management circuit, and the buffer memory. The processor is configured to: obtain a first bad block; determine whether the working mode of the first bad block can be adjusted; if the working mode of the first bad block can be adjusted, then: adjust the working mode of the first bad block from a first storage mode to a second storage mode to obtain a second bad block, wherein the first storage capacity of each first storage unit of the first bad block in the first storage mode is greater than the second storage capacity of each second storage unit of the second bad block in the second storage mode; detect the second bad block in the second storage mode; if the detection result of the second bad block is qualified, treat the second bad block as an adjusted block and record the adjusted block; according to the preset storage capacity and the storage capacity of each of the recorded multiple adjusted blocks, obtain multiple target adjusted blocks from the multiple adjusted blocks, combine the multiple target adjusted blocks into a virtual spare block and incorporate it into the spare area of ​​the rewritable non-volatile memory module, wherein the storage capacity of the virtual spare block is equal to the preset storage capacity.

[0018] Based on the above, the memory management method and memory controller provided by the embodiments of the present disclosure can make full use of those storage units that cannot work normally in the original working mode but can still be used after degradation. Specifically, by adjusting the working mode of the bad block from high storage density to low storage density (for example, from TLC to MLC or SLC), and verifying its availability after adjustment, the storage unit originally determined to be a bad block is effectively utilized. In addition, the present disclosure effectively supplements the spare resources in the OP space by combining multiple adjusted bad blocks into virtual spare blocks, thereby slowing down the consumption rate of the original spare blocks in the OP space. For bad blocks that still cannot work completely normally in the lowest storage mode, the present disclosure further improves the utilization efficiency of storage resources by extracting qualified physical pages therein and combining them for utilization. Since the technical solution provided by the present disclosure can extend the available time of the spare block, the service life of the storage device is correspondingly extended, and the reliability of the storage device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0020] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present disclosure;

[0021] Figure 2 is a flowchart of a memory management method according to an embodiment of the present disclosure;

[0022] Figure 3 is a flow chart of a method for determining whether the working mode of a first bad block can be adjusted according to another embodiment of the present disclosure;

[0023] Figure 4 is a flow chart of a method for determining whether the working mode of a first bad block can be adjusted according to another embodiment of the present disclosure;

[0024] Figure 5 is a flow chart of a method for determining whether the working mode of a first bad block can be adjusted according to yet another embodiment of the present disclosure;

[0025] Figure 6 is a flowchart of a processing method when the working mode of the first bad block cannot be adjusted according to an embodiment of the present disclosure;

[0026] Figure 7 is a schematic diagram of a working mode adjustment process of a physical block according to an embodiment of the present disclosure;

[0027] Figure 8 is a schematic diagram of a qualified physical page extraction process in a bad block according to an embodiment of the present disclosure;

[0028] Fig. 9 is a first exemplary schematic diagram of a process of constructing a virtual spare block according to an embodiment of the present disclosure;

[0029] Fig.10 is a schematic diagram of an adjusted block list and a virtual spare block mapping table according to an embodiment of the present disclosure;

[0030] Fig.11 4 is a second exemplary schematic diagram of a process for constructing a virtual spare block according to an embodiment of the present disclosure.

[0031] Description of Figure Numbers

[0032] 10: Host system

[0033] 20: Storage device

[0034] 211: First processor

[0035] 110: Second processor

[0036] 120: Host memory

[0037] 130: Data transmission interface circuit

[0038] 210: Memory Controller

[0039] 212: Data management circuit

[0040] 213: Memory interface control circuit

[0041] 214: Buffer memory

[0042] 220: Rewritable non-volatile memory module

[0043] 230: Connecting interface circuit

[0044] S210-S290: Process steps of the memory management method

[0045] S310-S350: Process steps of the method for adjusting the working mode of the first bad block

[0046] S410-S430: Another process step of the method for adjusting the working mode of the first bad block

[0047] S510-S540: Another process step of the method for adjusting the working mode of the first bad block

[0048] S610-S620: Processing steps when the working mode of the first bad block cannot be adjusted

[0049] TB1: First bad block

[0050] TB2: The second bad block

[0051] TB2': The second bad block

[0052] TB3: The third bad block

[0053] V1, V2: Virtual spare blocks

[0054] BB1-BB3: Physical blocks

[0055] PP1-PP9: Physical pages

[0056] PG1-PG3: spare page group

[0057] TB81, TB113: Alternate page group list

[0058] TB101: MLC adjusted block list

[0059] TB102: SLC adjusted block list

[0060] TB103, TB104: Virtual spare block mapping table

[0061] TB111, TB112: Virtual spare block mapping table

[0062] A71-A73, A81, A91-A92, A101-A102, A111-A118: Arrow DETAILED DESCRIPTION

[0063] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0064] Figure 1 FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present disclosure. Figure 1 , the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In the present embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0065] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0066] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0067] In this embodiment, the number of the data transmission interface circuit 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power consumption Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0068] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use the fast non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol to transmit data.

[0069] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0070] In the present embodiment, the host memory 120 is used to temporarily store commands or data executed by the processor 110. For example, in the present embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present disclosure is not limited thereto, and the host memory 120 may also be other suitable memories.

[0071] The memory controller 210 is used to execute a plurality of logic gates or control commands implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to commands of the host system 10 .

[0072] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control commands / program codes, and when the storage device 20 operates, these control commands / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in this embodiment, the control commands / program codes can be further executed to implement the memory management method provided by the present disclosure. The control commands / program codes corresponding to the memory management can be further implemented as a circuit unit in the form of hardware to implement the memory management method provided by the present disclosure.

[0073] It is worth mentioning that in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present disclosure is not limited thereto.

[0074] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0075] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., the write operation is performed according to the write command from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more storage units in the one or more physical units), and the read data is written to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., the read operation is performed according to the read command from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0076] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also called programming) operation, a read operation or an erase operation on the rewritable non-volatile memory module 220 .

[0077] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, these command sequences may include a write command sequence indicating writing data, a read command sequence indicating reading data, an erase command sequence indicating erasing data, and corresponding command sequences for indicating various memory operations. These command sequences may include one or more signals, or data on the bus. These signals or data may include command codes or program codes. For example, in a read command sequence, information such as a read identification code, a memory address, and a physical address may be included.

[0078] In the present disclosure, the memory controller 210 establishes a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the mapping relationship between the logical address of the logical unit (e.g., logical block, logical page or logical column) configured for the rewritable non-volatile memory module 220 and the physical address (physical address) of the physical unit (e.g., physical erase unit / physical block, physical page, physical column). In other words, the memory controller 210 can search for the physical unit mapped by a logical unit (e.g., search for the physical page mapped by a logical page; search for the physical address mapped by a logical address) through the logical to physical address mapping table (also called the logical to physical mapping table), and the memory controller 210 can search for the logical unit mapped by a physical unit (e.g., search for the logical page mapped by a physical page; search for the logical address mapped by a physical address) through the physical to logical address mapping table (also called the physical to logical mapping table).

[0079] The memory controller 210 also establishes a data structure to record various mapping relationships: including establishing an adjusted block list corresponding to different storage modes for the adjusted block, establishing a corresponding standby page group list for the standby page group, establishing a mapping table for the virtual standby block to record the corresponding relationship between it and the adjusted block, and establishing an image table for the virtual standby block to record the corresponding relationship between it and the standby page group. When data access operations need to be performed on the specified virtual standby block, the memory controller 210 can obtain the actual physical address by querying these mapping tables, and then perform corresponding data read and write operations.

[0080] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and commands from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., various mapping tables, index tables, address lists, adjusted block lists, spare page group lists, virtual spare block mapping tables, etc., system data related to the present disclosure), so that the processor 211 can quickly access the data, commands, or system data from the buffer memory 214.

[0081] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store data written by the host system 10 .

[0082] In the present embodiment, the rewritable non-volatile memory module 220 has a plurality of word lines, wherein each of the plurality of word lines is electrically connected to a plurality of storage cells, also known as columns (also known as physical columns). The plurality of columns on the same word line constitute a physical programming unit (also known as a physical page or physical page). Each physical page corresponds to a physical address for recording the location of the data stored in the physical page. In addition, the plurality of physical pages may constitute a physical block (also known as a physical erase unit or physical block). Each memory grain (chip) of the plurality of memory grains of the rewritable non-volatile memory module has a plurality of planes, and each plane has a plurality of physical blocks. It should be noted that the present disclosure is not limited to the size of each physical page and logical page.

[0083] The memory cell type (also known as storage mode) can be used to indicate the number of bits that each memory cell (Memory Cell, also known as memory cell) can store. Common types include SLC (single-layer memory cell, each memory cell stores 1 bit), MLC (multi-layer memory cell, each memory cell stores 2 bits), TLC (three-layer memory cell, each memory cell stores 3 bits), etc. Different storage modes differ in storage density, read and write speed, and durability, which affect the overall performance and characteristics of the flash memory. In addition, in this embodiment, each physical block can be set to a different working mode, and the memory cells it has are set to different storage modes. For example, when the working mode of a physical block is set to the TLC storage mode, each memory cell it has can store 3 bits. When this physical block is adjusted from the TLC storage mode to the SLC or MLC storage mode, the number of bits that each memory cell of this physical block can store will be adjusted to 1 bit or 2 bits.

[0084] Figure 2 It is a flowchart of a memory management method according to an embodiment of the present disclosure.

[0085] Reference Figure 2 In one embodiment, the processor of the memory controller 210 executes multiple program modules to perform a memory management method.

[0086] In step S210, the memory controller 210 obtains the first bad block. Specifically, the memory controller 210 may obtain the first bad block by periodically detecting the status of each physical block in the data area of ​​the rewritable non-volatile memory module 220. For example, in one embodiment, the memory controller 210 may detect the Program / Erase cycle (P / E cycle) value of each physical block, and when the P / E cycle of a physical block exceeds a first preset Program / Erase threshold, the physical block is determined to be the first bad block. Alternatively, in one embodiment, the memory controller 210 may verify the data in each physical block and record the number of Error Correction Code bits (ECC bits) of each data segment, and when the number of ECC bits of a data segment exceeds the preset Error Correction Code bit threshold, the physical block containing the data segment is determined to be the first bad block.

[0087] In one embodiment, when acquiring the first bad block, the memory controller 210 first detects whether each physical block in the data area of ​​the rewritable non-volatile memory module 220 meets the bad block determination criteria. These bad block determination criteria may include the detection of multiple parameter indicators. For example, the memory controller 210 may detect whether the number of programming and erasing times of the physical block exceeds the first preset programming and erasing threshold, or detect whether the number of error correction bits of the data in the physical block exceeds the first preset error correction bit threshold. In addition, the memory controller 210 may also monitor the read performance of the physical block to determine whether its read delay exceeds the first preset read delay threshold. The memory controller 210 may also record the write operation of the physical block to check whether the number of write failures exceeds the first preset write failure threshold. When it is detected that a physical block in the data area meets any of the above bad block determination criteria, the memory controller 210 determines that the physical block is the first bad block. By adopting multiple determination criteria, the memory controller 210 can timely and accurately identify the physical blocks with degraded performance, thereby providing a reliable basis for subsequent working mode adjustment and resource reorganization.

[0088] In step S220, the memory controller 210 determines whether the working mode of the first bad block can be adjusted. In one determination method, the memory controller 210 can determine whether the working mode of the first bad block is the lowest storage mode (e.g., SLC mode). If the working mode of the first bad block is not the lowest storage mode, it is determined that the working mode can be adjusted; if it is the lowest storage mode, it is determined that the working mode cannot be adjusted.

[0089] If the working mode of the first bad block can be adjusted, then in step S230, the memory controller 210 adjusts the working mode of the first bad block from the first storage mode to the second storage mode to obtain a second bad block. For example, if the working mode of the first bad block originally adopts the TLC mode, it can be adjusted to the MLC mode or the SLC mode, wherein the first storage capacity of each first storage unit of the first bad block in the first storage mode (such as the TLC mode) is greater than the second storage capacity of each second storage unit of the second bad block in the second storage mode (such as the MLC mode or the SLC mode).

[0090] Next, in step S240, the memory controller 210 detects the availability of the second bad block in the second storage mode. For example, the memory controller 210 may write detection data to the second bad block and attempt to read the detection data from the second bad block. If the reading result of the detection data is successful, the detection result of the second bad block is determined to be qualified, and the memory controller 210 treats the second bad block as an adjusted block and records the adjusted block. In other words, the memory controller 210 will regard the first bad block as a physical block that can store data normally after being degraded, and record this situation (marked as an adjusted block to record that this physical block is obtained after the degrade operation).

[0091] In one embodiment, the memory controller 210 may establish an adjusted block list, which may record the identification information of the first bad block and the corresponding physical address. However, in another embodiment, the adjusted block list may also record the status information of these physical pages (such as the read delay of the physical page, the number of error correction bits, and other parameters). By maintaining such a list, the memory controller 210 can more effectively manage and utilize these storage resources that are still working properly. It should be noted that the adjusted block list can also be classified according to different storage modes.

[0092] Next, in step S250, the memory controller 210 obtains a plurality of target adjusted blocks from the plurality of adjusted blocks according to the preset storage capacity and the respective storage capacities of the plurality of recorded adjusted blocks, and combines the plurality of target adjusted blocks into a virtual spare block and incorporates the virtual spare block into the spare area of ​​the rewritable non-volatile memory module 220. Specifically, the memory controller 210 selects a plurality of target adjusted blocks from the adjusted block list so that the total storage capacity of the target adjusted blocks is equal to the preset storage capacity (e.g., the storage capacity of an original TLC block). For example, if each adjusted block is in SLC mode, three adjusted blocks in SLC mode may be selected to be combined into a virtual spare block having a capacity equivalent to that of a TLC block. The preset storage capacity is, for example, the size of the storage space of the main data blocks of the data area of ​​the rewritable non-volatile memory module 220.

[0093] It should be noted that the size of the virtual spare block corresponding to the preset storage capacity varies with the preset storage capacity. In other words, as the system tasks vary, the preset storage capacity can vary accordingly, prompting the memory controller 210 to use multiple adjusted blocks to combine into appropriate virtual spare blocks corresponding to different preset storage capacities. In this way, the available storage space of the storage device 20 can be used more flexibly.

[0094] In more detail, in one embodiment, first, the memory controller 210 searches for available adjusted blocks from the adjusted block list. Based on the preset storage capacity (e.g., the storage capacity of a TLC mode physical block) and the storage capacity of each adjusted block recorded in the adjusted block list, the memory controller 210 selects an appropriate number of target adjusted blocks so that the total storage capacity of these target adjusted blocks is equal to the preset storage capacity. For example, the memory controller 210 may select an adjusted block in the MLC mode and an adjusted block in the SLC mode, or select three adjusted blocks in the SLC mode. Subsequently, the memory controller 210 combines the selected multiple target adjusted blocks into a virtual spare block. Finally, the memory controller 210 incorporates the virtual spare block into the spare area of ​​the rewritable non-volatile memory module 220, and establishes a mapping relationship between the virtual spare block and these target adjusted blocks in the virtual spare block mapping table, and records the identification information of the virtual spare block and the physical address information of each corresponding target adjusted block, so that the actual physical location can be correctly accessed during subsequent data access operations.

[0095] In another embodiment, before adjusting the working mode of the first bad block from the first storage mode to the second storage mode, the memory controller 210 needs to ensure that the valid data in the first bad block is properly preserved. Specifically, the memory controller 210 first obtains an available storage space from the spare area of ​​the rewritable non-volatile memory module 220 as the first data block. The first data block can be an ordinary spare block or a virtual spare block composed of multiple adjusted blocks or multiple spare page groups. After obtaining the first data block, the memory controller 210 moves the data in the first bad block to the first data block, and incorporates the first data block into the data area of ​​the rewritable non-volatile memory module 220, and updates the corresponding address mapping relationship. Through this data movement operation, the memory controller 210 ensures the security of the original data, so that the adjustment operation of the working mode can be safely performed on the first bad block later.

[0096] If it is determined in step S220 that the working mode of the first bad block cannot be adjusted, step S260 is executed.

[0097] In step S260, the memory controller 210 detects each physical page in the first bad block to obtain multiple qualified physical pages. Specifically, the memory controller 210 can perform the detection in the following manner: first, perform a read operation on each physical page in the first bad block, and check whether the read data can pass the error correction code (Error Correcting Code, referred to as ECC) check. If the data read from a physical page can pass the ECC check, or the number of error correction bits is within an acceptable range (for example, the number of error correction bits per 2KB of data does not exceed a preset threshold), the physical page is determined to be a qualified physical page.

[0098] In step S270, the memory controller 210 records the acquired physical addresses of the plurality of qualified physical pages as a spare page group corresponding to the first bad block. The memory controller 210 may establish a spare page group list, which may record the identification information of the first bad block and the physical address of the corresponding qualified physical page. However, in another embodiment, the spare page group list may also record the status information of these physical pages (such as the parameters such as the read delay and the number of error correction bits of the physical page). By maintaining such a list, the memory controller 210 may more effectively manage and utilize these storage resources that are still functioning normally.

[0099] Then in step S280, the memory controller 210 selects multiple target standby page groups from these standby page groups according to the preset storage capacity and the respective storage capacities of the multiple recorded standby page groups, so that the total storage capacity of the selected target standby page groups is equal to the preset storage capacity. In the selection process, the memory controller 210 can comprehensively consider multiple factors: for example, give priority to the standby page group where the physical page with smaller read latency is located, or give priority to the standby page group from the same physical block to improve data access efficiency. In addition, the memory controller 210 can also consider the distribution of qualified physical pages in each standby page group, and select a standby page group with a relatively concentrated distribution of physical pages, so that subsequent data access operations can be more efficient.

[0100] Finally, in step S290, the memory controller 210 combines the multiple target spare page groups into another virtual spare block, and incorporates it into the spare area of ​​the rewritable non-volatile memory module 220. In this process, the memory controller 210 needs to establish a mapping relationship between the virtual spare block and the target spare page group. This mapping relationship may include: identification information of the virtual spare block (e.g., the serial number / index of the virtual spare block), identification information of the corresponding multiple target spare page groups (e.g., the serial number / index of the corresponding target spare page group or the identification information of the corresponding physical block), physical addresses of qualified physical pages in each target spare page group, etc. By establishing such a mapping relationship, when data access operations need to be performed on the virtual spare block, the memory controller 210 can quickly locate the actual physical address, thereby ensuring the accuracy and efficiency of data operations.

[0101] In one embodiment, this organization method also facilitates the memory controller 210 to perform dynamic management. For example, when the performance of certain physical pages degrades, the mapping relationship can be updated in time and other appropriate physical pages can be selected for replacement.

[0102] Figure 3 It is a flowchart of a method for determining whether the working mode of a first bad block can be adjusted according to another embodiment of the present disclosure.

[0103] Reference Figure 3 In one embodiment, the memory controller 210 may determine whether the working mode of the first bad block can be adjusted in the following manner.

[0104] In step S310, the memory controller 210 first detects each physical page in the first bad block to obtain multiple qualified physical pages. Specifically, the memory controller 210 can perform a read operation on each physical page in the first bad block, and check whether the read data can pass the error correction code (ECC) check, or check whether the error correction bit number is within an acceptable range. If the detection result of a physical page meets the preset conditions, it is determined to be a qualified physical page.

[0105] Next, in step S320, the memory controller 210 determines whether the working mode of the first bad block is the lowest storage mode. In this embodiment, the memory controller 210 regards the single-level cell (SLC) mode as the lowest storage mode. If the current working mode of the first bad block is the SLC mode, the process proceeds to step S340; if the current working mode of the first bad block is not the SLC mode (for example, a storage mode such as a TLC mode or an MLC mode), the process proceeds to step S330.

[0106] In step S330, the memory controller 210 determines whether the total storage capacity after adjusting the first bad block to the next level storage mode is less than the total storage capacity of the multiple qualified physical pages obtained. For example, if the first bad block is currently in TLC mode, the memory controller 210 will calculate the storage capacity after adjusting it to MLC mode, and compare it with the total capacity of the current qualified physical pages. If the adjusted storage capacity is less than the total capacity of the qualified physical pages, it means that directly adjusting the storage mode will result in a loss of available storage space, and then enter step S340; if the adjusted storage capacity is not less than the total capacity of the qualified physical pages, it means that adjusting the storage mode is a feasible option, and then enter step S350. In other words, this step allows the memory controller to choose a method that can retain more storage space to perform bad block processing, so as to further improve the utilization efficiency of the storage space.

[0107] In step S340, the memory controller 210 determines that the working mode of the first bad block cannot be adjusted. In this case, the memory controller 210 will switch to using the spare page group to utilize these qualified physical pages.

[0108] In step S350, the memory controller 210 determines that the working mode of the first bad block can be adjusted, which means that the memory controller 210 can efficiently perform a storage mode degradation operation on the bad block, and provide an available adjusted block for subsequent construction of a virtual spare block.

[0109] Through this judgment method, the memory controller 210 can select the most appropriate processing solution for each bad block while ensuring that the storage capacity is fully utilized, or adjust its working mode to a lower storage mode for continued use, or extract qualified physical pages from it to form a spare page group.

[0110] Figure 4 It is a flowchart of a method for determining whether the working mode of a first bad block can be adjusted according to another embodiment of the present disclosure.

[0111] Reference Figure 4 In another embodiment, the memory controller 210 may use a more direct method to determine whether the working mode of the first bad block can be adjusted.

[0112] In step S410, the memory controller 210 determines whether the working mode of the first bad block is the lowest storage mode. Specifically, the memory controller 210 checks the current working mode of the first bad block: if the first bad block currently adopts the single-level cell (SLC) mode, it is regarded as the lowest storage mode; if the first bad block currently adopts the triple-level cell (TLC) mode or the multi-level cell (MLC) mode, it is regarded as a degradable storage mode.

[0113] In step S420, if the working mode of the first bad block is SLC mode, the memory controller 210 determines that the working mode of the first bad block cannot be adjusted. In this case, the memory controller 210 will turn to detect the availability of each physical page in the bad block to prepare for subsequent extraction of qualified physical pages to construct a spare page group.

[0114] In step S430, if the working mode of the first bad block is not the SLC mode, the memory controller 210 determines that the working mode of the first bad block can be adjusted. At this time, the memory controller 210 can perform a storage mode degradation operation on the bad block, such as adjusting the TLC mode to the MLC mode, or adjusting the MLC mode to the SLC mode, to try to continue using the physical block at a lower storage density.

[0115] Through this simplified judgment method, the memory controller 210 can quickly determine the processing direction of the bad block, thereby improving the efficiency of the working mode adjustment judgment. For bad blocks whose working mode is already SLC mode, the qualified physical page extraction process is directly entered; for bad blocks whose working mode is higher storage density, priority is given to trying to continue to use them by downgrading.

[0116] It should be noted that in another embodiment, the memory controller 210 may choose to downgrade the working mode of the first bad block directly from the triple-level cell (TLC) mode to the single-level cell (SLC) mode in certain specific cases, without first trying the multi-level cell (MLC) mode. For example, when the memory controller 210 detects that the read delay of the first bad block has exceeded the second preset read delay threshold (the threshold is higher than the first preset read delay threshold), or the number of error correction bits is close to but has not exceeded the maximum allowed number of error correction bits, considering that the performance degradation of the first bad block is relatively serious, if it is downgraded to the MLC mode, it may still not work stably. At this time, the memory controller 210 may directly downgrade it to the more stable SLC mode. Alternatively, when the memory controller 210 detects that the number of original spare blocks in the spare area is lower than the preset remaining number threshold, in order to maximize the success rate of subsequent bad block replacement operations, the memory controller 210 may also choose to directly downgrade the first bad block to the SLC mode to obtain a more reliable storage space.

[0117] Figure 5 It is a flowchart of a method for determining whether the working mode of a first bad block can be adjusted according to another embodiment of the present disclosure.

[0118] Reference Figure 5 In yet another embodiment, the memory controller 210 may determine whether its working mode can be adjusted according to the total storage capacity of the qualified physical pages in the first bad block.

[0119] In step S510 , the memory controller 210 detects each physical page in the first bad block to obtain a plurality of qualified physical pages.

[0120] In step S520, the memory controller 210 determines whether the storage capacity of the first bad block adjusted to the second storage mode is less than the total storage capacity of the plurality of qualified physical pages. For example, when the first bad block is currently in a triple-level cell (TLC) mode, the memory controller 210 calculates the total storage capacity after adjusting it to a multi-level cell (MLC) mode, and compares it with the total storage capacity that can be provided by the currently identified qualified physical pages.

[0121] In step S530, if the adjusted storage capacity is less than the total storage capacity of the qualified physical pages, the memory controller 210 determines that the working mode of the first bad block cannot be adjusted. This situation indicates that it is more appropriate to directly record these qualified physical pages as spare page groups.

[0122] In step S540 , if the adjusted storage capacity is not less than the total storage capacity of the qualified physical pages, the memory controller 210 determines that the operation mode of the first bad block can be adjusted.

[0123] Through this judgment method based on storage capacity comparison, the memory controller 210 can select a more effective data storage method between the two solutions of working mode adjustment and spare page group extraction, thereby maximizing the use of still available storage resources.

[0124] Figure 6 It is a flowchart of a processing method when the working mode of the first bad block cannot be adjusted according to an embodiment of the present disclosure.

[0125] Reference Figure 6 In one embodiment, when the working mode of the first bad block cannot be adjusted (for example, it is already in the single-level cell mode, or the adjusted storage capacity is insufficient to store the current valid data), the memory controller 210 may process the bad block by the following steps:

[0126] In step S610 , the memory controller 210 detects each physical page in the first bad block to obtain a plurality of qualified physical pages.

[0127] Specifically, the memory controller 210 can evaluate the availability of the physical page in one of multiple ways: the first way is that the memory controller 210 can write test data to each physical page and try to read it, and determine the availability of the physical page by comparing whether the written and read data are consistent; the second way is that the memory controller 210 can detect the number of error correction bits (Error Correction Code bit, referred to as ECC bits) when reading data. If the number of ECC bits of data read from a physical page does not exceed a preset error correction bit threshold (for example, the number of error correction bits for every 2KB of data is within an acceptable range), it is determined to be a qualified physical page; the third way is that the memory controller 210 can also measure the read delay of each physical page. If the read delay does not exceed the preset read delay threshold, it can also be determined to be a qualified physical page.

[0128] It should be noted that if the memory controller 210 has already obtained a plurality of qualified physical pages in the first bad block in the previous processing procedure, step S610 may not be executed, and step S620 may be directly executed.

[0129] In step S620, the memory controller 210 records the physical addresses of the obtained multiple qualified physical pages as the spare page group corresponding to the first bad block. Specifically, the memory controller 210 creates a new spare page group record item in the spare page group list, and the record item includes: identification information of the spare page group, identification information of the corresponding first bad block, physical address information of each qualified physical page, etc. By establishing and maintaining such a record, the memory controller 210 not only saves the location information of the qualified physical page, but also establishes the corresponding relationship between the qualified physical page and the bad block to which it belongs, so as to facilitate the subsequent rapid positioning and utilization of these physical pages that can still be used normally when constructing a virtual spare block. In addition, the memory controller 210 can also include the performance parameters (such as read delay, number of error correction bits, etc.) of each qualified physical page in the record item, so that when selecting qualified physical pages to form a virtual spare block in the future, physical pages with better performance can be selected first.

[0130] Figure 7 is a schematic diagram of a working mode adjustment process of a physical block according to an embodiment of the present disclosure.

[0131] Reference Figure 7 , Figure 7 Multiple possible paths for the memory controller 210 to adjust the working mode of the first bad block are shown. In one embodiment, the first storage mode of the first bad block TB1 is a triple-level cell (TLC) mode as an example for explanation, but it should be understood that the first storage mode can also be a multi-level cell (MLC) mode, a quad-level cell (QLC) mode, or other multi-layer storage modes.

[0132] As shown by arrow A71, the memory controller 210 can choose to adjust the working mode of the first bad block TB1 from the TLC mode to the MLC mode to obtain the second bad block TB2. In this case, since the storage density of the MLC mode is lower than that of the TLC mode, each storage unit only needs to store two bits of data, so the storage reliability of the data can be improved at the expense of part of the storage capacity.

[0133] As shown by arrow A72, the memory controller 210 may also choose to adjust the working mode of the first bad block TB1 directly from the TLC mode to the single-level cell (SLC) mode to obtain the second bad block TB2'. Although this adjustment method will reduce the storage capacity to one third of the original, since the SLC mode has the highest storage reliability and the lowest error rate, it is suitable for the situation where the performance degradation of the first bad block TB1 is more serious.

[0134] In addition, as shown by arrow A73, for the second bad block TB2 that has been adjusted to the MLC mode, if its detection result in the MLC mode is still unqualified, the memory controller 210 can further adjust its working mode from the MLC mode to the SLC mode to obtain the third bad block TB3. This step-by-step adjustment method enables the memory controller 210 to flexibly select the most suitable storage mode according to the actual condition of the bad block.

[0135] In the specific implementation process, the memory controller 210 needs to perform availability detection on the adjusted second bad block TB2. The memory controller 210 first writes preset detection data to the second bad block TB2, and then attempts to read the detection data from the second bad block TB2. If the memory controller 210 can successfully read the detection data, and the read data is consistent with the written data, the detection result of the second bad block TB2 is determined to be qualified; if the reading fails, or the read data is inconsistent with the written data, the detection result of the second bad block TB2 is determined to be unqualified.

[0136] When the detection result of the second bad block TB2 in the second storage mode (such as the MLC mode) is unqualified and its working mode can still be adjusted (ie, it is not currently in the lowest storage mode), the memory controller 210 will perform further working mode adjustment. Figure 7 As shown, the memory controller 210 adjusts the working mode of the second bad block TB2 from the second storage mode (MLC mode) to the third storage mode (SLC mode) to obtain the third bad block TB3. It should be noted here that the storage capacity (double bit) of each second storage unit of the second bad block TB2 in the second storage mode is greater than the storage capacity (single bit) of each third storage unit of the third bad block TB3 in the third storage mode. After the adjustment is completed, the memory controller 210 will detect the third bad block TB3. If the test result is qualified, the third bad block TB3 will be recorded in the adjusted block list as another adjusted block for subsequent use in constructing a virtual spare block.

[0137] In one embodiment, if the detection result of the third bad block TB3 in the SLC mode is still unqualified, at this time, since it is already the lowest storage mode, the memory controller 210 will switch to a more sophisticated management method. Specifically, the memory controller 210 will detect each physical page in the third bad block TB3 page by page, and identify qualified physical pages that can still be used normally. For those physical pages that can pass the test and whose performance parameters are within an acceptable range, the memory controller 210 records their physical addresses in the spare page group list. Although this page-level refined management method will bring certain management overhead, it can maximize the use of the part of the storage space that can still work normally, further improving the utilization efficiency of the bad blocks. When a sufficient number of qualified physical pages are accumulated, the memory controller 210 can combine these physical pages into virtual spare blocks to continue to provide available spare storage space for the storage device.

[0138] Through the adjustment mechanism of this working mode, the memory controller 210 can find a balance between storage capacity and data reliability, and maximize the service life of each physical block. For the adjusted adjusted blocks, the memory controller 210 records them in the adjusted block list for subsequent use in constructing virtual spare blocks.

[0139] In one embodiment, after the memory controller 210 has accumulated multiple spare page groups in the spare page group list, these spare page groups can be combined into a virtual spare block. Specifically, the memory controller 210 first selects multiple target spare page groups from these spare page groups based on the preset storage capacity (e.g., the storage capacity of a TLC mode physical block) and the storage capacity of each of the multiple recorded spare page groups. When selecting, the memory controller 210 ensures that the total storage capacity of these target spare page groups is equal to the preset storage capacity.

[0140] For example, if a TLC mode physical block contains 144 physical pages, and the current spare page group list records multiple spare page groups from different physical blocks: the first spare page group contains 60 qualified physical pages, the second spare page group contains 48 qualified physical pages, the third spare page group contains 36 qualified physical pages, and the fourth spare page group contains 25 qualified physical pages. The memory controller 210 can select the first, second and third spare page groups as target spare page groups, because the total number of their qualified physical pages (60+48+36=144) is exactly equal to the number of physical pages required by the preset storage capacity, so that a virtual spare block can be completely constructed. Such a selection not only ensures full utilization of storage capacity, but also facilitates subsequent data mapping and management.

[0141] It is worth mentioning that, in another embodiment, the memory controller 210 can also select to construct a virtual spare block of smaller capacity according to the number of qualified physical pages of the current spare page group. For example, if an SLC mode physical block contains 48 physical pages, and the following spare page groups are recorded in the current spare page group list: the first spare page group contains 30 qualified physical pages, the second spare page group contains 18 qualified physical pages, and the third spare page group contains 25 qualified physical pages. The memory controller 210 can select the first and second spare page groups as target spare page groups, because the total number of their qualified physical pages (30+18=48) is exactly equal to the preset storage capacity of the SLC mode physical block. Although the virtual spare block storage capacity constructed in this combination (or using an adjusted block of SLC size) is small, it can provide a more stable and more suitable storage space in some application scenarios that only need to use SLC size data blocks (for example, storing system parameters or log data that need to be frequently updated, etc.). This flexible combination strategy enables the memory controller 210 to more effectively utilize available storage resources according to actual application requirements.

[0142] After selecting the target spare page group, the memory controller 210 combines these target spare page groups into another virtual spare block, and incorporates the virtual spare block into the spare area of ​​the rewritable non-volatile memory module 220. At the same time, the memory controller 210 will establish a mapping relationship between the virtual spare block and these target spare page groups in the virtual spare block mapping table. The mapping relationship not only includes the identification information of the virtual spare block, but also records the identification information of each target spare page group constituting the virtual spare block, and the physical address information of each qualified physical page in these target spare page groups, so that the actual physical location can be correctly accessed during subsequent data access operations.

[0143] Figure 8 4 is a schematic diagram of a qualified physical page extraction process in a bad block according to an embodiment of the present disclosure.

[0144] Reference Figure 8 , Figure 8 The process of recording the spare page group by the memory controller 210 is shown. In this embodiment, a physical block BB1 having 9 physical pages (PP1 to PP9) is used as an example for explanation, but it should be understood that a physical block may have other numbers of physical pages, such as 64, 128 or 256 physical pages.

[0145] like Figure 8As shown, the memory controller 210 first detects the availability of each physical page in the physical block BB1. From the detection results, it can be seen that the physical pages PP1, PP2, PP5 and PP8 are qualified physical pages, while the physical pages PP3, PP4, PP6, PP7 and PP9 are unqualified physical pages (represented by grid filling in the figure).

[0146] As shown by arrow A81, the memory controller 210 organizes the detected qualified physical pages into a spare page group PG1. As shown by arrow A82, the memory controller 210 creates a new record item in the spare page group list TB81, which includes: identification information of the spare page group (PG1), corresponding physical block identification information (BB1), and physical address information (PP1, PP2, PP5, PP8) of the qualified physical pages included in the spare page group.

[0147] In another embodiment, the memory controller 210 may also record the total number of qualified physical pages of each spare page group in the spare page group list TB81. Figure 8 As shown, the total number of qualified physical pages of the standby page group PG1 is 4. By recording the number of qualified physical pages, the memory controller 210 can manage and utilize these standby page groups more efficiently. For example, when a virtual standby block needs to be built, the memory controller 210 can quickly screen and combine suitable standby page groups according to the number of qualified physical pages. If a standby page group has a large number of qualified physical pages, the memory controller 210 can give priority to the standby page group to reduce the number of standby page groups that need to be combined, thereby reducing management overhead. In addition, the information on the number of qualified physical pages can also help the memory controller 210 evaluate the currently available storage resources and rationally plan subsequent data storage strategies.

[0148] In another embodiment, when the memory controller 210 cannot select a target spare page group combination whose total storage capacity is exactly equal to the preset storage capacity from the current spare page group list, multiple strategies can be adopted to handle the situation.

[0149] For example, if a TLC mode physical block contains 144 physical pages, and the spare page groups recorded in the current spare page group list contain 50, 45, and 40 qualified physical pages, respectively, even if all spare page groups are selected, the total number of qualified physical pages (135) is still less than the number of physical pages required by the preset storage capacity (144). In this case, the memory controller 210 can choose to continue waiting for new spare page groups. Specifically, the memory controller 210 can set a waiting threshold time, and continue to detect other physical blocks during this time in order to obtain more spare page groups.

[0150] In addition, in yet another embodiment, the memory controller 210 can also give priority to the standby page groups storing more qualified physical pages. When a new physical block is detected and a new standby page group is obtained, the memory controller 210 will give priority to the standby page groups with more qualified physical pages for combination, which can reduce the number of standby page groups that need to be managed and reduce management overhead. At the same time, for the standby page groups with smaller remaining capacity, they can continue to be retained in the standby page group list, waiting to be used in combination with other standby page groups later.

[0151] On the other hand, in one embodiment, the memory controller 210 may also combine these spare page groups into virtual adjusted blocks of smaller capacity. For example, when the total number of qualified physical pages (135) is close to but does not reach the preset storage capacity (144) of the TLC mode physical block, the memory controller 210 may choose to combine these spare page groups into a virtual adjusted block with a capacity equivalent to the MLC mode physical block (96 physical pages are required). In this case, the memory controller 210 will record this virtual adjusted block in the adjusted block list and establish a mapping relationship between it and the corresponding spare page group. When a sufficient number of virtual adjusted blocks are subsequently accumulated (for example, two virtual adjusted blocks of MLC capacity, or three virtual adjusted blocks of SLC capacity), the memory controller 210 can combine them into a virtual spare block with a capacity equal to the preset storage capacity. Through this step-by-step combination method, the memory controller 210 can not only utilize the existing storage resources more timely, but also maintain a management mechanism consistent with the working mode adjustment scheme.

[0152] Fig. 9 FIG. 4 is a first exemplary schematic diagram of a process of constructing a virtual spare block according to an embodiment of the present disclosure.

[0153] Reference Fig. 9 , Fig. 9 FIG. 2 shows a process in which the memory controller 210 constructs a virtual spare block in different ways. In one embodiment, as shown by arrow A91, the memory controller 210 combines an adjusted block M1 in MLC mode and an adjusted block S1 in SLC mode into a virtual spare block V1. Since in MLC mode, a storage unit can store two bits of data, while in SLC mode, a storage unit only stores one bit of data, by combining an adjusted block in MLC mode and an adjusted block in SLC mode, the memory controller 210 can obtain a virtual spare block V1 (in the case of a physical block in TLC mode) with a storage capacity equivalent to that of a physical block in TLC mode. Fig. 9 It is marked as "VTLC", indicating that it has a storage capacity equivalent to TLC mode).

[0154] As shown by arrow A92, the memory controller 210 may also adopt another combination method to combine the three SLC mode adjusted blocks S2, S3 and S4 into a virtual spare block V2. Since the storage capacity of each SLC mode adjusted block is one third of the TLC mode physical block, the combination of the three SLC mode adjusted blocks can also obtain a virtual spare block V2 with a storage capacity equal to that of the TLC mode physical block.

[0155] In the process of constructing the virtual spare block, the memory controller 210 records these mapping relationships in the virtual spare block mapping table. For example, for the virtual spare block V1, the memory controller 210 records that it is composed of the adjusted blocks M1 and S1; for the virtual spare block V2, it records that it is composed of the adjusted blocks S2, S3 and S4. Through this mapping mechanism, when data access operations are required for the virtual spare block, the memory controller 210 can accurately find the physical location of the actual stored data.

[0156] Through this flexible combination method, the memory controller 210 can select the most suitable combination scheme to construct the virtual spare block according to the working mode of the existing adjusted blocks in the adjusted block list, so as to efficiently utilize the storage space that can still be used after the degradation.

[0157] Fig.10 It is a schematic diagram of an adjusted block list and a virtual spare block mapping table according to an embodiment of the present disclosure.

[0158] Reference Fig.10 In one embodiment, first, the memory controller 210 records the adjusted blocks of different working modes in corresponding lists. Fig.10 As shown, the memory controller 210 records the adjusted blocks of the MLC mode in the MLC adjusted block list TB101, and each record item includes the adjusted block serial number (such as M1, M2, etc.) and its corresponding physical address (such as MPB1, MPB2, etc.); similarly, the adjusted blocks of the SLC mode are recorded in the SLC adjusted block list TB102, and the record items include the adjusted block serial number (such as S1, S2, etc.) and the corresponding physical address (such as SPB1, SPB2, etc.).

[0159] As shown by arrow A101, when the memory controller 210 combines the adjusted blocks into virtual spare blocks, a mapping table TB103 that directly records the physical addresses can be established. In the mapping table TB103, the memory controller 210 records each virtual spare block sequence number (such as V1, V2, etc.) and its corresponding specific physical address. For example, the physical address corresponding to the virtual spare block V1 is "MPB1, SPB1", indicating that the virtual spare block is composed of an MLC mode adjusted block with a physical address of MPB1 and an SLC mode adjusted block with a physical address of SPB1. For another example, the physical address corresponding to the virtual spare block V2 is "SPB2, SPB3, SPB4", indicating that the virtual spare block is composed of three SLC mode adjusted blocks, and the physical addresses of these three SLC mode adjusted blocks are "SPB2, SPB3, SPB4" respectively.

[0160] In another embodiment, as shown by arrow A102, the memory controller 210 can also establish another mapping table TB104 based on the adjusted block sequence number. In the mapping table, the memory controller 210 records the correspondence between the virtual spare block sequence number and the adjusted block sequence number. For example, the adjusted block sequence number corresponding to the virtual spare block V1 is "M1, S1", indicating that the virtual spare block is composed of an MLC mode adjusted block with a sequence number of M1 and an SLC mode adjusted block with a sequence number of S1. For another example, the adjusted block sequence number corresponding to the virtual spare block V2 is "S2, S3, S4", indicating that the virtual spare block is composed of three SLC mode adjusted blocks with sequence numbers S2, S3 and S4 respectively.

[0161] In another embodiment, the memory controller 210 can also establish these two mapping tables at the same time. By maintaining these two different forms of mapping tables, the memory controller 210 can select a suitable mapping relationship according to actual needs. For example, when it is necessary to directly access the physical address, the mapping table TB103 can be used to achieve accurate positioning of the access data; when it is necessary to query the composition structure of the virtual spare block, the mapping table TB104 can be used to quickly query the general composition of the virtual spare block. This dual mapping mechanism not only improves the flexibility of data management, but also provides more convenience for subsequent data access operations.

[0162] Fig.11 4 is a second exemplary schematic diagram of a process for constructing a virtual spare block according to an embodiment of the present disclosure.

[0163] Reference Fig.11As shown by arrows A111, A112 and A113, the memory controller 210 extracts qualified physical pages from different physical blocks BB1, BB2 and BB3 to form spare page groups PG1, PG2 and PG3. Among them, spare page group PG1 contains physical pages PP1, PP2, PP5 and PP8; spare page group PG2 contains physical pages PP2, PP3 and PP4; spare page group PG3 contains physical pages PP5 and PP7. When the total number of qualified physical pages of these spare page groups reaches a preset storage capacity (for example, equivalent to the storage capacity of a TLC mode physical block), the memory controller 210 combines them into a virtual spare block V1 (in Fig.11 It is marked as "VTLC", indicating that it has a storage capacity equivalent to TLC mode).

[0164] As shown by arrow A114, the memory controller 210 establishes a corresponding relationship between the virtual spare block sequence number and the spare page group constituting the virtual spare block, and records the relationship in the mapping table TB111. For example, the adjusted block group corresponding to the virtual spare block V1 is "PG1, PG2, PG3", indicating that the virtual spare block is composed of these three spare page groups.

[0165] As shown by arrows A116, A117 and A118, the memory controller 210 also maintains a spare page group list TB113 for recording detailed information of each spare page group. The list includes identification information of the spare page group (such as PG1, PG2, PG3), corresponding physical block identification information (such as BB1, BB2, BB3) and qualified physical page information contained in each spare page group. Through this multi-level mapping relationship record, the memory controller 210 can not only track the composition structure of each virtual spare block, but also accurately locate the specific physical page position, thereby realizing refined management of storage resources.

[0166] In addition, in another embodiment, as shown by arrow A115, the memory controller 210 also establishes another more detailed mapping table TB112 to record the correspondence between the virtual spare block sequence number and the specific physical page address. For example, for the virtual spare block V1, its physical address is recorded as "PG1: PP1, PP2, PP5, PP8; PG2: PP2, PP3, PP4; PG3: PP5, PP7", which clearly identifies the specific physical pages included in each spare page group.

[0167] This detailed recording method has multiple advantages: first, when the memory controller 210 needs to write data to the virtual spare block, it can directly access the data according to the physical page address without the need for additional address conversion steps, thereby improving data access efficiency; second, since the location of each qualified physical page is clearly recorded, the memory controller 210 can achieve load balancing when writing data to avoid excessive use of certain physical pages; in addition, when some physical pages are abnormal, the memory controller 210 can quickly locate the problem location and adjust the composition of the virtual spare block in time to ensure the reliability of data storage.

[0168] Finally, this embodiment also provides a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code. When the computer readable code runs in the processor of the host system, the processor executes the process steps of the above-mentioned memory management method and realizes the function of the memory controller. The computer program product can be implemented in hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium. In another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK) and the like.

[0169] Based on the above, the memory management method and memory controller provided by the embodiments of the present disclosure can achieve the following effects:

[0170] By adjusting the working mode of the physical block with degraded performance from high storage density to low storage density (for example, from TLC to MLC or SLC), and verifying its availability after the adjustment, it is possible to fully utilize those storage units that cannot work normally in the original working mode but can still be used after degradation. At the same time, the memory controller 210 adopts a hierarchical adjustment strategy (for example, first downgrading from TLC to MLC, and then downgrading to SLC when necessary), which can find the best balance between storage capacity and data reliability.

[0171] Moreover, the memory controller 210 realizes flexible management of the degraded storage space by establishing data structures such as the adjusted block list, the spare page group list and the virtual spare block mapping table. For example, the memory controller 210 can combine multiple adjusted blocks into a virtual spare block, or extract qualified physical pages from the bad blocks of the lowest storage mode to form a spare page group, and then combine multiple spare page groups into a virtual spare block, thereby effectively supplementing the spare area resources of the rewritable non-volatile memory module 220.

[0172] In addition, by simultaneously maintaining the dual mapping relationship based on the adjusted block sequence number and the specific physical address in the virtual spare block mapping table, not only the data access efficiency is improved, but also the refined management of storage resources is achieved. When some storage units are abnormal, the memory controller 210 can quickly locate and adjust to ensure the stable operation of the storage device.

[0173] In summary, the embodiments of the present disclosure slow down the consumption of spare area resources and effectively extend the service life of the storage device by flexibly adjusting the working mode and finely managing the bad blocks.

[0174] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory management method, applicable to a storage device equipped with a rewritable non-volatile memory module, characterized in that: The method comprises: Get the first bad block; Determining whether the working mode of the first bad block can be adjusted; If the working mode of the first bad block can be adjusted, then: adjusting the working mode of the first bad block from a first storage mode to a second storage mode to obtain a second bad block, wherein a first storage capacity of each first storage unit of the first bad block in the first storage mode is greater than a second storage capacity of each second storage unit of the second bad block in the second storage mode; detecting the second bad block in the second storage mode; If the detection result of the second bad block is qualified, taking the second bad block as an adjusted block, and recording the adjusted block; According to the preset storage capacity and the respective storage capacities of the recorded multiple adjusted blocks, multiple target adjusted blocks are obtained from the multiple adjusted blocks, and the multiple target adjusted blocks are combined into a virtual spare block and incorporated into the spare area of ​​the rewritable non-volatile memory module, wherein the storage capacity of the virtual spare block is equal to the preset storage capacity.

2. The memory management method according to claim 1, characterized in that: The step of obtaining the first bad block includes: Detecting whether a physical block in a data area of ​​the rewritable non-volatile memory module meets a bad block determination criterion; and If the physical block in the data area meets the bad block determination standard, the physical block is determined to be the first bad block.

3. The memory management method according to claim 1, characterized in that: Before adjusting the working mode of the first bad block from the first storage mode to the second storage mode, the method further includes: Acquire a first spare block or a first virtual spare block from the spare area as a first data block; and The data in the first bad block is moved to the first data block, and the first data block is incorporated into the data area of ​​the rewritable non-volatile memory module.

4. The memory management method according to claim 1, characterized in that: The steps of obtaining the plurality of target adjusted blocks from the plurality of adjusted blocks according to the preset storage capacity and the respective storage capacities of the plurality of recorded adjusted blocks, and combining the plurality of target adjusted blocks into the virtual spare blocks and incorporating them into the spare area of ​​the rewritable non-volatile memory module include: Selecting the plurality of target aligned blocks from the plurality of recorded aligned blocks based on the preset storage capacity and the respective storage capacities of the plurality of recorded aligned blocks so that a total storage capacity of the plurality of target aligned blocks is equal to the preset storage capacity; combining the plurality of target aligned blocks into the virtual spare block; and The virtual spare block is incorporated into the spare area, and a mapping relationship between the virtual spare block and the plurality of target adjusted blocks is established.

5. The memory management method according to claim 1, characterized in that: The step of determining whether the working mode of the first bad block can be adjusted comprises: Determining whether the working mode of the first bad block is a minimum storage mode; If the working mode of the first bad block is not the lowest storage mode, determining that the working mode of the first bad block can be adjusted; If the working mode of the first bad block is the lowest storage mode, it is determined that the working mode of the first bad block cannot be adjusted.

6. The memory management method according to claim 5, characterized in that: If the working mode of the first bad block cannot be adjusted, the method further includes: The physical addresses of a plurality of qualified physical pages in the first bad block are recorded as a spare page group corresponding to the first bad block.

7. The memory management method according to claim 6, characterized in that: The method further comprises: According to the preset storage capacity and the storage capacities of the plurality of recorded spare page groups, selecting a plurality of target spare page groups from the plurality of spare page groups so that a total storage capacity of the plurality of target spare page groups is equal to the preset storage capacity; and The multiple target spare page groups are combined into another virtual spare block and incorporated into the spare area of ​​the rewritable non-volatile memory module, and a mapping relationship between the another virtual spare block and the multiple target spare page groups is established.

8. The memory management method according to claim 1, characterized in that: The step of determining whether the working mode of the first bad block can be adjusted comprises: Detecting each physical page in the first bad block to obtain a plurality of qualified physical pages; If the total storage capacity of the second bad block adjusted to the second storage mode is less than the total storage capacity of the multiple qualified physical pages of the first bad block, it is determined that the working mode of the first bad block cannot be adjusted, and the physical addresses of the multiple qualified physical pages are recorded as a spare page group corresponding to the first bad block; and If the total storage capacity of the second bad block adjusted to the second storage mode is not less than the total storage capacity of the plurality of qualified physical pages of the first bad block, it is determined that the working mode of the first bad block can be adjusted.

9. The memory management method according to claim 1, characterized in that: The step of detecting the second bad block in the second storage mode comprises: Writing detection data to the second bad block, and reading the detection data from the second bad block; If the reading result of the detection data is successful, determining that the detection result of the second bad block is qualified; and If the reading result of the detection data is unsuccessful, it is determined that the detection result of the second bad block is unqualified.

10. The memory management method according to claim 9, characterized in that: The method further comprises: If the detection result of the second bad block in the second storage mode is unqualified and the working mode of the second bad block can be adjusted, then: adjusting the operation mode of the second bad block from the second storage mode to a third storage mode to obtain a third bad block, wherein the second storage capacity of each second storage unit of the second bad block in the second storage mode is greater than the third storage capacity of each third storage unit of the third bad block in the third storage mode; and If the detection result of the third bad block is qualified, the third bad block is recorded as another adjusted block.

11. A memory controller for controlling a storage device equipped with a rewritable non-volatile memory module, characterized in that: The memory controller comprises: A memory interface control circuit, used for electrically connecting to the rewritable non-volatile memory module; A data management circuit electrically connected to the connection interface circuit of the storage device, for receiving data and commands from a host system via the connection interface circuit; A buffer memory for caching data; and a processor electrically connected to the memory interface control circuit, the data management circuit and the buffer memory, wherein the processor is configured to: Get the first bad block; Determining whether the working mode of the first bad block can be adjusted; If the working mode of the first bad block can be adjusted, then: adjusting the working mode of the first bad block from a first storage mode to a second storage mode to obtain a second bad block, wherein a first storage capacity of each first storage unit of the first bad block in the first storage mode is greater than a second storage capacity of each second storage unit of the second bad block in the second storage mode; detecting the second bad block in the second storage mode; If the detection result of the second bad block is qualified, taking the second bad block as an adjusted block, and recording the adjusted block; According to the preset storage capacity and the respective storage capacities of the recorded multiple adjusted blocks, multiple target adjusted blocks are obtained from the multiple adjusted blocks, and the multiple target adjusted blocks are combined into a virtual spare block and incorporated into the spare area of ​​the rewritable non-volatile memory module, wherein the storage capacity of the virtual spare block is equal to the preset storage capacity.

12. The memory controller according to claim 11, wherein: The bad block determination criteria include: The number of program-erase times of the physical block exceeds a first preset program-erase threshold; The number of error correction bits of the data in the physical block exceeds a first preset error correction bit threshold; The read latency of the physical block exceeds a first preset read latency threshold; or The number of write failures of the physical block exceeds a first preset write failure threshold.

13. The memory controller according to claim 11, wherein: The processor is also configured to: Before adjusting the working mode of the first bad block from the first storage mode to the second storage mode: Acquire a first spare block or a first virtual spare block from the spare area as a first data block; as well as The data in the first bad block is moved to the first data block, and the first data block is incorporated into the data area of ​​the rewritable non-volatile memory module.

14. The memory controller according to claim 11, wherein: The steps of obtaining the plurality of target adjusted blocks from the plurality of adjusted blocks according to the preset storage capacity and the respective storage capacities of the plurality of recorded adjusted blocks, and combining the plurality of target adjusted blocks into the virtual spare blocks and incorporating them into the spare area of ​​the rewritable non-volatile memory module include: Selecting the plurality of target aligned blocks from the plurality of recorded aligned blocks based on the preset storage capacity and the respective storage capacities of the plurality of recorded aligned blocks so that a total storage capacity of the plurality of target aligned blocks is equal to the preset storage capacity; combining the plurality of target aligned blocks into the virtual spare block; and The virtual spare block is incorporated into the spare area, and a mapping relationship between the virtual spare block and the plurality of target adjusted blocks is established.

15. The memory controller according to claim 11, wherein: The step of determining whether the working mode of the first bad block can be adjusted comprises: Determining whether the working mode of the first bad block is a minimum storage mode; If the working mode of the first bad block is not the lowest storage mode, determining that the working mode of the first bad block can be adjusted; If the working mode of the first bad block is the lowest storage mode, it is determined that the working mode of the first bad block cannot be adjusted.

16. The memory controller according to claim 15, characterized in that: If the working mode of the first bad block cannot be adjusted, the processor is further configured to: The physical addresses of a plurality of qualified physical pages in the first bad block are recorded as a spare page group corresponding to the first bad block.

17. The memory controller according to claim 16, wherein: The processor is also configured to: According to the preset storage capacity and the respective storage capacities of the plurality of recorded spare page groups, selecting a plurality of target spare page groups from the plurality of spare page groups so that a total storage capacity of the plurality of target spare page groups is equal to the preset storage capacity; as well as The multiple target spare page groups are combined into another virtual spare block and incorporated into the spare area of ​​the rewritable non-volatile memory module, and a mapping relationship between the another virtual spare block and the multiple target spare page groups is established.

18. The memory controller according to claim 11, wherein: The step of determining whether the working mode of the first bad block can be adjusted comprises: Detecting each physical page in the first bad block to obtain a plurality of qualified physical pages; If the total storage capacity of the second bad block adjusted to the second storage mode is less than the total storage capacity of the multiple qualified physical pages of the first bad block, it is determined that the working mode of the first bad block cannot be adjusted, and the physical addresses of the multiple qualified physical pages are recorded as a spare page group corresponding to the first bad block; and If the total storage capacity of the second bad block adjusted to the second storage mode is not less than the total storage capacity of the plurality of qualified physical pages of the first bad block, it is determined that the working mode of the first bad block can be adjusted.

19. The memory controller according to claim 11, wherein: The step of detecting the second bad block in the second storage mode comprises: Writing detection data to the second bad block, and reading the detection data from the second bad block; If the reading result of the detection data is successful, determining that the detection result of the second bad block is qualified; and If the reading result of the detection data is unsuccessful, it is determined that the detection result of the second bad block is unqualified.

20. The memory controller according to claim 19, wherein: The processor is also configured to: If the detection result of the second bad block in the second storage mode is unqualified and the working mode of the second bad block can be adjusted: adjusting the operating mode of the second bad block from the second storage mode to a third storage mode to obtain a third bad block, wherein the second storage capacity of each second storage unit of the second bad block in the second storage mode is greater than the third storage capacity of each third storage unit of the third bad block in the third storage mode; as well as If the detection result of the third bad block is qualified, the third bad block is recorded as another adjusted block.

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