Method and device for automatically adjusting chip pin network

Abstract

The invention discloses a method and a device for automatically adjusting a chip pin network. The method comprises the following steps of: determining a first target point in an FPGA (Field Programmable Gate Array) chip based on setting software; establishing a first coordinate system by taking the current first target point as an original point; determining a second target point in the circuit board, and establishing a second coordinate system; determining the position of the second end of each fly line in the first coordinate system according to the position of the second end of each fly line in the second coordinate system and the position of the current first target point in the second coordinate system; in the first coordinate system, when the number of the adjustable pins in each quadrant is matched with the number of the second ends of the fly lines in the same quadrant, a network of at least part of the adjustable pins in the FPGA chip is adjusted, so that the first ends of the fly lines with the set number and the second ends of the fly lines are located in the same quadrant of the first coordinate system. According to the invention, the network of the adjustable pins in the FPGA chip can be automatically, quickly and accurately adjusted, and the design efficiency and accuracy of a circuit board are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a method and device for automatically adjusting a chip pin network. Background Art

[0002] As an advanced integrated circuit technology, Field Programmable Gate Array (FPGA) has the unique advantage of allowing users to program and configure according to specific needs after production is completed, and flexibly realize diverse digital logic functions. Compared with one-time ASICs, the significant advantage of FPGA lies in its unparalleled flexibility and reusability, which means that designers can adapt to different application scenarios by reprogramming without redesigning hardware, greatly shortening product time to market and reducing development costs.

[0003] However, in the rapidly developing field of modern electronic design, the widespread application of FPGA technology has also brought unprecedented challenges, especially in the context of complex printed circuit board (PCB) design. FPGA has a large number of pins and its signal network is intricate. Accurate and fast adjustment of the pin network has become a difficult problem that designers must overcome. The process of pin adjustment is often not achieved overnight. Due to the complexity of signal distribution and the accuracy of design requirements, the same pin may need to undergo multiple adjustments and optimizations to ensure that the design meets all performance indicators.

[0004] Cadence software is the industry's leading electronic design automation tool, mainly used for PCB design. It is known for its powerful layout design function and is the industry's leading PCB design software. However, even with such powerful tool support, the automatic adjustment of FPGA pin network is still a problem to be solved. In the conventional Cadence design process, engineers need to execute the swap pin command and manually swap the FPGA pins by clicking on two pins. Due to the complexity of the FPGA network, designers often spend a lot of time adjusting the pins.

[0005] Among the mainstream software in the industry, only Altium Designer supports automatic FPGA pin adjustment, while other software only supports manual exchange of pin networks. This traditional method of manually adjusting pin networks is not only inefficient and consumes a lot of manpower and material resources, but also easily introduces design defects due to human errors, which in turn affects the reliability and stability of the product. Therefore, how to use more efficient and intelligent automated tools and methods to optimize the management of FPGA pin networks has become one of the keys to improving design efficiency. Summary of the invention

[0006] The present invention provides a method and device for automatically adjusting a chip pin network, which can automatically, quickly and accurately adjust the network of adjustable pins in an FPGA chip, thereby significantly improving the design efficiency and accuracy of a circuit board.

[0007] According to one aspect of the present invention, a method for automatically adjusting a chip pin network is provided, the method comprising:

[0008] Determining a first target point in the FPGA chip based on the setting software; wherein the FPGA chip includes a plurality of adjustable pins;

[0009] Establish a first coordinate system with the current first target point as the origin;

[0010] Based on the setting software, a second target point in the circuit board is determined, and a second coordinate system is established with the second target point; wherein the circuit board includes at least one FPGA chip, a plurality of pads, and a plurality of flying wires; a first end of each flying wire is connected to a corresponding adjustable pin, and a second end of each flying wire is connected to a corresponding pad;

[0011] Determine the position of the second end of each flying line in the first coordinate system according to the position of the second end of each flying line in the second coordinate system and the current position of the first target point in the second coordinate system;

[0012] In the first coordinate system, when the number of the adjustable pins in each quadrant matches the number of the second ends of the flying wires in the same quadrant, the network of at least part of the adjustable pins in the FPGA chip is adjusted so that the first ends of the set number of flying wires and the second ends of the flying wires are located in the same quadrant of the first coordinate system.

[0013] Optionally, determining the first target point in the FPGA chip based on the setting software includes:

[0014] The center of the FPGA chip is obtained through a setting function in the setting software, and the center of the FPGA chip is determined as the first target point.

[0015] Optionally, determining the position of the second end of each flying line in the first coordinate system according to the position of the second end of each flying line in the second coordinate system and the position of the current first target point in the second coordinate system includes:

[0016] Determine a first coordinate and each second coordinate, wherein the first coordinate is the coordinate of the current first target point in the second coordinate system, and each second coordinate is the coordinate of the second end of each flying line in the second coordinate system;

[0017] The position of the second end of each flying line in the first coordinate system is determined according to the difference between the horizontal coordinate in each second coordinate and the horizontal coordinate in the first coordinate, and the difference between the vertical coordinate in each second coordinate and the vertical coordinate in the first coordinate.

[0018] Optionally, before adjusting the network of at least part of the adjustable pins in the FPGA chip, the method includes:

[0019] Determine the number of adjustable pins in each quadrant in the first coordinate system and determine the number of second ends of the flying wires in each quadrant according to the positions of the second ends of the flying wires in the first coordinate system;

[0020] Determining whether the number of adjustable pins in each quadrant of the first coordinate system is greater than or equal to the number of second ends of the flying leads in the same quadrant;

[0021] If so, determining that the number of adjustable pins in each quadrant matches the number of second ends of the flying leads in the same quadrant;

[0022] If not, the position of the first target point is adjusted in the FPGA chip, and then the process returns to the step of establishing the first coordinate system with the current first target point as the origin.

[0023] Optionally, when after adjusting the position of the first target point multiple times, when there is a mismatch between the number of adjustable pins in at least one quadrant of the first coordinate system and the number of second ends of the flying wires in the same quadrant, the network of adjustable pins is adjusted so that the sum of the numbers of adjustable pins in two adjacent quadrants in the first coordinate system is greater than or equal to the sum of the numbers of the second ends of the flying wires in the two adjacent quadrants.

[0024] Optionally, the plurality of flying leads include a plurality of differential flying leads and a plurality of single-line flying leads;

[0025] The step of adjusting the network of at least part of the adjustable pins in the FPGA chip so that the first ends of a set number of the flying wires and the second ends of the flying wires are both located in the same quadrant of the first coordinate system includes:

[0026] Adjusting the network of adjustable pins connected to each differential flying lead to the same quadrant of the first coordinate system as the second end of the differential flying lead;

[0027] Remove the adjustable pins connected to each differential flying lead from the FPGA chip;

[0028] The network of adjustable pins connected to the single-wire flying lead is adjusted so that the first end and the second end of at least part of the single-wire flying lead are located in the same quadrant of the first coordinate system.

[0029] Optionally, after adjusting the network of adjustable pins connected to each differential flying lead to the same quadrant of the first coordinate system where the second end of the differential flying lead is located, the method further includes:

[0030] In each quadrant of the first coordinate system, determining whether there are any crossed differential flying wires;

[0031] If so, the networks of the adjustable pins connected to the differential flying leads that cross each other are exchanged in the same quadrant.

[0032] Optionally, after adjusting the network of at least part of the adjustable pins in the FPGA chip so that the first ends of a set number of the flying wires and the second ends of the flying wires are both located in the same quadrant of the first coordinate system, the method further comprises:

[0033] Determine whether there are intersecting flying lines in each quadrant of the first coordinate system;

[0034] If so, the networks of the adjustable pins to which the first ends of the mutually crossing flying leads are connected are exchanged in the same quadrant.

[0035] Optionally, when the actual duration of adjusting the network of the adjustable pin is greater than or equal to the set duration, adjusting the network of the adjustable pin is stopped.

[0036] According to another aspect of the present invention, there is provided a device for automatically adjusting a chip pin network, characterized in that it comprises: a first determining module, a first establishing module, a second establishing module, a second determining module and an adjusting module;

[0037] The first determination module is used to determine a first target point in the FPGA chip based on the setting software; wherein the FPGA chip includes a plurality of adjustable pins;

[0038] The first establishing module is used to establish a first coordinate system with the current first target point as the origin;

[0039] The second establishment module is used to determine a second target point in the circuit board based on the setting software, and establish a second coordinate system with the second target point; wherein the circuit board includes at least one FPGA chip, a plurality of pads and a plurality of flying wires; the first end of each flying wire is connected to the corresponding adjustable pin, and the second end of each flying wire is connected to the corresponding pad;

[0040] The second determination module is used to determine the position of the second end of each flying line in the first coordinate system according to the position of the second end of each flying line in the second coordinate system and the current position of the first target point in the second coordinate system;

[0041] The adjustment module is used to adjust the network of at least part of the adjustable pins in the FPGA chip in the first coordinate system when the number of the adjustable pins in each quadrant matches the number of the second ends of the flying wires in the same quadrant, so that the first ends of a set number of the flying wires and the second ends of the flying wires are both located in the same quadrant of the first coordinate system.

[0042] The embodiment of the present invention provides a method for automatically adjusting the chip pin network, the method comprising: first determining a first target point in an FPGA chip and determining a second target point in a circuit board based on setting software, and establishing a first coordinate system with the first target point as the origin, and establishing a second coordinate system with the second target point as the origin. Then, the position of the second end of each flying wire in the first coordinate system is determined according to the position of the second end of each flying wire in the circuit board in the second coordinate system and the position of the first target point in the second coordinate system. Then, when the number of adjustable pins in each quadrant of the first coordinate system matches the number of second ends of the flying wires in the same quadrant, the network of at least part of the adjustable pins in the FPGA chip is adjusted so that the first end of the set number of flying wires and the second end of the flying wires are both located in the same quadrant of the first coordinate system. In this embodiment, by importing the circuit board into the setting software and determining two coordinate systems through the setting software, the network of the adjustable pins can be automatically adjusted based on the setting software without manual adjustment. After adjusting the network of some adjustable pins, the first end and the second end of at least some of the flying wires can be located in the same quadrant of the first coordinate system, ensuring that the first end and the second end of the flying wire are closer, thereby improving the current situation of the intricate arrangement of the flying wires in the circuit board. In summary, the method for automatically adjusting the chip pin network provided in this embodiment can automatically, quickly and accurately adjust the network of adjustable pins in the FPGA chip, significantly improving the design efficiency and accuracy of the circuit board.

[0043] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 is a flow chart of a method for automatically adjusting a chip pin network provided according to an embodiment of the present invention;

[0046] Figure 2is a structural schematic diagram of an FPGA chip in setting software provided by an embodiment of the present invention;

[0047] Figure 3 is a schematic diagram of the structure of a circuit board in setting software provided by an embodiment of the present invention;

[0048] Figure 4 is a schematic diagram of the structure of another circuit board in setting software provided by an embodiment of the present invention;

[0049] Figure 5 is a schematic diagram of the structure of another circuit board in setting software provided by an embodiment of the present invention;

[0050] Figure 6 is a schematic diagram of the structure of another circuit board in setting software provided by an embodiment of the present invention;

[0051] Figure 7 is a flow chart of another method for automatically adjusting a chip pin network provided according to an embodiment of the present invention;

[0052] Figure 8 It is a structural schematic diagram of a device for automatically adjusting a chip pin network provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0054] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0055] Figure 1is a flow chart of a method for automatically adjusting a chip pin network according to an embodiment of the present invention, referring to Figure 1 The method for automatically adjusting the chip pin network provided in this embodiment includes the following steps:

[0056] S110 , determining a first target point in the FPGA chip based on the setting software.

[0057] Among them, the FPGA chip includes multiple adjustable pins.

[0058] Specifically, the setting software may be Cadence software. The first target point is located in the FPGA chip. Figure 2 is a schematic diagram of the structure of an FPGA chip in the setting software provided according to an embodiment of the present invention, with reference to Figure 2 , Figure 2 The red dot in the middle represents the pin 110 of the FPGA chip. The FPGA chip includes multiple pins 110. Some of the pins 110 are adjustable pins, which are network-adjustable pins. Another part of the pins 110 are non-adjustable pins, which may be ground pins, power pins, and the like.

[0059] S120: Establish a first coordinate system with the current first target point as the origin.

[0060] For details, please refer to Figure 2 The first coordinate system may be a rectangular coordinate system. After the first coordinate system is established, the position of each adjustable pin in the FPGA chip in the first coordinate system will be determined, and the position of the adjustable pin includes the quadrant of the first coordinate system to which the adjustable pin belongs.

[0061] S130, determining a second target point in the circuit board based on the setting software, and establishing a second coordinate system with the second target point.

[0062] The circuit board includes at least one FPGA chip, a plurality of pads and a plurality of flying leads; the first end of each flying lead is connected to the corresponding adjustable pin, and the second end of each flying lead is connected to the corresponding pad.

[0063] Specifically, the second target point can be located at any position in the circuit board. The second coordinate system can also be a rectangular coordinate system. The circuit board in this embodiment is a printed circuit board (PCB). Figure 3 is a schematic diagram of the structure of a circuit board in setting software according to an embodiment of the present invention, with reference to Figure 3 , Figure 3 A schematic diagram of the circuit board structure before adjusting the network of adjustable pins. Figure 3 The exemplary circuit board includes an FPGA chip, a plurality of pads and a plurality of flying wires ( Figure 3The medium blue lines are flying lines), and multiple flying lines are intertwined with each other.

[0064] In the circuit board, the first ends of different flying wires are connected to different networks of adjustable pins, and the second ends of different flying wires are connected to different pads. The flying wires connect the FPGA chip with other devices in the circuit board to realize information exchange between the FPGA chip and other devices.

[0065] S140, determining the position of the second end of each flying line in the first coordinate system according to the position of the second end of each flying line in the second coordinate system and the position of the current first target point in the second coordinate system.

[0066] Specifically, before executing step S140, first obtain the position of the second end of each flying line in the second coordinate system, which may be the coordinate of the second end of the flying line in the second coordinate system, and obtain the position of the first target point in the second coordinate system, which may be the coordinate of the first target point in the second coordinate system.

[0067] The quadrant to which the second end of the flying line belongs in the first coordinate system can be determined based on the difference between the coordinates of the second end of the flying line in the second coordinate system and the coordinates of the first target point in the second coordinate system. Exemplarily, the coordinates of the second end of a flying line in the second coordinate system are (x1, y1), and the coordinates of the first target point in the second coordinate system are (x2, y2). The quadrant to which the second end of the flying line belongs in the first coordinate system is determined based on the positive and negative difference of x1 minus x2 and the positive and negative difference of y1 minus y2. x3 = x1-x2, y3 = y1-y2, when x3 is positive and y3 is positive, it is determined that the second end of the flying line is in the first quadrant of the first coordinate system; when x3 is negative and y3 is positive, it is determined that the second end of the flying line is in the second quadrant of the first coordinate system; when x3 is negative and y3 is negative, it is determined that the second end of the flying line is in the third quadrant of the first coordinate system; when x3 is positive and y3 is negative, it is determined that the second end of the flying line is in the fourth quadrant of the first coordinate system.

[0068] S150. In the first coordinate system, when the number of adjustable pins in each quadrant matches the number of second ends of the flying wires in the same quadrant, adjust the network of at least part of the adjustable pins in the FPGA chip so that the first ends of a set number of flying wires and the second ends of the flying wires are located in the same quadrant of the first coordinate system.

[0069] Specifically, the number of the second ends of the flying leads can also be understood as the number of pads connected to the second ends of the flying leads. The set number can be the number of all flying leads connected to the adjustable pins, and the set number can also be manually set.

[0070] The matching of the number of adjustable pins in a quadrant with the number of second ends of the flying leads in the same quadrant means that the number of adjustable pins in the same quadrant is greater than or equal to the number of second ends of the flying leads in the same quadrant.

[0071] In each quadrant of the first coordinate system, when the number of adjustable pins matches the number of second ends of the flying wires, after adjusting the network of the adjustable pins, it can be ensured that the first end of the same flying wire and its second end are located in the same quadrant, thereby making the flying wire arrangement in the circuit board more neat after adjusting the network of the adjustable pins.

[0072] When the network of the adjustable pin of the FPGA chip is adjusted, the position of the first end of the flying wire will change. The network of the adjustable pin changes, which means that the network name and pin number of the adjustable pin change. For example, Figure 4 is a schematic diagram of the structure of another circuit board in setting software provided according to an embodiment of the present invention, Figure 5 is a schematic diagram of the structure of another circuit board in setting software provided according to an embodiment of the present invention, Figure 4 This is a schematic diagram of the structure before adjusting the network of adjustable pins. Figure 5 2 is a schematic diagram of the structure after adjusting the network of adjustable pins. The plurality of flying wires in the circuit board include a first flying wire 210 and a second flying wire 220. Figure 4 and Figure 5 The coordinate systems in are all the first coordinate systems. Figure 4 Before adjustment, the first end of the first flying wire 210 is connected to the adjustable pin P1 located in the fourth quadrant, the second end of the first flying wire 210 is located in the second quadrant, the first end of the second flying wire 220 is connected to the adjustable pin P2 located in the second quadrant, and the second end of the second flying wire 220 is located in the fourth quadrant. In order to make the first end of the first flying wire 210 and the second end thereof located in the same quadrant of the first coordinate system, and to make the first end of the second flying wire 220 and the second end thereof located in the same quadrant of the first coordinate system, reference is made to Figure 5 , adjust the network of the adjustable pin P1 connected to the first end of the first flying lead 210 and adjust the network of the adjustable pin P1 to the first quadrant, and adjust the network of the adjustable pin P2 connected to the first end of the second flying lead 220, and adjust the adjustable pin P2 to the fourth quadrant.

[0073] When there are many flying leads in the circuit board, the network adjustment method of the adjustable pins connected to the first end of each flying lead is the same and can be adjusted simultaneously, thereby improving the adjustment efficiency. Figure 6 is a schematic diagram of the structure of another circuit board in setting software provided according to an embodiment of the present invention, Figure 6 Can Figure 3 The schematic diagram of the circuit board after adjusting the adjustable pins is shown in the figure. Figure 6 Even if there are a large number of flying wires in the circuit board, the method provided in this embodiment can still make the flying wires in the circuit board smoother.

[0074] It should be noted that steps S110 to S150 provided in this embodiment can all be executed based on setting software, and there is no need to manually adjust the network of the adjustable pins.

[0075] The present embodiment provides a method for automatically adjusting the chip pin network, the method comprising: first determining the first target point in the FPGA chip and determining the second target point in the circuit board based on the setting software, and establishing a first coordinate system with the first target point as the origin, and establishing a second coordinate system with the second target point as the origin. Then, the position of the second end of each flying wire in the first coordinate system is determined according to the position of the second end of each flying wire in the circuit board in the second coordinate system and the position of the first target point in the second coordinate system. Then when the number of adjustable pins in each quadrant of the first coordinate system matches the number of second ends of the flying wires in the same quadrant, the network of at least part of the adjustable pins in the FPGA chip is adjusted so that the first end of the set number of flying wires and the second end of the flying wires are both located in the same quadrant of the first coordinate system. In the present embodiment, by importing the circuit board into the setting software and determining two coordinate systems through the setting software, the network of the adjustable pins can be automatically adjusted based on the setting software without manual adjustment. After adjusting the network of some adjustable pins, the first end and the second end of at least some of the flying wires can be located in the same quadrant of the first coordinate system, ensuring that the first end and the second end of the flying wire are closer, thereby improving the current situation of the intricate arrangement of the flying wires in the circuit board. In summary, the method for automatically adjusting the chip pin network provided in this embodiment can automatically, quickly and accurately adjust the network of adjustable pins in the FPGA chip, significantly improving the design efficiency and accuracy of the circuit board.

[0076] Optionally, determining the first target point in the FPGA chip based on setting software includes: obtaining the center of the FPGA chip through a setting function in the setting software, and determining the center of the FPGA chip as the first target point.

[0077] Specifically, the setting function can be an API function in the Cadence software. The center of the FPGA chip is obtained by traversing the numbers of the adjustable pins in the FPGA chip. After the first target point is determined, the first coordinate system will be determined. After the first coordinate system is determined, the adjustable pins in the FPGA chip will be divided into four quadrants. Whether the pins in the FPGA chip are adjustable can be set in the schematic diagram, and the information of the adjustable pins can be imported into the circuit board through the netlist. Setting the center of the FPGA chip as the initial first target point can ensure that the number of adjustable pins in each quadrant in the initially established first coordinate system is approximately equal, and when the position of the first target point is adjusted subsequently, the number of times the first target point is adjusted can be reduced.

[0078] Optionally, determining the position of the second end of each flying line in the first coordinate system according to the position of the second end of each flying line in the second coordinate system and the position of the current first target point in the second coordinate system includes:

[0079] Determine a first coordinate and each second coordinate, wherein the first coordinate is the coordinate of the current first target point in the second coordinate system, and each second coordinate is the coordinate of the second end of each flying line in the second coordinate system;

[0080] The position of the second end of each flying line in the first coordinate system is determined according to the difference between the abscissa in each second coordinate and the abscissa in the first coordinate, and the difference between the ordinate in each second coordinate and the ordinate in the first coordinate.

[0081] Specifically, the position of the second end of the flying line in the first coordinate system represents the quadrant to which the second end of the flying line belongs in the first coordinate system or the position on the coordinate axis in the first coordinate system.

[0082] In the second coordinate system, the coordinates of the current first target point and the coordinates of the second end of each flying line are determined, and the horizontal and vertical coordinates in these two coordinates are made different, and the quadrant of the second end of the flying line in the first coordinate system is determined according to the positive and negative difference of the horizontal coordinate and the positive and negative difference of the vertical coordinate. When the difference of the horizontal coordinate is 0 or the difference of the vertical coordinate is 0, the position of the second end of the flying line on the coordinate axis in the first coordinate system can be determined.

[0083] Optional, Figure 7 FIG. 1 is a flow chart of another method for automatically adjusting a chip pin network according to an embodiment of the present invention, referring to FIG. Figure 7 The method for automatically adjusting the chip pin network provided in this embodiment includes the following steps:

[0084] S210, determining a first target point in the FPGA chip based on the setting software.

[0085] Specifically, the content of step S210 is the same as that of step S110. For the description of step S210, please refer to the description of step S110, which will not be repeated here.

[0086] S220: Establish a first coordinate system with the current first target point as the origin.

[0087] Specifically, the content of step S220 is the same as that of step S120. For the description of step S220, please refer to the description of step S120, which will not be repeated here.

[0088] S230: Determine a second target point in the circuit board based on the setting software, and establish a second coordinate system with the second target point.

[0089] Specifically, the content of step S230 is the same as that of step S120. For the description of step S230, please refer to the description of step S130, which will not be repeated here.

[0090] S240, determining the position of the second end of each flying line in the first coordinate system according to the position of the second end of each flying line in the second coordinate system and the position of the current first target point in the second coordinate system.

[0091] Specifically, the content of step S240 is the same as that of step S140. For the description of step S240, please refer to the description of step S140, which will not be repeated here.

[0092] S250, determining the number of adjustable pins in each quadrant in the first coordinate system and determining the number of second ends of the flying wires in each quadrant according to the positions of the second ends of the flying wires in the first coordinate system.

[0093] Specifically, after the first coordinate system is determined, the number of adjustable pins in each quadrant of the first coordinate system can be determined. The position of the second end of the flying wire indicates the quadrant to which the second end of the flying wire belongs in the first coordinate system. Once the quadrant to which the second end of the flying wire belongs is determined, the number of the second ends of the flying wire in each quadrant can be easily determined.

[0094] S260, determining whether the number of adjustable pins in each quadrant of the first coordinate system is greater than or equal to the number of second ends of the flying wires in the same quadrant.

[0095] Specifically, in each quadrant of the first coordinate system, it is compared whether the number of adjustable pins is greater than or equal to the number of the second ends of the flying wires, if the number of adjustable pins is greater than or equal to the number of the second ends of the flying wires in the four quadrants of the first coordinate system, S270 is executed. Otherwise, S280 is executed.

[0096] If yes, then execute S270. If no, then execute S280.

[0097] S270. In the first coordinate system, determine whether the number of adjustable pins in each quadrant matches the number of second ends of the flying wires in the same quadrant.

[0098] S280, adjusting the position of the first target point in the FPGA chip, and then returning to step S220.

[0099] Specifically, the position of the adjusted first target point is still in the FPGA chip. When adjusting the position of the first target point, the adjustment direction of the first target point is determined according to the difference between the number of adjustable pins in each quadrant and the number of the second ends of the flying wires. For example, when the number of adjustable pins in the first quadrant is less than the number of the second ends of the flying wires in the first quadrant, and the number of adjustable pins in the second quadrant is greater than the number of the second ends of the flying wires in the second quadrant, the first target point is adjusted in a direction close to the first quadrant. When the position of the first target point is adjusted, the position of the first coordinate system will be adjusted, and similarly, the positions of the four quadrants will be adjusted.

[0100] S290, adjusting the network of at least part of the adjustable pins in the FPGA chip so that the first ends of a set number of flying wires and the second ends of the flying wires are located in the same quadrant of the first coordinate system.

[0101] Specifically, for the description of step S290, please refer to the description of step S150.

[0102] Optionally, when after adjusting the position of the first target point multiple times, there is a mismatch between the number of adjustable pins in at least one quadrant of the first coordinate system and the number of second ends of the flying wires in the same quadrant, the network of adjustable pins is adjusted so that the sum of the numbers of adjustable pins in two adjacent quadrants in the first coordinate system is greater than or equal to the sum of the numbers of the second ends of the flying wires in the two adjacent quadrants.

[0103] Specifically, after adjusting the position of the first target point for multiple times, the newly created first coordinate system still cannot ensure that the number of adjustable pins in the four quadrants matches the number of second ends of the flying wires in the same quadrant. When the sum of the numbers of adjustable pins in two adjacent quadrants is greater than or equal to the sum of the numbers of the second ends of the flying wires in two adjacent quadrants, the network of adjustable pins can be adjusted, so that the flying wires in two adjacent quadrants can share a row of adjustable pins near the first target point.

[0104] Optionally, the multiple flying leads include multiple differential flying leads and multiple single-line flying leads; two differential flying leads transmit a set of differential signals, the differential signals may include a first setting signal and a second setting signal, the first setting signal may be a differential P signal, and the second setting signal may be a differential N signal.

[0105] Adjusting the network of at least part of the adjustable pins in the FPGA chip so that the first ends of a set number of the flying wires and the second ends of the flying wires are all located in the same quadrant of the first coordinate system comprises the following steps:

[0106] S151, adjusting the network of adjustable pins connected to each differential flying lead to be in the same quadrant of the first coordinate system as the second end of the differential flying lead.

[0107] Specifically, when adjusting the network of adjustable pins, the network of adjustable pins connected to the differential flying leads is adjusted first. When adjusting, the adjustable pins are adjusted to appropriate positions in sequence according to the coordinates of the second ends of the differential flying leads, so that the distance between the first end and the second end of each differential flying lead in the same quadrant is as small as possible.

[0108] S152, remove the adjustable pins connected to each differential flying lead from the FPGA chip.

[0109] Specifically, after adjusting the network of adjustable pins connected to the differential flying leads, these adjustable pins are temporarily removed from the FPGA chip to avoid moving the network of adjustable pins connected to the differential flying leads to other quadrants during the subsequent adjustment of the network of adjustable pins connected to the single-line flying leads.

[0110] It should be noted that step S152 only temporarily removes the adjustable pins connected to the differential flying leads from the FPGA chip. After executing step S153, these adjustable pins can be moved back into the FPGA chip.

[0111] S153, adjusting the network of adjustable pins connected to the single-line flying lead so that the first end and the second end of at least part of the same single-line flying lead are located in the same quadrant of the first coordinate system.

[0112] Specifically, after the network of adjustable pins connected to the differential flying leads is adjusted reasonably, the network of adjustable pins connected to the single-line flying leads is adjusted so that the first end and the second end of at least some of the same single-line flying leads are located in the same quadrant of the first coordinate system. At least some of the single-line flying leads can be all the single-line flying leads.

[0113] When adjusting the network of adjustable pins connected to the flying leads, this embodiment first adjusts the network of adjustable pins connected to the differential flying leads, and then adjusts the network of adjustable pins connected to the single-line flying leads, to avoid the first end of the differential flying lead and its second end not being in the same quadrant of the first coordinate system, thereby causing a more disordered flying lead arrangement.

[0114] Optionally, after adjusting the network of adjustable pins connected to each differential flying lead to the same quadrant of the first coordinate system where the second end of the differential flying lead is located, it also includes: determining whether there are crossed differential flying leads in each quadrant of the first coordinate system; if so, exchanging the networks of adjustable pins connected to the differential flying leads that cross each other in the same quadrant.

[0115] Specifically, after adjusting the first end and the second end of the differential flying lead to the same quadrant, determine whether there is any crossover of the differential flying lead that transmits the first setting signal in the differential signal in the same quadrant; if there is a crossover, the network of adjustable pins at the first end of the differential flying lead that transmits the differential signal is exchanged as a whole, that is, the differential flying lead that transmits the first setting signal and the differential flying lead that transmits the second setting signal are exchanged to ensure that the differential flying leads in the same quadrant do not cross over, thereby further improving the neatness of the flying leads in the circuit board.

[0116] Optionally, after adjusting the network of at least part of the adjustable pins in the FPGA chip so that the first ends of a set number of flying wires and the second ends of the flying wires are all located in the same quadrant of the first coordinate system, it also includes: determining whether there are intersecting flying wires in each quadrant of the first coordinate system; if so, exchanging the network of adjustable pins connected to the first ends of the intersecting flying wires in the same quadrant.

[0117] Specifically, in the same quadrant of the first coordinate system, the network of adjustable pins connected to the first ends of the mutually intersecting flying wires is exchanged, so that the flying wires in each quadrant can be smoother.

[0118] Optionally, when the actual duration of adjusting the network of the adjustable pin is greater than or equal to the set duration, adjusting the network of the adjustable pin is stopped.

[0119] Specifically, when the network of the first adjustable pin is adjusted, the timing starts, and the time counted is the actual time. When the actual time is greater than or equal to the set time, the network of the adjustable pin is stopped. This setting can avoid entering an infinite loop. The set time can be 20 seconds.

[0120] Figure 8 is a schematic diagram of a structure of a device for automatically adjusting a chip pin network according to an embodiment of the present invention, with reference to Figure 8The device for automatically adjusting the chip pin network provided in this embodiment includes a first determination module 310, a first establishment module 320, a second establishment module 330, a second determination module 340 and an adjustment module 350; the first determination module 310 is used to determine a first target point in the FPGA chip based on the setting software; wherein the FPGA chip includes a plurality of adjustable pins; the first establishment module 320 is used to establish a first coordinate system with the current first target point as the origin; the second establishment module 330 is used to determine a second target point in the circuit board based on the setting software, and establish a second coordinate system with the second target point; wherein the circuit board includes at least one FPGA chip, a plurality of A soldering pad and a plurality of flying leads; the first end of each flying lead is connected to the corresponding adjustable pin, and the second end of each flying lead is connected to the corresponding soldering pad; a second determining module 340 is used to determine the position of the second end of each flying lead in the first coordinate system according to the position of the second end of each flying lead in the second coordinate system and the position of the current first target point in the second coordinate system; an adjusting module 350 is used to adjust the network of at least part of the adjustable pins in the FPGA chip in the first coordinate system when the number of adjustable pins in each quadrant matches the number of second ends of the flying leads in the same quadrant, so that the first ends of a set number of flying leads and the second ends of the flying leads are both located in the same quadrant of the first coordinate system.

[0121] The device for automatically adjusting the chip pin network provided in this embodiment has corresponding beneficial effects as the method for automatically adjusting the chip pin network provided in any embodiment of the present invention. For technical details not elaborated in this embodiment, please refer to the method for automatically adjusting the chip pin network provided in any embodiment of the present invention.

[0122] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0123] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for automatically adjusting a chip pin network, characterized in that: include: Determining a first target point in the FPGA chip based on the setting software; wherein the FPGA chip includes a plurality of adjustable pins; Establish a first coordinate system with the current first target point as the origin; Based on the setting software, a second target point in the circuit board is determined, and a second coordinate system is established with the second target point; wherein the circuit board includes at least one FPGA chip, a plurality of pads, and a plurality of flying wires; a first end of each flying wire is connected to a corresponding adjustable pin, and a second end of each flying wire is connected to a corresponding pad; Determine the position of the second end of each flying line in the first coordinate system according to the position of the second end of each flying line in the second coordinate system and the current position of the first target point in the second coordinate system; In the first coordinate system, when the number of the adjustable pins in each quadrant matches the number of the second ends of the flying wires in the same quadrant, the network of at least part of the adjustable pins in the FPGA chip is adjusted so that the first ends of the set number of flying wires and the second ends of the flying wires are located in the same quadrant of the first coordinate system.

2. The method for automatically adjusting chip pin network according to claim 1, characterized in that: The determining the first target point in the FPGA chip based on the setting software includes: The center of the FPGA chip is obtained through a setting function in the setting software, and the center of the FPGA chip is determined as the first target point.

3. The method for automatically adjusting chip pin network according to claim 1, characterized in that: The method of determining the position of the second end of each flying line in the first coordinate system according to the position of the second end of each flying line in the second coordinate system and the position of the current first target point in the second coordinate system comprises: Determine a first coordinate and each second coordinate, wherein the first coordinate is the coordinate of the current first target point in the second coordinate system, and each second coordinate is the coordinate of the second end of each flying line in the second coordinate system; The position of the second end of each flying line in the first coordinate system is determined according to the difference between the horizontal coordinate in each second coordinate and the horizontal coordinate in the first coordinate, and the difference between the vertical coordinate in each second coordinate and the vertical coordinate in the first coordinate.

4. The method for automatically adjusting chip pin network according to claim 1, characterized in that: Before adjusting the network of at least part of the adjustable pins in the FPGA chip, the method includes: Determine the number of adjustable pins in each quadrant in the first coordinate system and determine the number of second ends of the flying wires in each quadrant according to the positions of the second ends of the flying wires in the first coordinate system; Determining whether the number of adjustable pins in each quadrant of the first coordinate system is greater than or equal to the number of second ends of the flying leads in the same quadrant; If so, determining that the number of adjustable pins in each quadrant matches the number of second ends of the flying leads in the same quadrant; If not, the position of the first target point is adjusted in the FPGA chip, and then the process returns to the step of establishing the first coordinate system with the current first target point as the origin.

5. The method for automatically adjusting chip pin network according to claim 4, characterized in that: When, after adjusting the position of the first target point multiple times, there is a mismatch between the number of adjustable pins in at least one quadrant of the first coordinate system and the number of second ends of the flying wires in the same quadrant, the network of the adjustable pins is adjusted so that the sum of the numbers of adjustable pins in two adjacent quadrants in the first coordinate system is greater than or equal to the sum of the numbers of the second ends of the flying wires in the two adjacent quadrants.

6. The method for automatically adjusting chip pin network according to claim 1, characterized in that: The plurality of flying leads include a plurality of differential flying leads and a plurality of single-line flying leads; The step of adjusting the network of at least part of the adjustable pins in the FPGA chip so that the first ends of a set number of the flying wires and the second ends of the flying wires are both located in the same quadrant of the first coordinate system includes: Adjusting the network of adjustable pins connected to each differential flying lead to the same quadrant of the first coordinate system as the second end of the differential flying lead; Remove the adjustable pins connected to each differential flying lead from the FPGA chip; The network of adjustable pins connected to the single-wire flying lead is adjusted so that the first end and the second end of at least part of the single-wire flying lead are located in the same quadrant of the first coordinate system.

7. The method for automatically adjusting chip pin network according to claim 6, characterized in that: After the network of adjustable pins connected to each differential flying lead is adjusted to the same quadrant of the first coordinate system where the second end of the differential flying lead is located, the method further includes: In each quadrant of the first coordinate system, determining whether there are any crossed differential flying wires; If so, the networks of the adjustable pins connected to the differential flying leads that cross each other are exchanged in the same quadrant.

8. The method for automatically adjusting chip pin network according to claim 1, characterized in that: After adjusting the network of at least part of the adjustable pins in the FPGA chip so that the first ends of the set number of flying wires and the second ends of the flying wires are all located in the same quadrant of the first coordinate system, the method further includes: Determine whether there are intersecting flying lines in each quadrant of the first coordinate system; If so, the networks of the adjustable pins to which the first ends of the mutually crossing flying leads are connected are exchanged in the same quadrant.

9. The method for automatically adjusting a chip pin network according to any one of claims 1 to 8, characterized in that: When the actual time length of adjusting the network of the adjustable pin is greater than or equal to the set time length, the adjustment of the network of the adjustable pin is stopped.

10. A device for automatically adjusting a chip pin network, characterized in that: include: a first determining module, a first establishing module, a second establishing module, a second determining module, and an adjusting module; The first determination module is used to determine a first target point in the FPGA chip based on the setting software; wherein the FPGA chip includes a plurality of adjustable pins; The first establishing module is used to establish a first coordinate system with the current first target point as the origin; The second establishment module is used to determine a second target point in the circuit board based on the setting software, and establish a second coordinate system with the second target point; wherein the circuit board includes at least one FPGA chip, a plurality of pads and a plurality of flying wires; the first end of each flying wire is connected to the corresponding adjustable pin, and the second end of each flying wire is connected to the corresponding pad; The second determination module is used to determine the position of the second end of each flying line in the first coordinate system according to the position of the second end of each flying line in the second coordinate system and the current position of the first target point in the second coordinate system; The adjustment module is used to adjust the network of at least part of the adjustable pins in the FPGA chip in the first coordinate system when the number of the adjustable pins in each quadrant matches the number of the second ends of the flying wires in the same quadrant, so that the first ends of a set number of the flying wires and the second ends of the flying wires are both located in the same quadrant of the first coordinate system.

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