Three-dimensional network-on-chip mapping method and device based on monolithic three-dimensional integration

Abstract

The invention discloses a mapping method and device for a three-dimensional network-on-chip based on monolithic three-dimensional integration, and the method comprises the steps: carrying out the two-dimensional mapping of a current calculation task, and simulating the resource access times of each node in the calculation process of a current network; determining a plurality of access thresholds, determining a three-dimensional node and a two-dimensional node corresponding to each access threshold according to the resource access frequency of each node and the plurality of access thresholds, and simulating to obtain the performance of the current network based on the three-dimensional node and the two-dimensional node corresponding to each access threshold. Obtaining an optimal three-dimensional data packet bandwidth corresponding to each access threshold according to a simulation result; and determining a longest data path based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, and adding a three-dimensional data cache between two nodes corresponding to the longest data path. Therefore, the problems of high cost, poor heat dissipation, low data transmission efficiency and the like in related technologies are solved, and more acceleration calculation methods are provided for three-dimensional data stream design.

Description

Technical Field

[0001] The present application relates to the field of microelectronics technology, and in particular to a mapping method and device for a three-dimensional network-on-chip based on single-chip three-dimensional integration. Background Art

[0002] As the complexity of computing tasks increases, data communication in multi-core processors becomes one of the key factors affecting system performance.

[0003] In related technologies, in order to meet the needs of high-performance computing, the Network on Chip (NoC) connects multiple processing units through routers, effectively improving the data transmission efficiency; the current implementation of three-dimensional NoC is mainly formed by bonding chips containing two or more two-dimensional NoC structures.

[0004] However, the deep through silicon vias used in bonding can cause stress problems in silicon wafers and are costly. The three-dimensional NoC formed by bonding is still based on the traditional NoC framework, but only adds a communication transmission direction in the vertical direction. The three-dimensional communication is still mainly communication between nodes. In addition, the heat dissipation problem of this structure is also very serious and needs to be solved urgently. Summary of the invention

[0005] The present application provides a mapping method and device for a three-dimensional on-chip network based on a single-chip three-dimensional integration to solve the problems of high cost, poor heat dissipation and low data transmission efficiency in related technologies, and to provide more accelerated computing methods for three-dimensional data flow design.

[0006] The first aspect of the present application provides a mapping method for a three-dimensional network-on-chip based on a single-chip three-dimensional integration, comprising the following steps:

[0007] Map the current computing task in two dimensions and simulate the number of resource accesses of each node in the current network during the computing process;

[0008] Determine multiple access thresholds, and determine the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold according to the resource access times of each node and the multiple access thresholds, and simulate the performance of the current network based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, and obtain the optimal three-dimensional data packet bandwidth corresponding to each access threshold according to the simulation results;

[0009] Based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, a longest data path is determined, and a three-dimensional data cache is added between two nodes corresponding to the longest data path.

[0010] Optionally, determining the three-dimensional node and the two-dimensional node corresponding to each access threshold according to the resource access times of each node and multiple access thresholds includes:

[0011] For each access threshold, based on the number of resource accesses of each node, the nodes whose resource access times are greater than the preset access threshold are set as the three-dimensional nodes, and the remaining nodes are set as the two-dimensional nodes, so as to obtain the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold.

[0012] Optionally, simulating the performance of the current network based on the three-dimensional nodes and the two-dimensional nodes corresponding to each access threshold, and obtaining the optimal three-dimensional data packet bandwidth corresponding to each access threshold according to the simulation result, includes:

[0013] Determine an initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold;

[0014] Based on the initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold, the three-dimensional node and the two-dimensional node corresponding to each access threshold, simulation is performed to obtain a first performance result of the current network corresponding to each access threshold;

[0015] Based on a preset adjustment strategy, the initial three-dimensional data packet bandwidth corresponding to each access threshold is adjusted multiple times, and simulation is performed based on the three-dimensional data packet bandwidth after the multiple adjustments, the three-dimensional node and the two-dimensional node to obtain multiple performance results of the current network corresponding to each access threshold;

[0016] According to the first performance result of the current network corresponding to each access threshold and the multiple performance results of the current network corresponding to each access threshold, the three-dimensional data packet bandwidth corresponding to the optimal performance result is determined as the optimal three-dimensional data packet bandwidth corresponding to each access threshold.

[0017] Optionally, determining a plurality of access thresholds includes:

[0018] Get the current actual demand;

[0019] The multiple access thresholds are determined based on the current actual demand.

[0020] A second aspect of the present application provides a mapping device based on a three-dimensional network-on-chip with single-chip three-dimensional integration, including:

[0021] The simulation module is used to perform two-dimensional mapping of the current computing task and simulate the number of resource accesses of each node in the current network during the computing process;

[0022] A selection module is used to determine multiple access thresholds, and determine the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold according to the resource access times of each node and the multiple access thresholds, and simulate the performance of the current network based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, and obtain the optimal three-dimensional data packet bandwidth corresponding to each access threshold according to the simulation results;

[0023] The determination module is used to determine the longest data path based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, and add a three-dimensional data cache between two nodes corresponding to the longest data path.

[0024] Optionally, the selection module is specifically used to:

[0025] For each access threshold, based on the number of resource accesses of each node, the nodes whose resource access times are greater than the preset access threshold are set as the three-dimensional nodes, and the remaining nodes are set as the two-dimensional nodes, so as to obtain the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold.

[0026] Optionally, the selection module is specifically used to:

[0027] Determine an initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold;

[0028] Based on the initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold, the three-dimensional node and the two-dimensional node corresponding to each access threshold, simulation is performed to obtain a first performance result of the current network corresponding to each access threshold;

[0029] Based on a preset adjustment strategy, the initial three-dimensional data packet bandwidth corresponding to each access threshold is adjusted multiple times, and simulation is performed based on the three-dimensional data packet bandwidth after the multiple adjustments, the three-dimensional node and the two-dimensional node to obtain multiple performance results of the current network corresponding to each access threshold;

[0030] According to the first performance result of the current network corresponding to each access threshold and the multiple performance results of the current network corresponding to each access threshold, the three-dimensional data packet bandwidth corresponding to the optimal performance result is determined as the optimal three-dimensional data packet bandwidth corresponding to each access threshold.

[0031] Optionally, the selection module is specifically used to:

[0032] Get the current actual demand;

[0033] The multiple access thresholds are determined based on the current actual demand.

[0034] A third aspect of the present application provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute a mapping method for a three-dimensional network-on-chip based on monolithic three-dimensional integration as described in the above embodiment.

[0035] The fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, which is executed by a processor to implement a mapping method for a three-dimensional network-on-chip based on monolithic three-dimensional integration as described in the above embodiment.

[0036] Therefore, the current computing task is mapped in two dimensions, and the number of resource accesses of each node in the current network during the computing process is simulated; multiple access thresholds are determined, and the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold are determined according to the number of resource accesses of each node and the multiple access thresholds. Based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, the performance of the current network is simulated, and the optimal three-dimensional data packet bandwidth corresponding to each access threshold is obtained according to the simulation results; based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, the longest data path is determined, and a three-dimensional data cache is added between the two nodes corresponding to the longest data path, which solves the problems of high cost, poor heat dissipation and low data transmission efficiency in related technologies, and provides more accelerated computing methods for three-dimensional data flow design.

[0037] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0039] Figure 1 A schematic diagram of a bus-based multi-core system in the related art;

[0040] Figure 2 A schematic diagram of a typical on-chip network;

[0041] Figure 3 A schematic diagram of a three-dimensional NoC topology in the related art;

[0042] Figure 4 A schematic diagram of a typical two-dimensional NoC node;

[0043] Figure 5 A schematic diagram of a three-dimensional NoC node of a mapping method for a three-dimensional network on chip based on monolithic three-dimensional integration provided according to an embodiment of the present application;

[0044] Figure 6 A flowchart of a mapping method for a three-dimensional network-on-chip based on monolithic three-dimensional integration provided in an embodiment of the present application;

[0045] Figure 7 A flowchart of mapping of a three-dimensional NoC according to a mapping method of a three-dimensional network on chip based on monolithic three-dimensional integration provided in accordance with an embodiment of the present application;

[0046] Figure 8 A block diagram of a mapping device for a three-dimensional network-on-chip based on a single-chip three-dimensional integration provided according to an embodiment of the present application;

[0047] Fig. 9 It is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0048] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0049] The following describes a mapping method and device for a three-dimensional network-on-chip based on a single-chip three-dimensional integration according to an embodiment of the present application with reference to the accompanying drawings.

[0050] Before introducing the mapping method of the three-dimensional network on chip based on the single-chip three-dimensional integration of the embodiment of the present application, Figures 1 to 5 The following briefly introduces bus-based multi-core systems, typical on-chip networks, typical three-dimensional NoC topologies, two-dimensional NoC nodes, and a three-dimensional NoC node provided in an embodiment of the present application in the related art.

[0051] like Figure 1 and Figure 2 As shown, Figure 1 is a schematic diagram of a bus-based multi-core system in the related art, Figure 2 A schematic diagram of a typical on-chip network.

[0052] Specifically, in the traditional bus interconnection structure, multiple cores compete for the same bus resource, which will cause serious performance loss; in the classic NoC architecture, each core is a computing resource, called an IP, and each IP will communicate with a router responsible for controlling data transmission. Data communication between IPs is no longer a competition for the same bus resource, but is achieved through continuous forwarding by adjacent routers. Such a structure greatly improves the efficiency of data transmission; IP and router are collectively called a node.

[0053] like Figure 3 As shown, Figure 3 A schematic diagram of a three-dimensional NoC topology in related art.

[0054] Specifically, the number of IPs is increased in the vertical direction. However, the implementation of this solution is more difficult. The embodiment of the present application focuses on a low-cost three-dimensional NoC implementation method (slightly different from the three-dimensional NoC structure mentioned in, the three-dimensional NoC structure proposed in the embodiment of the present application does not directly stack IPs, but three-dimensionally stacks the circuit units inside the node to improve internal communication efficiency).

[0055] Further, such as Figure 4 and Figure 5 As shown, Figure 4 is a schematic diagram of a typical two-dimensional NoC node in the related art. Figure 5 A schematic diagram of a three-dimensional NoC node provided according to an embodiment of the present application.

[0056] The embodiment of the present application is different from the traditional three-dimensional NoC in that the three-dimensional method of NoC no longer uses nodes as the smallest unit. Figure 4 The modules with bold outlines in the middle can be placed in the back-end (i.e., the structure above the silicon circuit) through the monolithic three-dimensional integration process. According to the needs of computing tasks or chip design, some or all of these modules can be prepared in the back-end of the chip; Figure 5 The three-dimensional nodes shown replace the original two-dimensional nodes to form a three-dimensional NoC network that is different from the traditional solution.

[0057] Based on the above problems, this application proposes a mapping method for a three-dimensional network on chip based on a single-chip three-dimensional integration. In this method, the current computing task is mapped in two dimensions, and the number of resource accesses of each node in the current network during the computing process is simulated; multiple access thresholds are determined, and the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold are determined according to the number of resource accesses of each node and the multiple access thresholds. Based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, the performance of the current network is simulated, and the optimal three-dimensional data packet bandwidth corresponding to each access threshold is obtained according to the simulation results; based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, the longest data path is determined, and a three-dimensional data cache is added between the two nodes corresponding to the longest data path. In this way, the problems of high cost, poor heat dissipation and low data transmission efficiency in the related technology are solved, and more accelerated computing methods are provided for the design of three-dimensional data flows.

[0058] Specifically, Figure 6 A flowchart of a mapping method for a three-dimensional network-on-chip based on monolithic three-dimensional integration provided in an embodiment of the present application.

[0059] like Figure 6 As shown, the mapping method of the three-dimensional network on chip based on the single-chip three-dimensional integration includes the following steps:

[0060] In step S601, the current computing task is two-dimensionally mapped, and the number of resource accesses of each node in the current network during the computing process is simulated.

[0061] The resource access times refer to the frequency with which each node (or processing unit) accesses shared resources (such as memory, cache, etc.) during the execution of computing tasks, which is determined by simulating the activities of the current network during the computing process.

[0062] Specifically, the embodiments of the present application can first map the logical structure of the computing task or application to a two-dimensional on-chip network architecture. This mapping is to distribute the computing task to each node in the NoC (each node usually contains one or more computing resources, such as a processor core, and a router responsible for data transmission); the two-dimensional mapping considers the two-dimensional interconnection relationship between nodes and ignores the connection in the vertical direction. This mapping provides a preliminary network architecture for subsequent analysis and optimization; after completing the two-dimensional mapping, the execution process of the computing task on the NoC is simulated using simulation tools or algorithms; in this process, the number of times each node accesses other nodes (or resources) during the calculation process is recorded. The number of resource accesses is an important indicator for evaluating communication activities between nodes. In NoC, frequent communication between nodes will lead to higher network load and potential performance bottlenecks.

[0063] It can be understood that by understanding the number of resource accesses of each node, those nodes with higher communication needs can be identified. These nodes are more likely to become three-dimensional nodes in the three-dimensional NoC, improving the internal communication efficiency through monolithic three-dimensional integration technology; the simulation results can also provide data support for the optimization of packet bandwidth, the adjustment of network structure and the deployment of data cache.

[0064] In step S602, multiple access thresholds are determined, and the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold are determined according to the number of resource accesses of each node and the multiple access thresholds. Based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, the performance of the current network is simulated, and the optimal three-dimensional data packet bandwidth corresponding to each access threshold is obtained according to the simulation results.

[0065] Among them, the access threshold refers to a series of standards set when determining which nodes should be converted from two-dimensional (2D) to three-dimensional (3D). These thresholds are used to distinguish nodes with high resource access frequency from nodes with low resource access frequency, thereby guiding the optimization of the network structure; the access threshold can be a threshold set in advance by the user, a threshold obtained through a limited number of experiments, or a threshold obtained through a limited number of computer simulations, and is not specifically limited here; a three-dimensional node refers to a node whose resource access times are higher than the access threshold during the execution of a computing task. These nodes communicate with nodes in other layers in the vertical direction through monolithic three-dimensional integration technology; a two-dimensional node refers to a node whose resource access times are lower than or equal to the access threshold during the execution of a computing task. These nodes maintain communication on the original two-dimensional plane; the optimal three-dimensional data packet bandwidth refers to the data transmission rate that can maximize network performance, which is found through simulation and optimization processes after determining which nodes will be converted to three-dimensional nodes.

[0066] Specifically, obtaining the actual needs of the current computing task may involve the complexity of the computing task, the frequency of resource access, etc.; based on the actual needs, multiple resource access thresholds are set, and these thresholds will be used to distinguish which nodes should be configured as three-dimensional nodes and which nodes can continue to be two-dimensional nodes; for each access threshold, the nodes whose resource access times are greater than the threshold are set as three-dimensional nodes, and the remaining nodes are used as two-dimensional nodes; in this way, a set of corresponding three-dimensional nodes and two-dimensional nodes can be generated for each access threshold; an initial three-dimensional data packet bandwidth is set for each three-dimensional node corresponding to the access threshold; network simulation is performed using these three-dimensional nodes and two-dimensional nodes, as well as the set initial bandwidth, to obtain the first performance result of the current network; according to the preset adjustment strategy, the initial bandwidth is adjusted multiple times, and network simulation is performed after each adjustment to obtain multiple performance results; compare the multiple performance results corresponding to each access threshold, find the result with the best performance (such as lowest latency, lowest power consumption, etc.), and determine that the three-dimensional data packet bandwidth corresponding to the result is the optimal bandwidth.

[0067] It can be understood that through this step, three-dimensional nodes and two-dimensional nodes can be flexibly configured according to the actual needs of the current computing task and the number of resource accesses of the node, and the optimal three-dimensional data packet bandwidth can be determined through simulation, thereby optimizing the performance of the network; this method not only improves the efficiency of data transmission, but also reduces costs, providing strong support for the realization of high-performance three-dimensional on-chip networks.

[0068] Optionally, in some embodiments, three-dimensional nodes and two-dimensional nodes corresponding to each access threshold are determined based on the number of resource accesses of each node and multiple access thresholds, including: for each access threshold, based on the number of resource accesses of each node, nodes whose resource accesses are greater than a preset access threshold are set as three-dimensional nodes, and the remaining nodes are set as two-dimensional nodes, so as to obtain three-dimensional nodes and two-dimensional nodes corresponding to each access threshold.

[0069] It can be understood that according to the comparison between the number of resource accesses of each node and the preset multiple access thresholds, the nodes with access times higher than the threshold are set as three-dimensional nodes to optimize data transmission efficiency and performance; this strategy can accurately identify the key nodes with frequent data access in the network, and effectively alleviate the data congestion problem of these nodes through the setting of three-dimensional nodes; at the same time, the remaining nodes are used as two-dimensional nodes, maintaining the original network structure, thereby ensuring performance optimization while controlling costs and complexity. The implementation of this step not only improves the efficiency and bandwidth of data transmission, but also enhances the flexibility and scalability of the network, laying a solid foundation for the performance of three-dimensional on-chip networks in practical applications.

[0070] Optionally, in some embodiments, based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, the performance of the current network is simulated, and the optimal three-dimensional data packet bandwidth corresponding to each access threshold is obtained according to the simulation results, including: determining the initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold; simulating to obtain a first performance result of the current network corresponding to each access threshold based on the initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold, the three-dimensional nodes and the two-dimensional nodes corresponding to each access threshold; based on a preset adjustment strategy, adjusting the initial three-dimensional data packet bandwidth corresponding to each access threshold multiple times, and simulating to obtain multiple performance results of the current network corresponding to each access threshold based on the three-dimensional data packet bandwidth, three-dimensional nodes and two-dimensional nodes after multiple adjustments; determining the three-dimensional data packet bandwidth corresponding to the optimal performance result as the optimal three-dimensional data packet bandwidth corresponding to each access threshold according to the first performance result of the current network corresponding to each access threshold and the multiple performance results of the current network corresponding to each access threshold.

[0071] It is understandable that by determining the optimal three-dimensional data packet bandwidth, the performance of the network can be significantly improved, such as reducing latency and power consumption; the optimized bandwidth setting can more effectively utilize network resources, improve data transmission efficiency and overall system performance; reasonable bandwidth configuration helps reduce network congestion and data loss, thereby enhancing system stability and reliability.

[0072] Optionally, in some embodiments, determining multiple access thresholds includes: obtaining current actual demand; and determining multiple access thresholds based on the current actual demand.

[0073] It is understandable that it is necessary to fully understand and analyze the actual needs of the current computing tasks or application scenarios, including but not limited to the scale, complexity, data access mode, etc. of the computing tasks; then, set multiple different access thresholds based on these needs, in order to find the optimal node configuration and data packet bandwidth settings through simulation and performance evaluation, so as to meet the current actual needs and maximize network performance. This step plays a vital role in the entire process of determining the optimal three-dimensional data packet bandwidth, and directly determines the starting point and direction of node configuration and data packet bandwidth adjustment in subsequent steps. By reasonably setting the access threshold, the network performance under different configurations can be simulated and evaluated more accurately to find the optimal solution.

[0074] In step S603, based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, the longest data path is determined, and a three-dimensional data cache is added between two nodes corresponding to the longest data path.

[0075] Among them, the longest data path refers to the longest path from one node to another in the current network topology. This path usually refers to the path with the largest number of hops (that is, the largest number of routers or nodes passed through) or the maximum transmission delay; three-dimensional data cache refers to a high-speed storage unit added between key nodes of the longest data path in a three-dimensional network on chip (3D NoC) to reduce data transmission delays and improve system performance.

[0076] Specifically, based on each known access threshold and the corresponding optimal three-dimensional data packet bandwidth, the longest path through which the data packet is transmitted in the network is determined by simulating or analyzing the network structure. This path usually represents a potential bottleneck in the network because it involves the most nodes and possible delays. After identifying the longest data path, it is necessary to add a three-dimensional data cache between the two nodes corresponding to the path, which can achieve fast forwarding of data packets and reduce network delays.

[0077] It should be noted that by adding a three-dimensional data cache, the waiting time between nodes can be reduced, allowing data packets to pass through the network more quickly; since the three-dimensional data cache provides temporary storage space, data packets can be stored in the cache while waiting for the next transmission cycle, thereby reducing the overall transmission delay; adding a three-dimensional data cache for the longest data path can significantly improve the performance bottleneck of the network and improve the operating efficiency and stability of the entire network.

[0078] Therefore, the current computing task is mapped in two dimensions, and the number of resource accesses of each node in the current network during the computing process is simulated; multiple access thresholds are determined, and the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold are determined according to the number of resource accesses of each node and the multiple access thresholds. Based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, the performance of the current network is simulated, and the optimal three-dimensional data packet bandwidth corresponding to each access threshold is obtained according to the simulation results; based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, the longest data path is determined, and a three-dimensional data cache is added between the two nodes corresponding to the longest data path, which solves the problems of high cost, poor heat dissipation and low data transmission efficiency in related technologies, and provides more accelerated computing methods for three-dimensional data flow design.

[0079] To facilitate those skilled in the art to further understand the mapping method of the three-dimensional network-on-chip based on monolithic three-dimensional integration according to the embodiment of the present application, a detailed description is given below in conjunction with a specific embodiment of the present application.

[0080] Specifically, Figure 7 As shown, the mapping method of the three-dimensional network on chip based on single-chip three-dimensional integration has the following steps:

[0081] Step 1: Map the target network to a two-dimensional NoC, simulate the number of accesses to each resource during the calculation process, and set a threshold S based on the number and actual needs. If the number of accesses is higher than the threshold, the node needs to use a three-dimensional structure. If the number of accesses is lower than the threshold, the two-dimensional node continues to be used.

[0082] Step 2: According to the above results, set the nodes with access times higher than S as three-dimensional nodes, design the data packet bandwidth as W according to the requirements, and simulate the performance of the network such as delay and power consumption.

[0083] Step 3: Change the packet bandwidth W, simulate the performance results, and select the optimal W within the set range.

[0084] Step 4: Change the threshold S and repeat steps 1 to 3 any number of times to obtain the optimal structure.

[0085] Step 5: Based on the final result, find the longest data path in the overall network (the data packet passing through the largest number of nodes), add a three-dimensional data cache between the two nodes, realize direct connection, and complete the mapping.

[0086] According to the mapping method of the three-dimensional network on chip based on monolithic three-dimensional integration proposed in the embodiment of the present application, the current computing task is mapped in two dimensions, and the resource access times of each node in the current network during the computing process are simulated; multiple access thresholds are determined, and the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold are determined according to the resource access times of each node and the multiple access thresholds, and the performance of the current network is simulated based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, and the optimal three-dimensional data packet bandwidth corresponding to each access threshold is obtained according to the simulation results; based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, the longest data path is determined, and a three-dimensional data cache is added between the two nodes corresponding to the longest data path. In this way, the problems of high cost, poor heat dissipation and low data transmission efficiency in the related technology are solved, and more accelerated computing methods are provided for the design of three-dimensional data flow.

[0087] Next, a mapping device for a three-dimensional network-on-chip based on monolithic three-dimensional integration proposed in an embodiment of the present application will be described with reference to the accompanying drawings.

[0088] Figure 8 It is a block diagram of a mapping device of a three-dimensional network-on-chip based on a single-chip three-dimensional integration according to an embodiment of the present application.

[0089] like Figure 8 As shown, the mapping device 10 based on a three-dimensional network on a chip with single-chip three-dimensional integration includes: a simulation module 100 , a selection module 200 and a determination module 300 .

[0090] The simulation module 100 is used to perform two-dimensional mapping of the current computing task and simulate the resource access times of each node in the current network during the computing process;

[0091] The selection module 200 is used to determine multiple access thresholds, and determine the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold according to the resource access times of each node and the multiple access thresholds, and simulate the performance of the current network based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, and obtain the optimal three-dimensional data packet bandwidth corresponding to each access threshold according to the simulation results;

[0092] The determination module 300 is used to determine the longest data path based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, and add a three-dimensional data cache between two nodes corresponding to the longest data path.

[0093] Optionally, the selection module 200 is specifically used to: for each access threshold, based on the number of resource accesses of each node, set the nodes whose resource access times are greater than the preset access threshold as three-dimensional nodes, and the remaining nodes as two-dimensional nodes, so as to obtain three-dimensional nodes and two-dimensional nodes corresponding to each access threshold.

[0094] Optionally, the selection module 200 is specifically used to: determine the initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold; simulate based on the initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold, the three-dimensional node and the two-dimensional node corresponding to each access threshold to obtain the first performance result of the current network corresponding to each access threshold; based on a preset adjustment strategy, adjust the initial three-dimensional data packet bandwidth corresponding to each access threshold for multiple times, and simulate based on the three-dimensional data packet bandwidth, three-dimensional node and two-dimensional node after multiple adjustments to obtain multiple performance results of the current network corresponding to each access threshold; determine the three-dimensional data packet bandwidth corresponding to the optimal performance result as the optimal three-dimensional data packet bandwidth corresponding to each access threshold according to the first performance result of the current network corresponding to each access threshold and the multiple performance results of the current network corresponding to each access threshold.

[0095] Optionally, the selection module 200 is specifically used to: obtain current actual demand; and determine multiple access thresholds based on the current actual demand.

[0096] It should be noted that the above explanation of the mapping method embodiment of the 3D network-on-chip based on monolithic 3D integration is also applicable to the mapping device of the 3D network-on-chip based on monolithic 3D integration of this embodiment, which will not be repeated here.

[0097] According to the mapping device of the three-dimensional network on chip based on the three-dimensional integration of a single chip proposed in the embodiment of the present application, the current computing task is mapped in two dimensions, and the resource access times of each node in the current network during the computing process are simulated; multiple access thresholds are determined, and the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold are determined according to the resource access times of each node and the multiple access thresholds, and the performance of the current network is simulated based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, and the optimal three-dimensional data packet bandwidth corresponding to each access threshold is obtained according to the simulation results; based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, the longest data path is determined, and a three-dimensional data cache is added between the two nodes corresponding to the longest data path. In this way, the problems of high cost, poor heat dissipation and low data transmission efficiency in the related technology are solved, and more accelerated computing methods are provided for the design of three-dimensional data flow.

[0098] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0099] A memory 901 , a processor 902 , and a computer program stored in the memory 901 and executable on the processor 902 .

[0100] When the processor 902 executes the program, the mapping method of the three-dimensional network on chip based on monolithic three-dimensional integration provided in the above embodiment is implemented.

[0101] Furthermore, the electronic device further comprises:

[0102] The communication interface 903 is used for communication between the memory 901 and the processor 902 .

[0103] The memory 901 is used to store computer programs that can be executed on the processor 902 .

[0104] The memory 901 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0105] If the memory 901, the processor 902 and the communication interface 903 are implemented independently, the communication interface 903, the memory 901 and the processor 902 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 9 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0106] Optionally, in a specific implementation, if the memory 901, the processor 902 and the communication interface 903 are integrated on a chip, the memory 901, the processor 902 and the communication interface 903 can communicate with each other through an internal interface.

[0107] The processor 902 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0108] An embodiment of the present application also provides a computer-readable storage medium having a computer program stored thereon, characterized in that when the program is executed by a processor, the mapping method of a three-dimensional network on a chip based on monolithic three-dimensional integration is implemented as described above.

[0109] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0110] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0111] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0112] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0113] A person skilled in the art may understand that all or part of the steps in the above-mentioned embodiment method may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

Claims

1. A mapping method for a three-dimensional network-on-chip based on a single-chip three-dimensional integration, characterized in that: The following steps are involved: Map the current computing task in two dimensions and simulate the number of resource accesses of each node in the current network during the computing process; Determine multiple access thresholds, and determine the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold according to the resource access times of each node and the multiple access thresholds, and simulate the performance of the current network based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, and obtain the optimal three-dimensional data packet bandwidth corresponding to each access threshold according to the simulation results; Based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, a longest data path is determined, and a three-dimensional data cache is added between two nodes corresponding to the longest data path.

2. The method according to claim 1, characterized in that The determining of the three-dimensional node and the two-dimensional node corresponding to each access threshold according to the resource access times of each node and the multiple access thresholds includes: For each access threshold, based on the number of resource accesses of each node, the nodes whose resource access times are greater than the preset access threshold are set as the three-dimensional nodes, and the remaining nodes are set as the two-dimensional nodes, so as to obtain the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold.

3. The method according to claim 1, characterized in that The simulating the performance of the current network based on the three-dimensional nodes and the two-dimensional nodes corresponding to each access threshold, and obtaining the optimal three-dimensional data packet bandwidth corresponding to each access threshold according to the simulation result, includes: Determine an initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold; Based on the initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold, the three-dimensional node and the two-dimensional node corresponding to each access threshold, simulation is performed to obtain a first performance result of the current network corresponding to each access threshold; Based on a preset adjustment strategy, the initial three-dimensional data packet bandwidth corresponding to each access threshold is adjusted multiple times, and simulation is performed based on the three-dimensional data packet bandwidth after the multiple adjustments, the three-dimensional node and the two-dimensional node to obtain multiple performance results of the current network corresponding to each access threshold; According to the first performance result of the current network corresponding to each access threshold and the multiple performance results of the current network corresponding to each access threshold, the three-dimensional data packet bandwidth corresponding to the optimal performance result is determined as the optimal three-dimensional data packet bandwidth corresponding to each access threshold.

4. The method according to claim 1, characterized in that: The determining of multiple access thresholds includes: Get the current actual demand; The multiple access thresholds are determined based on the current actual demand.

5. A mapping device for a three-dimensional network-on-chip based on a single-chip three-dimensional integration, characterized in that: The following steps are involved: The simulation module is used to perform two-dimensional mapping of the current computing task and simulate the number of resource accesses of each node in the current network during the computing process; A selection module is used to determine multiple access thresholds, and determine the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold according to the resource access times of each node and the multiple access thresholds, and simulate the performance of the current network based on the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold, and obtain the optimal three-dimensional data packet bandwidth corresponding to each access threshold according to the simulation results; The determination module is used to determine the longest data path based on each access threshold and the optimal three-dimensional data packet bandwidth corresponding to each access threshold, and add a three-dimensional data cache between two nodes corresponding to the longest data path.

6. The mapping device of the three-dimensional network on chip based on single-chip three-dimensional integration according to claim 5, characterized in that: The selection module is specifically used for: For each access threshold, based on the number of resource accesses of each node, the nodes whose resource access times are greater than the preset access threshold are set as the three-dimensional nodes, and the remaining nodes are set as the two-dimensional nodes, so as to obtain the three-dimensional nodes and two-dimensional nodes corresponding to each access threshold.

7. The mapping device of the three-dimensional network-on-chip based on single-chip three-dimensional integration according to claim 5, characterized in that: The selection module is specifically used for: Determine an initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold; Based on the initial three-dimensional data packet bandwidth of the three-dimensional node corresponding to each access threshold, the three-dimensional node and the two-dimensional node corresponding to each access threshold, simulation is performed to obtain a first performance result of the current network corresponding to each access threshold; Based on a preset adjustment strategy, the initial three-dimensional data packet bandwidth corresponding to each access threshold is adjusted multiple times, and simulation is performed based on the three-dimensional data packet bandwidth after the multiple adjustments, the three-dimensional node and the two-dimensional node to obtain multiple performance results of the current network corresponding to each access threshold; According to the first performance result of the current network corresponding to each access threshold and the multiple performance results of the current network corresponding to each access threshold, the three-dimensional data packet bandwidth corresponding to the optimal performance result is determined as the optimal three-dimensional data packet bandwidth corresponding to each access threshold.

8. The mapping device of the three-dimensional network-on-chip based on single-chip three-dimensional integration according to claim 5, characterized in that: The selection module is specifically used for: Get the current actual demand; The multiple access thresholds are determined based on the current actual demand.

9. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a mapping method for a three-dimensional network-on-chip based on monolithic three-dimensional integration as described in any one of claims 1 to 4.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement a mapping method for a three-dimensional network-on-chip based on monolithic three-dimensional integration as claimed in any one of claims 1 to 4.

Images