Memory device error correction

Abstract

A memory device includes a first memory device configured to store a first error correction code of a first size during a first write operation; a second memory device configured to store a second error correction code of a second size greater than the first size during a second write operation; and a control logic circuit configured to control the first memory device and the second memory device. The control logic circuit includes an error correction circuit configured to generate one of a first error correction code and a second error correction code for writing data according to the puncturing option information.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0117625 filed in the Korean Intellectual Property Office on September 5, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to memory device error correction. Some aspects of the present disclosure relate to a memory device and a method of operating the same in which a differential error correction code (ECC) is applied to reduce redundancy. Background Art

[0004] Compute Express Link (CXL) is a high-performance interconnect protocol based on open standards that can provide fast data transfer between central processing units (CPUs), memories, and accelerators in data server system environments. CXL provides advantages such as high bandwidth, low latency, memory sharing capabilities, and compatibility with PCI Express (PCIe), and can enable efficient data exchange in high-performance computing tasks such as artificial intelligence (AI) and big data. Summary of the invention

[0005] According to some implementations, a memory device includes: a first memory device configured to store a first error correction code of a first size during a first write operation; a second memory device configured to store a second error correction code of a second size greater than the first size during a second write operation; and a control logic circuit configured to control the first memory device and the second memory device. The control logic circuit includes an error correction circuit configured to generate one of the first error correction code and the second error correction code for write data according to puncturing option information.

[0006] According to some implementations, a memory device includes: a first memory device; a second memory device; and a control logic circuit configured to control the first memory device and the second memory device. The control logic circuit includes an error correction circuit configured to generate a punctured error correction code for the first memory device or an original error correction code for the second memory device according to puncturing option information; and tracking logic configured to track an error rate of data read from the first memory device or the second memory device. The puncturing option information changes according to the error rate.

[0007] According to some implementations, a method of operating a memory device includes: receiving write data; setting an error correction code level according to punching option information; generating an error correction code for the write data according to the error correction code level; and storing the write data and the error correction code in a memory device corresponding to the error correction code level.

[0008] According to some implementations, a computing system includes a system bus, at least one heterogeneous memory device connected to the system bus, and at least one processor connected to the system bus. The at least one heterogeneous memory device changes a level of an error correction code according to puncturing option information.

[0009] According to some implementations, a method of operating a heterogeneous memory includes: reading data from a low-reliability memory device; performing an error correction operation on the read data; tracking a codeword error (CE) count based on the error correction operation; and when the value of the CE count is greater than or equal to a reference value, moving the data from the low-reliability memory device to a high-reliability memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages provided according to some implementations of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings.

[0011] Figure 1 is a diagram illustrating an example of a memory device according to some implementations.

[0012] Figure 2A and Figure 2B is a diagram conceptually illustrating an example of parity puncturing for ECC according to some implementations.

[0013] Figure 3A and Figure 3B is a diagram illustrating an example of optional ECC puncturing according to some implementations.

[0014] Figure 4 is a diagram illustrating an example of an error correction circuit according to some implementations.

[0015] Figure 5A and Figure 5B is a diagram showing an example of a configuration of optional ECC.

[0016] Figure 6 is a diagram illustrating a table of puncturing options / patterns according to error rate according to some implementations.

[0017] Figure 7 is a diagram illustrating an example of a memory device according to some implementations.

[0018] Figure 8 is a flow diagram illustrating example operation of a memory device according to some implementations.

[0019] Fig. 9 is a diagram illustrating example operations of a memory device according to some implementations.

[0020] Fig.10 is a diagram illustrating an example of a computing system according to some implementations.

[0021] Fig.11 is a diagram illustrating an example of a computing system according to some implementations.

[0022] Fig.12 is a diagram illustrating an example of a server system according to some implementations. DETAILED DESCRIPTION

[0023] Hereinafter, examples will be described with reference to the accompanying drawings.

[0024] Generally, when hybrid memory (e.g., a structure of volatile and non-volatile memory) is used in a compute fast link (CXL) environment, a high reliability error correction code (ECC) is used to compensate for the relatively low reliability of the non-volatile memory. Applying such high reliability ECC to volatile memory, which usually has a higher reliability, may be a waste of resources. For example, applying Reed-Solomon (RS) codes designed for NAND flash memory to dynamic random access memory (DRAM) will generate a lot of overhead.

[0025] In order to provide more efficient error correction, a memory device according to some implementations of the present disclosure can be implemented by applying an ECC that takes into account the reliability characteristics of different memories. By applying punctured ECC to heterogeneous memories (such as layered or hybrid memories) based on reliability, the memory device can reduce redundancy and provide improved system performance. Here, punctured ECC refers to the removal of the error correction code portion in a specific environment. For example, the original ECC (also referred to as the main ECC) has check bits for all bit positions, and the punctured ECC (also referred to as the slave ECC) removes some check bits. Some memory devices of the present disclosure apply the original ECC to non-volatile / slow access memory, and are equipped with multiple puncturing options, so that the punctured ECC can be applied to volatile / fast access memory depending on the quality of service (QoS) requirements. For example, the memory device of the present disclosure can apply customized ECC to multiple heterogeneous memories with one ECC block configuration.

[0026] Thus, memory devices and associated processes according to some implementations of the present disclosure may establish low computational cost ECC configurations for hybrid / tiered memory and provide multiple puncturing options depending on system requirements.

[0027] Figure 1 is a diagram illustrating a memory device 100 according to some implementations. Figure 1 , the memory device 100 includes a first memory device 110, a second memory device 120, and a control logic circuit 130. In some implementations, the memory device 100 may be a heterogeneous memory device. For example, the memory device 100 may be a compute express link (CXL) hybrid memory device.

[0028] The first memory device 110 may be a volatile / fast access memory device. For example, the first memory device 110 may be implemented as a DRAM. In some implementations, the first memory device 110 may apply a first ECC having a first size during a first write operation. For example, the first ECC may be a punctured ECC (e.g., from an ECC). In some implementations, the punctured ECC may be an optional ECC in which the length of the parity bits is reduced by code puncturing. In some implementations, the punctured ECC may be an ECC of a level selected from a plurality of levels corresponding to different ECCs. In some implementations, the first size may be variable according to an error rate.

[0029] In some implementations, the first ECC may be a 1-bit ECC (e.g., a Hamming code), which may provide relatively weak error correction capabilities, for example. For example, when the weight values ​​of a neural network layer learned in a machine learning system are stored / updated in a DRAM such as the first memory device 110, as long as the valid portion of the weight values ​​is accurate, there is little or no hindrance to the progress of learning. In this way, an ECC with a reduced first size may provide sufficient error correction performance. In some implementations, the first ECC is implemented with a most significant bit (MSB) protection code.

[0030] The second memory device 120 may be a non-volatile / slow access memory device. For example, the second memory device 120 may be implemented as a non-volatile memory (NVM) / storage class memory (SCM). In some implementations, the second memory device 120 may apply a second ECC having a second size greater than the first size during the second write operation. For example, the second ECC may be an original ECC (e.g., a main ECC). In some implementations, the second ECC may be implemented as a symbol ECC (e.g., a Reed-Solomon (RS) code, a low-density parity check (LDPC) code, etc.) having a relatively strong error correction capability. In some implementations, the second size may be a fixed value regardless of the error rate.

[0031] The control logic circuit 130 may be configured to control the first memory device 110 and the second memory device 120. The control logic circuit 130 may include an error correction circuit 131.

[0032] The error correction circuit 131 may be implemented to set the encoder / decoder through the puncturing option information. For example, the error correction circuit 131 may perform operations of changing the type of ECC (e.g., RS code, LDPC code, Hamming code, etc.) that may be used in the memory device 100 and changing the H matrix (parity check matrix) used in the memory device 100. In some implementations, the error correction circuit 131 may apply the ECC to which the first puncturing option is applied to the first memory device 110, and may apply the ECC to which the second puncturing option is applied to the second memory device 120. In some implementations, the error correction circuit 131 may change the puncturing option information according to the error rate during the memory data read operation. In some implementations, the puncturing option information may be a fixed value.

[0033] In some implementations, puncture option information (e.g., indicating which ECC, ECC type, and / or H matrix will be used for a given memory) can be set in a register during an initialization operation. In some implementations, the puncture option information can change in real time. In some implementations, the puncture option information can change based on the error rate of the data being read. In some implementations, there can be multiple puncturing options based on a range of error rates. In some implementations, the error correction circuit 131 can change the settings of the encoder / decoder based on the puncture option information. In some implementations, the size of the punctured error correction code when reliability takes precedence over operating speed can be larger than the size of the punctured error correction code when operating speed takes precedence over reliability.

[0034] In some implementations, the control logic circuit 130 can select storage locations within heterogeneous memory (hybrid / hierarchical memory) based on data attributes. The control logic circuit 130 can track data that causes errors (e.g., read errors) in low-reliability memory (e.g., using codeword error (CE) counts) and move the erroneous data to high-reliability memory during scrubbing.

[0035] When applying ECC encoding to write data, the memory device 100 can perform parity punching according to memory characteristics, so the use of unnecessary high-performance ECC can be limited, thereby reducing memory overhead. Therefore, the overall performance of the memory device 100 can be improved.

[0036] Figure 2A and Figure 2B is a diagram conceptually illustrating parity puncturing for ECC according to some implementations. Figure 2A The main ECC is shown as an example. Figure 2BAn optional ECC is shown in which the length of the parity bits is reduced by code puncturing in the main ECC. In this case, the optional ECC is intended to configure a low-delay code. Figure 2A and Figure 2B A bidirectional ECC configuration with ECC puncturing is shown.

[0037] When an error occurs in the transmitted data, ECC can detect / correct errors. The H matrix is ​​a check matrix used in multiple ECCs. In an error detection operation, the H matrix can determine whether the received data is complete. If the result is not 0 when the H matrix and the received data are multiplied, it is determined that an error has occurred. In an error correction operation, some ECCs can use the H matrix to determine where the error occurred and correct the error. In some cases, all parity bits may not be needed. In this case, unnecessary parity bits may be removed or punctured.

[0038] Figure 3A and Figure 3B is a diagram illustrating optional ECC puncturing according to some implementations of the present disclosure. Figure 3A As shown, the H matrix (H 1bit ) can ensure the correction of a random 1 bit in the 4-bit data. Figure 3B As shown, the H matrix with 3 redundancy (H 1MSB ) can ensure the correction of the most significant bit (MSB) in the 4-bit data. Here, the H matrix (H 1MSB ) can be obtained by 1bit ) removes the shaded columns and rows of parity punches from the H matrix (H 1bit )The modified matrix.

[0039] The error correction circuit 131 can configure ECC punching based on the parity bit redundancy level provided by the memory. When ECC encoding is applied to write data, the memory device 100 composed of heterogeneous memory can use parity punching according to the memory characteristics. When ECC is applied in the memory, the length of the ECC parity can be adjusted based on the memory reliability, thereby limiting the application of unnecessary high-performance ECC. Therefore, due to the reduction of parity (i.e., memory overhead) for data stored in high-reliability memory, this can bring performance enhancement.

[0040] For example, the ECC used in neural network applications can be a low-overhead valid bit protection code. When the weight values ​​of the neural network layer are stored / updated in DRAM, as long as the effective value of the weight value is accurate, the effectiveness of the learning process is little or not reduced. Activation values ​​can also be applied during the inference process. The data accuracy of the neural network weights can be any of 32 bits, 16 bits, or 8 bits. The code can be changed according to the data accuracy. For example, (136, 128)-DRAM ECC can be changed to 4×(32+n1, 32)-ECC or 8×(16+n2, 16)-ECC.

[0041] The on-die ECC inside the DRAM can support single error correction (SEC), single 2-symbol error correction (S2EC), and single error correction, double error correction (SECDED) levels. In order to correct a 1-bit error at any position, about 8 redundant parity bits are required for 128-bit data. When the four neural network layer weight values ​​are stored in (128+8) bits of data, the on-chip ECC can correct only one of the four weights. By dividing into four blocks, a code that can correct the value of the MSB 1 bit of each weight value can be designed. For example, (136, 128)-SEC can be changed to (34, 32)-1MSB repetition code × 4. Therefore, a valid value can be guaranteed for the four weight values.

[0042] Figure 4 is a diagram illustrating error correction circuit 131 according to some implementations. Figure 4 , the error correction circuit 131 may include an encoder / decoder 131 - 1 .

[0043] The error correction circuit 131 can change the method of generating the optional ECC by predefined puncturing options. In this case, the puncturing options can be H matrix editing options (which row / column to exclude; option 1), or it can be a configuration change of the encoder / decoder 131-1 specified by the selected puncturing options (option 2). At this time, the puncturing options / modes of the encoder can be shared with the decoder.

[0044] In some implementations, parity puncturing can remove portions of the parity / check bits generated by the ECC encoding. Such parity puncturing may reduce error coverage, but may reduce encoding / decoding delays and reduce memory usage. In some implementations, the error correction circuit 131 can adjust the puncturing level. By configuring the error correction circuit 131 with multiple options (puncturing option 1, puncturing option 2, etc.), user needs and memory specifications can be reflected. In some implementations, the error correction circuit 131 can use a flag / address to identify the destination (e.g., destination memory), and a dedicated puncturing option can be applied.

[0045] Figure 5Aand Figure 5B is a diagram showing an example of a configuration of optional ECC. When reliability is determined to be more important than operating speed, it can be applied Figure 5A The punctured ECC configuration shown. This can be applied when speed of operation is determined to be more important than reliability. Figure 5B The punctured ECC configuration shown.

[0046] Figure 6 is a diagram illustratively showing a table of puncturing options / modes according to error rates according to some implementations of the present disclosure. Figure 6 , the value of the punching option / mode can vary depending on the range of the error rate. For example, when the error rate r is 0 or higher and less than a 0 When the error rate r is at least a 0 and less than a 1 When the error rate r is not less than a n-1 and lower than a n , the n-bit puncturing option can be used. n And when it is less than 1, a system failure alarm can be issued.

[0047] In some implementations, error rates can be measured when training / testing DRAM in initialization operations. Punching options can be created and applied based on the measured error rates. In some implementations, when a new tiered memory is connected to the memory system, an internal controller can determine the ECC configuration to apply.

[0048] like Figure 6 As shown, the puncturing options applied to each region (eg, die / chip, etc.) in which the error rate is determined may be stored in internal registers of the control logic circuit 130 (controller).

[0049] A memory device according to some implementations may track an error rate of data reads in real time and change puncturing options according to the tracked error rate.

[0050] Figure 7 is a diagram illustrating a memory device 100a according to some implementations. Figure 7 , the memory device 100a may include a high-reliability memory device 110a, a low-reliability memory device 120a, and a control logic circuit 130a.

[0051] In this case, the memory device 100 a may communicate with the external device using a compute quick link (CXL) interface.

[0052] The high reliability memory device 110a may be implemented to store data and a punctured error correction code during a write operation. In some implementations, the punctured error correction code may include a Hamming code.

[0053] The low reliability memory device 120a may be implemented to store data and an original error correction code during a write operation. In some implementations, the original error correction code may be an RS code.

[0054] The control logic circuit 130a may include error correction circuits 131a and tracking logic 132. In some implementations, the control logic circuit 130a may move erroneous data from the low-reliability memory device 120a to the high-reliability memory device 110a based on an error rate.

[0055] The error correction circuit 131a may be implemented to change the puncturing option / level applicable to each memory layer or portion in real time according to the memory error rate. In some implementations, if the error rate is greater than or equal to a reference value, the puncturing level may be reduced. In some implementations, if the error rate is lower than a reference value, the puncturing level may be increased. In some implementations, the error correction circuit 131a may change the H matrix by parity puncturing corresponding to the puncturing option information. In some implementations, when the error rate is equal to or greater than a reference value, the error correction circuit 131a may reduce the puncturing level, and when the error rate is lower than the reference value, the puncturing level may be increased.

[0056] Tracking logic 132 may track memory error rates (eg, as measured by codeword error (CE) counts, etc.) In some implementations, tracking logic 132 may be activated during patrol scrubbing operations. By activating tracking logic 132 during patrol scrubbing operations, additional overhead may be minimized.

[0057] Aspects of the present disclosure may provide solutions to the memory aging problem. For example, erroneous data may be moved based on CE count tracking. Figure 7 As shown, erroneous data from the low reliability memory device 120a may be moved to the high reliability memory device 110a. For example, when an event (e.g., CE count>threshold) occurs in the tracking logic 132, the control logic circuit 130a may move the erroneous data read from the low reliability memory device 120 to the high reliability device 110a. In some implementations, the heterogeneous memory device may be configured to read data from the low reliability memory device, perform an error correction operation on the read data, track a codeword error (CE) count according to the error correction operation, and move the data from the low reliability memory device to the high reliability memory device when the value of the CE count is greater than or equal to a reference value.

[0058] In some implementations, error correction operations are performed using a sign code. In some implementations, low reliability memory devices apply a sign code during write operations, while high reliability memory devices apply a Hamming code that varies according to an error rate during write operations.

[0059] In some implementations, before moving data to a high-reliability memory device, the memory device 100a may notify the host and store the corresponding area in a register / cache within the control logic circuit 130a. The memory device 100a may store the corresponding area within the control logic circuit 130a by using the reliability, availability, and serviceability (RAS) driven by the host. Then, in some implementations, when an event occurs, the memory device 100a may move the data to the remaining high-reliability memory area through a demand data scrubbing operation. In this case, demand data scrubbing is an operation that checks the data read from the memory and corrects the data using ECC when necessary.

[0060] The memory device 100a according to some implementations moves erroneous hot data to a highly reliable memory in advance and can prevent system performance degradation and prevent possible failures.

[0061] Figure 8 is a flow chart illustrating an example of the operation of a memory device according to some implementations. For example, Figure 8 The process can be used Figure 1 , Figure 4 and Figure 7 The equipment and as reference Figure 1-Figure 7 Perform as described. Figure 8 The process can be used to store write data in memory.

[0062] The memory device may receive write data from a host device (e.g., an external device to which the memory device is connected) (S110). An ECC level corresponding to the puncturing option information may be set using a flag / address included in the write data (S120). An ECC code may be generated according to the set ECC level (S130). The write data and the ECC code may be stored in the corresponding memory device (S140).

[0063] In some implementations, the puncture option information may be set in a register during an initialization operation. In some implementations, an error rate of data read from different memory devices is tracked, and the puncture option information may be changed according to the tracked error rate. In some implementations, when the error rate is greater than a predetermined value, fault alarm information may be output to the system. In some implementations, when the error rate of data read from a first memory device is greater than or equal to a reference value, the erroneous data may be moved internally (without system intervention) to a second memory device different from the first memory device. Thereafter, the memory device may notify the system of information related to the data movement.

[0064] Fig. 9 is a diagram illustrating the operation of a memory device according to some implementations. For example, Fig. 9 The process can be used Figure 1 , Figure 4 and Figure 7 The equipment and as referenced Figure 1-7 Perform as described. Fig. 9 The process can be used to output the data read from the memory. Figure 8 The process of storing data is executed Fig. 9 process.

[0065] The memory device may read data and an ECC code from a corresponding first memory device or a second memory device in response to an address (S210). The memory device may perform an error correction operation according to a set ECC level corresponding to the selected memory device (S220). The memory device may output error-corrected data to a host (S230). In some implementations, the set ECC level may be changed according to an error rate of the read data. In some implementations, data movement may be performed according to an error rate of the read data.

[0066] The present disclosure is applicable to ECC for hybrid memory systems and storage class memories (SCMs), with two non-limiting examples provided.

[0067] The devices and processes according to the present disclosure can be combined with machine learning specific memory and memory-integration (PIM) technology. Since the present disclosure supports hybrid memory configuration, the present disclosure can be used to configure an accelerator for artificial intelligence learning.

[0068] Aspects of the present disclosure may be applied to computing systems.

[0069] Fig.10 is a diagram illustrating a computing system according to some implementations. Fig.10, the host device 200 and the plurality of CXL devices 220a, 220b, ..., 220h may communicate with each other through the CXL switch 210. The CXL switch 210 may be a component included in the CXL interface. The CXL switch 210 may be configured to mediate communication between the host device 200 and the CXL devices 220. For example, when the host device 200 and the CXL devices 220 communicate with each other, the CXL switch 210 may be configured to transmit information (such as a request, data, a response, or a signal) sent from the host device 200 or the CXL device 220 to the CXL device 220 or the host device 200. When the CXL devices 220a, 220b, ..., 220h communicate with each other, the CXL switch 210 may be configured to transmit information such as a request, data, a response, or a signal between the CXL devices 220a, 220b, ..., 220h.

[0070] Host device 200 may include CXL controller 201. CXL controller 201 may communicate with CXL device 220 via CXL switch 210. CXL controller 201 may be coupled to memory controller 202 and associated memory 203.

[0071] The CXL switch 210 may be used to implement storage clustering through one-to-many and many-to-one switching between connected CXL devices 220 a, 220 b, . . . , 220 h (e.g., (i) the CXL switch 210 connects multiple root ports to one endpoint, (ii) connects one root port to multiple endpoints, or (iii) multiple root ports may be connected to multiple endpoints).

[0072] In addition to providing packet switching functions for CXL packets, CXL switch 210 can also be used to connect CXL devices 220a, 220b, ..., 220h to one or more host devices 200. CXL switch 210 (i) allows CXL devices 220a, 220b, ..., 220h to include various types of memory with different characteristics, (ii) virtualizes the memory of CXL devices 220a, 220b, ..., 220h and allows data of different characteristics (e.g., access frequency) to be stored in the appropriate type of memory, and (iii) supports remote direct memory access (RDMA). In this case, "virtualizing" memory means performing memory address translation between processing circuits and memory.

[0073] The CXL device 220a may include a CXL controller 221, a processor 222, a memory controller 223, and a memory device 224. The other CXL devices 220a, 220b, ..., 220h may also include the same or similar components as the CXL device 220a.

[0074] The CXL controller 221 may be connected to the CXL switch 210. The CXL controller 221 may communicate with the host device 200 or other CXL devices through the CXL switch 210. The CXL controller 221 may include a PCIe 5.0 (or other version) architecture for a CXL.io path, and may add CXL-specific CXL.cache and CXL.mem paths. In some implementations, the CXL controller 221 may be configured to be backward compatible with older cache coherence protocols, such as CXL 1.1. The CXL controller 221 may be configured to implement the CXL.io, CXL.mem, and CXL.cache protocols or other suitable cache coherence protocols. The CXL controller 221 may be configured to support different CXL device types, such as type 1, type 2, or type 3 CXL devices. The CXL controller 221 may be configured to support PCIe protocols, such as the PCIe 5.0 protocol. CXL controller 221 may be configured to support the PIPE 5.x protocol using any suitable PIPE interface width (eg, 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit configurable PIPE interface widths).

[0075] Processor 222 may be configured to control the overall operation of CXL device 220a. Processor 222 may perform operations on data stored in memory device 224. Processor 222 may perform filtering on data stored in memory device 224.

[0076] The memory controller 223 may control the memory device 224 so that data is stored in the memory device 224 or data is read from the memory device 224. In some implementations, the memory controller 223 may be implemented to comply with a standard protocol, such as a DDR interface, an LPDDR interface, etc. The memory device 224 may store data or output stored data under the control of the memory controller 223. The memory controller 223 may be configured as described in reference to Figure 1-Figure 9 The configuration described can be used, for example, to implement ECC puncturing.

[0077] The memory controller 223 may be configured to manage the memory device 224. In some implementations, the memory controller 223 may allocate a portion of the memory device 224 as a cache buffer 225. The memory controller 223 may allocate the cache buffer 225 to other devices (eg, a host, other CXL devices).

[0078] In some implementations, at least a portion of the area of ​​the memory device 224 of the CXL device 220a may be allocated as a dedicated area of ​​the CXL device 220a, while the remaining area may be used as an accessible area by the host device 200 or other CXL devices 220b, ..., 220h.

[0079] In some implementations, the memory controller 223 may select a data block to be discarded from the data cached in the cache buffer 225 according to a cache replacement policy assigned to the cache buffer 225. As the cache replacement policy, a least recently used (LRU) replacement policy, a least frequently used (LFU) replacement policy, a re-reference interval prediction (RRIP) replacement policy, etc. may be used. However, in addition to the LRU replacement policy, other cache replacement policies that replace the cache according to recency may be used, and in addition to the LFU replacement policy, other cache replacement policies that replace the cache according to frequency may be used.

[0080] Fig.11 is a diagram illustrating a computing system 1000 according to some implementations. Fig.11 The computing system 1000 includes a first CPU ( 1010 a ), a second CPU ( 1010 b ), a GPU ( 1030 ), an NPU ( 1040 ), and may include a CXL switch 1015 , a CXL memory 1050 , a CXL storage device 1052 , a PCIe device 1054 , and an accelerator (CXL device) 1056 .

[0081] The first CPU 1010a, the second CPU 1010b, the GPU 1030, the NPU 1040, the CXL memory 1050, the CXL storage device 1052, the PCIe device 1054, and the accelerator 1056 may be commonly connected to the CXL switch 1015, and may communicate with each other through the CXL switch 1015. In some implementations, each of the first CPU 1010a, the second CPU 1010b, the GPU 1030, and the NPU 1040 may be a host device, and may be directly connected to each memory (1020a, 1020b, 1020c, 1020d, 1020e), respectively.

[0082] In some implementations, CXL memory 1050 and CXL storage device 1052 may be implemented to support Figures 1 to 10 The punching options are described in the memory device.

[0083] By one or more of the first CPU (1010a), the second CPU (1010b), the GPU (1030), and the NPU (1040), at least some areas of the memory 1060a of the CXL memory 1050 and the memory 1060b of the CXL storage device 1052 may be allocated to the first CPU 1010a, the second CPU 1010b, the GPU 1030, the NPU 1040, the CXL memory 1050 and the CXL storage device 1052, the PCIe device 1054, and at least one cache buffer in the accelerator 1056.

[0084] In some implementations, the CXL switch 1015 may be connected to a PCIe device 1054 or an accelerator 1056 configured to support various functions, and the PCIe device 1054 or the accelerator 1056 communicates with each of the first CPU 1010a, the second CPU 1010b, the GPU 1030, and the NPU 1040 through the CXL switch 1015, or may access the CXL memory 1050 and the CXL storage 1052. In some implementations, the CXL switch 1015 may be connected to an external network 1060 or a logical fabric, and may be configured to communicate with an external server through the external network 1060 or the logical fabric.

[0085] Aspects of the present disclosure are applicable to data server systems.

[0086] Fig.12 1 is a diagram illustrating a data server system 1100 according to some implementations. Fig.12 , the data server system 1100 is a facility that collects various data and provides services, and may also be referred to as a data storage center. The data server system 1100 may be a system for operating a search engine and a database, and may be a computing system used in a company or government agency such as a bank. The data server system 1100 may include application servers 1110a, ..., 1110h and storage servers 1120a, ..., 1120h. The number of application servers and the number of storage servers may be selected in various ways according to different implementations, and the number of application servers and the number of storage servers may be different.

[0087] The configuration of the first storage server 1120a will be described in detail below. Each of the application servers 1110a, ..., 1110h and the storage servers 1120a, ..., 1120h may have a similar structure, and the application servers 1110a, ..., 1110h and the storage servers 1120a, ..., 1120h may communicate with each other through the network NT.

[0088] The first storage server 1120a may include a processor 1121, a memory 1122, a switch 1123, a storage device 1125, a CXL memory 1124, and a network interface card (NIC) 2216. The processor 1121 may control the overall operation of the first storage server 1120a, and access the memory 1122 to execute instructions or process data loaded into the memory 1122. The processor 1121 and the memory 1122 may be directly connected, and the number of processors 1121 and the number of memories 1122 included in the first storage server 1120a may be selected in various ways.

[0089] In some implementations, the processor 1121 and the memory 1122 may provide a processor-memory pair. In some implementations, the number of processors 1121 and memory 1122 may be different. The processor 1121 may include a single-core processor or a multi-core processor. The above description of the storage server 1120 may be similarly applied to each of the application servers 1120a, ..., 1120h.

[0090] The switch 1123 may be configured to mediate or route communications between various components included in the first storage server 1120a. In some implementations, the switch 1123 may be a switch of FIG. Fig.10 For example, the switch 1123 may be a switch implemented based on the CXL protocol.

[0091] CXL memory 1124 and storage device 1125 may be capable of Figures 1 to 10 The described CXL device configures ECC according to the puncturing option. The CXL memory 1124 may be connected to the switch 1123. The storage device 1125 may include a CXL interface circuit (CXL_I / F), a controller (CTRL), and a NAND flash memory (NAND). The storage device 1125 may store data or output the stored data according to a request from the processor 1121. The application servers 1110a, ..., 1110h may not include the storage device 1125.

[0092] A network interface card (NIC) 1126 may be connected to the CXL switch 1123. The NIC 1126 may communicate with other storage servers 1120a, ..., 1120h or other application servers 1110a, ..., 1110h through a network (NT). In some implementations, the NIC 1126 may include a network interface card, a network adapter, etc. The NIC 1126 may be connected to the network NT through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NIC 1126 may include an internal memory, a digital signal processor (DSP), a host bus interface, etc., and may be connected to the processor 1121 or the switch 1123 through a host bus interface. In some implementations, the NIC 1126 may be integrated with at least one of the processor 1121, the switch 1123, and the storage device 1125.

[0093] In some implementations, the network (NT) can be implemented using Fibre Channel (FC) or Ethernet. In this case, FC is a medium for relatively high-speed data transmission, and optical switches that provide high performance / high availability can be used. Depending on the network (NT) access method, the storage server can provide file storage, block storage, or object storage.

[0094] In some implementations, the network NT may be a storage-only network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to an FC protocol (FCP). As another example, the SAN may be an IP-SAN implemented using a TCP / IP network and according to an iSCSI (SCSI over TCP / IP or Internet SCSI) protocol. In some implementations, the network NT may be a general network, such as a TCP / IP network. For example, the network (NT) may be implemented according to protocols such as FC over Ethernet (FCoE), network attached storage (NAS), and NVMe overFabrics (NVMe-oF).

[0095] In some implementations, at least one of the application servers 1110a, ..., 1110h can store data requested by a user or client to be stored in one of the storage servers 1120a, ..., 1120h through the network NT. At least one of the application servers 1110a, ..., 1110h can obtain data requested by a user or client to be read from one of the storage servers 1120a, ..., 1120h through the network NT. For example, at least one of the application servers 1110a, ..., 1110h can be implemented as a web server or a database management system (DBMS).

[0096] In some implementations, at least one of the application servers 1110a, ..., 1110h may access a memory, CXL memory, or storage device included in another application server through a network NT, or may access a memory, CXL memory, or storage device included in a storage server 1120a, ..., 1120h through a network (NT). Therefore, at least one of the application servers 1110a, ..., 1110h may perform various operations on data stored in other application servers or storage servers. For example, at least one of the application servers 1110a, ..., 1110h may execute a command to move or copy data between other application servers or storage servers. At this time, the data may be moved to the memory or CXL memory of the application server through the memory or CXL memory of the storage server or directly from the storage device memory of the storage server. For security or privacy considerations, data moving on the network may be encrypted.

[0097] In some implementations, reference Figures 1 to 12 Each component described or a combination of two or more components may be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), or the like.

[0098] The above-mentioned equipment can be realized by hardware components, software components or a combination of hardware components and software components. For example, the equipment and components described in the above examples can be realized using one or more general-purpose computers or special-purpose computers (such as processors, controllers, arithmetic logic units (ALUs), digital signal processors, microcomputers, field programmable gate arrays (FPGAs), programmable logic units (PLUs), microprocessors or any other equipment that can execute and respond to instructions). The processing device can execute an operating system (OS) and one or more software applications running on the operating system. In addition, the processing device can access, store, manipulate, process and generate data in response to the execution of software. For ease of understanding, the processing unit can be described as being used in some cases, but those skilled in the art will understand that the processing device may include multiple processing elements or multiple types of processing elements. For example, the processing device may include multiple processors or a processor and a controller. In addition, other processing configurations such as parallel processors are also possible.

[0099] Software may include computer programs, codes, instructions, or a combination of one or more thereof, and may configure a processing unit to operate on demand or command the processing unit independently or collectively. Software or data may be embodied in any type of machine, component, physical device, virtual device, computer storage medium, or device for interpreting instructions or data by or providing instructions or data to a processing device. Software may be distributed on networked computing systems so as to be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0100] The memory device of the present disclosure can support a hybrid memory system by configuring one ECC using ECC puncturing instead of configuring an independent ECC circuit. By adjusting the puncturing level, the memory device of the present disclosure can adjust the ECC level for volatile flash memory.

[0101] As described above, an error correction code may be generated according to a puncturing option during a write operation, and thus the overall system may be improved by reducing unnecessary memory usage.

[0102] Although the present disclosure includes a number of specific implementation details, they should not be viewed as limiting the scope of the claimed protection. Certain features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. On the contrary, various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, one or more features from a combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variant of a sub-combination.

[0103] While several examples have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the disclosure.

Claims

1. A memory device, comprising: a first memory device; a second memory device; and a control logic circuit configured to control the first memory device and the second memory device, The control logic circuit includes an error correction circuit, wherein the error correction circuit is configured to generate a a first error correction code of a first size, and A second error correction code of a second size, wherein the second size is greater than the first size, and wherein the control logic circuit is configured to store the first error correction code in the first memory device during the first write operation and to store the second error correction code in the second memory device during the second write operation.

2. The memory device according to claim 1, wherein: The first memory device is configured to apply a punctured error correction code, and The second memory device is configured to apply a raw error correction code.

3. The memory device according to claim 1, wherein: The first memory device is a volatile memory device, and The second memory device is a non-volatile memory device.

4. The memory device according to claim 1, wherein: The control logic circuit is configured to variably set the first size based on an error rate of data stored in the first memory device.

5. The memory device according to claim 1, wherein: The puncturing option information is set in registers during an initialization operation.

6. The memory device according to claim 1, wherein: The error correction circuit is configured to change the puncturing option information in real time.

7. The memory device according to claim 1, wherein: The error correction circuit is configured to change the puncturing option information based on an error rate of the read data.

8. The memory device according to claim 7, wherein: The error correction circuit is configured to change the puncturing option information depending on a range of error rates.

9. The memory device according to claim 1, wherein: The error correction circuit is configured to change a setting of an encoder or a decoder based on the puncturing option information.

10. The memory device of claim 1, wherein: The error correction circuit is configured to change at least one of a type of an error correction code or an H matrix based on puncturing option information.

11. A memory device comprising: a first memory device; a second memory device; as well as a control logic circuit configured to control the first memory device and the second memory device, Wherein, the control logic circuit includes an error correction circuit configured to generate a punctured error correction code for the first memory device or an original error correction code for the second memory device based on the puncturing option information, and tracking logic configured to track an error rate of data read from the first memory device or the second memory device, Wherein, the puncturing option information changes based on an error rate.

12. The memory device of claim 11, wherein: The memory device is configured to communicate with an external device using a compute fast link (CXL) interface, The punctured error correction code is a Hamming code, The original error correction code is a RS code, and The control logic circuit is configured to move erroneous data from the second memory device to the first memory device based on an error rate.

13. The memory device of claim 11, wherein: The error correction circuit is configured to change the H matrix by parity puncturing based on the puncturing option information.

14. The memory device of claim 11, wherein: The error correction circuit is configured to reduce the puncturing level when the error rate is at least a reference value, and to increase the puncturing level when the error rate is less than the reference value.

15. The memory device of claim 11, wherein: The control logic circuit is configured to activate the tracking logic during a patrol scrubbing operation.

16. A method of operating a memory device, the method comprising: Receive write data; Setting the error correction code level based on the puncture option information; generating an error correction code for writing data based on the error correction code level; as well as The write data and the error correction code are stored in a first memory device corresponding to the error correction code level.

17. The method according to claim 16, further comprising: The puncturing option information is set in the register during the initialization operation.

18. The method according to claim 16, further comprising: tracking an error rate of data read from the first memory device; as well as The punch option information is changed based on the error rate.

19. The method according to claim 18, further comprising: In response to the error rate being greater than a predetermined value, fault alarm information is output to the system.

20. The method of claim 16, further comprising: In response to an error rate of data read from the first memory device being greater than or equal to a reference value, the error data is moved to a second memory device different from the first memory device.

Images