Method for preparing a semiconductor device

Abstract

The present invention provides a method for preparing a semiconductor device, the method comprising the following steps: providing a substrate, on which gate structures arranged at intervals are formed, and sidewall structures are arranged on both sides of each gate structure; forming a cap protection layer, the cap protection layer covering the upper surface of the gate structure and the surface of the sidewall structure close to the upper surface of the gate structure; etching the substrate in sequence through a dry etching process and a wet etching process to form a sigma groove, and forming a silicon germanium epitaxial layer in the sigma groove, and removing the cap protection layer by etching and consuming the dry etching process; removing the sidewall structure. The present invention adds the step of forming the cap protection layer, so that the cap protection layer can protect the gate structure and the sidewall structure in the dry etching process, avoids the problem of over-etching of the gate hard mask and over-etching of the sidewall structure, effectively protects the gate hard mask, and thus retains a sufficient process window.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor device. Background Art

[0002] In the current conventional process of silicon germanium epitaxial growth, a plasma dry etching process is generally used to form a U-shaped or bowl-shaped groove 11 (such as Figure 1 As shown in FIG. 1 , the gate structure includes, from bottom to top, a stacked hard mask layer 22 located on a polysilicon gate 21, and a sidewall structure 23 is provided on the sidewall of the gate structure; the trench 11 is then etched by a wet etching process to form a sigma-shaped groove, and silicon germanium epitaxial growth is completed in the sigma-shaped groove, and finally the sidewall structure (as shown in FIG. Figure 2 as shown).

[0003] The plasma dry etching process includes multiple film layer etching steps, which results in over-etching of the stacked hard mask layer and over-etching of the sidewall structure, causing the height of the sidewall structure to be reduced too much, thereby exposing the sidewalls of the stacked hard mask layer too much. As a result, in the step of removing the sidewall structure, the film layer of the stacked hard mask layer that is made of the same material as the sidewall structure is corroded, causing the mask effect of the stacked hard mask layer to deteriorate, thereby affecting the morphology of the gate structure in subsequent processes. Summary of the invention

[0004] The object of the present invention is to provide a method for preparing a semiconductor device, which can avoid the problems of over-etching of a gate hard mask and over-etching of a sidewall structure.

[0005] In order to solve the above problems, the present invention provides a method for preparing a semiconductor device, comprising the following steps:

[0006] A substrate is provided, on which gate structures are arranged at intervals, and sidewall structures are arranged on both sides of each gate structure;

[0007] forming a capping protection layer, wherein the capping protection layer covers the upper surface of the gate structure and the surface of the sidewall structure close to the upper surface of the gate structure;

[0008] The substrate between the adjacent gate structures is sequentially etched by a dry etching process and a wet etching process to form a sigma trench, and silicon germanium epitaxial growth is performed in the sigma trench to form a silicon germanium epitaxial layer, wherein the dry etching process etches and consumes and removes the cap protection layer;

[0009] The side wall structure is removed.

[0010] Optionally, the specific steps of forming the sidewall structure are:

[0011] forming a protective layer and a surface oxide layer, wherein the protective layer covers the sidewalls of the gate structure, and the surface oxide layer covers the surface of the substrate and covers the upper surface of the gate structure and the surface of the protective layer;

[0012] Depositing a silicon nitride film layer on the surface oxide layer;

[0013] The silicon nitride film layer is etched to form a sidewall structure outside the protection layer and to expose a surface oxide layer on the substrate outside the gate structure.

[0014] Furthermore, the specific method of etching the silicon nitride film layer is:

[0015] In the dry etching reaction chamber, the silicon nitride film layer is etched by a dry etching process to form a sidewall structure outside the protective layer.

[0016] Furthermore, the material of the protective layer is silicon nitride, and the material of the surface oxide layer is silicon oxide.

[0017] Optionally, the gate structure includes a gate dielectric layer, a polysilicon gate, a first hard mask layer and a second hard mask layer from bottom to top, and the sidewall structure covers the sidewalls of the polysilicon gate, the sidewalls of the first hard mask layer and the sidewalls of the second hard mask layer.

[0018] Furthermore, the gate dielectric layer is a gate oxide layer or a high dielectric constant layer, the first hard mask layer is a silicon nitride layer, and the second hard mask layer is a silicon oxide layer.

[0019] Furthermore, the specific steps of forming the cap protection layer are:

[0020] Forming a silicon oxide film layer on the upper surface of the gate structure and the surface of the sidewall structure by a deposition process, wherein the silicon oxide film layer also covers the exposed surface oxide layer;

[0021] Cleaning the silicon oxide film layer on the surface oxide layer on the substrate by dry etching process;

[0022] The above two steps are repeated periodically until the thickness of the silicon oxide film layer retained on the upper surface of the gate structure and the sidewall structure nearby reaches a desired value, thereby forming a cap protection layer.

[0023] Furthermore, the step of forming the capping protection layer is performed in the dry etching reaction chamber.

[0024] Furthermore, the reaction gas used in the deposition process is SiCl4, and the bias power configured is not more than 50W;

[0025] The etching gases used in the dry etching process are CF4 and Ar, and the bias power is configured to be 180W~220W.

[0026] Optionally, the method for forming the sigma groove is specifically as follows:

[0027] In a dry etching reaction chamber, the substrate is etched by a dry etching process using the gate structure and the sidewall structure as masks to form a groove, and the dry etching process consumes the cap protection layer;

[0028] The recess is etched by a wet etching process to form a sigma trench.

[0029] Compared with the prior art, the present invention has the following unexpected technical effects:

[0030] The present invention provides a method for preparing a semiconductor device, the method comprising the following steps: providing a substrate, on which gate structures arranged at intervals are formed, and sidewall structures are arranged on both sides of each gate structure; forming a cap protection layer, the cap protection layer covering the upper surface of the gate structure and the surface of the sidewall structure close to the upper surface of the gate structure; etching the substrate between adjacent gate structures in turn by dry etching and wet etching to form a sigma groove, and performing silicon germanium epitaxial growth in the sigma groove to form a silicon germanium epitaxial layer, wherein the dry etching process etches and consumes and removes the cap protection layer; and removing the sidewall structure. The present invention achieves an unexpected technical effect by adding the step of forming the cap protection layer: the cap protection layer can protect the gate structure and the sidewall structure in the dry etching process, avoiding the problem of over-etching of the gate hard mask and over-etching of the sidewall structure, effectively protecting the gate hard mask, and thus retaining a sufficient process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the structure of a current semiconductor device when a U-shaped or bowl-shaped groove is formed.

[0032] Figure 2 This is a schematic diagram of the structure of the current semiconductor device after removing the sidewall structure.

[0033] Figure 3 A schematic flow chart of a method for preparing a semiconductor device provided in one embodiment of the present invention.

[0034] Figure 4 A schematic structural diagram of a substrate provided in one embodiment of the present invention.

[0035] Figure 5 It is a schematic diagram of the structure after forming the sidewall structure according to one embodiment of the present invention.

[0036] Figure 6 FIG. 1 is a schematic diagram of a structure after a silicon oxide film layer is formed according to an embodiment of the present invention.

[0037] Figure 7 It is a schematic diagram of the structure after etching the silicon oxide film layer according to an embodiment of the present invention.

[0038] Figure 8 It is a schematic structural diagram of forming a cap protection layer according to an embodiment of the present invention.

[0039] Fig. 9 It is a schematic diagram of the structure after forming a groove layer according to an embodiment of the present invention.

[0040] Fig.10 FIG. 4 is a schematic diagram of a structure after forming a sigma groove according to an embodiment of the present invention.

[0041] Fig.11 FIG. 1 is a schematic diagram of a structure after a sigma trench structure is formed according to an embodiment of the present invention.

[0042] Fig.12 It is a schematic diagram of the structure of an embodiment of the present invention after the side wall structure is removed.

[0043] Description of reference numerals:

[0044] 10-substrate; 11-trench; 21-polysilicon gate; 22-stacked hard mask layer;

[0045] 100-substrate; 111-groove; 112-sigma trench; 120-silicon germanium epitaxial layer; 210-gate structure; 211-gate dielectric layer; 212-polysilicon gate; 213-first hard mask layer; 214-second hard mask layer; 221-protective layer; 222-surface oxide layer; 231-silicon nitride film layer; 232-sidewall structure; 240-cap protective layer; 241-silicon oxide film layer. DETAILED DESCRIPTION

[0046] The following is a further detailed description of a method for preparing a semiconductor device of the present invention. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.

[0047] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.

[0048] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0049] like Figure 3 As shown, this embodiment provides a method for preparing a semiconductor device, which is applied to a 28nm sigma trench dry forming process, and utilizes the high and low bias power and gas system conversion of a dry etching machine to achieve protection of the gate structure and the sidewall structure.

[0050] The method for preparing the semiconductor device comprises the following steps:

[0051] Step S1: providing a substrate, on which gate structures arranged at intervals are formed, and sidewall structures are arranged on both sides of each gate structure;

[0052] Step S2: forming a capping protection layer, wherein the capping protection layer covers the upper surface of the gate structure and the surface of the sidewall structure close to the upper surface of the gate structure;

[0053] Step S3: etching the substrate between adjacent gate structures in sequence by dry etching and wet etching to form sigma trenches, and performing silicon germanium epitaxial growth in the sigma trenches to form silicon germanium epitaxial layers, wherein the dry etching process etches and consumes and removes the cap protection layer;

[0054] Step S4: removing the side wall structure.

[0055] The following combination Figure 4-Figure 12 A method for preparing a semiconductor device provided in this embodiment is described in detail.

[0056] like Figure 4-Figure 5 As shown, step S1 is first performed to provide a substrate 100 , on which gate structures 210 arranged at intervals are formed, and sidewall structures 232 are arranged on both sides of each gate structure 210 .

[0057] This step specifically includes the following steps:

[0058] like Figure 4 As shown, first, a substrate 100 is provided, and the substrate 100 may be a silicon substrate for forming a semiconductor device. Ions may be implanted into the substrate 100 to form an N-type semiconductor substrate 100 or a P-type semiconductor substrate 100, and the substrate 100 may include various doping regions according to design requirements known in the art, and the processes for forming the doping regions are all implemented using existing process technologies, which will not be described in detail here.

[0059] Next, a plurality of gate structures 210 are formed on the surface of the substrate 100 at intervals, and the gate structure 210 includes, from bottom to top, a gate dielectric layer 211, a polysilicon gate 212, a first hard mask layer 213, and a second hard mask layer 214. The gate dielectric layer 211 may be a gate oxide layer or a high dielectric constant layer, the first hard mask layer 213 is made of silicon nitride, and the second hard mask layer 214 is made of silicon oxide.

[0060] Next, a protective layer 221 and a surface oxide layer 222 are formed, wherein the protective layer 221 covers the sidewalls of the gate structure 210, and the surface oxide layer 222 covers the surface of the substrate 100 and covers the upper surface of the gate structure 210 and the surface of the protective layer 221. The material of the protective layer 221 is silicon nitride, and the material of the surface oxide layer 222 is the same as that of the second hard mask layer 214. The protective layer 221 covers the sidewalls of the polysilicon gate 212, the sidewalls of the first hard mask layer 213, and the sidewalls of the second hard mask layer 214.

[0061] Next, a silicon nitride film layer 231 is deposited on the surface oxide layer 222 .

[0062] like Figure 5 As shown, in a dry etching reaction chamber, the silicon nitride film layer 231 is etched by a dry etching process to form a sidewall structure 232 outside the protective layer 221 and expose the surface oxide layer 222 on the substrate 100 outside the gate structure 210 .

[0063] like Figure 6-Figure 8 Then, step S2 is performed to form a capping protection layer 240 , wherein the capping protection layer 240 covers the upper surface of the gate structure 210 and the surface of the sidewall structure 232 close to the upper surface of the gate structure 210 .

[0064] This step specifically includes the following steps:

[0065] like Figure 6As shown, in step S21, a silicon oxide film layer 241 is formed on the upper surface of the gate structure 210 and the surface of the sidewall structure 232 by a deposition process, and the silicon oxide film layer 241 also covers the exposed surface oxide layer 222. In detail, in the dry etching reaction chamber, the main reaction gas SiCl4 used in the dry etching reaction chamber is used, and a lower bias power is configured, for example, the bias power does not exceed 50W, and a silicon oxide film layer 241 is deposited on the surface of the gate structure 210 and the sidewall structure 232. During this reaction process, the deposition amount of the silicon oxide film layer 241 deposited on the upper surface of the gate structure 210 and the sidewall structure 232 near it will be significantly higher than the deposition amount of the silicon oxide film layer 241 on the surface oxide layer 222 located on the substrate 100.

[0066] like Figure 7 As shown, in step S22, the silicon oxide film layer 241 on the surface oxide layer 222 on the substrate 100 is cleaned by a dry etching process, so that the silicon oxide film layer 241 is retained only on the gate structure 210 and the sidewall structure 232. The etching gas of the dry etching process is CF4 and Ar, and the bias power is 180W~220W.

[0067] like Figure 8 As shown, in step S23, step S21 and step S22 are periodically repeated until the thickness of the silicon oxide film layer 241 retained on the upper surface of the gate structure 210 and the sidewall structure 232 near the gate structure 210 reaches a desired value, thereby forming a capping protection layer 240. The capping protection layer 240 only covers the upper surface of the second hard mask layer and the surface of the sidewall structure 232 near the upper surface of the gate structure 210, and exposes the surface of the sidewall structure 232 in a direction perpendicular to the substrate 100.

[0068] In this embodiment, the thickness of the capping protection layer 240 can be controlled by the number of repetitions, the thickness of the silicon oxide film layer 241 deposited each time, and the dry etching time each time, so that the first hard mask layer 213 and the second hard mask layer 214 in the gate structure 210 can meet the different process requirements of subsequent processes.

[0069] It should be noted that the process parameters for each execution of step S21 may be the same or may be slightly adjusted. Similarly, the process parameters for each execution of step S22 may be the same or may be slightly adjusted.

[0070] like Figure 9-11As shown, step S3 is then performed, in which the substrate 100 between adjacent gate structures 210 is sequentially etched by dry etching and wet etching processes to form sigma trenches 112, and silicon germanium epitaxial growth is performed in the sigma trenches 112 to form a silicon germanium epitaxial layer, wherein the dry etching process etches and consumes and removes the cap protection layer 240.

[0071] This step specifically includes the following steps:

[0072] like Fig. 9 As shown, first, in a dry etching reaction chamber, the substrate 100 is etched by a dry etching process using the gate structure 210 and the sidewall structure 232 as masks to form a groove 111. The groove 111 penetrates the surface oxide layer 222 and stops in the substrate 100. In the dry etching process, the cap protection layer 240 protects the upper surface of the gate structure 210 and the surface of the sidewall structure 232 near it, so that the etching gas of the dry etching process corrodes the cap protection layer 240 and consumes the cap protection layer 240, so that the upper surface of the gate structure 210 and the surface of the sidewall structure 232 near the upper surface of the gate structure 210 are not etched or are etched for a short time. At the same time, the second hard mask layer of the gate structure 210 is not consumed too much, and the protection layer 221, the surface oxide layer 222 and the sidewall structure 232 on the side wall of the gate structure 210 are not over-consumed. Their height changes are small, so that they still cover the side walls of the first hard mask layer 213 and the second hard mask layer 214, that is, the side walls of the first hard mask layer 213 are not exposed, which effectively protects the first hard mask layer 213, thereby retaining a sufficient process window.

[0073] In this step, the cap protection layer 240 may not be completely corroded, and may be removed by a special removal process.

[0074] like Fig.10 As shown, the recess 111 is then etched by a wet etching process to form a sigma trench 112 .

[0075] like Fig.11 As shown, silicon germanium epitaxial growth is performed in the sigma trench 112 by a selective epitaxial process to form a silicon germanium epitaxial layer 120. As an example, the selective epitaxial process can be ultra-high vacuum chemical vapor deposition (UHVCVD) or molecular beam epitaxy (MEB). In this embodiment, an ultra-high vacuum chemical vapor deposition process is used to form a silicon germanium epitaxial layer in the sigma trench 112, and the reaction gas includes SiH2Cl2, HCl and GeH4.

[0076] Then, step S4 is performed to remove the sidewall structure 232. Specifically, the sidewall structure 232 is removed by an isotropic etching (i.e., wet etching) process using a hot phosphoric acid solution. Since the sidewalls of the first hard mask layer 213 of the gate structure 210 are still protected by the protective layer 221 and the surface oxide layer 222, the wet etching solution does not contact the first hard mask layer 213. Therefore, the morphology of the first hard mask layer 213 is not affected, and the morphology of the gate structure 210 is maintained, so that the polysilicon gate 212 is well protected in subsequent processes.

[0077] In summary, the present invention provides a method for preparing a semiconductor device, the method for preparing a semiconductor device comprising the following steps: providing a substrate, on which gate structures arranged at intervals are formed, and sidewall structures are arranged on both sides of each gate structure; forming a capping protective layer, the capping protective layer covering the upper surface of the gate structure and the surface of the sidewall structure close to the upper surface of the gate structure; etching the substrate between adjacent gate structures in sequence by dry etching and wet etching to form a sigma groove, and performing silicon germanium epitaxial growth in the sigma groove to form a silicon germanium epitaxial layer, wherein the dry etching process etches and consumes and removes the capping protective layer; and removing the sidewall structure. The present invention achieves an unexpected technical effect by adding the step of forming a capping protective layer: the capping protective layer can protect the gate structure and the sidewall structure in the dry etching process, avoiding the problem of over-etching of the gate hard mask and over-etching of the sidewall structure, effectively protecting the gate hard mask, and thus retaining a sufficient process window.

[0078] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0079] It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: A substrate is provided, on which gate structures are formed at intervals, and both sides of each gate structure are sequentially provided with a protective layer, a surface oxide layer and a sidewall structure; A capping protection layer is formed, wherein the capping protection layer covers the upper surface of the gate structure and the surface of the sidewall structure close to the upper surface of the gate structure, wherein the specific steps of forming the capping protection layer are: Forming a silicon oxide film layer on the upper surface of the gate structure and the surface of the sidewall structure by a deposition process, wherein the silicon oxide film layer also covers the exposed surface oxide layer; Cleaning the silicon oxide film layer on the surface oxide layer on the substrate by dry etching process; Repeat the above two steps periodically until the thickness of the silicon oxide film layer retained on the upper surface of the gate structure and the sidewall structure nearby reaches a desired value, thereby forming a cap protection layer; The substrate between the adjacent gate structures is sequentially etched by a dry etching process and a wet etching process to form a sigma trench, and silicon germanium epitaxial growth is performed in the sigma trench to form a silicon germanium epitaxial layer, wherein the dry etching process etches and consumes and removes the cap protection layer; The side wall structure is removed.

2. The method for preparing a semiconductor device according to claim 1, wherein: The specific steps of forming the sidewall structure are: forming a protective layer and a surface oxide layer, wherein the protective layer covers the sidewalls of the gate structure, and the surface oxide layer covers the surface of the substrate and covers the upper surface of the gate structure and the surface of the protective layer; Depositing a silicon nitride film layer on the surface oxide layer; The silicon nitride film layer is etched to form a sidewall structure outside the protection layer and to expose a surface oxide layer on the substrate outside the gate structure.

3. The method for preparing a semiconductor device according to claim 2, wherein: The specific method of etching the silicon nitride film layer is: In the dry etching reaction chamber, the silicon nitride film layer is etched by a dry etching process to form a sidewall structure outside the protective layer.

4. The method for preparing a semiconductor device according to claim 2, wherein: The material of the protective layer is silicon nitride, and the material of the surface oxide layer is silicon oxide.

5. The method for preparing a semiconductor device according to claim 1, wherein: The gate structure includes a gate dielectric layer, a polysilicon gate, a first hard mask layer and a second hard mask layer from bottom to top, and the sidewall structure covers the sidewalls of the polysilicon gate, the sidewalls of the first hard mask layer and the sidewalls of the second hard mask layer.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The gate dielectric layer is a gate oxide layer or a high dielectric constant layer, the first hard mask layer is a silicon nitride layer, and the second hard mask layer is a silicon oxide layer.

7. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming the capping protection layer is performed in the dry etching reaction chamber.

8. The method for preparing a semiconductor device according to claim 1, wherein: The reaction gas used in the deposition process is SiCl4, and the bias power configured does not exceed 50W; The etching gases used in the dry etching process are CF4 and Ar, and the bias power is configured to be 180W~220W.

9. The method for preparing a semiconductor device according to claim 1, wherein: The method of forming the sigma groove is specifically as follows: In a dry etching reaction chamber, the substrate is etched by a dry etching process using the gate structure and the sidewall structure as masks to form a groove, and the dry etching process consumes the cap protection layer; The recess is etched by a wet etching process to form a sigma trench.

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