Manufacturing method of packaging structure, packaging structure and electronic equipment

Abstract

The invention provides a manufacturing method of a packaging structure, the packaging structure and electronic equipment, and relates to the technical field of semiconductors. The method comprises the steps that a first substrate structure is provided, the first substrate structure comprises a first surface and a second surface, a first packaging layer is formed on the first surface, and a first carrier plate is arranged on the second surface; a second substrate structure is provided, the second substrate structure comprises a third surface and a fourth surface, a second packaging layer is formed on the third surface, and a second carrier plate is arranged on the fourth surface; bonding the first packaging layer and the second packaging layer; removing the first support plate and the second support plate, forming a first stacking layer on the second surface of the first substrate structure, and forming a second stacking layer on the fourth surface of the second substrate structure; the first packaging layer and the second packaging layer are de-bonded, so that the first stacking layer and the second stacking layer can be manufactured at the same time, the first packaging structure and the second packaging structure are obtained, the processing efficiency is improved, and the warping problem caused by an asymmetric structure is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a packaging structure, a packaging structure and an electronic device. Background Art

[0002] At present, in the process of making the packaging structure, it is necessary to make the redistribution layer, the accumulation layer, etc. in sequence, which will cause the substrate structure to be easily warped during the production process and the equipment cannot be produced. In addition, the processing flow is also relatively complicated and the production efficiency is low. Summary of the invention

[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a method for manufacturing a packaging structure, a packaging structure and an electronic device.

[0004] In a first aspect, an embodiment of the present application provides a method for manufacturing a packaging structure, the method for manufacturing the packaging structure comprising:

[0005] Providing a first substrate structure, the first substrate structure comprising a first surface and a second surface arranged opposite to each other, forming a first packaging layer on the first surface, and disposing a first carrier on the second surface;

[0006] Providing a second substrate structure, the second substrate structure comprising a third surface and a fourth surface arranged opposite to each other, a second packaging layer is formed on the third surface, and a second carrier is arranged on the fourth surface;

[0007] bonding the first encapsulation layer to the second encapsulation layer;

[0008] removing the first carrier plate and the second carrier plate, forming a first accumulation layer on the second surface of the first substrate structure, and forming a second accumulation layer on the fourth surface of the second substrate structure;

[0009] Disposing a third carrier plate on a side of the first stacking layer away from the first substrate structure, and disposing a fourth carrier plate on a side of the second stacking layer away from the second substrate structure;

[0010] The first encapsulation layer and the second encapsulation layer are debonded to obtain a first encapsulation structure and a second encapsulation structure.

[0011] In a possible implementation, the first encapsulation layer includes a first redistribution layer and a second redistribution layer; the second encapsulation layer includes a third redistribution layer and a fourth redistribution layer;

[0012] The step of forming a first encapsulation layer on the first surface includes:

[0013] forming a first redistribution layer on the first surface of the first substrate structure;

[0014] Disposing a plurality of first conductive pillars on a side of the first redistribution layer away from the first substrate structure;

[0015] Plastic-sealing the first conductive column to form a first plastic-sealing layer;

[0016] forming a second redistribution layer on a side of the first plastic packaging layer away from the first redistribution layer;

[0017] The step of forming a second encapsulation layer on the third surface comprises:

[0018] forming a third redistribution layer on the third surface of the second substrate structure;

[0019] Disposing a plurality of second conductive pillars on a side of the third redistribution layer away from the second substrate structure;

[0020] Plastic-sealing the second conductive pillar to form a second plastic-sealing layer;

[0021] A fourth redistribution layer is formed on a side of the second plastic packaging layer away from the third redistribution layer.

[0022] In a possible implementation, the step of forming a second redistribution layer on a side of the first plastic encapsulation layer away from the first redistribution layer includes:

[0023] forming a second redistribution layer on a side of the first plastic packaging layer away from the first redistribution layer by a photolithography process, and retaining photoresist on a surface of the second redistribution layer;

[0024] The step of forming a fourth redistribution layer on a side of the second plastic encapsulation layer away from the third redistribution layer comprises:

[0025] forming a fourth redistribution layer on a side of the second plastic packaging layer away from the third redistribution layer by a photolithography process, and retaining photoresist on the surface of the fourth redistribution layer;

[0026] After the step of debonding the first encapsulation layer and the second encapsulation layer, the method further includes:

[0027] The photoresist on the surface of the second redistribution layer and / or the fourth redistribution layer is removed.

[0028] In a possible implementation, the step of providing a first substrate structure includes:

[0029] providing a first substrate;

[0030] Forming a plurality of first through holes penetrating the first substrate and a first wiring layer located on at least a portion of the surface of the first substrate via the first through holes on the first substrate, thereby obtaining the first substrate structure;

[0031] The step of forming a first encapsulation layer on the first surface comprises:

[0032] forming a first packaging layer electrically connected to the first wiring layer on the first surface;

[0033] The step of providing a second substrate structure comprises:

[0034] providing a second substrate;

[0035] Forming a plurality of second through holes penetrating the second substrate and a second wiring layer located on at least a portion of the surface of the second substrate via the second through holes on the second substrate, thereby obtaining the second substrate structure;

[0036] The step of forming a second encapsulation layer on the second surface comprises:

[0037] A second packaging layer electrically connected to the second wiring layer is formed on the second surface.

[0038] In a possible implementation manner, after the step of debonding the first encapsulation layer and the second encapsulation layer, the method further includes:

[0039] Disposing a first chip on a side of the first packaging layer away from the first substrate structure;

[0040] And / or, a second chip is arranged on a side of the second packaging layer away from the second substrate structure.

[0041] In a possible implementation manner, after the step of disposing a first chip on a side of the first packaging layer away from the first substrate structure, the method further includes:

[0042] Plastic-sealing the first chip to form a third plastic-sealing layer;

[0043] After the step of arranging a second chip on a side of the second packaging layer away from the second substrate structure, the method further includes:

[0044] The fourth chip is plastic-sealed to form a fourth plastic-sealing layer.

[0045] In a possible implementation manner, after the step of forming a first accumulation layer on the second surface of the first substrate structure, the method further includes:

[0046] forming a first solder resist layer on a side of the first buildup layer away from the first substrate structure;

[0047] After the step of forming a second buildup layer on the fourth surface of the second substrate structure, the method further includes:

[0048] A second solder resist layer is formed on a side of the second buildup layer away from the second substrate structure.

[0049] In a possible implementation manner, after the step of debonding the first encapsulation layer and the second encapsulation layer, the method further includes:

[0050] Removing the third carrier board, and providing a first external pin on a side of the first solder resist layer away from the first substrate structure;

[0051] And / or, the fourth carrier board is removed, and a second external pin is arranged on a side of the second solder resist layer away from the second substrate structure.

[0052] In a second aspect, an embodiment of the present application further provides a packaging structure, which is manufactured using the manufacturing method of the packaging structure described in any of the above aspects.

[0053] In a third aspect, an embodiment of the present application further provides an electronic device, wherein the electronic device includes the packaging structure described in any of the above aspects.

[0054] Based on any one of the above aspects, the manufacturing method of the packaging structure, the packaging structure and the electronic device provided in the embodiments of the present application can simultaneously manufacture the first stacking layer and the second stacking layer by bonding the first packaging layer and the second packaging layer. In this way, the first packaging structure and the second packaging structure can be obtained, which improves the processing efficiency and solves the warping problem caused by the asymmetric structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0056] Figure 1 A schematic diagram of a process for manufacturing a packaging structure provided in this embodiment;

[0057] Figure 2 A schematic diagram of the structure of the first substrate structure and the second substrate structure provided in this embodiment;

[0058] Figure 3 A schematic diagram of the bonding structure of the first substrate structure and the second substrate structure provided in this embodiment;

[0059] Figure 4 This is a schematic diagram of a process of manufacturing a packaging structure provided in this embodiment;

[0060] Figure 5 A second process diagram of the method for manufacturing the packaging structure provided in this embodiment;

[0061] Figure 6 One of the sub-step schematic diagrams of step S110 provided in this embodiment;

[0062] Figure 7 A schematic diagram of the manufacturing process of the first encapsulation layer and the second encapsulation layer provided in this embodiment;

[0063] Figure 8 One of the structural schematic diagrams of the packaging structure provided in this embodiment;

[0064] Fig. 9 The second structural schematic diagram of the packaging structure provided in this embodiment;

[0065] Fig.10 One of the sub-step schematic diagrams of step S120 provided in this embodiment;

[0066] Fig.11 The second schematic diagram of sub-steps of step S110 provided in this embodiment;

[0067] Fig.12 A schematic diagram of the manufacturing process of the first substrate structure and the second substrate structure provided in this embodiment;

[0068] Fig.13 The second sub-step schematic diagram of step S120 provided in this embodiment;

[0069] Fig.14 The third structural diagram of the packaging structure provided in this embodiment;

[0070] Fig.15 This is the fourth structural schematic diagram of the packaging structure provided in this embodiment.

[0071] Icons: 110-first substrate structure; 111-first surface; 112-second surface; 113-first substrate; 114-first wiring layer; 120-second substrate structure; 121-third surface; 122-fourth surface; 123-second substrate; 124-second wiring layer; 210-first packaging layer; 211-first redistribution layer; 212-second redistribution layer; 220-second packaging layer; 221-third redistribution layer; 222-fourth redistribution layer; 310-first carrier; 320-second carrier Board; 330-third carrier board; 340-fourth carrier board; 410-first stacking layer; 420-second stacking layer; 510-first conductive column; 520-second conductive column; 610-first plastic encapsulation layer; 620-second plastic encapsulation layer; 630-third plastic encapsulation layer; 640-fourth plastic encapsulation layer; 710-first chip; 720-second chip; 810-first filling layer; 820-second filling layer; 910-first solder resist layer; 920-second solder resist layer; 930-first external pin; 940-second external pin. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0073] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0074] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0075] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0076] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0077] This embodiment provides a solution that can solve the above-mentioned problem. The specific implementation methods of this application are described in detail below in conjunction with the accompanying drawings.

[0078] Please refer to Figure 1 , Figure 1 The flowchart of the method for manufacturing the packaging structure provided in this embodiment is illustrated. The method may include the following steps.

[0079] In step S110 , a first substrate structure 110 is provided. The first substrate structure 110 includes a first surface 111 and a second surface 112 that are oppositely disposed. A first packaging layer 210 is formed on the first surface 111 , and a first carrier 310 is disposed on the second surface 112 .

[0080] In this embodiment, please refer to Figure 2 The first substrate structure 110 may include a first surface 111 and a second surface 112 that are oppositely arranged. In a direction perpendicular to the first substrate structure 110 , the first packaging layer 210 may be located on the first surface 111 of the first substrate structure 110 , and the first carrier 310 may be located on the second surface 112 of the first substrate structure 110 .

[0081] Specifically, the first encapsulation layer 210 may completely cover the first surface 111 of the first substrate structure 110, and the first encapsulation layer 210 may include a plurality of stacked redistribution layers. The first carrier 310 may be a glass carrier.

[0082] Step S120 , providing a second substrate structure 120 , wherein the second substrate structure 120 comprises a third surface 121 and a fourth surface 122 oppositely disposed, a second packaging layer 220 is formed on the third surface 121 , and a second carrier 320 is disposed on the fourth surface 122 .

[0083] In this embodiment, please refer to Figure 2 The second substrate structure 120 may include a third surface 121 and a fourth surface 122 that are arranged opposite to each other. In a direction perpendicular to the second substrate structure 120, the second packaging layer 220 may be located on the third surface 121 of the second substrate structure 120, and the second carrier 320 may be located on the fourth surface 122 of the second substrate structure 120.

[0084] Specifically, the second substrate structure 120 is the same as the first substrate structure 110, the second encapsulation layer 220 may completely cover the third surface 121 of the second substrate structure 120, and the second encapsulation layer 220 may include a plurality of stacked redistribution layers. The second carrier 320 may be a glass carrier.

[0085] Step S130 , bonding the first encapsulation layer 210 and the second encapsulation layer 220 .

[0086] In this embodiment, please refer to Figure 3 , a bonding adhesive may be coated on a side of the first encapsulation layer 210 away from the first substrate structure 110 and / or a side of the second encapsulation layer 220 away from the second substrate structure 120, and the first encapsulation layer 210 and the second encapsulation layer 220 may be bonded by the bonding adhesive. Exemplarily, the bonding adhesive may be a high temperature resistant debonding material or a laser debonding material.

[0087] Step S140 , removing the first carrier 310 and the second carrier 320 , forming a first accumulation layer 410 on the second surface 112 of the first substrate structure 110 , and forming a second accumulation layer 420 on the fourth surface 122 of the second substrate structure 120 .

[0088] In this embodiment, please refer to Figure 4 , the first carrier 310 and the second carrier 320 may be removed first, and then the first stacking layer 410 and the second stacking layer 420 may be formed. The first stacking layer 410 and the second stacking layer 420 are symmetrically arranged, the first stacking layer 410 is located on the second surface 112 of the first substrate structure 110, and the second stacking layer 420 is located on the fourth surface 122 of the second substrate structure 120. The orthographic projection of the first stacking layer 410 on the first substrate structure 110 may completely overlap with the orthographic projection of the first encapsulation layer 210 on the first substrate structure 110, and the orthographic projection of the second stacking layer 420 on the second substrate structure 120 may completely overlap with the orthographic projection of the second encapsulation layer 220 on the second substrate structure 120. The material of the first stacking layer 410 and the second stacking layer 420 may include an insulating material, and exemplarily, the insulating material may be an Ajinomoto Build-up Film (ABF).

[0089] In step S150 , a third carrier plate 330 is disposed on a side of the first stacking layer 410 away from the first substrate structure 110 , and a fourth carrier plate 340 is disposed on a side of the second stacking layer 420 away from the second substrate structure 120 .

[0090] In this embodiment, please refer to Figure 5, a third carrier plate 330 may be disposed on a side of the first stacking layer 410 away from the first substrate structure 110, and a fourth carrier plate 340 may be disposed on a side of the second stacking layer 420 away from the second substrate structure 120, the orthographic projection of the third carrier plate 330 on the first substrate structure 110 may completely overlap with the orthographic projection of the first stacking layer 410 on the first substrate structure 110, and the orthographic projection of the fourth carrier plate 340 on the second substrate structure 120 may completely overlap with the orthographic projection of the second stacking layer 420 on the second substrate structure 120. The third carrier plate 330 and the fourth carrier plate 340 may be identical glass carrier plates.

[0091] Step S160 , debonding the first encapsulation layer 210 and the second encapsulation layer 220 to obtain a first encapsulation structure and a second encapsulation structure.

[0092] In this embodiment, please refer to Figure 5 , the first encapsulation layer 210 and the second encapsulation layer 220 can be debonded by heating or laser, thereby obtaining a completely identical first encapsulation structure and a second encapsulation structure.

[0093] In some examples, if the first packaging layer 210 and the second packaging layer 220 are connected by a high-temperature resistant debonding material, the bonding position of the first packaging layer 210 and the second packaging layer 220 can be heated to soften the high-temperature resistant debonding material, thereby achieving debonding of the first packaging layer 210 and the second packaging layer 220.

[0094] It should be noted that the method of debonding the first encapsulation layer 210 and the second encapsulation layer 220 is not limited to heating and laser. The first encapsulation layer 210 and the second encapsulation layer 220 can also be debonded by other methods, such as mechanical debonding, chemical debonding, etc. The specific debonding method can be selected according to the material of the bonding glue and the actual bonding method, and is not specifically limited here.

[0095] In the above design, by bonding the first encapsulation layer 210 and the second encapsulation layer 220, the first stacking layer 410 and the second stacking layer 420 can be manufactured simultaneously, so that the first encapsulation structure and the second encapsulation structure can be obtained, which improves the processing efficiency and solves the warping problem caused by the asymmetric structure.

[0096] In a possible implementation, the first encapsulation layer 210 may include a first redistribution layer 211 and a second redistribution layer 212 that are stacked, and the orthographic projection of the first redistribution layer 211 on the first substrate structure 110 may completely overlap with the orthographic projection of the second redistribution layer 212 on the first substrate structure 110. The second encapsulation layer 220 may include a third redistribution layer 221 and a fourth redistribution layer 222 that are stacked, and the orthographic projection of the third redistribution layer 221 on the second substrate structure 120 may completely overlap with the orthographic projection of the fourth redistribution layer 222 on the second substrate structure 120.

[0097] When forming the first encapsulation layer 210 on the first surface 111, please refer to Figure 6 , step S110 may include the following sub-steps.

[0098] Step S111 , forming a first redistribution layer 211 on the first surface 111 of the first substrate structure 110 .

[0099] In this embodiment, please refer to Figure 7 , a first redistribution layer 211 that completely covers the first surface 111 may be formed on the first surface 111 of the first substrate structure 110 .

[0100] Step S112 , disposing a plurality of first conductive pillars 510 on a side of the first redistribution layer 211 away from the first substrate structure 110 .

[0101] In this embodiment, please refer to Figure 7 A plurality of first conductive pillars 510 may be disposed at intervals on a side of the first redistribution layer 211 away from the first substrate structure 110 , and the plurality of first conductive pillars 510 may be electrically connected to the first redistribution layer 211 , respectively.

[0102] Preferably, the first conductive pillar 510 may be a copper pillar.

[0103] It should be noted that the number of the first conductive pillars 510 can be determined according to actual needs and is not specifically limited here.

[0104] Step S113 , plastic-sealing the first conductive pillar 510 to form a first plastic-sealing layer 610 .

[0105] In this embodiment, please refer to Figure 7 , the plurality of first conductive pillars 510 may be plastic-encapsulated to form a first plastic-encapsulation layer 610, and the first plastic-encapsulation layer 610 may fill the gaps between the plurality of first conductive pillars 510 and completely cover the first redistribution layer 211. After the first plastic-encapsulation layer 610 is formed, the first plastic-encapsulation layer 610 may be ground until the surface of the first conductive pillar 510 is exposed, so that the surface of the first plastic-encapsulation layer 610 is flush with the surface of the first conductive pillar 510.

[0106] The material of the first plastic encapsulation layer 610 can be an insulating material, for example, it can include epoxy molding compound (Epoxy Molding Compound, EMC). Epoxy molding compound (Epoxy Molding Compound, EMC) is a powdered molding compound composed of epoxy resin as a base resin, high-performance phenolic resin as a curing agent, silicon micropowder as a filler, and a variety of additives. Epoxy molding compound (Epoxy Molding Compound, EMC) is easy to shape and has a hard texture. It can effectively prevent external water and oxygen from contacting the first redistribution layer 211 and the first conductive column 510, and can also improve the reliability of the packaging structure.

[0107] Step S114 , forming a second redistribution layer 212 on a side of the first plastic packaging layer 610 away from the first redistribution layer 211 .

[0108] In this embodiment, please refer to Figure 7 After grinding the first plastic encapsulation layer 610 , a second redistribution layer 212 may be formed on a side of the first plastic encapsulation layer 610 away from the first redistribution layer 211 , and the second redistribution layer 212 and the first redistribution layer 211 may be electrically connected through the first conductive pillar 510 .

[0109] For some examples, see Figure 8 The number of the first redistribution layer 211 may be one, the number of the second redistribution layers 212 may be three, and the three second redistribution layers 212 are stacked.

[0110] It should be noted that the number of the first redistribution layer 211 and the second redistribution layer 212 can be set according to actual needs and is not specifically limited here.

[0111] In another possible implementation, please refer to Fig. 9 After the first redistribution layer 211 is formed on the first surface 111 of the first substrate structure 110, the first substrate structure 110 and the first redistribution layer 211 may be cut, and then the first conductive pillar 510 may be plastic-sealed to prevent warping during processing.

[0112] When forming the second encapsulation layer 220 on the third surface 121, please refer to Fig.10 , step S120 may include the following sub-steps.

[0113] Step S121 , forming a third redistribution layer 221 on the third surface 121 of the second substrate structure 120 .

[0114] In this embodiment, please refer to Figure 7, a third redistribution layer 221 that completely covers the third surface 121 may be formed on the third surface 121 of the second substrate structure 120 .

[0115] In step S122 , a plurality of second conductive pillars 520 are disposed on a side of the third redistribution layer 221 away from the second substrate structure 120 .

[0116] In this embodiment, please refer to Figure 7 A plurality of second conductive pillars 520 may be disposed at intervals on a side of the third redistribution layer 221 away from the second substrate structure 120 , and the plurality of second conductive pillars 520 may be electrically connected to the third redistribution layer 221 , respectively.

[0117] Preferably, the second conductive pillar 520 may be a copper pillar.

[0118] It should be noted that the number of the second conductive pillars 520 can be determined according to actual needs and is not specifically limited here.

[0119] Step S123 , plastic-sealing the second conductive pillar 520 to form a second plastic-sealing layer 620 .

[0120] In this embodiment, please refer to Figure 7 , the plurality of second conductive pillars 520 may be plastic-encapsulated to form a second plastic-encapsulation layer 620, which may fill the gaps between the plurality of second conductive pillars 520 and completely cover the third redistribution layer 221. After the second plastic-encapsulation layer 620 is formed, the second plastic-encapsulation layer 620 may be ground until the surface of the second conductive pillars 520 is exposed, so that the surface of the second plastic-encapsulation layer 620 is flush with the surface of the second conductive pillars 520.

[0121] The material of the second plastic encapsulation layer 620 can be the same as that of the first plastic encapsulation layer 610, both of which are insulating materials, for example, can include epoxy molding compound (EMC). The second plastic encapsulation layer 620 can effectively prevent external water and oxygen from contacting the third redistribution layer 221 and the second conductive column 520, and can also improve the reliability of the packaging structure.

[0122] Step S124 , forming a fourth redistribution layer 222 on a side of the second plastic encapsulation layer 620 away from the third redistribution layer 221 .

[0123] In this embodiment, please refer to Figure 7 After grinding the second plastic encapsulation layer 620 , a fourth redistribution layer 222 may be formed on a side of the second plastic encapsulation layer 620 away from the third redistribution layer 221 , and the fourth redistribution layer 222 and the third redistribution layer 221 may be electrically connected through the second conductive pillar 520 .

[0124] In some examples, please refer again to Figure 8 The number of the third redistribution layer 221 may be one, the number of the fourth redistribution layers 222 may be three, and the three fourth redistribution layers 222 are stacked.

[0125] It should be noted that the number of the third redistribution layer 221 and the fourth redistribution layer 222 can be set according to actual needs and is not specifically limited here.

[0126] In another possible implementation, please refer again to Fig. 9 After forming the third redistribution layer 221 on the third surface 121 of the second substrate structure 120, the second substrate structure 120 and the third redistribution layer 221 may be cut, and then the second conductive pillar 520 may be plastic-sealed to prevent warping during processing.

[0127] In one possible implementation, in step S114, when the second redistribution layer 212 is formed on the side of the first plastic encapsulation layer 610 away from the first redistribution layer 211, the second redistribution layer 212 can be formed on the side of the first plastic encapsulation layer 610 away from the first redistribution layer 211 by a photolithography process, and the photoresist on the surface of the second redistribution layer 212 is retained.

[0128] In this embodiment, after the second redistribution layer 212 is formed by the photolithography process, the photoresist on the side of the second redistribution layer 212 away from the first plastic encapsulation layer 610 may be retained. When there are multiple second redistribution layers 212, the photoresist between the multiple second redistribution layers 212 may be removed, and only the photoresist on the side of the multiple second redistribution layers 212 farthest from the first plastic encapsulation layer 610 may be retained.

[0129] In step S124, when the fourth redistribution layer 222 is formed on the side of the second plastic encapsulation layer 620 away from the third redistribution layer 221, the fourth redistribution layer 222 can be formed on the side of the second plastic encapsulation layer 620 away from the third redistribution layer 221 by a photolithography process, and the photoresist on the surface of the fourth redistribution layer 222 is retained.

[0130] In this embodiment, after the fourth redistribution layer 222 is formed by the photolithography process, the photoresist on the side of the fourth redistribution layer 222 away from the second plastic encapsulation layer 620 may be retained. When there are multiple fourth redistribution layers 222, the photoresist between the multiple fourth redistribution layers 222 may be removed, and only the photoresist on the side of the multiple fourth redistribution layers 222 farthest from the second plastic encapsulation layer 620 may be retained.

[0131] After the first encapsulation layer 210 and the second encapsulation layer 220 are debonded, the photoresist on the surface of the second redistribution layer 212 and / or the fourth redistribution layer 222 may be removed.

[0132] In this embodiment, the photoresist on the surface of the second redistribution layer 212 and / or the fourth redistribution layer 222 can be removed after the first encapsulation layer 210 and the second encapsulation layer 220 are debonded. In this way, the second redistribution layer 212 and the fourth redistribution layer 222 can be protected to avoid damage to the second redistribution layer 212 and the fourth redistribution layer 222 during the encapsulation process.

[0133] In one possible implementation, see Fig.11 , step S110 may further include the following sub-steps.

[0134] Step S115 , providing a first substrate 113 .

[0135] Step S116 , forming a plurality of first through holes penetrating the first substrate 113 and a first wiring layer 114 located on at least a portion of the surface of the first substrate 113 via the first through holes, thereby obtaining the first substrate structure 110 .

[0136] In this embodiment, please refer to Fig.12 , a plurality of first through holes can be formed on the first substrate 113 by laser drilling, and a first routing layer 114 that at least partially covers the first substrate 113 is formed on the surface of the plurality of first through holes and the first substrate 113. Specifically, the first routing layer 114 may include a seed layer and a metal layer, the seed layer is located on the inner wall of the first through hole and at least a portion of the surface of the first substrate 113, and the metal layer is located on a side of the seed layer away from the first through hole. In addition, the first substrate structure 110 may further include a filling layer, the filling layer may be located in the first through hole and on the surface of the first substrate 113, wherein the filling layer at least partially exposes the first routing layer 114. Exemplarily, the material of the filling layer includes but is not limited to Ajinomoto Build-up Film (ABF). The first substrate 113 may be a glass substrate.

[0137] In step S110 , when the first packaging layer 210 is formed on the first surface 111 , the first packaging layer 210 electrically connected to the first wiring layer 114 may be formed on the first surface 111 .

[0138] Please refer to Fig.13 , step S120 may further include the following sub-steps.

[0139] Step S125 , providing a second substrate 123 .

[0140] Step S126 , forming a plurality of second through holes penetrating the second substrate 123 and a second wiring layer 124 located on at least a portion of the surface of the second substrate 123 via the second through holes, thereby obtaining the second substrate structure 120 .

[0141] In this embodiment, please refer to Fig.12 , a plurality of second through holes can be formed on the second substrate 123 by laser drilling, and a second routing layer 124 at least partially covering the second substrate 123 is formed on the surface of the plurality of second through holes and the second substrate 123. Specifically, the second routing layer 124 may include a seed layer and a metal layer, the seed layer is located on the inner wall of the second through hole and at least a portion of the surface of the second substrate 123, and the metal layer is located on the side of the seed layer away from the second through hole. In addition, the second substrate structure 120 may also include a filling layer, the filling layer may be located in the second through hole and on the surface of the second substrate 123, wherein the filling layer at least partially exposes the second routing layer 124. Exemplarily, the material of the filling layer includes but is not limited to Ajinomoto Build-up Film (ABF). The second substrate 123 may be a glass substrate.

[0142] In step S120 , when forming the second packaging layer 220 on the second surface 112 , the second packaging layer 220 electrically connected to the second wiring layer 124 may be formed on the second surface 112 .

[0143] In one possible implementation, see Fig.13 After the first encapsulation layer 210 and the second encapsulation layer 220 are debonded, a first chip 710 may be disposed on a side of the first encapsulation layer 210 away from the first substrate structure 110 .

[0144] In this embodiment, multiple first chips 710 can be arranged on the side of the first packaging layer 210 away from the first substrate structure 110, and the multiple first chips 710 are arranged in the same layer. A connecting pin is arranged on the side of the first chip 710 close to the first packaging layer 210, and the first chip 710 can be electrically connected to the first packaging layer 210 through the connecting pin.

[0145] The multiple first chips 710 may be chips of the same structure or chips of different structures. For example, the multiple first chips 710 may be high bandwidth memory (HBM) chips, application specific integrated circuit (ASIC) chips, system on chip (SoC), etc., and the multiple first chips 710 may all be system chips.

[0146] After setting the first chip 710, a first filling layer 810 may also be set between the first chip 710 and the first packaging layer 210. The first filling layer 810 may be used to fill the gap between the first chip 710 and the first packaging layer 210. In this way, the bonding strength between the first chip 710 and the first packaging layer 210 may be increased, the first chip 710 and the first packaging layer 210 may be protected, and the reliability of the packaging structure may be improved.

[0147] In addition, please refer again Fig.13 After the first encapsulation layer 210 and the second encapsulation layer 220 are debonded, the second chip 720 may also be disposed on a side of the second encapsulation layer 220 away from the second substrate structure 120 .

[0148] In this embodiment, multiple second chips 720 can be arranged on the side of the second packaging layer 220 away from the second substrate structure 120. The multiple second chips 720 are arranged in the same layer. Connecting pins are arranged on the side of the second chip 720 close to the second packaging layer 220. The second chip 720 can be electrically connected to the second packaging layer 220 through the connecting pins.

[0149] The plurality of second chips 720 may be chips of the same structure or chips of different structures. For example, the plurality of second chips 720 may be high bandwidth memory (HBM) chips, application specific integrated circuit (ASIC) chips, system on chip (SoC), etc., and the plurality of second chips 720 may also all be system chips.

[0150] After setting the second chip 720, a second filling layer 820 may also be set between the second chip 720 and the second packaging layer 220. The second filling layer 820 may be used to fill the gap between the second chip 720 and the second packaging layer 220. In this way, the bonding strength between the second chip 720 and the second packaging layer 220 may be increased, the second chip 720 and the second packaging layer 220 may be protected, and the reliability of the packaging structure may be improved.

[0151] In one possible implementation, see Fig.14After the first chip 710 is arranged on a side of the first encapsulation layer 210 away from the first substrate structure 110, the first chip 710 may be plastic-encapsulated to form a third plastic-encapsulation layer 630 that completely covers the first chip 710. The orthographic projection of the third plastic-encapsulation layer 630 on the first encapsulation layer 210 may completely cover the orthographic projection of the first chip 710 on the first encapsulation layer 210. The material of the third plastic-encapsulation layer 630 may be an insulating material, for example, may include epoxy molding compound (EMC).

[0152] After the second chip 720 is arranged on a side of the second encapsulation layer 220 away from the second substrate structure 120, the fourth chip may be further encapsulated to form a fourth encapsulation layer 640 that completely covers the second chip 720, and the orthographic projection of the fourth encapsulation layer 640 on the second encapsulation layer 220 may completely cover the orthographic projection of the second chip 720 on the second encapsulation layer 220. The material of the fourth encapsulation layer 640 may be an insulating material, for example, may include epoxy molding compound (EMC).

[0153] In a possible implementation, after the first stacking layer 410 is formed on the second surface 112 of the first substrate structure 110 , a first solder resist layer 910 may be formed on a side of the first stacking layer 410 away from the first substrate structure 110 . The first solder resist layer 910 may be used to protect the first stacking layer 410 .

[0154] After the second buildup layer 420 is formed on the fourth surface 122 of the second substrate structure 120 , a second solder resist layer 920 may be formed on a side of the second buildup layer 420 away from the second substrate structure 120 . The second solder resist layer 920 may be used to protect the second buildup layer 420 .

[0155] Exemplarily, the materials of the first solder resist layer 910 and the second solder resist layer 920 may both be green paint.

[0156] In one possible implementation, see Fig.15 After the first packaging layer 210 and the second packaging layer 220 are debonded, the third carrier 330 may be removed, and a first external pin 930 may be arranged on a side of the first solder resist layer 910 away from the first substrate structure 110 .

[0157] In this embodiment, one end of the first external pin 930 may be electrically connected to the first stacking layer 410 , and the other end of the first external pin 930 may be connected to other components, which helps the package structure to be further electrically connected to other components.

[0158] In some examples, the first external pin 930 can be a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, or a micro bump.

[0159] In addition, after the first packaging layer 210 and the second packaging layer 220 are debonded, the fourth carrier 340 may be removed, and a second external pin 940 may be disposed on a side of the second solder resist layer 920 away from the second substrate structure 120 .

[0160] In this embodiment, one end of the second external pin 940 may be electrically connected to the second stacking layer 420 , and the other end of the second external pin 940 may be connected to other components, which helps the package structure to be further electrically connected to other components.

[0161] In some examples, the second external pin 940 can be a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, or a micro bump.

[0162] An embodiment of the present application also provides a packaging structure, which can be manufactured using the manufacturing method of the packaging structure provided in this embodiment.

[0163] An embodiment of the present application also provides an electronic device, which may include the packaging structure provided by this embodiment.

[0164] In summary, the present embodiment provides a method for manufacturing a packaging structure, a packaging structure and an electronic device. By bonding the first packaging layer and the second packaging layer, the first stacking layer and the second stacking layer can be simultaneously manufactured. In this way, the first packaging structure and the second packaging structure can be obtained, which improves the processing efficiency and solves the warping problem caused by the asymmetric structure.

[0165] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0166] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for manufacturing a packaging structure, characterized in that: The method comprises: Providing a first substrate structure, the first substrate structure comprising a first surface and a second surface arranged opposite to each other, forming a first packaging layer on the first surface, and disposing a first carrier on the second surface; Providing a second substrate structure, the second substrate structure comprising a third surface and a fourth surface arranged opposite to each other, a second packaging layer is formed on the third surface, and a second carrier is arranged on the fourth surface; bonding the first encapsulation layer to the second encapsulation layer; removing the first carrier plate and the second carrier plate, forming a first accumulation layer on the second surface of the first substrate structure, and forming a second accumulation layer on the fourth surface of the second substrate structure; Disposing a third carrier plate on a side of the first stacking layer away from the first substrate structure, and disposing a fourth carrier plate on a side of the second stacking layer away from the second substrate structure; The first encapsulation layer and the second encapsulation layer are debonded to obtain a first encapsulation structure and a second encapsulation structure.

2. The method for manufacturing a packaging structure according to claim 1, characterized in that: The first packaging layer includes a first redistribution layer and a second redistribution layer; the second packaging layer includes a third redistribution layer and a fourth redistribution layer; The step of forming a first encapsulation layer on the first surface includes: forming a first redistribution layer on the first surface of the first substrate structure; Disposing a plurality of first conductive pillars on a side of the first redistribution layer away from the first substrate structure; Plastic-sealing the first conductive column to form a first plastic-sealing layer; forming a second redistribution layer on a side of the first plastic packaging layer away from the first redistribution layer; The step of forming a second encapsulation layer on the third surface comprises: forming a third redistribution layer on the third surface of the second substrate structure; Disposing a plurality of second conductive pillars on a side of the third redistribution layer away from the second substrate structure; Plastic-sealing the second conductive pillar to form a second plastic-sealing layer; A fourth redistribution layer is formed on a side of the second plastic packaging layer away from the third redistribution layer.

3. The method for manufacturing a packaging structure according to claim 2, characterized in that: The step of forming a second redistribution layer on a side of the first plastic encapsulation layer away from the first redistribution layer comprises: forming a second redistribution layer on a side of the first plastic packaging layer away from the first redistribution layer by a photolithography process, and retaining photoresist on a surface of the second redistribution layer; The step of forming a fourth redistribution layer on a side of the second plastic encapsulation layer away from the third redistribution layer comprises: forming a fourth redistribution layer on a side of the second plastic packaging layer away from the third redistribution layer by a photolithography process, and retaining photoresist on the surface of the fourth redistribution layer; After the step of debonding the first encapsulation layer and the second encapsulation layer, the method further includes: The photoresist on the surface of the second redistribution layer and / or the fourth redistribution layer is removed.

4. The method for manufacturing a packaging structure according to claim 1, characterized in that: The step of providing a first substrate structure comprises: providing a first substrate; Forming a plurality of first through holes penetrating the first substrate and a first wiring layer located on at least a portion of the surface of the first substrate via the first through holes on the first substrate, thereby obtaining the first substrate structure; The step of forming a first encapsulation layer on the first surface comprises: forming a first packaging layer electrically connected to the first wiring layer on the first surface; The step of providing a second substrate structure comprises: providing a second substrate; Forming a plurality of second through holes penetrating the second substrate and a second wiring layer located on at least a portion of the surface of the second substrate via the second through holes on the second substrate, thereby obtaining the second substrate structure; The step of forming a second encapsulation layer on the second surface comprises: A second packaging layer electrically connected to the second wiring layer is formed on the second surface.

5. The method for manufacturing a packaging structure according to claim 1, characterized in that: After the step of debonding the first encapsulation layer and the second encapsulation layer, the method further includes: Disposing a first chip on a side of the first packaging layer away from the first substrate structure; And / or, a second chip is arranged on a side of the second packaging layer away from the second substrate structure.

6. The method for manufacturing a packaging structure according to claim 5, characterized in that: After the step of disposing a first chip on a side of the first packaging layer away from the first substrate structure, the method further includes: Plastic-sealing the first chip to form a third plastic-sealing layer; After the step of arranging a second chip on a side of the second packaging layer away from the second substrate structure, the method further includes: The fourth chip is plastic-sealed to form a fourth plastic-sealing layer.

7. The method for manufacturing a packaging structure according to claim 1, characterized in that: After the step of forming a first accumulation layer on the second surface of the first substrate structure, the method further comprises: forming a first solder resist layer on a side of the first buildup layer away from the first substrate structure; After the step of forming a second buildup layer on the fourth surface of the second substrate structure, the method further includes: A second solder resist layer is formed on a side of the second buildup layer away from the second substrate structure.

8. The method for manufacturing a packaging structure according to claim 7, characterized in that: After the step of debonding the first encapsulation layer and the second encapsulation layer, the method further includes: Removing the third carrier board, and providing a first external pin on a side of the first solder resist layer away from the first substrate structure; And / or, the fourth carrier board is removed, and a second external pin is arranged on a side of the second solder resist layer away from the second substrate structure.

9. A packaging structure, characterized in that: The packaging structure is manufactured using the packaging structure manufacturing method described in any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises the packaging structure according to claim 9.

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