Chip with latch protection function
By designing a latch protection circuit in the chip, detecting and clamping the voltage of the test port, the problem of chip damage caused by voltage drop in the latch test is solved, and the chip is effectively protected and tested.
Patent Information
- Application Number
- CN202411442777.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-03-07
AI Technical Summary
During the latch test of the chip, the chip may be damaged and cannot pass the latch test because the parasitic diode of the LDO-powered MOS tube is turned on.
A chip with latch protection function is designed, including a latch protection circuit, which is used to detect the voltage of the test port and short the test port to the ground port when the voltage drops to the preset voltage, thereby clamping the voltage of the test port to prevent it from dropping below -0.7V.
Effectively prevents damage caused by voltage drop in the chip during latch test, ensuring that the chip can pass the test without damage.
Smart Images
Figure CN119582120A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chip with a latch protection function. Background Art
[0002] When some important ports inside the chip face latch-up testing, due to the limitations of its own process and device structure, parasitic currents will be generated in the surrounding heat sinks, which may cause latch-up risks and lead to chip damage.
[0003] Figure 1 FIG. 1 shows a schematic diagram of a chip integrated with an LDO according to the prior art. Figure 1 , a low dropout linear regulator (Low Dropout Regulator, LDO) is integrated inside the chip 100, and the test port (pin) BP5 of the chip 100 is connected to the output terminal OUT of the LDO. Before the mass production of the chip 100, the test port BP5 of the chip 100 needs to be subjected to electrostatic discharge (ESD) and latch-up tests. However, because the N-type buried layer (NBL) of the MOS tube powered by the LDO inside the chip 100 is usually connected to the output terminal OUT of the LDO during design, when the external test equipment performs a negative current extraction test on the test port BP5 in the latch test, because the current that the LDO can provide is limited and cannot effectively compensate for this negative current, the voltage of the test port BP5 may drop sharply, and may even drop below -0.7V, causing the parasitic diode of the MOS tube powered by the LDO inside the chip 100 to be turned on. Figure 1For example, when the voltage of the test port BP5 drops below -0.7V, its four parasitic diodes will be turned on, and the test port BP5 will draw current from the substrate (psub) of the chip 100, resulting in a minority carrier injection effect, which may damage the chip 100 and fail the latch test. Specifically, the principle of the minority carrier injection effect causing damage to the chip 100 includes: 1) Due to the process level and the structure of the transistor itself, the collector of the transistor is formed by the NBL layer, which is in direct contact with the substrate (psub). When the substrate undergoes a minority carrier injection effect, if it interferes with the transistor in the bandgap reference module in the LDO, it may cause the reference voltage to increase, and the voltages related to the reference power supply in the chip 100 will increase accordingly, especially if the voltage of the analog power supply of the chip 100 becomes higher, which may easily cause the MOS tube to break down. 2) Test port BP5 draws current from the substrate of chip 100. The isolation structure usually uses the reverse bias characteristic of the PN junction to block the flow of current. However, although the built-in electric field in the depletion region of the PN junction can effectively repel majority carriers, it will accelerate the movement of minority carriers. Therefore, when a sufficient number of minority carriers enter the isolation island, it may trigger a latch effect, causing positive feedback in the parasitic transistors inside chip 100, thereby damaging chip 100. 3) Test port BP5 draws current from the substrate of chip 100. This current will produce a voltage drop on the substrate resistance. If this voltage drop is large, it may cause the PN junction formed by the isolation island and the substrate, which was originally in a reverse bias state, to lose its reverse bias characteristic. At this time, the substrate injects charge into the isolation island, and leakage occurs on the isolation island, resulting in substrate de-biasing.
[0004] In view of the above problem, there are two ways to deal with it in the prior art. One is to choose not to perform a negative current extraction test on the test port BP5 of the chip 100, but only perform an overvoltage test, and prohibit drawing a large current from this port when in use. The other is to increase the NBL spacing, but this will increase the area of the chip 100 and increase the cost.
[0005] Therefore, in order to solve the above problems, a new chip needs to be proposed. Summary of the invention
[0006] In view of the above problems, an object of the present invention is to provide a chip with a latch protection function, so as to protect the chip from being damaged when a negative current is drawn from a test port.
[0007] According to one aspect of the present invention, there is provided a chip, comprising a power port and a ground port; a voltage converter connected between the power port and the ground port, the voltage converter being used to obtain a power supply voltage according to an input voltage of the power port; a functional circuit connected between an output end of the voltage converter and the ground port to receive the power supply voltage; a test port connected to the output end of the voltage converter; and a latch protection circuit for detecting the voltage of the test port and short-circuiting the test port with the ground port when the voltage of the test port drops to a preset voltage.
[0008] Optionally, the latch protection circuit includes a voltage detection unit, which is used to detect the voltage of the test port and generate a clamp control signal when the voltage of the test port drops to a preset voltage; and a clamp unit, which is connected between the test port and the ground port and turns on the conductive path between the test port and the ground port according to the clamp control signal.
[0009] Optionally, the voltage detection unit includes a first transistor, a first end of which receives a first bias current, a second end of which is connected to the test port, and a substrate of which is connected to the ground port; a second transistor, a first end of which receives a second bias current, a second end of which is connected to the ground port, a control end of which is connected to its first end and the control end of the first transistor, and a substrate of which is connected to the ground port, wherein the first end of the first transistor is also used to provide the clamping control signal, and the current value of the first bias current is equal to the current value of the second bias current.
[0010] Optionally, the voltage detection unit further includes a first resistor connected between the second end of the first transistor and the test port.
[0011] Optionally, the clamping unit includes an inverter, whose input end is connected to the first end of the first transistor; a third transistor, whose first end is connected to the test port, the second end is connected to the ground port, and the control end is connected to the output end of the inverter.
[0012] Optionally, the clamping unit further includes a second resistor connected between the output end of the inverter and the ground port.
[0013] Optionally, the chip further includes a pre-start module connected to the power port, for generating the pre-start voltage, the first bias current and the second bias current according to the input voltage, and the power supply terminal of the inverter is connected to the pre-start voltage.
[0014] Optionally, a size ratio of the first transistor to the second transistor is 1:K, where K is greater than 1.
[0015] Optionally, the chip further includes an ESD protection circuit connected between the test port and the ground port, and the preset voltage ranges from -200mV to -500mV.
[0016] Optionally, the voltage converter is a low voltage difference linear voltage regulator circuit, the functional circuit is an inverter, and after the power port is powered on, the pre-start module outputs the pre-start voltage, the first bias current and the second bias current to the bandgap reference module in the low voltage difference linear voltage regulator circuit to generate a reference voltage.
[0017] The chip with latch protection function provided by the present invention comprises a latch protection circuit connected to a test port, wherein the latch protection circuit is used to detect the voltage of the test port and short-circuit the test port with a ground port when the voltage of the test port drops to a preset voltage, so as to clamp the voltage of the test port and prevent it from dropping below -700mV to cause a latch effect in the chip, thereby achieving the purpose of protecting the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0019] Figure 1 A schematic diagram of the structure of a chip integrated with an LDO according to the prior art is shown;
[0020] Figure 2 A schematic structural diagram of a chip integrated with an LDO according to an embodiment of the present invention is shown;
[0021] Figure 3 Shows Figure 1 The simulation schematic diagram of the chip shown in the figure when performing a negative current extraction test;
[0022] Figure 4 Shows Figure 2 The chip shown is a simulation schematic diagram of a negative current extraction test. DETAILED DESCRIPTION
[0023] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.
[0024] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.
[0025] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.
[0026] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.
[0027] Figure 2 A schematic structural diagram of a chip integrated with an LDO according to an embodiment of the present invention is shown.
[0028] See also Figure 2 The chip 200 includes a power port VIN, a ground port GND, a test port BP5, a voltage converter 210, a functional circuit 220, an ESD protection circuit 230, and a latch protection circuit 240. The voltage converter 210 is connected between the power port VIN and the ground port GND. The voltage converter 210 is used to obtain a power supply voltage according to the input voltage of the power port VIN, and output it from its output terminal OUT. The functional circuit 220 is connected between the output terminal OUT of the voltage converter 210 and the ground port GND to receive the power supply voltage. The test port BP5 is connected to the output terminal OUT of the voltage converter 210. The functional circuit 220 has a MOS tube powered by the power supply voltage.
[0029] It is understandable that, although in the embodiment of the present invention, the voltage converter 210 takes a low dropout linear regulator (Low Dropout Regulator, LDO) as an example, and the functional circuit 220 takes an inverter as an example, in actual applications, the voltage converter 210 is not limited to LDO, and the functional circuit 220 is not limited to inverter.
[0030] The LDO is connected between the power port VIN and the ground port GND, and has an output terminal OUT. The output terminal OUT of the LDO is connected to the test port BP5 of the chip 200 .
[0031] The inverter includes transistors M1 and M2 connected in series between the output terminal OUT of the LDO and the ground port GND. The control terminal of the transistor M1 is connected to the control terminal of the transistor M2, and their common node serves as the input terminal of the inverter to receive the input signal IN. The second terminal of the transistor M1 is connected to the first terminal of the transistor M2, and their common node serves as the output terminal of the inverter to provide the output signal IN_b. The inverter has multiple parasitic diodes.
[0032] The ESD protection circuit 230 is connected between the test port BP5 and the ground port GND, and is used to implement electrostatic discharge protection for the chip 200 .
[0033] The latch protection circuit 240 is connected to the test port BP5, and is used to detect the voltage of the test port BP5, and short the test port BP5 with the ground port GND when the voltage of the test port BP5 drops to a preset voltage, so as to clamp the voltage of the test port BP5 so that it will not be pulled down to below -700mV, thereby ensuring that the chip 200 will not have a latch effect. Among them, the reason for the voltage of the test port BP5 to drop to the preset voltage includes extracting a negative current from the test port BP5 when performing a negative current extraction test. Among them, the preset voltage is less than zero, and the range of the preset voltage is, for example, -200mV to -500mV.
[0034] The latch protection circuit 240 includes a pre-start module 241 and a protection module 242. The pre-start module 241 is connected to the power port VIN, and is used to generate bias currents I1, I2 and a pre-start voltage Vpre according to the input voltage of the power port VIN, and the current values of the bias currents I1 and I2 are equal. Among them, when a pre-start module (Vpre) is provided inside the chip 200, the latch protection circuit 240 can reuse the original pre-start module in the chip 200, thereby saving chip area. In the prior art, the pre-start module is a power supply with a relatively low load capacity inside the chip 200. After the power port VIN is powered on, it will output the pre-start voltage Vpre and the bias currents I1, I2 to the bandgap reference module in the LDO to generate a reference voltage.
[0035] The protection module 242 includes a voltage detection unit 242a and a clamping unit 242b, and the voltage detection unit 242a and the clamping unit 242b are connected to the node A. After receiving the bias currents I1 and I2, the voltage detection unit 242a detects the voltage of the test port BP5, and generates a clamping control signal when the voltage of the test port BP5 drops to a preset voltage. The clamping unit 242b is connected between the test port BP5 and the ground port GND, and is used to conduct the conductive path between the test port BP5 and the ground port GND according to the clamping control signal, thereby clamping the voltage of the test port BP5.
[0036] The voltage detection unit 242a includes transistors Mn1 and Mn2, wherein the first end of transistor Mn1 receives bias current I1, the first end of transistor Mn2 receives bias current I2, the second end of transistor Mn1 is connected to test port BP5, the second end of transistor Mn2 is connected to ground port GND, the first end of transistor Mn2 is also connected to its control end and the control end of transistor Mn1, the first end of transistor Mn1 also provides the clamp control signal, and the substrates of transistors Mn1 and Mn2 are both connected to ground port GND. Wherein, transistor Mn1 is turned on when it is detected that the voltage of test port BP5 is reduced to a preset voltage, thereby pulling down the voltage of node A to obtain a clamp control signal. The size (width-to-length ratio) ratio of transistors Mn1 and Mn2 is 1:K (K>1), so the threshold voltage of transistor Mn1 is greater than the threshold voltage of transistor Mn2, and the voltage range of the preset voltage can be set by setting the value of K.
[0037] Furthermore, in order to protect the transistor Mn1 from electrostatic discharge (ESD), a resistor R1 may be disposed between the second end of the transistor Mn1 and the test port BP5. At this time, the voltage drop of the resistor R1 may also affect the voltage range of the preset voltage.
[0038] The clamp unit 242b includes an inverter inv and a transistor Mn3. The power supply end of the inverter inv is connected to the pre-start voltage Vpre and the ground port GND respectively, and the input end of the inverter inv is connected to the first end of the transistor Mn1. The transistor Mn3 is connected between the test port BP5 and the ground port GND, and the control end of the transistor Mn3 is connected to the output end of the inverter inv.
[0039] Furthermore, the clamping unit 242b further includes a resistor R2 connected between the output terminal of the inverter inv and the ground port GND. The resistor R2 and the transistor Mn3 form an ESD protection structure, which can also play a certain ESD protection role when the test port BP5 is not drawn with negative current.
[0040] Figure 3 Shows Figure 1 The chip shown is a simulation schematic diagram of a negative current extraction test.
[0041] See also Figure 3 In the absence of a latch protection circuit, when there is a 120mA pull current at the test port BP5 (i.e., a 120mA negative current is drawn from the test port BP5), the voltage of the test port BP5 is pulled down to about -0.76V, and the parasitic diode of the MOS tube powered by the LDO in the chip 100 is turned on. The chip 100 provides the extracted 120mA negative current through the parasitic diode, ESD, and LDO, which can easily cause a latch effect in the chip 100 and cause damage.
[0042] Figure 4 Shows Figure 2 The chip shown is a simulation schematic diagram of a negative current extraction test.
[0043] See also Figure 4 In the case where the chip 200 is provided with a latch protection circuit 240, when there is a 120mA pull current at the test port BP5 (i.e., a 120mV negative current is extracted from the test port BP5), after a short response process, the transistor Mn1 is turned on, and the voltage at point A is pulled down to the threshold voltage of the inverter inv, so that the output voltage of the inverter inv, i.e., the voltage at point B, becomes higher, and the transistor Mn3 is turned on. The transistor Mn3 provides most of the extracted current, and the voltage at the test port BP5 is clamped at about -0.27V.
[0044] pass Figure 3 and Figure 4 It can be seen from the comparison that the latch protection circuit 240 provided in the embodiment of the present invention can prevent the occurrence of substrate minority carrier injection when a negative current is drawn from the test port BP5 of the chip 200, so as to protect the chip 200.
[0045] Optionally, the transistors Mn1 to Mn3 and the transistor M2 are N-type MOS (Metal-Oxide-Semiconductor) transistors, wherein the first end of the NMOS transistor is a drain end, the second end is a source end, and the control end is a gate end.
[0046] Optionally, the transistor M2 is a PMOS transistor, wherein the first end of the PMOS transistor is a source end, the second end is a drain end, and the control end is a gate end.
[0047] It can be understood that the latch protection circuit provided in the embodiment of the present invention can be applied to any test port that needs to perform a negative current extraction test. When the chip has multiple test ports that need to perform a negative current extraction test, only one latch protection circuit can be set, and the latch protection circuit is selectively connected to one of the test ports to be tested for negative current extraction through a switch.
[0048] The chip with latch protection function provided by the present invention comprises a latch protection circuit connected to a test port, wherein the latch protection circuit is used to detect the voltage of the test port and short-circuit the test port with a ground port when the voltage of the test port drops to a preset voltage, so as to clamp the voltage of the test port and prevent it from dropping below -0.7V to cause a latch effect in the chip, thereby achieving the purpose of protecting the chip.
[0049] The embodiments of the present invention are as above, and these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.
Claims
1. A chip with a latch protection function, comprising: Power port and ground port; A voltage converter, connected between the power port and the ground port, the voltage converter being used to obtain a supply voltage according to an input voltage of the power port; a functional circuit connected between the output terminal of the voltage converter and the ground port to receive the supply voltage; A test port connected to the output end of the voltage converter; as well as The latch protection circuit is used to detect the voltage of the test port and short-circuit the test port and the ground port when the voltage of the test port drops to a preset voltage.
2. The chip according to claim 1, wherein: The latch protection circuit comprises: a voltage detection unit, configured to detect the voltage of the test port and generate a clamp control signal when the voltage of the test port drops to a preset voltage; and The clamping unit is connected between the test port and the ground port, and conducts a conductive path between the test port and the ground port according to the clamping control signal.
3. The chip according to claim 2, wherein: The voltage detection unit comprises: A first transistor, a first end of which receives a first bias current, a second end of which is connected to the test port, and a substrate of which is connected to the ground port; a second transistor, a first end receiving a second bias current, a second end connected to the ground port, a control end connected to the first end and the control end of the first transistor, and a substrate connected to the ground port, The first end of the first transistor is also used to provide the clamp control signal, and the current value of the first bias current is equal to the current value of the second bias current.
4. The chip according to claim 3, wherein: The voltage detection unit also includes: The first resistor is connected between the second end of the first transistor and the test port.
5. The chip according to claim 4, wherein: The clamping unit comprises: an inverter, an input end of which is connected to the first end of the first transistor; A third transistor has a first end connected to the test port, a second end connected to the ground port, and a control end connected to the output end of the inverter.
6. The chip according to claim 5, wherein: The clamping unit further comprises: The second resistor is connected between the output terminal of the inverter and the ground port.
7. The chip according to claim 5, further comprising: A pre-start module is connected to the power port and is used to generate a pre-start voltage, the first bias current and the second bias current according to the input voltage, and the power supply end of the inverter is connected to the pre-start voltage.
8. The chip according to claim 3, wherein: The size ratio of the first transistor to the second transistor is 1:K, where K is greater than 1.
9. The chip according to claim 1, further comprising: An ESD protection circuit is connected between the test port and the ground port. The preset voltage ranges from -200mV to -500mV.
10. The chip according to claim 7, wherein: The voltage converter is a low voltage difference linear voltage regulator circuit, the functional circuit is an inverter, and after the power port is powered on, the pre-start module will output the pre-start voltage, the first bias current and the second bias current to the bandgap reference module in the low voltage difference linear voltage regulator circuit to generate a reference voltage.