SCR device for ESD protection and electrostatic protection circuit

Abstract

The utility model provides an SCR device used for ESD protection and an electrostatic protection circuit, the SCR device comprises an SCR structure, a BJT transistor structure triggered by NPN and a GGNMOS transistor structure triggered by PNP, so that the SCR device is provided with an SCR current discharge path, a BJT current discharge path and a GGNMOS current discharge path, the trigger voltage Vt of the SCR device is reduced, and the ESD protection circuit is used for ESD protection. The maintaining voltage Vh of the SCR device is improved to avoid the latch-up effect, and the ESD robustness of the SCR device is enhanced to resist the impact of ESD pulses.

Description

Technical Field

[0001] The utility model relates to the technical field of electrostatic protection, in particular to an SCR device and an electrostatic protection circuit for ESD protection. Background Art

[0002] With the continuous development of integrated circuit technology, chip damage caused by electrostatic discharge (ESD) events has become more and more serious, seriously restricting the reliability of semiconductor products. Therefore, it is very necessary to provide effective on-chip ESD protection design for chips. Ideal ESD protection devices have faster turn-on speed, lower trigger voltage, timely response to ESD events and sufficiently high maintenance voltage to avoid latch-up effect. More importantly, they need to have high enough ESD robustness to withstand the impact of ESD pulses. However, ESD devices in practical applications cannot achieve the performance of ideal ESD protection devices, and each has its own advantages and disadvantages. Among the many available ESD protection devices, SCR (Silicon-Controlled-Rectifier) ​​devices have very high area efficiency and are widely used.

[0003] like Figure 1 As shown, the conventional SCR device includes a well region NW and a well region PW that are adjacently arranged, each of the well region NW and the well region PW having an N+ region and a P+ region that are spaced apart, the N+ region and the P+ region located in the well region NW are electrically connected to form an anode of the SCR device, and the N+ region and the P+ region located in the well region PW are electrically connected to form a cathode of the SCR device. Under normal working conditions, the SCR device is in a cut-off state; when the ESD pulse is higher than the PN junction avalanche breakdown voltage of the well region NW and the well region PW, the PN junction of the well region NW and the well region PW reversely breaks down, and the generated electrons and holes form a voltage drop in the well region NW and the well region PW, which finally causes the parasitic NPN and PNP transistors inside the SCR device to turn on and form positive feedback; at the same time, driven by the current gain, the SCR device exhibits a strong conductivity modulation effect, presenting a negative differential resistance state, causing the SCR device to enter a low resistance state, and causing the IV curve to have a strong snapback, causing the SCR device's holding voltage Vh to be generally very low, usually only 1V to 2V, which can easily cause a latch effect. Utility Model Content

[0004] The utility model aims to provide an SCR device and an electrostatic protection circuit for ESD protection, which can reduce the trigger voltage of the SCR device and increase the maintenance voltage of the SCR device.

[0005] In order to solve the above problems, the utility model provides an SCR device for ESD protection, including an SCR structure, an NPN-triggered BJT transistor structure and a PNP-triggered GGNMOS transistor structure, so that the SCR device has an SCR current discharge path, a BJT current discharge path and a GGNMOS current discharge path.

[0006] Optionally, the SCR device has an anode and a cathode, and the SCR device includes a substrate, an N-well region and a P-well region adjacently arranged in the substrate, a first N+ region and a first P+ region spaced apart in the N-well region, a second N+ region and a second P+ region spaced apart in the P-well region, a third N+ region and a third P+ region located at the junction of the N-well region and the P-well region, a gate structure is arranged on the substrate of the second N+ region and the third N+ region, the second P+ region, the third P+ region, the gate structure and the second N+ region are connected to the cathode, and the first N+ region and the first P+ region are both connected to the anode.

[0007] Further, the first N+ region, the first P+ region, the N-well region, the P-well region, the second N+ region and the second P+ region form the SCR structure, the third N+ region, the P-well region and the second N+ region form a PNP-triggered GGNMOS transistor structure, and the third P+ region, the N-well region and the first P+ region form an NPN-triggered BJT transistor structure.

[0008] Furthermore, the ion concentration of the third P+ region is inversely proportional to the value of the current amplification factor of the SCR device.

[0009] Furthermore, the N-well region and the P-well region are adjacent and in contact with each other, the first N+ region and the first P+ region are isolated by an STI structure, the second N+ region and the second P+ region are isolated by an STI structure, the first P+ region is located between the first N+ region and the P-well region, and the second N+ region is located between the second P+ region and the N-well region.

[0010] Further, the third N+ region includes a first part and a second part, the first part and the second part are adjacent and contacting each other, the first part and the third P+ region are adjacent and contacting each other and are arranged between the first P+ region and the second N+ region, the first part is located between the third P+ region and the second N+ region, the third P+ region and the first P+ region are isolated by an STI structure, the first part and the second N+ region are spaced apart, and the third P+ region is arranged around the outside of the second part.

[0011] Further, a length of the second portion in a direction from the first P+ region to the third P+ region is the same as a length of the third P+ region in a direction from the first P+ region to the third P+ region.

[0012] Furthermore, the shape of the second part is a regular pattern.

[0013] Further, the gate structure is disposed on the substrate between the first portion and the second N+ region, and in the direction from the first P+ region to the third P+ region, the gate structure simultaneously covers a portion of the first portion and the second N+ region.

[0014] On the other hand, the utility model also provides an electrostatic protection circuit, including the SCR device for ESD protection, the SCR device including an SCR structure, an NPN-triggered BJT transistor structure and a PNP-triggered GGNMOS transistor structure, so that the SCR device has an SCR current discharge path, a BJT current discharge path and a GGNMOS current discharge path.

[0015] Compared with the prior art, the utility model has the following unexpected beneficial effects:

[0016] The utility model provides an SCR device and an electrostatic protection circuit for ESD protection. The SCR device comprises an SCR structure, an NPN-triggered BJT transistor structure and a PNP-triggered GGNMOS transistor structure, so that the SCR device has an SCR current discharge path, a BJT current discharge path and a GGNMOS current discharge path. The unexpected technical effect achieved by the application is: reducing the trigger voltage Vt of the SCR device, increasing the holding voltage Vh of the SCR device to avoid the latch effect, and enhancing the ESD robustness of the SCR device to resist the impact of ESD pulses.

[0017] Furthermore, the utility model introduces the third N+ region so that the third N+ region, the P-well region and the second N+ region form a PNP-triggered GGNMOS transistor structure, and the junction breakdown of the N+ region and the P-well region replaces the junction breakdown of the N-well region and the P-well region of the traditional SCR device, thereby reducing the trigger voltage Vt of the SCR device; by introducing the third P+ region, the third P+ region, the N-well region and the first P+ region form an NPN-triggered BJT transistor structure, and the junction breakdown of the P+ region and the N-well region replaces the junction breakdown of the N-well region and the P-well region of the traditional SCR device. Since the third P+ region serves as the base of the parasitic NPN, the present application achieves the unexpected technical effect of reducing the current amplification factor β of the SCR device, thereby increasing the holding voltage Vh of the SCR device.

[0018] Furthermore, the ion concentration of the third P+ region is inversely proportional to the value of the current amplification factor β of the SCR device, that is, as the ion concentration of the third P+ region increases, the current amplification factor β will decrease accordingly. The unexpected technical effect achieved by the present application is: increasing the holding voltage Vh of the SCR device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of an SCR device;

[0020] Figure 2 A schematic diagram of the three-dimensional structure of an SCR device for ESD protection provided by an embodiment of the utility model;

[0021] Figure 3 for Figure 2 Schematic diagram of the cross-sectional structure at the dotted line A1A2;

[0022] Figure 4 for Figure 2 A schematic diagram of the cross-sectional structure at the dotted line B1B2;

[0023] Figure 5 A graph showing the relationship between anode current and voltage of an SCR device provided in one embodiment of the utility model.

[0024] Description of reference numerals:

[0025] 100-substrate; 111-N well region; 112-P well region; 121-first N+ region; 122-first P+ region; 123-third P+ region; 124-second portion; 125-first portion; 126-second N+ region; 127-second P+ region; 130-STI structure; 200-gate structure. DETAILED DESCRIPTION

[0026] The following is a further detailed description of an SCR device and an electrostatic protection circuit for ESD protection of the utility model. The utility model will be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the utility model are shown. It should be understood that those skilled in the art can modify the utility model described herein and still achieve the beneficial effects of the utility model. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation to the utility model.

[0027] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would make the utility model confusing with unnecessary details. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just routine work for those skilled in the art.

[0028] In order to make the purpose and features of the utility model more obvious and easy to understand, the specific implementation of the utility model is further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.

[0029] Figure 2 A schematic diagram of the three-dimensional structure of an SCR device for ESD protection provided in this embodiment. Figure 2 As shown, this embodiment provides an electrostatic protection circuit, which is mainly used in the field of low-voltage ESD protection, and the electrostatic protection circuit includes an SCR device for ESD protection.

[0030] like Figure 2-Figure 4 As shown, the SCR device includes an SCR structure, an NPN-triggered BJT (bipolar junction transistor) transistor structure and a PNP-triggered GGNMOS (gate grounded N-type field effect transistor) transistor structure, so that the SCR device has an SCR current discharge path ①, a BJT current discharge path ③ and a GGNMOS current discharge path ②, thereby reducing the trigger voltage Vt of the SCR device, increasing the holding voltage Vh of the SCR device to avoid the latch effect, and enhancing the ESD robustness of the SCR device to resist the impact of ESD pulses.

[0031] In detail, the SCR device has an anode and a cathode, and the SCR device includes a substrate 100, an N-well region 111 and a P-well region 112 adjacently arranged in the substrate 100, a first N+ region 121 and a first P+ region 122 spaced apart in the N-well region 111, a second N+ region 126 and a second P+ region 127 spaced apart in the P-well region 112, and a third N+ region and a third P+ region 123 located at the junction of the N-well region 111 and the P-well region 112, a gate structure 200 is arranged on the substrate 100 of the second N+ region 126 and the third N+ region, the second P+ region 127, the third P+ region 123, the gate structure 200 and the second N+ region 126 are connected to the cathode, and the first N+ region 121 and the first P+ region 122 are both connected to the anode.

[0032] In this embodiment, the first N+ region 121, the first P+ region 122, the N-well region 111, the P-well region 112, the second N+ region 126 and the second P+ region 127 form the SCR structure, thereby obtaining an SCR current discharge path ①; in this embodiment, the third N+ region is introduced so that the third N+ region, the P-well region 112 and the second N+ region 126 form a PNP-triggered GGNMOS transistor structure, and the junction breakdown of the N+ region and the P-well region 112 (i.e., the GGNMOS current discharge path ②) of the traditional SCR device N-well region 111 and the P-well region 112 is replaced by the junction breakdown of the N+ region and the P-well region 112 (i.e., the GGNMOS current discharge path ②). Path ①), thereby reducing the trigger voltage Vt of the SCR device; by introducing the third P+ region 123, the third P+ region 123, the N-well region 111 and the first P+ region 122 form an NPN-triggered BJT transistor structure, and the junction breakdown of the N-well region 111 and the P-well region 112 of the traditional SCR device (i.e., SCR current discharge path ①) is replaced by the junction breakdown of the P+ region and the N-well region 111 (i.e., the BJT current discharge path ③). Since the third P+ region 123 serves as the base of the parasitic NPN, the current amplification factor β of the SCR device is reduced, thereby increasing the holding voltage Vh of the SCR device. Wherein, the substrate 100 can be a P-type substrate 100.

[0033] The N-well region 111 and the P-well region 112 are disposed adjacently and in contact with each other in the substrate 100, and both the N-well region 111 and the P-well region 112 extend from a side surface of the substrate 100 into the substrate 100. The first N+ region 121 and the first P+ region 122 are isolated and disposed in the N-well region 111 by an STI (shallow trench structure) structure 130. The first N+ region 121 and the first P+ region 122 extend from a side surface of the substrate 100 into the substrate 100, and the depths of the first N+ region 121 and the first P+ region 122 are both less than the depth of the N-well region 111 and less than the depth of the STI structure 130.

[0034] The second N+ region 126 and the second P+ region 127 are isolated and arranged in the P-well region 112 by the STI structure 130. The second N+ region 126 and the second P+ region 127 extend from a side surface of the substrate 100 into the substrate 100, and the depths of the second N+ region 126 and the second P+ region 127 are both smaller than the depth of the P-well region 112 and also smaller than the depth of the isolation of the STI structure 130.

[0035] The first P+ region 122 is arranged on a side of the first N+ region 121 close to the P-well region 112, that is, the first P+ region 122 is located between the first N+ region 121 and the P-well region 112; the second N+ region 126 is arranged on a side of the second P+ region 127 close to the N-well region 111, that is, the second N+ region 126 is located between the second P+ region 127 and the N-well region 111.

[0036] The third N+ region includes a first portion 125 and a second portion 124, the first portion 125 and the second portion 124 are arranged adjacent to and in contact with each other. The first portion 125 and the third P+ region 123 are arranged between the first P+ region 122 and the second N+ region 126, and the first portion 125 and the third P+ region 123 are arranged adjacent to and in contact with each other, the first portion 125 is located between the third P+ region 123 and the second N+ region 126, the third P+ region 123 and the first P+ region 122 are isolated by the STI structure 130, the first portion 125 and the second N+ region 126 are arranged at intervals, the third P+ region 123 is arranged around the outside of the second portion 124, and the length of the second portion 124 in the direction from the first P+ region 122 to the third P+ region 123 is the same as the length of the third P+ region 123 in the direction from the first P+ region 122 to the third P+ region 123. The second portion 124 is in a regular shape, such as a polygon (preferably a parallelogram), an ellipse, and the like.

[0037] The gate structure 200 is disposed on the substrate 100 between the first portion 125 and the second N+ region 126, and in the direction from the first P+ region 122 to the third P+ region 123, the gate structure 200 simultaneously covers a portion of the first portion 125 and the second N+ region 126. The gate structure 200 includes a gate oxide layer and a polysilicon layer from bottom to top, and the polysilicon layer is connected to the cathode.

[0038] like Figure 3As shown, the polysilicon layer, the second N+ region 126 and the second P+ region 127 are all connected to the cathode, so that the third N+ region, the P-well region 112 and the second N+ region 126 form a PNP-triggered GGNMOS transistor structure, and the junction breakdown of the N+ region and the P-well region 112 replaces the junction breakdown of the N-well region 111 and the P-well region 112 of the traditional SCR device, thereby effectively solving the problem of the trigger voltage Vt of the SCR device being too high. However, since the maintenance voltage Vh of the SCR device is very low, and after being turned on, the GGNMOS current discharge path ② cannot compete with the SCR current discharge path ①, more current is discharged from the SCR current discharge path ①, resulting in a lower maintenance voltage Vh.

[0039] like Figure 4 As shown, the third P+ region 123, the N-well region 111 and the first P+ region 122 are all connected to the cathode to form an NPN-triggered BJT transistor structure, and the junction breakdown voltage of the N-well region 111 and the P-well region 112 of the traditional SCR device is replaced by the junction breakdown of the P+ region and the N-well region 111 as a trigger, which can reduce the trigger voltage Vt. Furthermore, since the third P+ region 123 serves as the base of the parasitic NPN, the ion concentration of the third P+ region 123 is inversely proportional to the value of the current amplification factor β of the SCR device, that is, the current amplification factor β will decrease as the ion concentration of the third P+ region 123 increases, thereby increasing the holding voltage Vh of the SCR device.

[0040] As shown in the following table, a current pulse similar to that of the SCR device when an actual electrostatic discharge event occurs is used. For example, the pulse parameters are set to rising edge time t1 = 10ns, pulse width 130ns, and falling edge time t2 = 10ns. At this time, the pulse number TLPi and the instantaneous current value are as follows:

[0041] <![CDATA[ TLPi ]]> Transient current value 1 1.00E-05 2 1.00E-04 3 2.00E-04 4 3.00E-04 5 4.00E-04 6 5.00E-04 7 6.00E-04 8 7.00E-04 9 8.00E-04 10 9.00E-04 11 1.00E-03 12 1.10E-03 3 1.20E-03 14 1.30E-03 15 1.80E-03 16 2.10E-03 17 2.30E-03 18 3.00E-03 19 4.00E-03 20 4.30E-03 21 5.00E-03 22 5.50E-03 23 6.00E-03 24 7.00E-03 25 8.00E-03 26 1.00E-02

[0042] Each pulse value is calculated through computer-aided design (TCAD) of integrated circuit technology and devices, and the voltage and time relationship (i.e., voltage-time curve) under each pulse value is obtained. The values ​​of the 55% to 85% time period in the voltage-time curve are taken for arithmetic averaging, thus obtaining the following: Figure 5 By comparing the current-voltage curve b with the current-voltage curve a of the traditional SCR device, it can be seen that the voltage at m is larger than the voltage at m′, that is, the maintenance voltage Vh of the SCR device of this embodiment is larger than the maintenance voltage Vh of the traditional SCR device, and the voltage at n is smaller than the voltage at n′, that is, the trigger voltage Vt of the SCR device of this embodiment is smaller than the trigger voltage Vt of the traditional SCR device. This makes the SCR device of this embodiment significantly lower the trigger voltage and increase the maintenance voltage compared with the traditional SCR device.

[0043] In addition, the third N+ region of this embodiment can be formed simultaneously with the first N+ region 121 and the second N+ region 126, and the third P+ region 123 can be formed simultaneously with the first P+ region 122 and the second P+ region 127, which means that this embodiment does not need to add additional masks and has cost advantages.

[0044] In summary, the utility model provides an SCR device and an electrostatic protection circuit for ESD protection, wherein the SCR device includes an SCR structure, an NPN-triggered BJT transistor structure, and a PNP-triggered GGNMOS transistor structure, so that the SCR device has an SCR current discharge path, a BJT current discharge path, and a GGNMOS current discharge path. The unexpected technical effect achieved by the present application is that the trigger voltage Vt of the SCR device is reduced, and the holding voltage Vh of the SCR device is increased to avoid the latch effect, thereby enhancing the ESD robustness of the SCR device to resist the impact of ESD pulses.

[0045] Furthermore, the utility model introduces the third N+ region so that the third N+ region, the P-well region and the second N+ region form a PNP-triggered GGNMOS transistor structure, and the junction breakdown of the N+ region and the P-well region replaces the junction breakdown of the N-well region and the P-well region of the traditional SCR device, thereby reducing the trigger voltage Vt of the SCR device; by introducing the third P+ region, the third P+ region, the N-well region and the first P+ region form an NPN-triggered BJT transistor structure, and the junction breakdown of the P+ region and the N-well region replaces the junction breakdown of the N-well region and the P-well region of the traditional SCR device. Since the third P+ region serves as the base of the parasitic NPN, the present application achieves an unexpected technical effect of reducing the current amplification factor β of the SCR device, thereby increasing the holding voltage Vh of the SCR device.

[0046] Furthermore, the ion concentration of the third P+ region is inversely proportional to the value of the current amplification factor β of the SCR device, that is, as the ion concentration of the third P+ region increases, the current amplification factor β will decrease accordingly. The unexpected technical effect achieved by the present application is to increase the holding voltage Vh of the SCR device.

[0047] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0048] It is understandable that, although the utility model has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the utility model. For any technician familiar with the art, without departing from the scope of the technical solution of the utility model, the above disclosed technical content can be used to make many possible changes and modifications to the technical solution of the utility model, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the utility model without departing from the content of the technical solution of the utility model still falls within the scope of protection of the technical solution of the utility model.

Claims

1. An SCR device for ESD protection, characterized in that: Including SCR structure, NPN triggered BJT transistor structure and PNP triggered GGNMOS transistor structure; The SCR device has an anode and a cathode, and includes a substrate, an N-well region and a P-well region adjacently arranged in the substrate, a first N+ region and a first P+ region arranged in the N-well region at intervals, a second N+ region and a second P+ region arranged in the P-well region at intervals, a third N+ region and a third P+ region located at the junction of the N-well region and the P-well region, a gate structure is arranged on the substrate of the second N+ region and the third N+ region, the second P+ region, the third P+ region, the gate structure and the second N+ region are connected to the cathode, and the first N+ region and the first P+ region are both connected to the anode; Among them, the first N+ region, the first P+ region, the N-well region, the P-well region, the second N+ region and the second P+ region form the SCR structure, the third N+ region, the P-well region and the second N+ region form a PNP-triggered GGNMOS transistor structure, and the third P+ region, the N-well region and the first P+ region form an NPN-triggered BJT transistor structure.

2. The SCR device for ESD protection according to claim 1, characterized in that: The ion concentration of the third P+ region is inversely proportional to the value of the current amplification factor of the SCR device.

3. The SCR device for ESD protection according to claim 1, characterized in that: The N-well region and the P-well region are adjacent and in contact with each other, the first N+ region and the first P+ region are isolated by an STI structure, the second N+ region and the second P+ region are isolated by an STI structure, the first P+ region is located between the first N+ region and the P-well region, and the second N+ region is located between the second P+ region and the N-well region.

4. The SCR device for ESD protection according to claim 1, characterized in that: The third N+ region includes a first part and a second part, the first part and the second part are adjacent to and in contact with each other, the first part and the third P+ region are adjacent to and in contact with each other and are arranged between the first P+ region and the second N+ region, the first part is located between the third P+ region and the second N+ region, the third P+ region and the first P+ region are isolated by an STI structure, the first part and the second N+ region are spaced apart, and the third P+ region is arranged around the outside of the second part.

5. The SCR device for ESD protection according to claim 4, characterized in that: A length of the second portion in a direction from the first P+ region to the third P+ region is the same as a length of the third P+ region in a direction from the first P+ region to the third P+ region.

6. The SCR device for ESD protection according to claim 4, characterized in that: The second part has a regular shape.

7. The SCR device for ESD protection according to claim 4, characterized in that: The gate structure is disposed on the substrate between the first portion and the second N+ region, and in a direction from the first P+ region to the third P+ region, the gate structure simultaneously covers a portion of the first portion and the second N+ region.

8. An electrostatic protection circuit, characterized in that: The invention comprises an SCR device for ESD protection as claimed in any one of claims 1 to 7.

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