Adjustable chip power-on sequence control circuit

Abstract

The utility model relates to chip on -line control technical field, concretely for adjustable chip power -on time sequence control circuit. Including at least two stages of DC -DC power module of concatenation, every stage DC -DC power module includes input power end, output voltage end, enable control end (EN) and power good signal end (PG). The utility model discloses through the DC -DC power module of cascaded setting, utilizes the RC delay circuit between power good signal end (PG) of preceding stage module and enable control end (EN) of rear stage module, has realized the flexible adjustment of rear stage module power -on delay time, need not to rely on complex control chip or software program, can accurate matching chip required power -on time sequence only through the adjustment of resistance capacitor parameter, has reduced circuit complexity and cost.

Description

Technical Field

[0001] This utility model relates to the field of chip power-on control technology, specifically an adjustable chip power-on sequence control circuit. Background Technology

[0002] In integrated circuit systems, the reliable operation of chips places stringent requirements on the power-on timing of power supplies. This is especially true in scenarios with multi-voltage domain power supply, where the order and time intervals of power-on for different voltages directly affect chip performance and stability. Incorrect timing can trigger latch-up effects, leading to chip malfunctions or even permanent damage. Traditional power-on timing control schemes typically rely on complex power management integrated circuits (PMICs) or programmable logic devices (such as CPLDs) combined with software control. While these schemes can achieve timing adjustment, they suffer from complex circuit structures, high costs, and limited hardware design flexibility. For systems requiring multi-level voltage outputs, achieving timing adjustability through simple hardware circuits while ensuring stability during rapid power-on and power-off cycles, while meeting specific chip power-on sequences (e.g., 3.3V, 1.8V, 1.2V, 1.0V staged power-on), has become a pressing technical direction for optimization in current power system design. Existing solutions fall short in balancing cost, circuit complexity, and timing control accuracy. There is an urgent need for a simple, highly adjustable, and reliable hardware circuit solution to meet the stringent power timing requirements of high-performance chips. Utility Model Content

[0003] This disclosure proposes an adjustable chip power-on sequence control circuit, with the aim of overcoming at least one of the defects existing in the prior art.

[0004] To achieve the above objectives, the technical solution disclosed in this utility model is as follows:

[0005] According to one aspect of this disclosure, an adjustable chip power-on sequence control circuit is provided, comprising at least two cascaded DC-DC power modules, each of which includes an input power terminal, an output voltage terminal, an enable control terminal (EN), and a power good signal terminal (PG).

[0006] An RC delay circuit is connected between the power good signal terminal (PG) of the front-stage DC-DC power module and the enable control terminal (EN) of the rear-stage DC-DC power module. The RC delay circuit is used to adjust the power-on delay time of the rear-stage DC-DC power module.

[0007] A discharge diode is connected in parallel between the enable control terminal (EN) and ground. The discharge diode is used to quickly release the charge stored in the capacitor of the RC delay circuit when the circuit is powered off.

[0008] Furthermore, it includes four cascaded DC-DC power modules, namely the first DC-DC power module (P1U1), the second DC-DC power module (P2U1), the third DC-DC power module (P3U1), and the fourth DC-DC power module (P4U1).

[0009] The second DC-DC power module (P2U1), the third DC-DC power module (P3U1), and the fourth DC-DC power module (P4U1) all have a discharge diode (D) connected in parallel between their enable control terminal (EN) and ground. The anode of the discharge diode (D) is grounded, and the cathode is electrically connected to the enable control terminal (EN).

[0010] Furthermore, the input power terminal of the first DC-DC power module (P1 U1) is connected to a 12V DC voltage (VCC12V), and its enable control terminal (EN) is electrically connected to the input power terminal through a voltage divider resistor circuit. The voltage divider resistor circuit includes a first voltage divider resistor (P1 R3) and a second voltage divider resistor (P1 R8) connected in series between the 12V DC voltage (VCC12V) and ground, and the enable control terminal (EN) is connected to the series node of the two.

[0011] Furthermore, the enable control terminal (EN) of the second DC-DC power module (P2U1) is electrically connected to the power good signal terminal (3V3_PG) of the first DC-DC power module (P1U1) through a first series resistor (P2R8), and a first capacitor (P2C15) is connected in parallel between the enable control terminal (EN) and ground. The first series resistor (P2R8) and the first capacitor (P2C15) constitute an RC delay circuit.

[0012] Furthermore, the enable control terminal (EN) of the fourth DC-DC power module (P4U1) is electrically connected to the power good signal terminal (1V2_PG) of the third DC-DC power module (P3U1) through a third series resistor (P4R8), and a third capacitor (P4C15) is connected in parallel between the enable control terminal (EN) and ground. The third series resistor (P4R8) and the third capacitor (P4C15) constitute an RC delay circuit.

[0013] Furthermore, the first DC-DC power module (P1 U1) outputs a voltage of 3.3V (3V3), the second DC-DC power module (P2 U1) outputs a voltage of 1.8V (1V8), the third DC-DC power module (P3 U1) outputs a voltage of 1.2V (1V2), and the fourth DC-DC power module (P4 U1) outputs a voltage of 1.0V (1V0), and the power-on sequence of the output voltages is 3.3V, 1.8V, 1.2V, and 1.0V.

[0014] Furthermore, the power good signal terminal (3V3_PG) of the first DC-DC power module (P1 U1) outputs a high-level signal after the output voltage stabilizes. This high-level signal provides a start signal to the enable control terminal (EN) of the second DC-DC power module (P2U1) through the first series resistor (P2R8).

[0015] Furthermore, the resistance values ​​of the first series resistor (P2R8), the second series resistor (P3R8), and the third series resistor (P4R8), and the corresponding capacitance values ​​of the first capacitor (P2C15), the second capacitor (P3C15), and the third capacitor (P4C15) are adjustable to adjust the power-on delay time of the subsequent DC-DC power supply module.

[0016] Furthermore, the discharge diode (D) is used to conduct when the circuit is powered off, quickly releasing the charge stored in the first capacitor (P2C15), the second capacitor (P3C15), and the third capacitor (P4C15), so that the voltage of the enable control terminal (EN) drops rapidly to the turn-off voltage.

[0017] The output voltage terminals of the first DC-DC power module (P1 U1), the second DC-DC power module (P2 U1), the third DC-DC power module (P3 U1), and the fourth DC-DC power module (P4 U1) are all connected in parallel with a filter capacitor bank. The filter capacitor bank includes multiple filter capacitors (P1 C7-P1 C12, P2 C7-P2 C12, P3 C7-P3 C12, P4 C7-P4 C12) connected in parallel between the output voltage terminal and ground.

[0018] The voltage obtained by the enable control terminal (EN) of the first DC-DC power module (P1 U1) through the voltage divider resistor circuit meets its startup voltage requirements, so as to ensure that the first DC-DC power module (P1 U1) is powered on before the subsequent DC-DC power module.

[0019] The beneficial effects of this utility model are:

[0020] This invention utilizes a cascaded DC-DC power supply module and an RC delay circuit between the power good signal terminal (PG) of the front-end module and the enable control terminal (EN) of the rear-end module to achieve flexible adjustment of the power-on delay time of the rear-end module. This eliminates the need for complex control chips or software programs; precise matching of the chip's required power-on timing can be achieved simply by adjusting the resistor and capacitor parameters, reducing circuit complexity and cost. The discharge diode rapidly releases the charge stored in the capacitor when the circuit is powered off, causing the enable control terminal voltage to drop quickly to the turn-off threshold. This ensures rapid and synchronized power-off of each stage, avoiding timing disorder caused by residual charge and effectively improving system stability in rapid power-on / off scenarios.

[0021] Furthermore, this invention utilizes the characteristics of the DC-DC module's own PG and EN pins, combined with the hardware logic of basic RC circuits and diodes, to construct a low-cost, high-reliability timing control architecture. It can ensure the first-stage module is powered on first through a voltage divider resistor circuit, and can achieve precise sequencing of voltage outputs (3.3V→1.8V→1.2V→1.0V) through a multi-stage RC delay circuit. This fundamentally prevents latch-up from occurring at the hardware level, providing the chip with a power timing environment that meets specifications, and combining circuit simplicity, parameter adjustability, and operational stability.

[0022] The above description is only an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, the preferred embodiments of this utility model are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0023] Figure 1 This is a circuit architecture diagram of a multi-stage cascaded DC-DC power module in one embodiment of the present invention;

[0024] Figure 2 This is a circuit diagram showing the cascaded primary and secondary modules in one embodiment of the present invention;

[0025] Figure 3 This is a circuit diagram of the final-stage module cascade in one embodiment of the present invention;

[0026] Figure 4 This is a power-on timing diagram of multiple voltage levels in one embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0028] The term "comprising," and any variations thereof, used in the specification and claims of this application, is intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product, or apparatus. Furthermore, the use of "and / or" in the specification and claims indicates at least one of the connected objects, such as A and / or B, indicating the inclusion of A alone, B alone, or both A and B.

[0029] In this embodiment of the invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this embodiment of the invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0030] The present invention provides the following preferred embodiments:

[0031] To address the issues of high circuit complexity and cost in chip power-on timing control within multi-voltage domain power supply systems, this embodiment provides an adjustable power-on timing control circuit based on cascaded DC-DC power modules. This circuit achieves precise timing adjustment and stable control through hardware logic. For example... Figures 1 to 3 As shown, the circuit includes at least two cascaded DC-DC power supply modules. Each module has an input power supply terminal, an output voltage terminal, an enable control terminal (EN), and a power good signal terminal (PG). An RC delay circuit is connected between the PG terminal of the front-end module and the EN terminal of the rear-end module. The power-on delay time of the rear-end module is adjusted by utilizing the charging and discharging characteristics of the resistor and capacitor, without the need for complex control chips or software intervention.

[0032] Specifically, the RC delay circuit consists of a series resistor and a parallel capacitor: when the upstream PG signal outputs a valid level (e.g., high level), the resistor limits the current and charges the capacitor, causing the EN terminal voltage to gradually rise to the module startup threshold. The delay time is determined by the RC time constant. Upon power-down, the discharge diode connected in parallel between the EN terminal and ground conducts, providing a low-impedance discharge path for the capacitor, quickly releasing the stored charge and ensuring the EN terminal voltage drops rapidly to the shutdown threshold, avoiding timing disruptions caused by residual charge. It's important to understand that the PG signal of a DC-DC module is typically activated after the output voltage stabilizes, indicating a normal power supply state. Using this as the enable trigger signal for subsequent modules ensures that the preceding stage voltage stabilizes before starting the subsequent stage, meeting the chip's strict requirements for voltage setup sequence.

[0033] Furthermore, this circuit architecture expands the number of timing control stages through modular cascading, with each stage's RC parameters independently adjustable to adapt to the varying timing interval requirements of different chips. For example, after the first-stage module powers on, its PG signal triggers the secondary module via an RC delay circuit. Once the secondary module's output stabilizes, it triggers the next stage via its own PG signal, forming a chain-like timing control. The unidirectional conductivity of the discharge diode ensures that its cutoff during power-on does not affect the RC charging process, while its conduction during power-off accelerates discharge, improving the system's response consistency in rapid power-on / off scenarios. The advantage of this embodiment is that it utilizes the inherent pin characteristics of the DC-DC module and basic passive components to construct the timing control logic, significantly simplifying the circuit structure while ensuring control accuracy, reducing system cost and design complexity, and providing reliable hardware-level timing guarantees for multi-voltage domain chips.

[0034] Example 2

[0035] To meet the chip's stringent requirements for the power-on sequence of multi-level voltages, this embodiment further refines the circuit structure based on Embodiment 1, employing a four-stage cascaded DC-DC power supply module, defined as the first module (P1U1), the second module (P2U1), the third module (P3U1), and the fourth module (P4U1), corresponding to output voltages of 3V3, 1V8, 1V2, and 1V0. Figure 1 As shown, discharge diodes (D1, D2, D3) are connected in parallel between the EN terminal of the second, third, and fourth modules and ground. The anode of the diode is grounded, and the cathode is electrically connected to the EN terminal to form a dedicated discharge circuit.

[0036] When the circuit is powered on, the discharge diode is reverse-biased and cut off, not affecting the charging process of the RC delay circuit to the EN terminal; when powered off, the input power supply voltage drops, the EN terminal voltage is higher than the ground potential, the diode is forward-biased, allowing the charge stored in the capacitor to be quickly released to ground through the diode, preventing the EN terminal voltage from remaining at an effective level due to slow capacitor discharge, and ensuring synchronous and rapid shutdown of each module. Taking the second module as an example, if... Figure 2As shown, its EN terminal (1V8_EN) is grounded through the discharge diode P2D1. This diode conducts rapidly when the system is powered off, accelerating the discharge of capacitor P2C15 and causing the EN terminal voltage to drop quickly to the turn-off threshold. Combined with the synchronous failure of the PG signal in the preceding stage, the 1V8 voltage is turned off in time, avoiding timing chaos caused by the voltage of the subsequent stage lagging behind the preceding stage.

[0037] It's important to understand that in a multi-stage cascaded structure, the discharge diode of each module independently acts on its corresponding EN terminal, ensuring that the power-down process of each stage is not affected by the residual charge of the preceding capacitor, maintaining the consistency of the power-down timing. This design is particularly suitable for scenarios sensitive to power-down speed, such as high-frequency power switching or sudden power outages, effectively preventing internal parasitic effects caused by asynchronous voltage shutdown and improving system reliability. This embodiment, by clearly defining the cascade relationship of the four modules and the connection method of the discharge diodes, extends timing control from single delay adjustment to multi-dimensional stability optimization, constructing a complete power-up and power-down control logic at the hardware level, providing the chip with a voltage timing environment that meets specifications.

[0038] Example 3

[0039] To address the startup control issue of the primary DC-DC module, this embodiment optimizes the enable logic of the first module (P1U1), allowing it to power on before subsequent modules, thus establishing a benchmark for timing control. For example... Figure 2 As shown, the input power supply terminal of P1 U1 is connected to a 12V DC voltage (VCC12V). Its EN terminal is connected to the input power supply terminal through a voltage divider resistor circuit. This voltage divider circuit consists of a first voltage divider resistor (P1R3) and a second voltage divider resistor (P1R8) connected in series between VCC12V and ground. The EN terminal is connected to the series node of the two resistors. The voltage divider ratio is set to ensure that the voltage at the EN terminal meets the module startup requirements.

[0040] Specifically, the resistance value of the voltage divider resistor is selected based on the threshold voltage of the module's EN terminal to ensure that the EN terminal voltage immediately reaches an effective level after the input power is turned on, triggering P1U1 to start and output a 3V3 voltage. Unlike subsequent modules that rely on the preceding stage's PG signal, the first-stage module is directly controlled by the input power supply voltage divider, avoiding the first-stage startup delay problem in cascaded structures and ensuring the stability of the entire timing chain's starting point. Figure 2 As shown in the elliptical region, the voltage divider network formed by P1R3 and P1R8 provides a stable bias voltage for the EN terminal. This design does not require additional control signals and achieves priority control only through passive components, simplifying the drive circuit of the first-stage module.

[0041] Furthermore, the voltage divider resistor circuit and the subsequent RC delay circuit form a hierarchical control: after the first-stage module powers on, its PG signal (3V3_PG) serves as the enable trigger source for the second-stage module, activating the second module after RC delay, and so on. This design ensures a strict voltage output sequence from the first stage to the last stage, meeting the chip's power-on requirements of 3V3→1V8→1V2→1V0. It is important to understand that the accuracy and power selection of the voltage divider resistors must match the electrical characteristics of the module's EN terminal to avoid startup anomalies caused by voltage divider deviations, while also considering circuit power consumption and reliability. This embodiment, through the design of the first-stage voltage divider circuit, clarifies the starting logic of the timing control chain, working in conjunction with the subsequent cascaded structure to construct a complete multi-stage voltage power-on sequence control system.

[0042] Example 4

[0043] To achieve power-on delay adjustment of the secondary DC-DC module, this embodiment uses the second module (P2U1) as an example to describe in detail the specific structure and working principle of the RC delay circuit. Figure 2 As shown, the EN terminal (1V8_EN) of P2U1 is electrically connected to the PG signal terminal (3V3_PG) of the first module through the first series resistor (P2R8). Simultaneously, a first capacitor (P2C15) is connected in parallel between the EN terminal and ground, forming an RC delay network. When P2U1 outputs a stable 3V3 voltage, the 3V3_PG signal becomes high, charging P2C15 through P2R8. The voltage at the EN terminal gradually rises as the capacitor charges until it reaches the start-up threshold of P2U1, triggering the 1V8 voltage output.

[0044] The delay time is determined by the resistance of P2R8 and the capacitance of P2C15. By adjusting these parameters, the power-on interval of the second module relative to the first module can be precisely controlled to meet the chip's specific timing requirements. For example, increasing the resistance of P2R8 or the capacitance of P2C15 will prolong the charging time and increase the delay; conversely, decreasing these parameters will shorten the delay. It is important to note that the RC parameters must match the input impedance and threshold voltage of the module's EN terminal to ensure that the charging curve conforms to the module's startup characteristics and avoids unstable operation due to excessively slow voltage rise.

[0045] like Figure 2As shown in the elliptical region, the 3V3_PG signal, after being current-limited by P2R8, charges P2C15, forming a typical first-order RC circuit response, whose voltage rise follows an exponential law. This hardware delay mechanism eliminates the need for a complex timing controller, achieving adjustable delay solely through passive components, significantly reducing circuit complexity. Simultaneously, this RC network works in conjunction with the discharge diode (P2D1): during power-up, delay is achieved through resistor charging; during power-down, rapid turn-off is achieved through diode discharge, balancing power-up timing adjustment and power-down stability control. This embodiment clarifies the practical application of the RC delay circuit in a cascaded module through the connection relationships of specific circuit components and the principle of parameter adjustment, providing a hardware implementation path for the flexibility and accuracy of timing control.

[0046] Example 5

[0047] To address the timing control requirements of the final-stage DC-DC module, this embodiment uses the fourth module (P4U1) as an example to describe its cascade logic with the preceding modules and the construction of the RC delay circuit. For example... Figure 3 As shown, the EN terminal (1V0_EN) of P4U1 is electrically connected to the PG signal terminal (1V2_PG) of the third module through a third series resistor (P4R8). A third capacitor (P4C15) is connected in parallel between the EN terminal and ground, forming the third-stage RC delay circuit. When the third module outputs a stable 1V2 voltage, the 1V2_PG signal becomes high, charging P4C15 through P4R8. The voltage at the EN terminal gradually rises to the start-up threshold, triggering the 1V0 voltage output, thus achieving a delayed power-on of the final stage voltage relative to the previous stage.

[0048] As the final stage of the four-stage cascaded structure, the delay control of the fourth module directly affects the timing of the chip core voltage build-up. Its RC parameters must be strictly designed according to the chip datasheet to ensure that the 1V0 voltage starts up only after 3V3, 1V8, and 1V2 have stabilized, thus avoiding the risk of latch-up caused by premature core voltage power-up. Figure 3 As shown in the elliptical region, the 1V2_PG signal charges P4C15 after being current-limited by P4R8. The delay time is determined by the product of the two signals and can be precisely adjusted by replacing resistors or capacitors with different values. It is important to understand that the threshold voltage at the EN terminal of the final stage module may differ from that of the preceding stage. Therefore, the RC parameters need to be adjusted according to the specific module specifications to ensure that the charging curve meets the startup requirements.

[0049] Similar to the intermediate stage modules, the EN terminal of the fourth module also has a parallel discharge diode (P4D1) connected to it. Upon power-down, this diode rapidly releases the charge from P4C15, ensuring that the 1V0 voltage shuts down synchronously with the preceding stage voltage, thus preventing circuit anomalies caused by a delayed core voltage shutdown. This embodiment demonstrates the independence and coordination of each RC delay circuit in a multi-stage cascaded structure through the specific circuit construction of the final stage module. This ensures that the voltage output from the first stage to the last stage strictly follows a preset sequence, and that the delay time of each stage can be independently adjusted to adapt to the varying timing parameter requirements of different chips.

[0050] Example 6

[0051] To clarify the specific specifications and power-on sequence of the multi-stage voltage output, this embodiment defines the output voltage and timing relationship of the four-stage DC-DC module based on the chip's power supply requirements. For example... Figure 1 As shown, the first module (P1 U1) outputs 3.3V (3V3), which serves as the chip's primary power supply voltage; the second module (P2 U1) outputs 1.8V (1V8), the third module (P3 U1) outputs 1.2V (1V2), and the fourth module (P4 U1) outputs 1.0V (1V0), which are the chip's core voltages. According to the chip datasheet, the power-on sequence must be 3V3 → 1V8 → 1V2 → 1V0 to avoid latch-up effects caused by bias anomalies between different voltage domains.

[0052] The output voltage of each module is precisely adjusted through internal feedback circuitry, such as... Figure 2 , 3 The FB pin feedback network shown (such as P1 R6 and P1 R7, which divide the output voltage and feed it back to the internal error amplifier of the module) ensures that the output voltage is stable at the target value. In terms of timing control, the first-stage module is directly started by the voltage divider resistors, while the second-stage module relies on the PG signal from the previous stage, which is then delayed by an RC circuit, to start, forming a strict sequential triggering. For example, after the 3V3 voltage stabilizes, the 3V3_PG signal activates the EN terminal of the second module, which is then delayed by an RC circuit to start with the 1V8 voltage; after the 1V8 voltage stabilizes, the 1V8_PG signal activates the third module, and so on, until the 1V0 voltage finally starts.

[0053] It's important to understand that this voltage-level output and sequential control mechanism essentially translates the chip's timing requirements into the startup logic of each module through hardware circuitry, which can be automatically implemented without software intervention. For example... Figure 4The timing diagram example shown (although this embodiment focuses on voltage sequence, the principle is the same) illustrates that the rising edges of each voltage level occur in a preset order, and the delay time of each level can be adjusted via RC parameters to ensure that the chip's specific requirements, such as "rising time is less than 5ms," are met. This embodiment, by clearly defining the functional positioning and power-on sequence of each output voltage level, directly links the circuit design with the chip's power supply requirements, ensuring that the hardware architecture, from function to timing, strictly matches the application scenario, thereby improving the overall reliability of the system.

[0054] Example 7

[0055] Regarding the logical triggering relationship between the PG signal and the EN terminal, this embodiment uses the cascading of the first and second modules as an example to explain the signal transmission mechanism in detail. Figure 2 As shown, the PG signal terminal (3V3_PG) of the first module (P1 U1) outputs a high-level signal after the 3V3 voltage stabilizes. This signal is transmitted to the EN terminal (1V8_EN) of the second module (P2U1) through the first series resistor (P2R8), serving as the enable signal to start the second module. It is important to understand that the high level of the PG signal indicates that the preceding stage voltage has reached a stable state. Triggering the subsequent module at this point avoids malfunctions in the subsequent module due to fluctuations in the preceding stage voltage, ensuring the reliability of timing control.

[0056] The first series resistor (P2R8) serves a dual function of current limiting and delay in this process: on the one hand, it limits the drive current at the PG signal output terminal, protecting the PG pin of the preceding module; on the other hand, it forms an RC network with the parallel capacitor (P2C15) at the EN terminal, allowing the EN terminal voltage to gradually rise through charging delay, thus achieving precise timing interval control. This design utilizes the module's inherent signal (PG) as the control source, eliminating the need for additional timing generation circuitry and reducing signal synchronization complexity.

[0057] Furthermore, the level characteristics of the PG signal need to match the input characteristics of the EN terminal of the subsequent module. For example, the high level of 3V3_PG needs to be higher than the start-up threshold of the EN terminal to ensure effective triggering. Figure 2 As shown in the internal circuit of the EN terminal of P2U1, when the 1V8_EN voltage reaches the module's set start-up level (e.g., 1.2V), the module activates and begins to convert its output. This process is entirely automated by the hardware signal chain, requiring no external intervention. This embodiment clarifies the state transfer logic between cascaded modules through the specific connection method between the PG signal and the EN terminal, integrating power status monitoring and enable control into the same signal chain, thus achieving high efficiency and reliability in timing control.

[0058] Example 8

[0059] To achieve flexible adjustment of the power-on delay time, this embodiment emphasizes the adjustability of the resistor and capacitor parameters in the RC delay circuit. For example... Figure 2 , 3 As shown, the series resistors (P2R8, P3R8, P4R8) and parallel capacitors (P2C15, P3C15, P4C15) of each module adopt a replaceable component design. By selecting resistors with different resistance values ​​or capacitors with different capacitance values, the power-on delay time of the subsequent module can be precisely adjusted to match the chip's specific requirements for timing intervals.

[0060] For example, if the chip requires at least a 2ms delay to start up after the 1V8 voltage stabilizes at 3V3, the required RC time constant can be calculated using the following formula to select a suitable combination of P2R8 and P2C15:

[0061] Among them, V TH This sets the threshold voltage for the EN terminal. It's important to understand that this adjustment process involves only passive component replacement, requiring no modification to the circuit layout or software, significantly improving design flexibility. Furthermore, the accuracy levels of resistors and capacitors must be selected based on timing control precision requirements. For example, a combination of high-precision thin-film resistors and tantalum capacitors can achieve more precise delay control, while ordinary surface-mount components are suitable for scenarios with less stringent timing requirements.

[0062] This adjustable parameter design is particularly suitable for scenarios requiring compatibility with multiple chip models. The same hardware platform can meet the timing requirements of different chips by replacing RC components, reducing R&D costs and time. Simultaneously, each RC network level is independently adjustable, allowing for personalized configuration based on specific delay requirements for each voltage level, avoiding the limitations of traditional fixed-timing circuits. This embodiment, by clearly defining the component parameter adjustment mechanism, transforms the circuit design from a fixed-function approach to a configurable architecture, further enhancing the applicability and engineering value of the solution.

[0063] Example 9

[0064] To comprehensively optimize circuit performance, this embodiment integrates the synergistic effects of the discharge diode, filter capacitor bank, and voltage divider resistor circuit to construct a complete power-on / off control system. For example... Figures 1 to 3 As shown, each module output is connected in parallel with a filter capacitor bank (such as P1C7-P1C12) to suppress output voltage ripple and improve steady-state stability; discharge diodes (D1-D3) quickly release the charge of the EN terminal capacitor when powered off, ensuring that each module is turned off synchronously; the voltage divider resistor circuit of the first-stage module ensures that it is powered on first, providing a stable trigger source for the subsequent stages.

[0065] Specifically, the filter capacitor bank consists of multiple capacitors of different capacitance values ​​connected in parallel, taking into account both high-frequency and low-frequency filtering requirements, such as... Figure 2The combination of multilayer ceramic capacitors and electrolytic capacitors at the output of P1 and U1 effectively filters out power supply noise, providing a clean power supply voltage for the chip. The unidirectional conductivity of the discharge diode ensures that it does not affect RC charging during power-on and forms a low-resistance discharge path during power-off, such as... Figure 1 The cathode of D1 is connected to the EN terminal of the second module, and the anode is grounded. When the power is off, the voltage at the EN terminal is higher than the ground potential, the diode conducts, and P2C15 discharges quickly to avoid the 1V8 voltage from shutting down lagging behind.

[0066] The voltage divider resistor circuit (P1R3, P1R8) in the primary module uses precise resistance ratios to ensure that the EN terminal voltage strictly meets the startup threshold. Figure 2 As shown in the elliptical region, this voltage divider node directly determines the startup timing of the first-stage module and is the timing starting point of the entire cascaded structure. It's important to understand that these three design components (filtering, discharging, and voltage divider) do not work independently, but rather form a synergistic effect through electrical connections: the voltage divider circuit ensures the startup of the first stage, the RC delay controls the timing of subsequent stages, the filter capacitor stabilizes the output, and the discharge diode ensures rapid power-down, together constructing a power supply system that combines timing accuracy, steady-state performance, and dynamic response.

[0067] This embodiment integrates the functions of various circuit components, clearly defining the complete signal chain and energy flow from input power supply to output voltage, and demonstrating the collaborative working mechanism of various components in the hardware design. This multi-dimensional optimized design, while meeting the chip power-on timing requirements, improves the reliability of the system under different operating scenarios, providing an efficient and concise engineering solution for multi-voltage domain power supply systems.

[0068] Although the present invention has been specifically described above with reference to preferred embodiments, it should be understood that the present invention is not limited to the embodiments described above. Rather, various modifications and variations can be made by those skilled in the art without departing from the essence of the present invention, and such modifications and variations should fall within the scope defined by the appended claims and their equivalents.

Claims

1. An adjustable chip power-on sequence control circuit, characterized in that, It includes at least two cascaded DC-DC power modules, each of which includes an input power terminal, an output voltage terminal, an enable control terminal (EN), and a power good signal terminal (PG). An RC delay circuit is connected between the power good signal terminal (PG) of the front-stage DC-DC power module and the enable control terminal (EN) of the rear-stage DC-DC power module. The RC delay circuit is used to adjust the power-on delay time of the rear-stage DC-DC power module. A discharge diode is connected in parallel between the enable control terminal (EN) and ground. The discharge diode is used to quickly release the charge stored in the capacitor of the RC delay circuit when the circuit is powered off.

2. The adjustable chip power-on sequence control circuit as described in claim 1, characterized in that, It includes four cascaded DC-DC power modules, namely the first DC-DC power module (P1 U1), the second DC-DC power module (P2 U1), the third DC-DC power module (P3 U1) and the fourth DC-DC power module (P4 U1); The second DC-DC power module (P2U1), the third DC-DC power module (P3U1), and the fourth DC-DC power module (P4U1) all have a discharge diode (D) connected in parallel between their enable control terminal (EN) and ground. The anode of the discharge diode (D) is grounded, and the cathode is electrically connected to the enable control terminal (EN).

3. The adjustable chip power-on sequence control circuit as described in claim 2, characterized in that, The input power terminal of the first DC-DC power module (P1 U1) is connected to a 12V DC voltage (VCC12V). Its enable control terminal (EN) is electrically connected to the input power terminal through a voltage divider resistor circuit. The voltage divider resistor circuit includes a first voltage divider resistor (P1 R3) and a second voltage divider resistor (P1 R8) connected in series between the 12V DC voltage (VCC12V) and ground. The enable control terminal (EN) is connected to the series node of the two.

4. The adjustable chip power-on sequence control circuit as described in claim 2, characterized in that, The enable control terminal (EN) of the second DC-DC power module (P2U1) is electrically connected to the power good signal terminal (3V3_PG) of the first DC-DC power module (P1U1) through a first series resistor (P2R8), and a first capacitor (P2C15) is connected in parallel between the enable control terminal (EN) and ground. The first series resistor (P2R8) and the first capacitor (P2C15) constitute an RC delay circuit.

5. The adjustable chip power-on sequence control circuit as described in claim 2, characterized in that, The enable control terminal (EN) of the fourth DC-DC power module (P4U1) is electrically connected to the power good signal terminal (1V2_PG) of the third DC-DC power module (P3U1) through a third series resistor (P4R8), and a third capacitor (P4C15) is connected in parallel between the enable control terminal (EN) and ground. The third series resistor (P4R8) and the third capacitor (P4C15) constitute an RC delay circuit.

6. The adjustable chip power-on sequence control circuit as described in claim 2, characterized in that, The first DC-DC power module (P1 U1) outputs a voltage of 3.3V (3V3), the second DC-DC power module (P2 U1) outputs a voltage of 1.8V (1V8), the third DC-DC power module (P3 U1) outputs a voltage of 1.2V (1V2), and the fourth DC-DC power module (P4 U1) outputs a voltage of 1.0V (1V0). The power-on sequence of the output voltages is 3.3V, 1.8V, 1.2V, and 1.0V.

7. The adjustable chip power-on sequence control circuit as described in claim 2, characterized in that, After the output voltage stabilizes, the power good signal terminal (3V3_PG) of the first DC-DC power module (P1 U1) outputs a high-level signal. This high-level signal provides a start signal to the enable control terminal (EN) of the second DC-DC power module (P2U1) through the first series resistor (P2R8).

8. The adjustable chip power-on sequence control circuit as described in claim 2, characterized in that, The resistance values ​​of the first series resistor (P2R8), the second series resistor (P3R8), and the third series resistor (P4R8), and the corresponding capacitance values ​​of the first capacitor (P2C15), the second capacitor (P3C15), and the third capacitor (P4C15) are adjustable to adjust the power-on delay time of the subsequent DC-DC power supply module.

9. The adjustable chip power-on sequence control circuit as described in claim 2, characterized in that, The discharge diode (D) is used to conduct when the circuit is powered off, quickly releasing the charge stored in the first capacitor (P2C15), the second capacitor (P3C15), and the third capacitor (P4C15), so that the voltage of the enable control terminal (EN) drops rapidly to the turn-off voltage. The output voltage terminals of the first DC-DC power module (P1 U1), the second DC-DC power module (P2 U1), the third DC-DC power module (P3 U1), and the fourth DC-DC power module (P4 U1) are all connected in parallel with a filter capacitor bank. The filter capacitor bank includes multiple filter capacitors (P1 C7-P1 C12, P2 C7-P2 C12, P3 C7-P3 C12, P4 C7-P4 C12) connected in parallel between the output voltage terminal and ground. The voltage obtained by the enable control terminal (EN) of the first DC-DC power module (P1 U1) through the voltage divider resistor circuit meets its startup voltage requirements, so as to ensure that the first DC-DC power module (P1 U1) is powered on before the subsequent DC-DC power module.

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