Low-Switching-Loss Modulation Method and System for Four-Level Split Inverter of SiC Devices

Abstract

The present invention belongs to the field of power electronics technology. The present invention relates to a low switching loss modulation method and system for a four-level split inverter of SiC devices. An i-phase final modulation wave is obtained according to the i-phase original sinusoidal modulation wave and a superimposed signal generated from the three-phase original sinusoidal modulation waves; an i-phase lower modulation wave, an i-phase upper modulation wave, and an i-phase intermediate modulation wave are obtained according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave, the DC bus voltage, and the DC bus intermediate capacitor voltage; an i-phase drive signal S i1 and an i-phase drive signal S i2 are generated according to the set upper-layer stacked carrier and the magnitude of the i-phase upper modulation wave, an i-phase drive signal S i3 and an i-phase drive signal S i4 are generated according to the set middle-layer stacked carrier and the magnitude of the i-phase intermediate modulation wave, and an i-phase drive signal S i5 and an i-phase drive signal S i6 are generated according to the set lower-layer stacked carrier and the magnitude of the i-phase lower modulation wave. The present invention can achieve equal voltage sharing of the DC bus capacitors, reduce the number of switching times, and reduce the switching loss.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, relates to inverter modulation technology, and specifically relates to a low-switching-loss modulation method and system for a four-level split inverter with SiC devices. Background Art

[0002] An inverter is a key device in power electronics systems such as new energy power generation and electric drive. Compared with traditional two-level inverters, four-level inverters have more output levels, can reduce the voltage stress of power switching devices, and are beneficial to reducing output current harmonics. Traditional four-level inverters use silicon (Si) material power switching devices, which have small switching losses and relatively slow switching speeds, restricting the performance of four-level inverters. Metal oxide semiconductor field effect transistors made of silicon carbide material (hereinafter referred to as: SiC MOSFET) are a new type of power semiconductor switching device, which has advantages such as small switching losses and fast switching speeds. Applying SiC MOSFETs to a highly reliable four-level split inverter can further increase its switching frequency, improve control accuracy and response speed.

[0003] However, the four-level split inverter with SiC devices has the following problems. First, if the four-level split inverter with SiC devices adopts the traditional modulation strategy, the capacitor voltages of the DC bus cannot be equalized, and the intermediate capacitor voltage of the DC bus will gradually decay to 0V during operation, resulting in an increase in output current harmonics. Second, if the four-level split inverter with SiC devices adopts the traditional modulation strategy, the number of switching times of SiC MOSFETs is large within one fundamental wave period, the switching losses are relatively large, the efficiency of the inverter is reduced, and the heat generation of SiC MOSFETs is increased. Summary of the Invention

[0004] In view of the above problems such as large switching losses in the prior art, the present invention provides a low-switching-loss modulation method and system for a four-level split inverter with SiC devices, which can equalize the capacitor voltages of the DC bus, reduce output current harmonics, thereby outputting a good current waveform, improving current quality, and at the same time can reduce the number of switching times of SiC devices, reduce switching losses, and improve the efficiency of the four-level split inverter with SiC devices.

[0005] In the first aspect of the present invention, a low-switching-loss modulation method for a four-level split inverter with SiC devices is provided, and its specific steps are as follows:

[0006] Superposition signal generation step: generating a superposition signal according to three-phase original sine modulation waves;

[0007] Modulation wave generation step: obtaining the final modulation wave of phase i according to the original sine modulation wave of phase i and the superposition signal, where i = A, B, C;

[0008] Three modulation wave generation steps: Obtain the lower modulation wave of phase i and the upper modulation wave of phase i based on the magnitude of the final modulation wave of phase i, the final modulation wave of phase i, and the DC bus voltage, and obtain the intermediate modulation wave of phase i based on the final modulation wave of phase i, the DC bus voltage, and the voltage of the intermediate capacitor of the DC bus;

[0009] Drive signal generation step: Generate the drive signal S of phase i according to the set upper-layer stacked carrier wave and the magnitude of the upper modulation wave of phase i i1 and the drive signal S of phase i i2 , generate the drive signal S of phase i according to the set middle-layer stacked carrier wave and the magnitude of the intermediate modulation wave of phase i i3 and the drive signal S of phase i i4 , generate the drive signal S of phase i according to the set lower-layer stacked carrier wave and the magnitude of the lower modulation wave of phase i i5 and the drive signal S of phase i i6 .

[0010] In some embodiments, in the superimposed signal generation step, the method for generating the superimposed signal according to the three-phase original sine modulation wave is as follows:

[0011] Subtract the original sine modulation wave of phase A from 1 to obtain the first signal s a1 , subtract the original sine modulation wave of phase B from 1 to obtain the second signal s b1 , subtract the original sine modulation wave of phase C from 1 to obtain the third signal s c1 ; Use the original sine modulation wave of phase A as the first comparison signal. If the first comparison signal > 0, then obtain the signal s au equal to the first signal s a1 , otherwise obtain the signal s au equal to the original sine modulation wave of phase A; Use the original sine modulation wave of phase B as the second comparison signal. If the second comparison signal > 0, then obtain the signal s bu equal to the second signal s b1 , otherwise obtain the signal s bu equal to the original sine modulation wave of phase B; Use the original sine modulation wave of phase C as the third comparison signal. If the third comparison signal > 0, then obtain the signal s cu equal to the third signal s c1 , otherwise obtain the signal s cu equal to the original sine modulation wave of phase C; Respectively for the signal s au 、signals bu and the signal s cu takes the absolute value to obtain the signal s a_u and the signal s b_u and the signal s c_u , take the signal s a_u and the signal s b_u and the signal s c_u The minimum of the three signals is the first minimum value s min1 ;

[0012] Add 1 to the original A-phase sinusoidal modulation wave to obtain the fourth signal s a2 , add 1 to the original B-phase sinusoidal modulation wave to obtain the fifth signal s b2 , add 1 to the original C-phase sinusoidal modulation wave to obtain the sixth signal s c2 ; Using the original A-phase sinusoidal modulation wave as the fourth comparison signal, if the fourth comparison signal ≤ 0, then obtain the signal s ad equal to the fourth signal s a2 , otherwise obtain the signal s ad equal to the original A-phase sinusoidal modulation wave; Using the original B-phase sinusoidal modulation wave as the fifth comparison signal, if the fifth comparison signal ≤ 0, then obtain the signal s bd equal to the fifth signal s b2 , otherwise obtain the signal s bd equal to the original B-phase sinusoidal modulation wave; Using the original C-phase sinusoidal modulation wave as the sixth comparison signal, if the sixth comparison signal ≤ 0, then obtain the signal s cd equal to the sixth signal s c2 , otherwise obtain the signal s cd equal to the original C-phase sinusoidal modulation wave; Respectively, take the absolute value of the signals s ad and the signal s bd and the signal s cd to obtain the signals s a_d and the signal s b_d and the signals c_d , take the signal s a_d , signal s b_d , signal s c_d The smallest of the three signals is the second smallest value s min2 ;

[0013] Take the first minimum value s min1 , the second smallest value s min2 The minimum value in is the third minimum value s min3 ;

[0014] Using the first minimum value s min1 Subtract the second smallest value s min2 The resulting difference s min Is the seventh comparison signal. If the difference s min > 0, then the signal c _ alpha Is equal to -1, otherwise the signal c _ alpha Is equal to 1;

[0015] The third minimum value s min3 Multiply by the signal c _ alpha To obtain the superimposed signal.

[0016] In some embodiments, in the modulation wave generation step, the method for obtaining the i-phase final modulation wave according to the i-phase original sine modulation wave and the superimposed signal is: after adding the i-phase original sine modulation wave and the superimposed signal, multiply by 300 to obtain the i-phase final modulation wave.

[0017] In some embodiments, in the three modulation wave generation step, the method for obtaining the i-phase lower modulation wave according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave, and the DC bus voltage is:

[0018] Multiply the DC bus voltage by -1 / 6 to obtain the first modulation wave s i11 , multiply the i-phase final modulation wave by 2 / 3 and then add -1 / 6 times the DC bus voltage to obtain the second modulation wave s i12 ;

[0019] If the i-phase final modulation wave > 0, the i-phase lower modulation wave is the first modulation waves i11 ; if the final modulation wave of phase i ≤ 0, the lower modulation wave of phase i is the second modulation wave s i12 .

[0020] In some embodiments, in the three modulation wave generation step, the method for obtaining the intermediate modulation wave of phase i based on the final modulation wave of phase i, the DC bus voltage, and the voltage of the intermediate capacitor of the DC bus is as follows: multiply the voltage of the intermediate capacitor of the DC bus by 3, divide by the DC bus voltage, then multiply by the final modulation wave of phase i, and finally multiply by 1 / 3 to obtain the intermediate modulation wave of phase i.

[0021] In some embodiments, the method for obtaining the upper modulation wave of phase i based on the magnitude of the final modulation wave of phase i, the final modulation wave of phase i, and the DC bus voltage is as follows:

[0022] Multiply the final modulation wave of phase i by 2 / 3 and then add 1 / 6 times the DC bus voltage to obtain the third modulation wave s i31 , multiply the DC bus voltage by 1 / 6 to obtain the fourth modulation wave s i32 ;

[0023] If the final modulation wave of phase i > 0, the upper modulation wave of phase i is the third modulation wave s i31 ; if the final modulation wave of phase i ≤ 0, the upper modulation wave of phase i is the fourth modulation wave s i32 .

[0024] In some embodiments, in the drive signal generation step, the method for generating the drive signal S of phase i based on the set upper stacked carrier wave and the magnitude of the upper modulation wave of phase i i1 and the drive signal S of phase i i2 is as follows: when the upper modulation wave of phase i ≥ the set upper stacked carrier wave, S i1 is at a high level and S i2 is at a low level; when the upper modulation wave of phase i < the set upper stacked carrier wave, S i1 is at a low level and S i2 is at a high level;

[0025] The method for generating the drive signal S of phase i and the drive signal S of phase i based on the set middle stacked carrier wave and the magnitude of the intermediate modulation wave of phase i i3 and the drive signal S of phase i i4 is as follows: when the intermediate modulation wave of phase i ≥ the set middle stacked carrier wave, S i3 is at a high level and S i4 is at a low level; when the intermediate modulation wave of phase i < the set middle stacked carrier wave, S i3 is at a low level and S i4 is at a high level;

[0026] Generate the i-phase drive signal S according to the set lower-layer stacked carrier wave and the magnitude of the i-phase lower modulation wave i5 and the i-phase drive signal S i6 The method is as follows: when the i-phase lower modulation wave ≥ the set lower-layer stacked carrier wave, S i5 is at a high level and S i6 is at a low level; when the i-phase lower modulation wave < the set lower-layer stacked carrier wave, S i5 is at a low level and S i6 is at a high level.

[0027] In the second aspect of the present invention, a low-switching-loss modulation system for a four-level split inverter of SiC devices is provided, which is used to implement the low-switching-loss modulation method for a four-level split inverter of SiC devices described in the first aspect of the present invention, and includes:

[0028] A superimposed signal generation module that generates a superimposed signal according to three-phase original sinusoidal modulation waves;

[0029] A modulation wave generation module that generates an i-phase final modulation wave according to the i-phase original sinusoidal modulation wave and the superimposed signal;

[0030] A three-modulation-wave generation module that generates an i-phase lower modulation wave and an i-phase upper modulation wave according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage, and generates an i-phase intermediate modulation wave according to the i-phase final modulation wave, the DC bus voltage and the DC bus intermediate capacitor voltage;

[0031] A drive signal generation module that generates the i-phase drive signal S i1 and the i-phase drive signal S i2 , generates the i-phase drive signal S i3 and the i-phase drive signal S i4 according to the set middle-layer stacked carrier wave and the magnitude of the i-phase intermediate modulation wave, and generates the i-phase drive signal S i5 and the i-phase drive signal S i6 .

[0032] In some embodiments, the three-modulation-wave generation module includes:

[0033] A lower modulation wave generation module that generates an i-phase lower modulation wave according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage;

[0034] An intermediate modulation wave generation module that generates an i-phase intermediate modulation wave according to the i-phase final modulation wave, the DC bus voltage and the DC bus intermediate capacitor voltage;

[0035] An upper modulation wave generation module that generates an i-phase upper modulation wave according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage.

[0036] In some embodiments, the drive signal generation module includes:

[0037] Logic module I, when the i-phase upper modulation wave ≥ the set upper-layer stacked carrier wave, outputs S i1 as a high level, S i2 as a low level; when the i-phase upper modulation wave < the set upper-layer stacked carrier wave, outputs S i1 as a low level, S i2 as a high level;

[0038] Logic module II, when the i-phase intermediate modulation wave ≥ the set middle-layer stacked carrier wave, outputs S i3 as a high level, S i4 as a low level; when the i-phase intermediate modulation wave < the set middle-layer stacked carrier wave, outputs S i3 as a low level, S i4 as a high level;

[0039] Logic module III, when the i-phase lower modulation wave ≥ the set lower-layer stacked carrier wave, outputs S i5 as a high level, S i6 as a low level; when the i-phase lower modulation wave < the set lower-layer stacked carrier wave, outputs S i5 as a low level, S i6 as a high level.

[0040] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0041] The low-switching-loss modulation method and system of the SiC device four-level split inverter provided by the present invention obtain the final modulation wave by superimposing signals, and obtain three modulation waves, namely the upper modulation wave, the intermediate modulation wave, and the lower modulation wave, according to the magnitude of the final modulation wave, the final modulation wave, the DC bus voltage, and the DC bus intermediate capacitor voltage. At any moment, the three modulation waves are clamped at a specific level U dc / 2, 0, - U dc / 2. On the one hand, it can achieve the equal voltage sharing of the DC bus capacitors, thereby outputting a good current waveform and improving the power quality. On the other hand, after the clamping level is compared with the upper-layer, middle-layer, and lower-layer three-layer stacked carrier waves, it will not cause the SiC MOSFET to switch, and can effectively reduce the switching loss. Description of the Drawings

[0042] Figure 1 is the circuit diagram of the fluctuating bus SiC device isolated output inverter described in the embodiment of the present invention;

[0043] Figure 2 is the flowchart of the low-switching-loss modulation method of the SiC device four-level split inverter described in the embodiment of the present invention;

[0044] Figure 3 Schematic diagram of the superposition signal generation according to the embodiment of the present invention;

[0045] Figure 4 Schematic diagram of the modulation wave generation according to the embodiment of the present invention;

[0046] Figure 5 Schematic diagram of the three modulation wave generation according to the embodiment of the present invention;

[0047] Figure 6 Schematic diagram of the drive signal generation according to the embodiment of the present invention;

[0048] Figure 7 Schematic diagram of the A-phase three modulation wave generation link according to the embodiment of the present invention;

[0049] Figure 8 Schematic diagram of the A-phase drive signal generation link according to the embodiment of the present invention;

[0050] Figure 9 The upper-layer stacked carrier U c1 and the A-phase upper modulation wave s Az3 Waveform diagram;

[0051] Figure 10 The middle-layer stacked carrier U c2 and the A-phase intermediate modulation wave s Az2 Waveform diagram;

[0052] Figure 11 The lower-layer stacked carrier U c3 and the A-phase lower modulation wave s Az1 Waveform diagram;

[0053] Figure 12 Structure block diagram of the low switching loss modulation system of the SiC device four-level split inverter according to the embodiment of the present invention;

[0054] Figure 13 Waveform diagram of the three-phase output current using the traditional stacked carrier modulation method;

[0055] Figure 14 Waveform diagram of the three-phase output current using the low switching loss modulation method and system of the SiC device four-level split inverter according to the embodiment of the present invention;

[0056] Figure 15Schematic diagram of the driving signal waveform of phase A using the traditional stacked carrier modulation method;

[0057] Figure 16 Schematic diagram of the driving signal waveform of phase A using the low-switching-loss modulation method and system of the four-level split inverter with SiC devices according to the embodiments of the present invention.

[0058] In the figure, 1. superimposed signal generation module, 2. modulation wave generation module, 3. triple modulation wave generation module, 4. driving signal generation module, 5. phase A modulation module, 6. phase B modulation module, 7. phase C modulation module. Detailed implementation manners

[0059] Next, the present invention will be specifically described through exemplary embodiments in conjunction with the accompanying drawings. However, it should be understood that, without further description, the elements, structures, and features in one embodiment can also be beneficially combined into other embodiments.

[0060] Figure 1 The main topological circuit of the four-level split inverter with SiC devices shown, where U dc is the DC bus voltage, C 1 , C 2 , C 3 are the DC bus capacitors; Q a1 to Q a6 are the SiC MOSFET power switch devices of phase A, D a1 to D a10 are the SiC Schottky diodes of phase A, L a1 to L a6 are the isolation inductors of phase A; i a , i b , i c are the three-phase currents; L a , L b , L c are the three-phase load inductors, R a , R b , R c are the three-phase load resistors. It should be noted that since the three-phase circuits of A, B, and C are completely symmetrical and the topological circuit structures of the three phases of A, B, and C are exactly the same, Figure 1 only the topological circuit structure of phase A is given in the figure, and the topological circuit structures of phase B and phase C are the same as that of phase A.

[0061] Continue to refer to Figure 1, since the ABC three-phase bridge arms are completely symmetrical, the connection method of the main circuit is illustrated by taking phase A as an example. The DC voltage source U dc provides the overall voltage for the DC bus. The DC bus is connected in series with DC bus capacitors C 1 , DC bus capacitors C 2 , and DC bus capacitors C 3 from top to bottom; U dc One end of C 1 is connected to point P at one end of U dc , and the other end of C 3 is connected to point N. C 1 and C 2 are connected to point O 1 ; C 2 and C 3 are connected to point O 2 ; One end of Q a1 and D a1 is connected to the positive pole P point of the DC bus. The other end of D a1 is connected to Q a2 at point X a1 . The other end of Q a1 is connected to D a2 at point X a2 ; a2 The other end of Q is connected to the other end of D a2 and one end of Q a3 , D a3 are connected through point X a3 ; a3 The other end of Q is connected to D a4 at point X a4 . The other end of D a3 is connected to Q a4 at point X a5 . The other end of Q a4 is connected to D a4 and the other end of Q a5 , D a5 are connected through point X a6 . The other end of D a5 is connected to Q a6 at point X a7 . The other end of Q a5 is connected to D a6 at point X a8 . The other end of Q a6With D a6 The other end is connected to the negative N point of the DC bus. The isolation inductor L a3 and L a4 are in parallel, and one end is connected in parallel to point X a13 Point X a4 and X a13 are connected through inductor L a3 Point X a5 and X a13 are connected through inductor L a4 The isolation inductor L a1 and L a2 are in parallel, and one end is connected in parallel to point X a9 Point X a1 and X a9 are connected through inductor L a1 Point X a2 and X a9 are connected through inductor L a2 D a7 One end of is connected to the parallel combination of L a1 and L a2 at point X a9 The other end is connected to D a8 at point X a10 D a8 The other end is connected to point X a6 The isolation inductor L a5 and L a6 are in parallel, and one end is connected in parallel to point X a12 Point X a7 and X a12 are connected through inductor L a5 Point X a8 and X a12 are connected through inductor L a6 D a9 One end is connected to point X a3 The other end is connected to D a10 at point X a11 D a10 The other end is connected to the parallel combination of L a5 and L a6 at point X a12 O 1 Point O is connected to point X a10 Point O 2 is connected to point X a11 L a is in series with R a Point X a13 is connected to the load neutral point O through the series combination of L a and R a The connection mode of the main circuits of phase B and phase C is the same as that of phase A, which will not be elaborated here.

[0062] For the above four-level split inverter of SiC devices, a low-switching-loss modulation method and system for the four-level split inverter of SiC devices provided by the present invention generate a superimposed signal required for generating a final modulation wave according to three-phase original sinusoidal modulation waves, and the three-phase original sinusoidal modulation waves are superimposed with the superimposed signal to generate three-phase final modulation waves. Three modulation waves are generated from the three final modulation waves, the DC bus voltage, and the DC bus intermediate capacitor voltage, and the three modulation waves are compared with a stacked carrier wave to generate drive signals. On the one hand, the equal voltage sharing of the DC bus capacitors can be realized, so as to output a good current waveform and improve the power quality. On the other hand, after the clamping level is compared with the upper, middle, and lower three-layer stacked carrier waves, the SiC MOSFET switch will not act, and the switching loss can be effectively reduced.

[0063] The following will describe in detail the above low-switching-loss modulation method and system for the four-level split inverter of SiC devices of the present invention with reference to the drawings and embodiments.

[0064] See Figure 2 , an embodiment of the first aspect of the present invention provides a low-switching-loss modulation method for a four-level split inverter of SiC devices, and its specific steps are as follows:

[0065] S1. Stacked carrier wave generation step: Generate a superimposed signal according to three-phase original sinusoidal modulation waves.

[0066] Specifically, see Figure 3 , the method for generating a superimposed signal according to three-phase original sinusoidal modulation waves is as follows:

[0067] 1 minus the original sinusoidal modulation wave of phase A s A Get the first signal s a1 , 1 minus the original sinusoidal modulation wave of phase B s B Get the second signal s b1 , 1 minus the original sinusoidal modulation wave of phase C s C Get the third signal s c1 ; Use the original sinusoidal modulation wave of phase A s A As the first comparison signal s ac1 , if the first comparison signal s ac1 >0, then get the signal s au Equal to the first signal s a1 , otherwise get the signal s auEqual to the original sine modulation wave of phase A s A ; Using the original sine modulation wave of phase B s B as the second comparison signal s bc1 , if the second comparison signal s bc1 > 0, then the obtained signal s bu is equal to the second signal s b1 , otherwise the obtained signal s bu is equal to the original sine modulation wave of phase B s B ; Using the original sine modulation wave of phase C s C as the third comparison signal s cc1 , if the third comparison signal s cc1 > 0, then the obtained signal s cu is equal to the third signal s c1 , otherwise the obtained signal s cu is equal to the original sine modulation wave of phase C s C ; Taking the absolute value of the signals s au , signal s bu , signal s cu to obtain signals s a_u , signal s b_u , signal s c_u , taking the minimum signal among the signals s a_u , signal s b_u , signal s c_u as the first minimum value s min1 ;

[0068] 1 plus the original sine modulation wave of phase A s A to obtain the fourth signal s a2 , 1 plus the original sine modulation wave of phase B s B to obtain the fifth signal s b2, the original sinusoidal modulation wave of phase C plus 1 s C Obtain the sixth signal s c2 ; Use the original sinusoidal modulation wave of phase A s A as the fourth comparison signal s ac2 , if the fourth comparison signal s ac2 ≤0, then obtain the signal s ad equal to the fourth signal s a2 , otherwise obtain the signal s ad equal to the original sinusoidal modulation wave of phase A s A ; Use the original sinusoidal modulation wave of phase B s B as the fifth comparison signal s bc2 , if the fifth comparison signal s bc2 ≤0, then obtain the signal s bd equal to the fifth signal s b2 , otherwise obtain the signal s bd equal to the original sinusoidal modulation wave of phase B s B ; Use the original sinusoidal modulation wave of phase C s C as the sixth comparison signal s cc2 , if the sixth comparison signal s cc2 ≤0, then obtain the signal s cd equal to the sixth signal s c2 , otherwise obtain the signal s cd equal to the original sinusoidal modulation wave of phase C s C ; Take the absolute value of the signals s ad and the signals s bd and the signals s cd to obtain the signals s a_d and the signals s b_d and the signals s c_d , take the signal s a_d, Signal s b_d , Signal s c_d The smallest signal among the three signals is the second minimum value s min2 ;

[0069] Take the first minimum value s min1 , the second minimum value s min2 The minimum value among them is the third minimum value s min3 ;

[0070] Using the first minimum value s min1 Subtract the second minimum value s min2 The obtained difference s min Is the seventh comparison signal. If the difference s min > 0, then the obtained signal c _ alpha Is equal to -1, otherwise the obtained signal c _ alpha Is equal to 1;

[0071] The third minimum value s min3 Multiply by the signal c _ alpha To obtain the superimposed signal s z .

[0072] S2. Modulation wave generation step: Obtain the final modulation wave of the i-phase according to the original sine modulation wave of the i-phase and the superimposed signal.

[0073] Specifically, in some embodiments, refer to Figure 4 , the method for obtaining the final modulation wave of the i-phase according to the original sine modulation wave of the i-phase and the superimposed signal is: After adding the original sine modulation wave of the i-phase and the superimposed signal, multiply by 300 to obtain the final modulation wave of the i-phase.

[0074] Specifically, continue to refer to Figure 4 , the original sine modulation wave of the A-phase s A Add the superimposed signal s z Then multiply by 300 to obtain the final modulation wave of the A-phase s Az . The original sine modulation wave of the B-phase s B Add the superimposed signal s zAfter that, multiply by 300 to obtain the final modulation wave of phase B s Bz 。The original sine modulation wave of phase C s C Plus the superimposed signal s z After that, multiply by 300 to obtain the final modulation wave of phase C s Cz 。

[0075] S3. Three modulation wave generation steps: Obtain the lower modulation wave and upper modulation wave of phase i according to the magnitude of the final modulation wave of phase i, the final modulation wave of phase i, and the DC bus voltage, and obtain the intermediate modulation wave of phase i according to the final modulation wave of phase i, the DC bus voltage, and the voltage of the intermediate capacitor of the DC bus.

[0076] Specifically, in some embodiments, refer to Figure 5 , the method for obtaining the lower modulation wave of phase i according to the magnitude of the final modulation wave of phase i, the final modulation wave of phase i, and the DC bus voltage is:

[0077] The DC bus voltage U dc Multiply by -1 / 6 to obtain the first modulation wave s i11 , the final modulation wave of phase i s iz Multiply by 2 / 3 and then add -1 / 6 times the DC bus voltage U dc To obtain the second modulation wave s i12 ;

[0078] If the final modulation wave of phase i s iz > 0, the lower modulation wave of phase i s iz1 Is the first modulation wave s i11 ; If the final modulation wave of phase i s iz ≤0, the lower modulation wave of phase i s iz1 Is the second modulation wave s i12 。

[0079] Specifically, in some embodiments, continue to refer to Figure 5 , the method for obtaining the intermediate modulation wave of phase i according to the final modulation wave of phase i, the DC bus voltage, and the voltage of the intermediate capacitor of the DC bus is: The voltage of the intermediate capacitor of the DC bus U dc2 Multiply by 3 and divide by the DC bus voltage U dc After that, multiply by the final modulation wave of phase i siz , multiply by 1 / 3 to obtain the intermediate modulation wave of phase i s iz2 .

[0080] Specifically, in some embodiments, continue to refer to Figure 5 , according to the magnitude of the final modulation wave of phase i, the method for the final modulation wave of phase i and the upper modulation wave of the DC bus voltage on phase i is as follows:

[0081] The final modulation wave of phase i s iz Multiply by 2 / 3 and then add 1 / 6 times the DC bus voltage U dc To obtain the third modulation wave s i31 , the DC bus voltage U dc Multiply by 1 / 6 to obtain the fourth modulation wave s i32 ;

[0082] If the final modulation wave of phase i s iz > 0, the upper modulation wave of phase i s iz3 Is the third modulation wave s i31 ; If the final modulation wave of phase i s iz ≤0, the upper modulation wave of phase i s iz3 Is the fourth modulation wave s i32 .

[0083] S4, driving signal generation step: Refer to Figure 6 , according to the set upper-layer stacked carrier U c1 , the magnitude of the upper modulation wave of phase i s iz3 Generate the driving signal S of phase i i1 And the driving signal S of phase i i2 , according to the set middle-layer stacked carrier U c2 , the magnitude of the intermediate modulation wave of phase i s iz2 Generate the driving signal S of phase i i3 And the driving signal S of phase i i4 , according to the set lower-layer stacked carrier U c3 , the magnitude of the lower modulation wave of phase i s iz1 Generate the driving signal S of phase i i5 And the driving signal S of phase i i6 .

[0084] Specifically, in some embodiments, continue to refer to Figure 6 , in the driving signal generation step, according to the set upper-layer stacked carrier U c1 , the i-phase upper modulation wave s iz3 , the method for generating the i-phase driving signal S i1 and the i-phase driving signal S i2 is as follows: when the i-phase upper modulation wave s iz3 ≥ the set upper-layer stacked carrier U c1 , the driving signal S i1 is at a high level, and the driving signal S i2 is at a low level; when the i-phase upper modulation wave s iz3 < the set upper-layer stacked carrier U c1 , the driving signal S i1 is at a low level, and the driving signal S i2 is at a high level.

[0085] Specifically, in some embodiments, continue to refer to Figure 6 , according to the set middle-layer stacked carrier U c2 , the i-phase intermediate modulation wave s iz2 , the method for generating the i-phase driving signal S i3 and the i-phase driving signal S i4 is as follows: when the i-phase intermediate modulation wave s iz2 ≥ the set middle-layer stacked carrier U c2 , the driving signal S i3 is at a high level, and the driving signal S i4 is at a low level; when the i-phase intermediate modulation wave s iz2 < the set middle-layer stacked carrier U c2 , the driving signal S i3 is at a low level, and the driving signal S i4 is at a high level.

[0086] Specifically, in some embodiments, continue to refer to Figure 6 , according to the set lower-layer stacked carrier U c3 , the i-phase lower modulation wave s iz1 , the method for generating the i-phase driving signal S i5 and the i-phase driving signal S i6The method is as follows: the i-phase lower modulation wave s iz1 ≥ the set lower-layer stacked carrier wave U c3 When, the drive signal S i5 is at a high level, and the drive signal S i6 is at a low level; the i-phase lower modulation wave s iz1 < the set lower-layer stacked carrier wave U c3 When, the drive signal S i5 is at a low level, and the drive signal S i6 is at a high level.

[0087] In Figures 3 - 6 In each of the links shown, the signal is judged and selected through the selection switch Switch. The Switch switch is divided into an input side and an output side. On the input side, there are three-way signals input. The terminals “+” and “-” are signal input terminals, the terminal in is a comparison signal input terminal, and the terminal O is a signal output terminal. When the signal of the comparison signal terminal in is greater than 0, the signal received by the “+” terminal is output at the O terminal; when the comparison signal received by the in terminal is less than 0, the signal received by the “-” terminal is output at the O terminal.

[0088] It should be noted that since the A-phase modulation, B-phase modulation, and C-phase regulation are the same, the modulation principle of the above method will be introduced below taking the A-phase regulation as an example.

[0089] See Figure 7 , in the A-phase three-modulation wave generation link, the DC bus voltage U dc is multiplied by -1 / 6 to obtain the first modulation wave s A11 , and the A-phase final modulation wave s Az is multiplied by 2 / 3 and then added with -1 / 6 times the DC bus voltage U dc to obtain the second modulation wave s A12 ; if the A-phase final modulation wave s Az > 0, the A-phase lower modulation wave s Az1 is the first modulation wave s A11 ; if the A-phase final modulation wave s Az ≤ 0, the A-phase lower modulation wave s Az1 is the second modulation wave s A12 . The DC bus intermediate capacitor voltage U dc2Multiply by 3 and divide by the DC bus voltage U dc Then, multiply by the final modulation wave of phase A s Az And then multiply by 1 / 3 to obtain the intermediate modulation wave of phase A s Az2 . The final modulation wave of phase A s Az Multiply by 2 / 3 and add 1 / 6 times the DC bus voltage U dc To obtain the third modulation wave s A31 , the DC bus voltage U dc Multiply by 1 / 6 to obtain the fourth modulation wave s A32 ;

[0090] If the final modulation wave of phase A s Az > 0, the upper modulation wave of phase A s Az3 Is the third modulation wave s A31 ; if the final modulation wave of phase A s Az ≤0, the upper modulation wave of phase A s Az3 Is the fourth modulation wave s A32 .

[0091] See Figure 8 , in the generation link of the driving signal of phase A, when the upper modulation wave of phase A s Az3 ≥ the set upper-layer stacked carrier wave U c1 , the driving signal S A1 Is at a high level, and the driving signal S A2 Is at a low level; when the upper modulation wave of phase A s Az3 < the set upper-layer stacked carrier wave U c1 , the driving signal S A1 Is at a low level, and the driving signal S A2 Is at a high level. When the intermediate modulation wave of phase A s Az2 ≥ the set middle-layer stacked carrier wave U c2 , the driving signal S A3 Is at a high level, and the driving signal S A4 Is at a low level; when the intermediate modulation wave of phase A s Az2 < the set middle-layer stacked carrier wave U c2When the driving signal S A3 is at a low level, the driving signal S A4 is at a high level. When the lower modulation wave of phase A s Az1 ≥ the set lower-layer stacked carrier wave U c3 the driving signal S A5 is at a high level, and the driving signal S A6 is at a low level; when the lower modulation wave of phase A s Az1 < the set lower-layer stacked carrier wave U c3 the driving signal S A5 is at a low level, and the driving signal S A6 is at a high level.

[0092] To more intuitively show the basic principle of the low-switching-loss modulation method of the SiC device four-level split inverter, Figure 9 the upper-layer stacked carrier wave U c1 and the upper modulation wave of phase A s Az3 are shown in waveform, Figure 10 the middle-layer stacked carrier wave U c2 and the intermediate modulation wave of phase A s Az2 are shown in waveform, Figure 11 the lower-layer stacked carrier wave U c3 and the lower modulation wave of phase A s Az1 are shown in waveform. It can be seen that at any moment, the lower modulation wave of phase A s Az1 , the intermediate modulation wave of phase A s Az2 , and the upper modulation wave of phase A s Az3 are all clamped at a specific level U dc / 2, 0, - U dc / 2. Through the above modulation method, on the one hand, the equal voltage sharing of the DC bus capacitors can be realized, so as to output a good current waveform and improve the power quality. On the other hand, after the clamping level is compared with the stacked three-carrier wave, the SiC MOSFET switch will not act, and the switching loss can be effectively reduced.

[0093] The above specifically introduces the driving signals S A1 , S A2 , S A3 , S A4 , S A5 , S A6In the generation process, the driving signal generation methods for the B-phase and C-phase are the same, and will not be elaborated here.

[0094] See Figure 12 , in the embodiment of the second aspect of the present invention, a low-switching-loss modulation system for a SiC device four-level split inverter is provided, which is used to implement the low-switching-loss modulation method for the SiC device four-level split inverter described in the embodiment of the first aspect of the present invention. It includes a superimposed signal generation module 1, a modulation wave generation module 2, an A-phase modulation module 5, a B-phase modulation module 6, and a C-phase modulation module 7, which are three-phase single-carrier modulation modules. Each phase modulation module includes a three-modulation wave generation module 3 and a driving signal generation module 4.

[0095] The superimposed signal generation module 1 generates a superimposed signal according to the three-phase original sinusoidal modulation waves.

[0096] The modulation wave generation module 2 generates the i-phase final modulation wave according to the i-phase original sinusoidal modulation wave and the superimposed signal.

[0097] The three-modulation wave generation module 3 generates the i-phase lower modulation wave and the i-phase upper modulation wave according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave, and the DC bus voltage, and generates the i-phase intermediate modulation wave according to the i-phase final modulation wave, the DC bus voltage, and the DC bus intermediate capacitor voltage.

[0098] The driving signal generation module 4 generates the i-phase driving signal S i1 and the i-phase driving signal S i2 according to the set upper-layer stacked carrier and the magnitude of the i-phase upper modulation wave, and generates the i-phase driving signal S i3 and the i-phase driving signal S i4 according to the set middle-layer stacked carrier and the magnitude of the i-phase intermediate modulation wave, and generates the i-phase driving signal S i5 and the i-phase driving signal S i6 .

[0099] In some embodiments, the three-modulation wave generation module includes:

[0100] The lower modulation wave generation module generates the i-phase lower modulation wave according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave, and the DC bus voltage;

[0101] The intermediate modulation wave generation module generates the i-phase intermediate modulation wave according to the i-phase final modulation wave, the DC bus voltage, and the DC bus intermediate capacitor voltage;

[0102] The upper modulation wave generation module generates the i-phase upper modulation wave according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave, and the DC bus voltage.

[0103] In some embodiments, the drive signal generation module includes:

[0104] Logic module Ⅰ, when the i-phase upper modulation wave ≥ the set upper-layer stacked carrier wave, outputs S i1 as a high level, S i2 as a low level; when the i-phase upper modulation wave < the set upper-layer stacked carrier wave, outputs S i1 as a low level, S i2 as a high level;

[0105] Logic module Ⅱ, when the i-phase intermediate modulation wave ≥ the set middle-layer stacked carrier wave, outputs S i3 as a high level, S i4 as a low level; when the i-phase intermediate modulation wave < the set middle-layer stacked carrier wave, outputs S i3 as a low level, S i4 as a high level;

[0106] Logic module Ⅲ, when the i-phase lower modulation wave ≥ the set lower-layer stacked carrier wave, outputs S i5 as a high level, S i6 as a low level; when the i-phase lower modulation wave < the set lower-layer stacked carrier wave, outputs S i5 as a low level, S i6 as a high level.

[0107] To verify the effectiveness of the above-mentioned SiC device four-level split inverter low-switching-loss modulation method and system of the present invention, simulation verification is carried out in MATLAB / Simulink. The DC bus voltage is 600V, the three DC bus capacitors are 1000 μF, the load resistance is 30 Ω, and the load inductance is 2 mH. In the simulation model, for the SiC device four-level split inverter, the traditional fixed-layer stacked triangular carrier modulation method and the SiC device four-level split inverter low-switching-loss modulation method and system proposed by the present invention are respectively used for modulation. Figure 13 The three-phase output current waveforms using the traditional fixed-layer stacked triangular carrier modulation method are given. Since it does not have the function of stabilizing the DC bus capacitor voltage, during the operation process, the intermediate bus capacitor voltage gradually decays to 0, and the corresponding three-phase current is severely distorted. Through Fourier analysis, the total harmonic distortion rates THD of the partial A, B, and C phase currents in the dynamic process are 4.54%, 4.92%, and 4.81% respectively. Figure 14 The three-phase current waveforms using the SiC device four-level split inverter low-switching-loss modulation method and system proposed by the present invention are given. Since the proposed method has the function of stabilizing the DC bus capacitor voltage and the three capacitor voltages of the DC bus are balanced, the sinusoidality of the three-phase output current waveforms is significantly improved. Through Fourier analysis, the total harmonic distortion rates THD of the A, B, and C phase currents are 2.49%, 2.50%, and 2.51% respectively.

[0108] Figure 15 The waveform of the driving signal of phase A using the traditional fixed-layer triangular carrier modulation method is given; Figure 16 The waveform of the driving signal of phase A using the low-switching-loss modulation method and system of the four-level split inverter with SiC devices proposed in the present invention is given. By comparison Figure 15 and Figure 16 , it can be seen that using the low-switching-loss modulation method and system of the four-level split inverter with SiC devices proposed in the present invention can reduce the switching times of SiC MOSFETs, effectively reduce the switching loss, and improve the efficiency of the four-level split inverter with SiC devices.

[0109] The above embodiments are used to explain the present invention, rather than limit the present invention. Any modifications and changes made to the present invention within the spirit and scope of the claims of the present invention fall within the protection scope of the present invention.

Claims

1. A low switching loss modulation method for a SiC device four-level split inverter, characterized in that: The specific steps are: The superposition signal generation step is as follows: the superposition signal is generated according to the three-phase original sinusoidal modulation wave; the method for generating the superposition signal according to the three-phase original sinusoidal modulation wave is as follows: 1 minus the original sinusoidal modulation wave of phase A to obtain the first signal s a1 , 1 minus the original sinusoidal modulation wave of phase B to obtain the second signal s b1 , 1 minus the C-phase original sinusoidal modulation wave to obtain the third signal s c1 ; Take the original sinusoidal modulation wave of phase A as the first comparison signal. If the first comparison signal>0, the signal s au Equal to the first signal s a1 Otherwise, the signal s au Equal to the original sinusoidal modulation wave of phase A; the original sinusoidal modulation wave of phase B is used as the second comparison signal. If the second comparison signal>0, the signal is obtained. s bu Equal to the second signal s b1 Otherwise, the signal s bu Equal to the original sinusoidal modulation wave of phase B; The original sinusoidal modulation wave of phase C is used as the third comparison signal. If the third comparison signal > 0, the signal is obtained. s cu Equal to the third signal s c1 Otherwise, the signal s cu Equal to the original sinusoidal modulation wave of phase C; respectively s au ,Signal s bu ,Signal s cu Take the absolute value to get the signal s a_u ,Signal s b_u ,Signal s c_u , get the signal s a_u ,Signal s b_u ,Signal s c_u The minimum signal among the three signals is the first minimum value s min1 ; 1 plus the original sinusoidal modulation wave of phase A to obtain the fourth signal s a2 , 1 plus the original sinusoidal modulation wave of phase B to obtain the fifth signal s b2 , 1 plus the original sinusoidal modulation wave of phase C to obtain the sixth signal s c2 ; Take the original sinusoidal modulation wave of phase A as the fourth comparison signal. If the fourth comparison signal ≤ 0, the signal is obtained. s ad Equal to the fourth signal s a2 Otherwise, the signal s ad Equal to the original sinusoidal modulation wave of phase A; the original sinusoidal modulation wave of phase B is used as the fifth comparison signal. If the fifth comparison signal ≤ 0, the signal is obtained. s bd Equal to the fifth signal s b2 Otherwise, the signal s bd Equal to the original sinusoidal modulation wave of phase B; The original sinusoidal modulation wave of phase C is used as the sixth comparison signal. If the sixth comparison signal is ≤0, the signal is obtained. s cd Equal to the sixth signal s c2 Otherwise, the signal s cd Equal to the original sinusoidal modulation wave of phase C; respectively s ad ,Signal s bd ,Signal s cd Take the absolute value to get the signal s a_d ,Signal s b_d ,Signal s c_d , get the signal s a_d ,Signal s b_d ,Signal s c_d The smallest signal among the three signals is the second smallest value s min2 ; Take the first minimum value s min1 , the second minimum s min2 The minimum value in is the third smallest value s min3 ; Take the first minimum s min1 Subtract the second smallest value s min2 The difference obtained s min is the seventh comparison signal. If the difference s min >0, then the signal is obtained c _ alpha Equal to -1, otherwise get a signal c _ alpha is equal to 1; The third minimum s min3 Multiply the signal c _ alpha Obtaining a superimposed signal; Modulation wave generation steps: obtain the final modulation wave of phase i according to the original sinusoidal modulation wave of phase i and the superimposed signal, i=A, B, C; Three modulation wave generation steps: according to the size of the final modulation wave of phase i, the final modulation wave of phase i and the DC bus voltage, obtain the lower modulation wave of phase i and the upper modulation wave of phase i; according to the final modulation wave of phase i, the DC bus voltage and the DC bus intermediate capacitor voltage, obtain the intermediate modulation wave of phase i; The method of obtaining the lower modulation wave of phase i according to the size of the final modulation wave of phase i, the final modulation wave of phase i and the DC bus voltage is: The DC bus voltage is multiplied by -1 / 6 to obtain the first modulation wave s i11 The final modulation wave of phase i is multiplied by 2 / 3 and then added with -1 / 6 times the DC bus voltage to obtain the second modulation wave s i12 ; If the final modulation wave of phase i>0, the modulation wave of phase i is the first modulation wave s i11 ; If the final modulation wave of phase i is ≤0, the modulation wave of phase i is the second modulation wave s i12 ; According to the size of the final modulation wave of phase i, the final modulation wave of phase i and the modulation wave on phase i of the DC bus voltage, the method is: The final modulation wave of phase i is multiplied by 2 / 3 and then added with 1 / 6 of the DC bus voltage to obtain the third modulation wave. s i31 , multiply the DC bus voltage by 1 / 6 to get the fourth modulation wave s i32 ; If the final modulation wave of phase i>0, the modulation wave on phase i is the third modulation wave s i31 ; If the final modulation wave of phase i is ≤0, the modulation wave on phase i is the fourth modulation wave s i32 ; The method of obtaining the intermediate modulation wave of phase i according to the final modulation wave of phase i, the DC bus voltage and the intermediate capacitor voltage of the DC bus is as follows: the intermediate capacitor voltage of the DC bus is multiplied by 3 and divided by the DC bus voltage, multiplied by the final modulation wave of phase i, and then multiplied by 1 / 3 to obtain the intermediate modulation wave of phase i; Driving signal generation step: Generate the i-phase driving signal S according to the size of the upper layer stacked carrier and the i-phase modulation wave i1 and i-phase drive signal S i2 , according to the size of the set middle layer stacked carrier and the i phase intermediate modulation wave, the i phase drive signal S is generated i3 and i-phase drive signal S i4 , according to the setting of the lower layer stacked carrier and the size of the i-phase down modulation wave, the i-phase drive signal S is generated. i5 and i-phase drive signal S i6 .

2. The low switching loss modulation method for a SiC device four-level split inverter according to claim 1, characterized in that: In the modulation wave generation step, the method for obtaining the final modulation wave of phase i according to the original sinusoidal modulation wave of phase i and the superimposed signal is: the original sinusoidal modulation wave of phase i is added with the superimposed signal and then multiplied by 300 to obtain the final modulation wave of phase i.

3. The low switching loss modulation method for a SiC device four-level split inverter according to claim 1, characterized in that: In the driving signal generating step, the i-phase driving signal S is generated according to the setting of the upper layer stacked carrier and the magnitude of the i-phase modulation wave. i1 and i-phase drive signal S i2 The method is: when the modulation wave on phase i is greater than or equal to the upper layer stacked carrier, S i1 is high level, S i2 When the modulation wave on phase i is less than the upper layer stacked carrier, S i1 is low level, S i2 is high level; The i-phase drive signal S is generated by setting the size of the middle-layer stacked carrier and the i-phase intermediate modulation wave. i3 and i-phase drive signal S i4 The method is: when the intermediate modulation wave of phase i is greater than or equal to the set middle layer stacked carrier, S i3 is high level, S i4 When the intermediate modulation wave of phase i is less than the set middle layer stacked carrier wave, S i3 is low level, S i4 is high level; The i-phase drive signal S is generated by setting the lower layer stacked carrier and the size of the i-phase down modulation wave. i5 and i-phase drive signal S i6 The method is: when the modulation wave of phase i is greater than or equal to the lower stacked carrier, S i5 is high level, S i6 is low level; when the modulation wave of phase i is less than the set lower layer stacked carrier, S i5 is low level, S i6 is high level.

4. A low switching loss modulation system for a four-level split inverter of a SiC device, used to implement a low switching loss modulation method for a four-level split inverter of a SiC device as claimed in any one of claims 1 to 3, characterized in that: include: A superposition signal generating module generates a superposition signal according to the three-phase original sinusoidal modulation wave; A modulation wave generation module generates an i-phase final modulation wave according to an i-phase original sinusoidal modulation wave and a superimposed signal; Three modulation wave generation modules, generating an i-phase lower modulation wave and an i-phase upper modulation wave according to the size of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage, and generating an i-phase intermediate modulation wave according to the i-phase final modulation wave, the DC bus voltage and the DC bus intermediate capacitor voltage; The driving signal generation module generates the i-phase driving signal S according to the size of the upper layer stacked carrier and the i-phase modulation wave. i1 and i-phase drive signal S i2 , according to the size of the set middle layer stacked carrier and the i phase intermediate modulation wave, the i phase drive signal S is generated i3 and i-phase drive signal S i4 , according to the setting of the lower layer stacked carrier and the size of the i-phase down modulation wave, the i-phase drive signal S is generated. i5 and i-phase drive signal S i6 .

5. The SiC device four-level split inverter low switching loss modulation system according to claim 4, characterized in that: The three-modulation wave generation module includes: A down-modulation wave generating module generates an i-phase down-modulation wave according to the magnitude of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage; An intermediate modulation wave generating module generates an i-phase intermediate modulation wave according to an i-phase final modulation wave, a DC bus voltage and a DC bus intermediate capacitor voltage; The upper modulation wave generating module generates the i-phase upper modulation wave according to the size of the i-phase final modulation wave, the i-phase final modulation wave and the DC bus voltage.

6. The SiC device four-level split inverter low switching loss modulation system according to claim 4, characterized in that: The driving signal generating module comprises: Logic module I, when the modulation wave on phase i ≥ the set upper layer stacked carrier, output S i1 is high level, S i2 When the modulation wave on phase i is less than the set upper layer stacked carrier, the output S i1 is low level, S i2 is high level; Logic module II, when the intermediate modulation wave of phase i ≥ the set middle layer stacked carrier, output S i3 is high level, S i4 When the intermediate modulation wave of phase i is less than the set middle layer stacked carrier wave, the output S i3 is low level, S i4 is high level; Logic module III, when the modulation wave of phase i is greater than or equal to the set lower layer stacked carrier, output S i5 is high level, S i6 When the modulation wave of phase i is less than the set lower layer stacking carrier, the output S i5 is low level, S i6 is high level.

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