A chip power-on reset circuit

Abstract

This invention discloses a chip power-on reset circuit, including a sampling unit and a control unit. The control unit and the sampling unit are connected. The sampling unit is used to collect the voltage when the chip is powered on and feed it back to the control unit. The control unit feeds back a chip reset signal based on the feedback from the sampling unit and the chip's operating voltage range. The control unit includes an eighth resistor, a ninth resistor, a tenth resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a second operational amplifier, and a seventh operational amplifier. One end of the ninth resistor and one end of the thirteenth resistor are connected to a power supply. The other end of the ninth resistor is connected to one end of the tenth resistor and the non-inverting input of the second operational amplifier. The inverting input of the second operational amplifier is connected to one end of the eighth resistor. The output terminal of the second operational amplifier is connected to the other end of the eighth resistor. The other end of the thirteenth resistor is connected to one end of the fourteenth resistor and the non-inverting input of the seventh operational amplifier.

Description

Technical Field

[0001] This invention relates to the field of chip power-on reset technology, and in particular to a chip power-on reset circuit. Background Technology

[0002] Before and during power-on, the internal circuit components of a chip are in an uncertain state. Power-on reset can clear these uncertain states and bring the internal circuit of the chip to an initial state so that the chip can operate normally and output correct operation signals. Publication number CN102111136A discloses a chip power-on reset circuit. This circuit can reduce the power consumption of the power-on reset circuit after the power supply stabilizes. However, this circuit cannot be compatible with the reset methods required by different signal chips, nor can it feed back the required reset signal and reset method based on the voltage jitter state during power-on according to the chip's operating voltage range. Summary of the Invention

[0003] To address the aforementioned technical problems, the present invention aims to provide a chip power-on reset circuit, comprising a sampling unit and a control unit. The control unit and the sampling unit are connected. The sampling unit is used to collect the voltage of the chip when it is powered on and feed it back to the control unit. The control unit feeds back a chip reset signal based on the feedback from the sampling unit and the chip's operating voltage range. The control unit includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a second operational amplifier U2, and a seventh operational amplifier U7. One end of the ninth resistor R9 and one end of the thirteenth resistor R13 are connected to the control unit. The first terminal is connected to the power supply. The other end of the ninth resistor R9 is connected to one end of the tenth resistor R10 and the non-inverting input of the second operational amplifier U2. The inverting input of the second operational amplifier U2 is connected to one end of the eighth resistor R8. The output terminal of the second operational amplifier U2 is connected to the other end of the eighth resistor R8. The other end of the thirteenth resistor R13 is connected to one end of the fourteenth resistor R14 and the non-inverting input of the seventh operational amplifier U7. The inverting input of the seventh operational amplifier U7 is connected to one end of the twelfth resistor R12. The output terminal of the seventh operational amplifier U7 is connected to the other end of the twelfth resistor R12. The other ends of the tenth resistor R10 and the fourteenth resistor R14 are connected to the ground terminal.

[0004] Furthermore, the control unit also includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eleventh resistor R11, a first operational amplifier U1, and a fifth operational amplifier U5. One end of the first resistor R1 is connected to the output terminal of the first operational amplifier U1. The non-inverting input of the first operational amplifier U1 is connected to one end of the second resistor R2 and one end of the third resistor R3. The other end of the third resistor R3 is connected to the output terminal of the second operational amplifier U2 and one end of the fifth resistor R5. The inverting input of amplifier U1 is connected to the other end of the first resistor R1 and one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to one end of the seventh resistor R7 and the output of the seventh operational amplifier U7. The other end of the seventh resistor R7 is connected to the other end of the fifth resistor R5 and the non-inverting input of the fifth operational amplifier U5. The inverting input of the fifth operational amplifier U5 is connected to one end of the sixth resistor R6 and one end of the eleventh resistor R11. The other end of the sixth resistor R6 is connected to the output of the fifth operational amplifier U5. The other ends of the second resistor R2 and the eleventh resistor R11 are connected to the ground terminal.

[0005] Furthermore, the control unit also includes a third operational amplifier U3, a sixth operational amplifier U6, a third MOSFET Q3, a first diode D1, a second diode D2, and a first connector P1. The non-inverting input of the third operational amplifier U3 is connected to the inverting input of the sixth operational amplifier U6 and the first connector P1. The inverting input of the third operational amplifier U3 is connected to the output of the fifth operational amplifier U5. The output of the third operational amplifier U3 is connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to the cathode of the first diode D1 and the gate of the third MOSFET Q3. The anode of the first diode D1 is connected to the output of the sixth operational amplifier U6. The non-inverting input of the sixth operational amplifier U6 is connected to the output of the first operational amplifier U1. The source of the third MOSFET Q3 is connected to the ground terminal.

[0006] Furthermore, the control unit also includes a fifteenth resistor R15, a sixteenth resistor R16, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a first MOSFET Q1, a second MOSFET Q2, and a first capacitor C1. One end of the fifteenth resistor R15 is connected to the power supply, and the other end of the fifteenth resistor R15 is connected to one end of the sixteenth resistor R16 and the source of the first MOSFET Q1. The gate of the first MOSFET Q1 is connected to the output of the sixth operational amplifier U6. The drain of the first MOSFET Q1 is connected to one end of the twentieth resistor R20 and the source of the second MOSFET Q2. The gate of the second MOSFET Q2 is connected to the output of the third operational amplifier U3. The drain of the second MOSFET Q2 is connected to one end of the nineteenth resistor R19 and one end of the twenty-first resistor R21. The other end of the nineteenth resistor R19 is connected to one end of the first capacitor C1. The other ends of the sixteenth resistor R16, the twentieth resistor R20, the twenty-first resistor R21, and the first capacitor C1 are connected to the ground terminal.

[0007] Furthermore, the control unit also includes a 23rd resistor R23, a 24th resistor R24, a 26th resistor R26, a 27th resistor R27, a 28th resistor R28, a 29th resistor R29, a fourth operational amplifier U4, a fourth transistor Q4, and a second connector P2. One end of the 26th resistor R26 and one end of the 29th resistor R29 are connected to the power supply. The other end of the 26th resistor R26 and one end of the 27th resistor R27 are connected to the non-inverting input of the fourth operational amplifier U4. The inverting input of the fourth operational amplifier U4 is connected to the first power supply. One end of capacitor C1 is connected to the drain of the third MOSFET Q3. The output of the fourth operational amplifier U4 and one end of the twenty-third resistor R23 are connected to the base of the fourth transistor Q4. The collector of the fourth transistor Q4 and one end of the twenty-fourth resistor R24 ​​are connected to the second connector P2. The emitter of the fourth transistor Q4 and one end of the twenty-eighth resistor R28 and the other end of the twenty-ninth resistor R29 are connected. The other ends of the twenty-third resistor R23, the twenty-fourth resistor R24, the twenty-seventh resistor R27, and the twenty-eighth resistor R28 are connected to the ground terminal.

[0008] Furthermore, the control unit also includes a 25th resistor R25, a 5th MOSFET Q5, and a 3rd connector P3. One end of the 25th resistor R25 is connected to the source of the 5th MOSFET Q5 and the 3rd connector P3. The gate of the 5th MOSFET Q5 is connected to the base of the 4th transistor Q4. The drain of the 5th MOSFET Q5 is connected to the emitter of the 4th transistor Q4. The other end of the 25th resistor R25 is connected to the ground terminal.

[0009] Furthermore, the control unit also includes a seventeenth resistor R17 and an eighteenth resistor R18. One end of the eighteenth resistor R18 is connected to the gate of the first MOSFET Q1, one end of the seventeenth resistor R17 is connected to the gate of the second MOSFET Q2, and the other ends of the seventeenth resistor R17 and the eighteenth resistor R18 are connected to the ground terminal.

[0010] Furthermore, the control unit also includes a 22nd resistor R22, one end of which is connected to the gate of the third MOSFET Q3, and the other end of which is connected to the ground terminal.

[0011] The advantages of this invention compared to the prior art are:

[0012] This invention is compatible with the reset methods required by different signal chips, and based on the chip's operating voltage range, it feeds back the required reset signal and reset method according to the voltage jitter state during power-on. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the overall structure of the present invention.

[0015] Figure 2 A schematic diagram of the control unit circuit structure provided by the present invention. Detailed Implementation

[0016] To make the objectives and advantages of the present invention clearer, the present invention will be specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection specifically claimed by the present invention.

[0017] This invention discloses a chip power-on reset circuit, including a sampling unit and a control unit. The control unit and the sampling unit are connected. The sampling unit is used to collect the voltage when the chip is powered on and feed it back to the control unit. The control unit feeds back a chip reset signal based on the feedback from the sampling unit and the chip's operating voltage range. The control unit includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a second operational amplifier U2, and a seventh operational amplifier U7. One end of the ninth resistor R9 and one end of the thirteenth resistor R13 are connected to the power supply. The other end of the ninth resistor R9 is connected to one end of the tenth resistor R10 and the non-inverting input of the second operational amplifier U2. The inverting input of the second operational amplifier U2 is connected to one end of the eighth resistor R8. The output of the second operational amplifier U2 is connected to the other end of the eighth resistor R8. The other end of the thirteenth resistor R13 is connected to one end of the fourteenth resistor R14 and the non-inverting input of the seventh operational amplifier U7. The inverting input of the seventh operational amplifier U7 is connected to one end of the twelfth resistor R12. The output of the seventh operational amplifier U7 is connected to the other end of the twelfth resistor R12. The other ends of the tenth resistor R10 and the fourteenth resistor R14 are connected to the ground terminal.

[0018] Specifically, the control unit also includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eleventh resistor R11, a first operational amplifier U1, and a fifth operational amplifier U5. One end of the first resistor R1 is connected to the output terminal of the first operational amplifier U1. The non-inverting input of the first operational amplifier U1 is connected to one end of the second resistor R2 and one end of the third resistor R3. The other end of the third resistor R3 is connected to the output terminal of the second operational amplifier U2 and one end of the fifth resistor R5. The inverting input of amplifier U1 is connected to the other end of the first resistor R1 and one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to one end of the seventh resistor R7 and the output of the seventh operational amplifier U7. The other end of the seventh resistor R7 is connected to the other end of the fifth resistor R5 and the non-inverting input of the fifth operational amplifier U5. The inverting input of the fifth operational amplifier U5 is connected to one end of the sixth resistor R6 and one end of the eleventh resistor R11. The other end of the sixth resistor R6 is connected to the output of the fifth operational amplifier U5. The other ends of the second resistor R2 and the eleventh resistor R11 are connected to the ground terminal.

[0019] Specifically, the control unit also includes a third operational amplifier U3, a sixth operational amplifier U6, a third MOSFET Q3, a first diode D1, a second diode D2, and a first connector P1. The non-inverting input of the third operational amplifier U3 is connected to the inverting input of the sixth operational amplifier U6 and the first connector P1. The inverting input of the third operational amplifier U3 is connected to the output of the fifth operational amplifier U5. The output of the third operational amplifier U3 is connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to the cathode of the first diode D1 and the gate of the third MOSFET Q3. The anode of the first diode D1 is connected to the output of the sixth operational amplifier U6. The non-inverting input of the sixth operational amplifier U6 is connected to the output of the first operational amplifier U1. The source of the third MOSFET Q3 is connected to the ground terminal.

[0020] Specifically, the control unit also includes a fifteenth resistor R15, a sixteenth resistor R16, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a first MOSFET Q1, a second MOSFET Q2, and a first capacitor C1. One end of the fifteenth resistor R15 is connected to the power supply, and the other end of the fifteenth resistor R15 is connected to one end of the sixteenth resistor R16 and the source of the first MOSFET Q1. The gate of the first MOSFET Q1 is connected to the output of the sixth operational amplifier U6. The drain of the first MOSFET Q1 is connected to one end of the twentieth resistor R20 and the source of the second MOSFET Q2. The gate of the second MOSFET Q2 is connected to the output of the third operational amplifier U3. The drain of the second MOSFET Q2 is connected to one end of the nineteenth resistor R19 and one end of the twenty-first resistor R21. The other end of the nineteenth resistor R19 is connected to one end of the first capacitor C1. The other ends of the sixteenth resistor R16, the twentieth resistor R20, the twenty-first resistor R21, and the first capacitor C1 are connected to the ground terminal.

[0021] Specifically, the control unit also includes a 23rd resistor R23, a 24th resistor R24, a 26th resistor R26, a 27th resistor R27, a 28th resistor R28, a 29th resistor R29, a fourth operational amplifier U4, a fourth transistor Q4, and a second connector P2. One end of the 26th resistor R26 and one end of the 29th resistor R29 are connected to the power supply. The other end of the 26th resistor R26 and one end of the 27th resistor R27 are connected to the non-inverting input of the fourth operational amplifier U4. The inverting input of the fourth operational amplifier U4 is connected to the first power supply. One end of capacitor C1 is connected to the drain of the third MOSFET Q3. The output of the fourth operational amplifier U4 and one end of the twenty-third resistor R23 are connected to the base of the fourth transistor Q4. The collector of the fourth transistor Q4 and one end of the twenty-fourth resistor R24 ​​are connected to the second connector P2. The emitter of the fourth transistor Q4 and one end of the twenty-eighth resistor R28 and the other end of the twenty-ninth resistor R29 are connected. The other ends of the twenty-third resistor R23, the twenty-fourth resistor R24, the twenty-seventh resistor R27, and the twenty-eighth resistor R28 are connected to the ground terminal.

[0022] Specifically, the control unit also includes a 25th resistor R25, a 5th MOSFET Q5, and a 3rd connector P3. One end of the 25th resistor R25 is connected to the source of the 5th MOSFET Q5 and the 3rd connector P3. The gate of the 5th MOSFET Q5 is connected to the base of the 4th transistor Q4. The drain of the 5th MOSFET Q5 is connected to the emitter of the 4th transistor Q4. The other end of the 25th resistor R25 is connected to the ground terminal.

[0023] Specifically, the control unit also includes a seventeenth resistor R17 and an eighteenth resistor R18. One end of the eighteenth resistor R18 is connected to the gate of the first MOS transistor Q1, one end of the seventeenth resistor R17 is connected to the gate of the second MOS transistor Q2, and the other ends of the seventeenth resistor R17 and the eighteenth resistor R18 are connected to the ground terminal.

[0024] Specifically, the control unit also includes a 22nd resistor R22, one end of which is connected to the gate of the third MOS transistor Q3, and the other end of which is connected to the ground terminal.

[0025] See appendix Figure 1 Appendix Figure 2In this embodiment, the sampling unit is used to collect the voltage when the chip is powered on and feed it back to the control unit. The control unit feeds back a chip reset signal based on the feedback from the sampling unit and the chip's operating voltage range. The power signal passes through the ninth resistor R9 and the tenth resistor R10 to the ground circuit. The signal at the tenth resistor R10 is fed back to the non-inverting input of the second operational amplifier U2. Adjusting the resistance value of the tenth resistor R10 can change the amplitude of the signal at the tenth resistor R10. The amplitude of the signal at the tenth resistor R10 is set to the operating voltage of the chip. The output of the second operational amplifier U2 is negatively fed back through the eighth resistor R8 and the inverting input of the second operational amplifier U2. To prevent signal interference from downstream circuits, the power signal is routed through the thirteenth resistor R13 and the fourteenth resistor R14 to the ground circuit. Adjusting the resistance of the fourteenth resistor R14 changes the signal amplitude at its terminal. The signal amplitude at the fourteenth resistor R14 is the specified deviation value of the chip's operating voltage. The signal at the fourteenth resistor R14 is fed back to the non-inverting input of the seventh operational amplifier U7. The output of the seventh operational amplifier U7 is negatively fed back through the twelfth resistor R12 and the inverting input of the seventh operational amplifier U7 to prevent signal interference from downstream circuits. This allows the chip's operating voltage and its specified deviation to be set while preventing interference from downstream circuits.

[0026] See appendix Figure 2 In this embodiment, the output signal of the second operational amplifier U2 is fed to the ground circuit via the third resistor R3 and the second resistor R2. The signal at the second resistor R2 is fed back to the non-inverting input of the first operational amplifier U1. At the same time, the output signal of the seventh operational amplifier U7 is fed back to the inverting input of the first operational amplifier U1 via the fourth resistor R4. The output of the first operational amplifier U1 is negatively fed back through the first resistor R1 and the inverting input of the first operational amplifier U1, so that the amplitude of the output signal of the first operational amplifier U1 is the lower deviation value of the chip's operating voltage. The output signal of the seventh operational amplifier U7 is fed back to the non-inverting input of the fifth operational amplifier U5 via the seventh resistor R7. At the same time, the output signal of the second operational amplifier U2 is fed back to the non-inverting input of the fifth operational amplifier U5 via the fifth resistor R5. The output signal of the fifth operational amplifier U5 is fed to the ground circuit via the sixth resistor R6 and the eleventh resistor R11. The signal at the eleventh resistor R11 is fed back to the inverting input of the fifth operational amplifier U5, so that the amplitude of the output signal of the fifth operational amplifier U5 is the upper deviation value of the chip's operating voltage. In this way, the operating voltage range can be automatically calculated when the chip's operating voltage and its specified deviation value are set.

[0027] See appendix Figure 2In this embodiment, the sampling unit collects the voltage when the chip is powered on and feeds it back to the first connector P1 on the control unit. The output signal of the first operational amplifier U1 is fed back to the non-inverting input of the sixth operational amplifier U6, and the output signal of the fifth operational amplifier U5 is fed back to the inverting input of the third operational amplifier U3. When the first connector P1 receives a signal, the signal at the first connector P1 is fed back to the inverting input of the sixth operational amplifier U6 and the non-inverting input of the third operational amplifier U3. When the voltage is fluctuating during power-on and the amplitude is below the specified deviation of the working voltage, the sixth operational amplifier U6 outputs. The output signal of the sixth operational amplifier U6 is fed back to the gate of the third MOS transistor Q3 after passing through the first diode D1. The gate of the third MOS transistor Q3 and the... When the voltage difference between the sources of the three MOSFETs Q3 exceeds the conduction threshold, Q3 turns on. During power-up, if the voltage fluctuates and the amplitude is above the specified upper deviation of the operating voltage, the third operational amplifier U3 outputs. The signal from the output of the third operational amplifier U3 is fed back to the gate of the third MOSFET Q3 via the second diode D2, turning on Q3. When Q3 turns on, the hysteresis time of resetting the silent state of the internal circuit of the chip is reset. The twenty-second resistor R22 is used to discharge the parasitic capacitance of the gate of the third MOSFET Q3. In this way, during the initial power-up, when the power-up voltage fluctuates violently, the chip reset signal can be continuously fed back, so that the internal circuit of the chip is always in a silent state, preventing the chip from erroneous operation, crash, or freeze due to unstable power-up voltage.

[0028] See appendix Figure 2In this embodiment, the power signal passes through the fifteenth resistor R15 and the sixteenth resistor R16 to the grounding circuit. When the voltage changes from severe fluctuation to slight fluctuation during the power-on process and the amplitude is within the operating voltage range of the chip, the sixth operational amplifier U6 is turned off and the third operational amplifier U3 is turned off. The output signal of the sixth operational amplifier U6 is fed back to the gate of the first MOS transistor Q1. The eighteenth resistor R18 is used to discharge the parasitic capacitance of the gate of the first MOS transistor Q1. The output signal of the third operational amplifier U3 is fed back to the gate of the second MOSFET Q2. The seventeenth resistor R17 is used to discharge the parasitic capacitance of the gate of the second MOSFET Q2. The signal at the sixteenth resistor R16 passes through the source and drain of the first MOSFET Q1, and the twentieth resistor R20 to the ground circuit. The signal at the twentieth resistor R20 passes through the source and drain of the second MOSFET Q2, and the twenty-first resistor R21 to the ground circuit. The signal at the twenty-first resistor R21 passes through the nineteenth resistor R19, causing the potential of the first capacitor C1 to rise. The output signal of the third operational amplifier U3 is fed back to the gate of the second MOSFET Q2. When the power-on voltage fluctuates violently again and its amplitude is above the specified upper deviation of the operating voltage, the third operational amplifier U3 outputs, and the gate of the second MOSFET Q2 and the second... When the voltage difference between the source and the terminal of MOSFET Q2 exceeds the turn-on threshold, MOSFET Q2 is turned off, while MOSFET Q3 is turned on. The signal at the terminal of the first capacitor C1 passes through the drain and source of MOSFET Q3 to the ground circuit. The output signal of the sixth operational amplifier U6 is fed back to the gate of MOSFET Q1. When the power-on voltage fluctuates violently again and its amplitude is below the specified deviation of the operating voltage, the sixth operational amplifier U6 outputs, and the voltage difference between the gate and the source of MOSFET Q1 exceeds the turn-on threshold, MOSFET Q1 is turned off, while MOSFET Q3 is turned on. This instantaneous delay in the silent state of the internal circuit of the chip after initial power-on and when the voltage fluctuates is within the operating voltage range of the chip, prevents the instantaneous voltage fluctuation at the end of the reset signal feedback.

[0029] See appendix Figure 2In this embodiment, the signal at the first capacitor C1 is fed back to the inverting input of the fourth operational amplifier U4. The power signal passes through the twenty-sixth resistor R26 and the twenty-seventh resistor R27 to the ground circuit. The twenty-seventh resistor R27 is fed back to the non-inverting input of the fourth operational amplifier U4. Adjusting the resistance value of the twenty-seventh resistor R27 can change the signal amplitude at the twenty-seventh resistor R27. The signal amplitude at the twenty-seventh resistor R27 is the signal amplitude of the silent state lag time of the internal circuit of the chip. When the potential of the first capacitor C1 rises to a certain amplitude, the fourth operational amplifier U4 is cut off, and the power signal passes through the twenty-eighth resistor R28 and the twenty-ninth resistor R29 to the ground circuit. In the grounding circuit, the signal at the 28th resistor R28 passes through the emitter and base of the 4th transistor Q4, and the 23rd resistor R23 to the grounding circuit. The emitter and base of the 4th transistor Q4 are forward biased, and Q4 is turned on. The signal at the 28th resistor R28 passes through the emitter and collector of the 4th transistor Q4, and the 24th resistor R24 ​​to the grounding circuit. The signal at the 24th resistor R24 ​​is high. When the 4th operational amplifier U4 outputs, the 4th transistor Q4 is cut off, and the signal at the 24th resistor R24 ​​is low. Simultaneously, the output of the 4th operational amplifier U4... The signal is synchronously fed back to the gate of the fifth MOSFET Q5. When the fourth operational amplifier U4 outputs, the voltage difference between the gate and source of the fifth MOSFET Q5 is higher than the conduction threshold, and the fifth MOSFET Q5 is turned on. The power signal passes through the twenty-sixth resistor R26, the drain of the fifth MOSFET Q5, the source of the fifth MOSFET Q5, and the twenty-fifth resistor R25 to the ground circuit. The twenty-fifth resistor R25 is at a high level. When the chip model is low-level reset, the chip reset pin is connected to the control unit through the second connector P2. The signal at the twenty-fourth resistor R24 ​​is fed back to the chip reset pin through the second connector P2. When the chip is initially powered on, it enters the reset state when the reset pin receives a low-level feedback, and exits the reset state when the reset pin receives a high-level feedback. When the chip model is high-level reset, the chip reset pin is connected to the control unit through the third connector P3. The signal at the twenty-fifth resistor R25 is fed back to the chip's reset pin through the third connector P3. When the chip is initially powered on, it enters the reset state when the reset pin receives a high-level feedback, and exits the reset state when the reset pin receives a low-level feedback. The connection is made as needed according to the chip signal, so the reset circuit can be compatible with the reset methods required by different chip models.

[0030] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No markings in the claims should be construed as limiting the scope of the claims.

Claims

1. A chip power-on reset circuit, comprising a sampling unit and a control unit, characterized in that, The control unit and the sampling unit are connected. The sampling unit is used to collect the voltage when the chip is powered on and feed it back to the control unit. The control unit feeds back a chip reset signal based on the feedback from the sampling unit and the chip's operating voltage range. The control unit includes an eighth resistor, a ninth resistor, a tenth resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a second operational amplifier, a seventh operational amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eleventh resistor, a first operational amplifier, a fifth operational amplifier, a third operational amplifier, a sixth operational amplifier, a third MOSFET, a first diode, a second diode, a first connector, a twenty-third resistor, a twenty-fourth resistor, a twenty-sixth resistor, and a... Resistors 27, 28, and 29; the fourth operational amplifier; the fourth transistor; the second connector; the first capacitor; one end of the ninth resistor; one end of the thirteenth resistor; connected to the power supply; the other end of the ninth resistor; one end of the tenth resistor; the non-inverting input of the second operational amplifier; the inverting input of the second operational amplifier; one end of the eighth resistor; the output of the second operational amplifier; the other end of the thirteenth resistor; one end of the fourteenth resistor; the non-inverting input of the seventh operational amplifier; one end of the twelfth resistor; the output of the seventh operational amplifier; the other end of the twelfth resistor; one end of the first resistor; the output of the first operational amplifier; the non-inverting input of the first operational amplifier; one end of the second resistor; and the third resistor... One end is connected; the other end of the third resistor is connected to the output terminal of the second operational amplifier; one end of the fifth resistor is connected; the inverting input of the first operational amplifier is connected to the other end of the first resistor; one end of the fourth resistor is connected; the other end of the fourth resistor is connected to one end of the seventh resistor; the output terminal of the seventh operational amplifier is connected; the other end of the seventh resistor is connected to the other end of the fifth resistor; the non-inverting input of the fifth operational amplifier is connected; the inverting input of the fifth operational amplifier is connected to one end of the sixth resistor; one end of the eleventh resistor is connected; the other end of the sixth resistor is connected to the output terminal of the fifth operational amplifier; the non-inverting input of the third operational amplifier is connected to the inverting input of the sixth operational amplifier; the first connector is connected; the inverting input of the third operational amplifier is connected to the output terminal of the fifth operational amplifier; the output terminal of the third operational amplifier is connected to the anode of the second diode; the cathode of the second diode is connected. The first diode's cathode is connected to the third MOSFET's gate; the first diode's anode is connected to the sixth operational amplifier's output; the sixth operational amplifier's non-inverting input is connected to the first operational amplifier's output; the third MOSFET's source is connected to ground; one end of the twenty-sixth resistor and one end of the twenty-ninth resistor are connected to the power supply; the other end of the twenty-sixth resistor and one end of the twenty-seventh resistor are connected to the fourth operational amplifier's non-inverting input; the fourth operational amplifier's inverting input is connected to one end of the first capacitor and the third MOSFET's drain; the fourth operational amplifier's output and one end of the twenty-third resistor are connected to the fourth transistor's base; the fourth transistor's collector and one end of the twenty-fourth resistor are connected to the second connector; and the fourth transistor's emitter and one end of the twenty-eighth resistor and the other end of the twenty-ninth resistor are connected...The second resistor, eleventh resistor, tenth resistor, fourteenth resistor, twenty-third resistor, twenty-fourth resistor, twenty-seventh resistor, twenty-eighth resistor, and the other end of the first capacitor are connected to the ground terminal.

2. The chip power-on reset circuit according to claim 1, characterized in that, The control unit further includes a fifteenth resistor, a sixteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a first MOSFET, a second MOSFET, and a first capacitor. One end of the fifteenth resistor is connected to the power supply, and the other end of the fifteenth resistor is connected to one end of the sixteenth resistor and the source of the first MOSFET. The gate of the first MOSFET is connected to the output of the sixth operational amplifier. The drain of the first MOSFET is connected to one end of the twentieth resistor and the source of the second MOSFET. The gate of the second MOSFET is connected to the output of the third operational amplifier. The drain of the second MOSFET is connected to one end of the nineteenth resistor and one end of the twenty-first resistor. The other end of the nineteenth resistor is connected to one end of the first capacitor. The other ends of the sixteenth resistor, the twentieth resistor, and the twenty-first resistor are connected to the ground terminal.

3. The chip power-on reset circuit according to claim 2, characterized in that, The control unit also includes a 25th resistor, a 5th MOSFET, and a 3rd connector. One end of the 25th resistor is connected to the source of the 5th MOSFET and the 3rd connector. The gate of the 5th MOSFET is connected to the base of the 4th transistor. The drain of the 5th MOSFET is connected to the emitter of the 4th transistor. The other end of the 25th resistor is connected to the ground terminal.

4. The chip power-on reset circuit according to claim 3, characterized in that, The control unit further includes a seventeenth resistor and an eighteenth resistor. One end of the eighteenth resistor is connected to the gate of the first MOS transistor, one end of the seventeenth resistor is connected to the gate of the second MOS transistor, and the other ends of the seventeenth resistor and the eighteenth resistor are connected to the ground terminal.

5. The chip power-on reset circuit according to claim 4, characterized in that, The control unit also includes a 22nd resistor, one end of which is connected to the gate of the 3rd MOS transistor, and the other end of which is connected to the ground terminal.

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