A rapidio wire rate dynamic configuration method and switching network system

Abstract

The present application relates to the field of RapidIO switching network, and provides a RapidIO line rate dynamic configuration method and a switching network system, the method comprising: a RIO management node performing link scanning on an FPGA node, and issuing a dynamic configuration RapidIO line rate instruction to the FPGA node when the link state is poor; after the FPGA node receives the dynamic configuration RapidIO line rate instruction, starting the dynamic configuration of the RapidIO line rate. The present application detects the link state in real time through the RIO management node, and when the link state is poor, starts the dynamic configuration of the RapidIO line rate of the FPGA node through the instruction issuing mode, solves the problem of poor link state of the FPGA node, can effectively ensure the normal communication of the RapidIO switching network, and is simple in software implementation.

Description

Technical Field

[0001] This invention relates to the field of RapidIO switching networks, and more specifically, to a RapidIO line rate dynamic configuration method and switching network system. Background Technology

[0002] RapidIO bus, as a bus interconnect standard in the embedded field, meets the needs of the rapid development of embedded systems with its high bandwidth, low latency, and high reliability. RapidIO bus is increasingly used for high-speed interconnection between chips and modules. Multiple chips and modules are interconnected with RapidIO switching chips via the RapidIO bus, connecting to the RapidIO switching network.

[0003] Currently, in the use of domestic RapidIO switching networks, there are instances where poor link conditions lead to RapidIO nodes going offline, causing abnormal communication interruptions and further resulting in system malfunctions.

[0004] The probability of the aforementioned poor link status increases with the increase of the RapidIO link line rate. Therefore, when the above problems occur, at the software level, the RapidIO line rate of the poorly performing node is reduced to improve link quality, thereby preventing the RapidIO node from going offline and ensuring normal system communication.

[0005] Existing literature and patents do not cover methods for dynamically adjusting the RapidIO line rate of FPGA nodes. Summary of the Invention

[0006] This invention aims to provide a RapidIO line rate dynamic configuration method and switching network system, which solves the problem of poor FPGA node link status in domestic RapidIO switching networks without significantly increasing system software costs. This method can effectively ensure normal system communication.

[0007] This invention provides a method for dynamically configuring RapidIO line rates, comprising:

[0008] The RIO management node performs a link scan on the FPGA node and issues a dynamic configuration RapidIO line rate command to the FPGA node when the link status is poor.

[0009] After receiving the RapidIO line rate configuration command, the FPGA node initiates RapidIO line rate dynamic configuration.

[0010] In some embodiments, the RIO management node performs a link scan on the FPGA node by reading the RIO Port Error and Status CSR register values ​​of the RapidIO switching chip port.

[0011] In some embodiments, after the RIO management node issues a dynamic configuration RapidIO line rate command to the FPGA node, it needs to determine whether it has received an SPI response from the FPGA node. If it has received an SPI response from the FPGA node, the RIO management node returns to its initial state and continues to perform link scanning on the FPGA node.

[0012] In some embodiments, the FPGA node receives a dynamic configuration RapidIO line rate command, and after the SPI control module parses and processes the configuration RapidIO line rate command, it outputs a RapidIO reconfiguration pulse signal RIO_recfg_pulse and a RapidIO reconfiguration line rate signal RIO_recfg_rate to the RIO line rate dynamic configuration module.

[0013] The RIO line rate dynamic configuration module receives the reconfiguration pulse signal RIO_recfg_pulse and the RapidIO reconfiguration line rate signal RIO_recfg_rate from the SPI control module, and generates RapidIO line rate dynamic configuration related parameters under the control of the RapidIO reconfiguration line rate signal RIO_recfg_rate.

[0014] After the parameters related to the RapidIO line rate dynamic configuration are set, the RapidIO reconfiguration completion signal RIO_recfg_done is output to the SPI control module. After receiving the RapidIO reconfiguration completion signal RIO_recfg_done, the SPI control module sends SPI response information back to the RIO management node.

[0015] In some embodiments, the FPGA node needs to monitor whether the RapidIO reconfiguration pulse signal RIO_recfg_pulse is valid. If it is, it generates the RapidIO IP core dynamic configuration parameters based on the RapidIO reconfiguration line rate signal RIO_recfg_rate. In the process of generating the RapidIO IP core dynamic configuration parameters based on the RapidIO reconfiguration line rate signal RIO_recfg_rate, it generates the RapidIO line rate dynamic configuration related parameters.

[0016] After the parameters related to RapidIO line rate dynamic configuration are set, the process transitions to setting the Gt_reset signal in the RapidIO IP core dynamic configuration parameters to 1, and then generates the RapidIO reconfiguration completion signal RIO_recfg_done through a delay.

[0017] In some embodiments, the delay determination includes:

[0018] After setting the Gt_reset signal in the RapidIO IP core dynamic configuration parameters to 1, check if the delay reaches the first threshold. If so, set the Gt_reset signal to 0.

[0019] After setting the Gt_reset signal to 0, determine whether the delay reaches the second threshold. If so, generate the RapidIO reconfiguration completion signal RIO_recfg_done.

[0020] The present invention also provides a RapidIO switching network system, including an FPGA node, a RapidIO switching chip, and a RIO management node;

[0021] Both the FPGA node and the RIO management node are interconnected with the RapidIO switching chip via the RapidIO bus; the RIO management node is interconnected with the FPGA node via the SPI bus.

[0022] The RapidIO switching network uses the aforementioned RapidIO line rate dynamic configuration method for dynamic configuration of RapidIO line rates.

[0023] In some embodiments, the FPGA node includes a RIO line rate dynamic configuration module and an SPI control module and a RapidIO IP core interconnected with the RIO line rate dynamic configuration module.

[0024] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0025] This invention uses an RIO management node to monitor the link status in real time. When the link status is poor, it initiates dynamic configuration of the RapidIO line rate on the FPGA node through command issuance, thereby solving the problem of poor FPGA node link status. This effectively ensures normal communication in the RapidIO switching network and is simple to implement in software. Attached Figure Description

[0026] Figure 1 This is a schematic diagram illustrating the implementation principle of the RapidIO switching network in an embodiment of the present invention.

[0027] Figure 2This is a flowchart illustrating the workflow of the RIO management node in an embodiment of the present invention.

[0028] Figure 3 This is a schematic diagram of the RapidIO switching network and FPGA node implementation in an embodiment of the present invention.

[0029] Figure 4 for Figure 3 Workflow diagram of the FPGA node. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0032] Example

[0033] See Figure 1 An embodiment of the present invention provides a RapidIO switching network system, comprising an FPGA node, a RapidIO switching chip, and a RIO management node;

[0034] The FPGA node is interconnected with the RapidIO switching chip via the RapidIO bus;

[0035] The RIO management node is interconnected with the RapidIO switching chip via the RapidIO bus;

[0036] The RIO management node is interconnected with the FPGA node via an SPI bus.

[0037] In some implementations, the FPGA node chip uses domestically produced K7, V7, Z7 and above FPGA devices;

[0038] In some implementations, the RapidIO switching chip uses the CPS1848 or a corresponding domestically produced RapidIO switching device.

[0039] Based on the RapidIO switching network system implemented above, when performing the RapidIO line rate dynamic configuration method:

[0040] The RIO management node performs a link scan on the FPGA node, and when the link status is poor, it issues a dynamic configuration RapidIO line rate command to the FPGA node.

[0041] After receiving the RapidIO line rate configuration command, the FPGA node initiates RapidIO line rate dynamic configuration.

[0042] See Figure 2 The working process of the RIO management node in the RapidIO line rate dynamic configuration method is as follows:

[0043] The link scanning process of the RIO management node enters the initial state after power-on reset.

[0044] Then, the RIO management node performs a link scan on the FPGA node by reading the RIO Port Error and StatusCSR register values ​​of the RapidIO switching chip port, and enters the link status determination process.

[0045] If the link status is poor, the process transitions to the SPI configuration command sending state to send RapidIO line rate configuration commands to the FPGA node via the SPI bus. After the RIO management node sends the dynamic configuration RapidIO line rate command to the FPGA node, it needs to check whether it has received an SPI response from the FPGA node. If it does, the RIO management node returns to the initial state and continues link scanning of the FPGA node. If the link status is good, the process transitions to the RIO link configuration state, and then to the RIO scan completion state.

[0046] See Figure 3 The specific operation process of the FPGA node in the RapidIO line rate dynamic configuration method is as follows:

[0047] The FPGA node receives the configuration RapidIO line rate command issued by the RIO management node through the SPI bus. After the SPI control module parses and processes the configuration RapidIO line rate command, it outputs the RapidIO reconfiguration pulse signal RIO_recfg_pulse and the RapidIO reconfiguration line rate signal RIO_recfg_rate to the RIO line rate dynamic configuration module.

[0048] The RIO line rate dynamic configuration module receives the reconfiguration pulse signal RIO_recfg_pulse and the RapidIO reconfiguration line rate signal RIO_recfg_rate from the SPI control module. Under the control of the RapidIO reconfiguration line rate signal RIO_recfg_rate, it generates RapidIO line rate dynamic configuration related parameters, including transmit queue depth parameter C_tx_depth, receive queue depth parameter C_rx_depth, line rate mode parameter C_mode_xg, receive clock data recovery configuration parameter Rxcdr_cfg, Cpll division ratio parameter Cpll_fbdiv, Rx end division ratio parameter Rxout_div, Tx end division ratio parameter Txout_div, receive clock data recovery lock time parameter Rxcdr_lock_time, clock multiplication factor parameter Clkfbout_mult_f, clock division factor parameter Clkout0_divde_f, clock division factor parameter Clkout1_divde_f, and clock division factor parameter Clkout2_divde_f.

[0049] After the parameters related to the dynamic configuration of the 12 RapidIO line rates are set, the RapidIO reconfiguration completion signal RIO_recfg_done is output to the SPI control module. After receiving the RapidIO reconfiguration completion signal RIO_recfg_done, the SPI control module sends SPI response information back to the RIO management node.

[0050] See Figure 4 The FPGA node line-rate dynamic configuration process enters the initial state after power-on reset. The FPGA node needs to monitor the validity of the RapidIO reconfiguration pulse signal RIO_recfg_pulse. If valid, it generates RapidIO IP core dynamic configuration parameters based on the RapidIO reconfiguration line-rate signal RIO_recfg_rate. During this process, RapidIO line-rate dynamic configuration parameters are generated. After these parameters are set, the process transitions to setting the Gt_reset signal in the RapidIO IP core dynamic configuration parameters to 1. Finally, a delay is used to determine the RapidIO reconfiguration completion signal RIO_recfg_done.

[0051] The delay determination includes:

[0052] After setting the Gt_reset signal in the RapidIO IP core dynamic configuration parameters to 1, check if the delay reaches the first threshold. If so, set the Gt_reset signal to 0.

[0053] After setting the Gt_reset signal to 0, determine whether the delay reaches the second threshold. If so, generate the RapidIO reconfiguration completion signal RIO_recfg_done.

[0054] The first threshold is less than the second threshold. For example, the first threshold can be set to 1ms and the second threshold to 10ms, depending on the actual needs.

[0055] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method of RapidIO link rate dynamic configuration, the method comprising: The RIO management node performs link scanning on the FPGA node by reading the RIO Port Error and Status CSR register value state of the RapidIO switch chip port, and issues a dynamic configuration RapidIO line rate instruction to the FPGA node when the link state is poor; after the RIO management node issues the dynamic configuration RapidIO line rate instruction to the FPGA node, it needs to judge whether SPI response information from the FPGA node is received, and if the SPI response information from the FPGA node is received, the RIO management node returns to the initial state and continues to perform link scanning on the FPGA node; After the FPGA node receives the dynamic configuration RapidIO line rate instruction, the RapidIO line rate dynamic configuration is started; after the FPGA node receives the dynamic configuration RapidIO line rate instruction, the configuration RapidIO line rate instruction is parsed and processed by the SPI control module, and then a RapidIO reconfiguration pulse signal RIO_recfg_pulse and a RapidIO reconfiguration line rate signal RIO_recfg_rate are output to the RIO line rate dynamic configuration module; The RIO line rate dynamic configuration module receives the reconfiguration pulse signal RIO_recfg_pulse and the RapidIO reconfiguration line rate signal RIO_recfg_rate input from the SPI control module, and generates RapidIO line rate dynamic configuration related parameters under the control of the RapidIO reconfiguration line rate signal RIO_recfg_rate; After the RapidIO line rate dynamic configuration related parameters are set, a RapidIO reconfiguration completion signal RIO_recfg_done is output to the SPI control module; after the SPI control module receives the RapidIO reconfiguration completion signal RIO_recfg_done, SPI response information is fed back to the RIO management node; The FPGA node needs to monitor whether the RapidIO reconfiguration pulse signal RIO_recfg_pulse is valid, and if so, generates RapidIO IP core dynamic configuration parameters according to the RapidIO reconfiguration line rate signal RIO_recfg_rate, and in the process of generating the RapidIO IP core dynamic configuration parameters according to the RapidIO reconfiguration line rate signal RIO_recfg_rate, RapidIO line rate dynamic configuration related parameters are generated; After the RapidIO line rate dynamic configuration related parameters are set, the Gt_reset signal in the RapidIO IP core dynamic configuration parameters is set to 1, and then the RapidIO reconfiguration completion signal RIO_recfg_done is generated through delay judgment; the delay judgment includes: ​ If the delay reaches the first threshold value after setting the Gt_reset signal in the dynamic configuration parameter of the RapidIO IP core to 1, the Gt_reset signal is set to 0; If the delay reaches the second threshold value after setting the Gt_reset signal to 0, a RapidIO reconfiguration completion signal RIO_recfg_done is generated.

2. A RapidIO switching network system, characterized by, The system comprises FPGA nodes, a RapidIO switching chip and a RIO management node; The FPGA nodes and the RIO management node are interconnected with the RapidIO switching chip through a RapidIO bus; the RIO management node is interconnected with the FPGA nodes through an SPI bus; The RapidIO switching network system adopts the RapidIO line rate dynamic configuration method of claim 1 to perform RapidIO line rate dynamic configuration.

3. The RapidIO switch network system of claim 2, wherein, The FPGA node comprises a RIO line rate dynamic configuration module and an SPI control module and a RapidIO IP core interconnected with the RIO line rate dynamic configuration module.

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