Method for preparing flash memory device

Abstract

The present application provides a method for preparing a flash memory device. Before preparing a gate oxide layer, at least two tilted ion implantation processes are performed on the surface of the isolation structure exposed in the peripheral logic area to ensure that the two side corners of the isolation structure in the peripheral logic area (the edge of the active area) are in full contact with the implanted dopant ions, thereby improving the ion concentration distribution in the edge area of ​​the active area. Si vacancies exist in the bonds formed by the Si-doped ions, and the vacancies are conducive to oxidation reactions at the SiO2 / Si interface. As a result, in the subsequent high-temperature furnace tube oxidation process for preparing the gate oxide layer, the growth rate of the gate oxide layer at the two side corners of the isolation structure is greater than the growth rate of the gate oxide layer on the substrate surface away from the top corners of the isolation structure, resulting in thickening of the gate oxide layer at the edge of the active area, thereby reducing the electric field distribution at the edge of the active area, thereby improving the morphology and profile of the gate oxide layer near the two side corners of the isolation structure and the TDDB performance of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a flash memory device. Background Art

[0002] In the preparation of flash memory devices, the FG-first (floating gate preparation first) technology route is used because the floating gate is prepared before the final STI (shallow trench isolation structure). The STI is usually composed of an isolation structure and a pad oxide layer. The pad oxide layer on the surface of the isolation structure usually adopts a double-layer oxide layer. However, this can easily cause the floating gate in the storage area to be over-oxidized (consumed by misoxidation), resulting in a decrease in the coupling ratio (coupling coefficient), affecting the performance of the storage area device of the flash memory device.

[0003] In addition, if a single-layer oxide layer is used as the liner oxide layer on the surface of the isolation structure, the peripheral logic area will cause the gate oxide in the corner area of ​​the active area to be too thin due to insufficient corner rounding of the isolation structure. This can easily cause the electric field at the edge of the active area to be too large, and ultimately cause the high-voltage PMOS (such as 5VPMOS) to fail due to TDDB (time-dependent dielectric breakdown). Summary of the Invention

[0004] The present application provides a method for preparing a flash memory device, which can solve at least one of the problems in the traditional flash memory device preparation process, such as the floating gate of the storage area being over-oxidized, affecting the coupling coefficient, and the gate oxide layer at the top corner position of the active area / isolation structure (shallow trench isolation structure) in the peripheral area being too thin, thereby affecting the TDDB performance of the device.

[0005] The present invention provides a method for manufacturing a flash memory device, comprising:

[0006] A substrate is provided, the substrate comprising a storage area and a peripheral logic area, a pad oxide layer and a floating gate material layer being sequentially formed on a surface of the substrate, wherein a plurality of isolation structures are formed in the floating gate material layer, the pad oxide layer, and a portion of the thickness of the substrate;

[0007] Etching and removing a certain thickness of the isolation structure in the storage area, wherein the remaining thickness of the isolation structure in the storage area protrudes a certain height above the surface of the substrate;

[0008] forming an ONO dielectric layer, wherein the ONO dielectric layer covers the floating gate material layer and the isolation structure of the storage area, and the floating gate material layer and the isolation structure of the peripheral logic area;

[0009] Etching and removing the ONO dielectric layer, the floating gate material layer, the isolation structure of a certain thickness and the liner oxide layer in the peripheral logic area;

[0010] Coating a photoresist layer on the ONO dielectric layer in the storage area and on the substrate surface and isolation structure in the peripheral logic area;

[0011] defining an opening pattern for ion implantation on the photoresist layer to obtain a patterned photoresist layer, wherein the patterned photoresist layer opens an isolation structure of the peripheral logic area;

[0012] Using the patterned photoresist layer as a mask, performing at least two tilted ion implantation processes on the surface of the isolation structure exposed in the peripheral logic region, so that both side corners of the isolation structure in the peripheral logic region are completely in contact with the implanted dopant ions;

[0013] removing the patterned photoresist layer; and

[0014] A gate oxide layer is formed on the substrate surface of the peripheral logic area by a high-temperature furnace tube oxidation process, wherein the thickness of the gate oxide layer close to the top corners on both sides of the isolation structure is greater than the thickness of the gate oxide layer away from the top corners of the isolation structure.

[0015] Optionally, in the preparation method of the flash memory device, during the process of performing at least two ion tilted injection processes on the surface of the isolation structure exposed in the peripheral logic area using the patterned photoresist layer as a mask, at least one N-type ion tilted injection is performed tilted to the left and at least one N-type ion tilted injection is performed tilted to the right, so that the left top corner and the right top corner of the isolation structure of the peripheral logic area are completely in contact with the injected doped ions.

[0016] Optionally, in the method for preparing the flash memory device, in the process of performing N-type ion tilted implantation by tilting the surface of the isolation structure exposed in the peripheral logic area to the left with the patterned photoresist layer as a mask, the tilt angle is 0° to 15°; the ion implantation energy is 8Kev to 15Kev; and the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .

[0017] Optionally, in the method for preparing the flash memory device, in the process of performing N-type ion tilt implantation by tilting the surface of the isolation structure exposed in the peripheral logic area to the right with the patterned photoresist layer as a mask, the tilt angle is 0° to 15°; the ion implantation energy is 8Kev to 15Kev; and the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .

[0018] Optionally, in the method for preparing the flash memory device, the ion concentration at the top corners on both sides of the isolation structure is greater than the ion concentration on the upper surface of the isolation structure.

[0019] Optionally, in the preparation method of the flash memory device, in the process of forming a gate oxide layer on the surface of the substrate in the peripheral logic area through a high-temperature furnace tube oxidation process, the process temperature is 700°C to 900°C, and the oxygen flow rate is 1sccm to 3sccm.

[0020] Optionally, in the method for preparing the flash memory device, the thickness of the gate oxide layer near the top corners on both sides of the isolation structure is The thickness of the gate oxide layer away from the top corner of the isolation structure is

[0021]

[0022] Optionally, in the method for preparing the flash memory device, after forming a gate oxide layer on the surface of the isolation structure in the peripheral logic area and the surface of the substrate by a high-temperature furnace oxidation process, the method for preparing the flash memory device further comprises:

[0023] forming a gate material layer, wherein the gate material layer covers the gate oxide layer and the isolation structure of the peripheral logic area and the ONO dielectric layer of the storage area;

[0024] The gate material layer is etched to define the gate of the peripheral logic area.

[0025] The technical solution of this application has at least the following advantages:

[0026] The present application provides a method for preparing a flash memory device. Before preparing a gate oxide layer, at least two tilted ion implantation processes are performed on the surface of the isolation structure exposed in the peripheral logic region so that both side corners of the isolation structure in the peripheral logic region (edges of the active region) are fully contacted with the implanted dopant ions, thereby improving the ion concentration distribution in the edge region of the active region. Si vacancies exist in the Si-doped ion (e.g., Si-P) bond, and the vacancies are conducive to oxidation reactions at the SiO2 / Si interface. As a result, in the subsequent high-temperature furnace tube oxidation process for preparing the gate oxide layer, the growth rate of the gate oxide layer at the top corners of the isolation structure is greater than the growth rate of the gate oxide layer on the substrate surface away from the top corners of the isolation structure, thereby causing the gate oxide layer at the top corners of the isolation structure (edges of the active region) to grow thicker, thereby reducing the electric field distribution at the edge of the active region (weakening the electric field at the edge of the active region), thereby improving the TDDB performance of the device, and improving the morphology and profile of the gate oxide layer near the top corners of the isolation structure, that is, improving the morphology and profile of the top corners of the final STI. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0028] Figure 1 is a flow chart of a method for preparing a flash memory device according to an embodiment of the present invention;

[0029] Figure 2-Figure 7 Schematic diagram of the semiconductor structure in each process step of preparing a flash memory device according to an embodiment of the present invention;

[0030] The description of the accompanying drawings is as follows:

[0031] 10 - substrate, 11 - isolation structure, 20 - pad oxide layer, 30 - floating gate material layer, 40 - ONO dielectric layer, 50 - photoresist layer, 60 - gate oxide layer. DETAILED DESCRIPTION

[0032] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0033] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0035] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0036] The present invention provides a method for preparing a flash memory device. Figure 1 , Figure 1 1 is a flow chart of a method for preparing a flash memory device according to an embodiment of the present invention, wherein the method for preparing a flash memory device comprises:

[0037] First, perform step S1: refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after the isolation structure is formed in an embodiment of the present application. A substrate 10 is provided, and the substrate 10 includes a storage area and a peripheral logic area. A pad oxide layer 20 and a floating gate material layer 30 are sequentially formed on the surface of the substrate 10, wherein a plurality of isolation structures 11 are formed in the floating gate material layer 30, the pad oxide layer 20 and a partial thickness of the substrate 10.

[0038] In the peripheral logic region, the substrate 10 between the isolation structures 11 is an active region.

[0039] Then, execute step S2: refer to Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after etching away a certain thickness of the isolation structure of the storage area according to an embodiment of the present application. A layer of photoresist is coated on the surface of the isolation structure 11 and the floating gate material layer 30, and an opening pattern for etching the isolation structure of a certain thickness of the storage area is defined on the photoresist. Then, using the photoresist after forming the opening pattern as a mask, the isolation structure 11 of a certain thickness of the storage area is etched away, wherein the remaining thickness of the isolation structure 11 of the storage area protrudes a certain height from the surface of the substrate 10.

[0040] In this embodiment, during the process of etching away a certain thickness of the isolation structure 11 of the storage area, a plurality of storage area trenches are formed in the floating gate material layer 30 .

[0041] Next, execute step S3: refer to Figure 4 , Figure 4 Schematic diagram of the semiconductor structure after the ONO dielectric layer is formed in an embodiment of the present application, wherein an ONO dielectric layer 40 is formed, wherein the ONO dielectric layer 40 covers the floating gate material layer 30 of the storage area and the sidewalls and bottom walls of the storage area trench, as well as the isolation structure 11 covering the bottom wall of the storage area, and the floating gate material layer 30 and the isolation structure 11 of the peripheral logic area.

[0042] Further, step S4 is performed: refer to Figure 5 , Figure 5This is a schematic diagram of the semiconductor structure after the ONO dielectric layer, floating gate material layer, isolation structure of a certain thickness and pad oxide layer of the peripheral logic area are etched away in an embodiment of the present application. The ONO dielectric layer 40, floating gate material layer 30, isolation structure of a certain thickness and pad oxide layer 20 of the peripheral logic area are etched away.

[0043] Preferably, a dry etching process or a wet etching process may be used to etch away the ONO dielectric layer 40 , the floating gate material layer 30 , the isolation structure 11 of a certain thickness, and the liner oxide layer 20 in the peripheral logic region.

[0044] Next, execute step S5: refer to Figure 6(a) and Figure 6(b), Figure 6(a) is a schematic diagram of the semiconductor structure of an embodiment of the present application in which the first ion tilted implantation process is performed on the surface of the isolation structure exposed in the peripheral logic area, and Figure 6(b) is a schematic diagram of the semiconductor structure of an embodiment of the present application in which the second ion tilted implantation process is performed on the surface of the isolation structure exposed in the peripheral logic area, and a photoresist layer 50 is coated on the ONO dielectric layer 40 in the storage area and on the surface of the substrate 10 and the isolation structure 11 in the peripheral logic area.

[0045] Further, step S6 is performed: defining an opening pattern for ion implantation on the photoresist layer 50 to obtain a patterned photoresist layer 50 , wherein the patterned photoresist layer 50 opens the isolation structure 11 of the peripheral logic area.

[0046] Next, execute step S7: Continuing to refer to Figures 6(a) and 6(b), using the patterned photoresist layer 50 as a mask, perform at least two ion tilted implantation processes on the surface of the isolation structure exposed in the peripheral logic area, so that the top corners on both sides of the isolation structure of the peripheral logic area are completely in contact with the implanted dopant ions.

[0047] Preferably, in the process of performing at least two ion tilted injection processes on the surface of the isolation structure 11 exposed in the peripheral logic area using the patterned photoresist layer as a mask, at least one N-type ion tilted injection is performed tilted toward the left and at least one N-type ion tilted injection is performed tilted toward the right, so that the left top corner and the right top corner of the isolation structure in the peripheral logic area are completely in contact with the injected doped ions.

[0048] As shown in FIG6(b), in the process of performing N-type ion tilted implantation by tilting the surface of the isolation structure exposed in the peripheral logic area to the left with the patterned photoresist layer as a mask, the tilt angle β is 0° to 15°; the ion implantation energy is 8Kev to 15Kev; and the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .

[0049] Furthermore, as shown in FIG6(a), in the process of performing N-type ion tilt implantation by tilting the surface of the isolation structure exposed in the peripheral logic area to the right with the patterned photoresist layer as a mask, the tilt angle α is 0° to 15°; the ion implantation energy is 8Kev to 15Kev; and the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .

[0050] In this embodiment, the patterned photoresist layer is used as a mask to perform phosphorus (P) ion tilted implantation at least once to the left and at least once to the right on the surface of the isolation structure exposed in the peripheral logic region.

[0051] Preferably, the ion concentration at the top corners on both sides of the isolation structure 11 is greater than the ion concentration on the upper surface of the isolation structure away from the top corners of the isolation structure.

[0052] Further, step S8 is performed: refer to Figure 7 , Figure 7 1 is a schematic diagram of a semiconductor structure after a gate oxide layer is formed according to an embodiment of the present application, and the patterned photoresist layer 50 is removed.

[0053] In this embodiment, the patterned photoresist layer 50 may be removed by an ashing process.

[0054] Finally, step S9 is performed: a gate oxide layer 60 is formed on the surface of the substrate in the peripheral logic area through a high-temperature furnace tube oxidation process, wherein the thickness of the gate oxide layer 60 on the surface of the substrate 10 close to the top corners on both sides of the isolation structure is greater than the thickness of the gate oxide layer 60 on the surface of the substrate 10 away from the top corners of the isolation structure 11.

[0055] Preferably, in the process of forming the gate oxide layer 60 on the surface of the substrate 10 in the peripheral logic region by a high-temperature furnace tube oxidation process, the process temperature is 700° C. to 900° C., and the flow rate of oxygen is 1 sccm to 3 sccm.

[0056] In this embodiment, the thickness of the gate oxide layer 60 near the top corners of the isolation structure is The thickness of the gate oxide layer 60 away from the top corner of the isolation structure 11 is

[0057] The present application performs at least two ion tilted implantation processes in different directions on the surface of the isolation structure exposed in the peripheral logic area before preparing the gate oxide layer, so that the two side corners of the isolation structure in the peripheral logic area (edge ​​of the active area) are fully contacted with the implanted dopant ions, thereby improving the ion concentration distribution in the edge area of ​​the active area. Si vacancies will exist in the Si-doped ion bonds (such as Si-P bonds), and the vacancies are conducive to the oxidation reaction at the SiO2 / Si interface, so that in the subsequent high-temperature furnace tube oxidation process for preparing the gate oxide layer, the growth rate of the gate oxide layer at the two side corners of the isolation structure is greater than the growth rate of the gate oxide layer on the substrate surface away from the top corners of the isolation structure, thereby making the single-layer gate oxide layer at the two side corners of the isolation structure (edge ​​of the active area) grow thicker, thereby reducing the electric field distribution at the edge of the active area (the electric field at the edge of the active area is weakened), thereby improving the TDDB performance of the device, and improving the morphology and profile of the gate oxide layer near the two side corners of the isolation structure, that is, improving the morphology and profile of the final STI two side corners.

[0058] Furthermore, after forming the gate oxide layer 60 on the surface of the isolation structure 11 in the peripheral logic area and the surface of the substrate 10 by a high-temperature furnace oxidation process, the method for preparing the flash memory device may further include:

[0059] Step S10: forming a gate material layer (not shown), wherein the gate material layer covers the gate oxide layer and the isolation structure of the peripheral logic area and the ONO dielectric layer of the storage area; and

[0060] Step S11: etching the gate material layer to define the gate of the peripheral logic area, wherein the gate of the peripheral logic area is the gate of the MOS device; the gate material layer deposited in the storage area serves as the control gate of the flash memory unit.

[0061] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for preparing a flash memory device, characterized in that: include: Providing a substrate, the substrate comprising a storage area and a peripheral logic area, wherein a pad oxide layer and a floating gate material layer are sequentially formed on the surface of the substrate, wherein a plurality of isolation structures are formed in the floating gate material layer, the pad oxide layer, and a portion of the thickness of the substrate; Etching and removing a certain thickness of the isolation structure in the storage area, wherein the remaining thickness of the isolation structure in the storage area protrudes a certain height above the surface of the substrate; forming an ONO dielectric layer, wherein the ONO dielectric layer covers the floating gate material layer and the isolation structure of the storage area, and the floating gate material layer and the isolation structure of the peripheral logic area; Etching and removing the ONO dielectric layer, the floating gate material layer, the isolation structure of a certain thickness and the liner oxide layer in the peripheral logic area; Coating a photoresist layer on the ONO dielectric layer in the storage area and on the substrate surface and isolation structure in the peripheral logic area; defining an opening pattern for ion implantation on the photoresist layer to obtain a patterned photoresist layer, wherein the patterned photoresist layer opens an isolation structure of the peripheral logic area; Using the patterned photoresist layer as a mask, performing at least two tilted ion implantation processes on the surface of the isolation structure exposed in the peripheral logic region, so that both side corners of the isolation structure in the peripheral logic region are completely in contact with the implanted dopant ions; removing the patterned photoresist layer; and A gate oxide layer is formed on the substrate surface of the peripheral logic area by a high-temperature furnace tube oxidation process, wherein the thickness of the gate oxide layer close to the top corners on both sides of the isolation structure is greater than the thickness of the gate oxide layer away from the top corners of the isolation structure.

2. The method for preparing a flash memory device according to claim 1, wherein: In the process of performing at least two ion tilted injection processes on the surface of the isolation structure exposed in the peripheral logic area using the patterned photoresist layer as a mask, at least one N-type ion tilted injection is performed tilted to the left and at least one N-type ion tilted injection is performed tilted to the right, so that the left and right top corners of the isolation structure of the peripheral logic area are completely in contact with the injected doped ions.

3. The method for preparing a flash memory device according to claim 2, wherein: In the process of performing N-type ion tilt implantation by tilting the surface of the isolation structure exposed in the peripheral logic area to the left using the patterned photoresist layer as a mask, the tilt angle is 0° to 15°; the ion implantation energy is 8Kev to 15Kev; and the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .

4. The method for preparing a flash memory device according to claim 2, wherein: In the process of performing N-type ion tilt implantation by tilting the surface of the isolation structure exposed in the peripheral logic area to the right side using the patterned photoresist layer as a mask, the tilt angle is 0° to 15°; the ion implantation energy is 8Kev to 15Kev; and the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .

5. The method for preparing a flash memory device according to claim 1, wherein: The ion concentration at the top corners on both sides of the isolation structure is greater than the ion concentration on the upper surface of the isolation structure.

6. The method for preparing a flash memory device according to claim 1, wherein: In the process of forming a gate oxide layer on the surface of the substrate in the peripheral logic area through a high-temperature furnace tube oxidation process, the process temperature is 700° C. to 900° C., and the flow rate of oxygen is 1 sccm to 3 sccm.

7. The method for preparing a flash memory device according to claim 1, wherein: The thickness of the gate oxide layer near the top corners on both sides of the isolation structure is The thickness of the gate oxide layer away from the top corner of the isolation structure is 8. The method for preparing a flash memory device according to claim 1, wherein: After forming a gate oxide layer on the surface of the isolation structure in the peripheral logic area and the surface of the substrate by a high-temperature furnace tube oxidation process, the method for preparing the flash memory device further includes: forming a gate material layer, wherein the gate material layer covers the gate oxide layer and the isolation structure of the peripheral logic area and the ONO dielectric layer of the storage area; The gate material layer is etched to define the gate of the peripheral logic area.

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