A doped hafnium zirconium oxide multi-bit ferroelectric memory cell and its fabrication method
By doping elements into the hafnium zirconium oxide multistate ferroelectric layer and performing high-temperature annealing, a mixed O-phase and T-phase crystal is formed, which solves the multistable polarization instability problem of FeRAM, realizes a multistate memory with high durability and low power consumption, and is suitable for large-scale memory arrays.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI JIAOTONG UNIV
- Filing Date
- 2024-10-31
- Publication Date
- 2026-06-30
AI Technical Summary
Existing ferroelectric random access memory (FeRAM) suffers from the instability and defects of hafnium-based ferroelectric thin films, making it difficult to achieve multistable polarization, which makes it difficult to meet the requirements of fast response speed and high storage density of DRAM, while also having the problem of high write power consumption.
By employing a doped hafnium zirconium oxide multistate ferroelectric layer, and by adding dopants such as calcium, strontium, and barium to the hafnium zirconium oxide solid solution, combined with high-temperature annealing, a mixed crystal structure of O-phase and T-phase is formed, which optimizes the stability of polarization states and electric field strength, thereby achieving multistate storage.
It achieves high durability and fast switching capability of polymorphic memory, reduces operating voltage, improves memory rewrite performance and long-term stability, and approaches the durability index of DRAM. It is suitable for large-scale memory arrays and is compatible with existing CMOS processes.
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Figure CN119584546B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of novel storage materials and microelectronic devices, specifically to a doped hafnium zirconium oxide multi-bit ferroelectric storage cell and its preparation method. Background Technology
[0002] Ferroelectric random access memory (FeRAM) is a non-volatile memory material characterized by high-speed read / write capabilities, low operating voltage, high integration density, and low power consumption. It is considered one of the effective solutions to replace DRAM in the future.
[0003] Compared with current DRAM which uses the charge storage principle, nonferrous memory has a wider range of application prospects because it does not require voltage to maintain the storage state and does not require periodic refresh of the stored content. However, due to the limitations of current material technology, mainstream nonferrous memory on the market generally has disadvantages such as slow read and write speeds and high write power consumption, making it difficult to replace or even surpass current DRAM.
[0004] By replacing traditional DRAM dielectric materials with ferroelectric thin films, multiple stable states (such as "00", "01", "10", "11") can be achieved using the different polarization directions of the ferroelectric material. Increasing the number of stable storage states from two to multiple allows FeRAM to simultaneously possess the fast response speed of DRAM and the high storage density advantages of NAND. Since the ferroelectric polarization intensity varies with voltage, incompletely polarized multi-state storage can be achieved using voltages lower than the voltage required for complete polarization switching.
[0005] Simultaneously, it needs to meet the requirements of low-voltage read / write for DRAM and endurance equivalent to DRAM. However, due to the presence and instability of defects in hafnium-based ferroelectric thin films, the polarization of continuously polarized ferroelectric thin films will decay with the increase of the number of flips due to the instability and randomness of defects, making it difficult to form highly durable multistable polarization.
[0006] Therefore, the introduction of phase composition (ferroelectric phase O-phase, antiferroelectric phase T-phase) modulation method of hafnium zirconium oxide thin film to enable ferroelectric capacitors to form multiple steady-state polarization current peaks and achieve multi-steady-state storage has become an urgent goal. Summary of the Invention
[0007] In view of the above-mentioned defects and deficiencies in the existing technology, the present invention aims to provide a novel ultra-low power multi-state lossless read ferroelectric memory container and its preparation method to solve the above-mentioned technical problems.
[0008] To achieve the above objectives, the present invention provides a hafnium-zirconium-oxygen multi-bit ferroelectric memory cell, comprising:
[0009] A first electrode and a second electrode, with a multi-state ferroelectric layer disposed between them;
[0010] The multi-state ferroelectric layer includes a hafnium-zirconium oxide solid solution and doping elements.
[0011] A further improvement of the present invention is that, in the multi-state ferroelectric layer, the doping element is a Group II element calcium (Ca), strontium (Sr), or barium (Ba); or a Group III element scandium (Sc), yttrium (Y), aluminum (Al), gallium (Ga), and indium (In); or a lanthanide element lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu). In the doped hafnium-zirconium oxide solid solution, the ratio of hafnium oxide to zirconium oxide is 0.1–10; the concentration of the doping element is 0.1%–20%.
[0012] A further improvement of the present invention is that the thickness of the first electrode and the second electrode is 2 to 50 nm.
[0013] A further improvement of the present invention is that the materials of the first electrode and the second electrode are any one of ruthenium, molybdenum, titanium, gold, silver, nickel, platinum, tungsten, aluminum, indium, tin, and chromium, or any one of alloys of the above materials, oxynitrides, and metal oxide semiconductors.
[0014] A further improvement of the present invention is that the thickness of the polymorphic ferroelectric layer is 1.5 to 30 nm.
[0015] This invention also provides a method for fabricating a doped hafnium zirconium oxide multi-bit ferroelectric memory cell, which includes the following steps:
[0016] S1: Growing an insulating material as an insulating dielectric layer on the surface of the semiconductor. In this step, the insulating material can be grown by methods such as sol-gel, spin coating, chemical vapor deposition, thermal oxidation, vacuum evaporation, magnetron sputtering, pulsed laser deposition, atomic layer deposition, or molecular beam epitaxy.
[0017] S2: Prepare a first electrode on the surface of the insulating dielectric layer; in this step, a conductive dielectric is deposited as the first electrode by methods such as spin coating, magnetron sputtering, atomic layer deposition or vacuum evaporation.
[0018] S3: Prepare a multi-state ferroelectric layer on the surface of the first electrode. In this step, the multi-state ferroelectric layer is prepared by methods such as sol-gel, spin coating, chemical vapor deposition, thermal oxidation, vacuum evaporation, magnetron sputtering, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy.
[0019] S4: Fabricate a second electrode on a multi-state ferroelectric layer; in this method, a conductive medium can be deposited as the second electrode by methods such as spin coating, magnetron sputtering, atomic layer deposition or vacuum evaporation.
[0020] S5: The device is subjected to high-temperature annealing treatment. Under the combined action of doping elements and electrode stress, the material of the multistate ferroelectric layer undergoes a phase transformation to form a mixed crystal of ferroelectric, antiferroelectric and nonferroelectric phases.
[0021] A further improvement of the present invention is that, in step S5, the temperature of the high-temperature annealing treatment is 350–650°C.
[0022] The combined effects of doping ratio, electrode stress, and temperature control can adjust the stability of polymorphisms and the write voltage level of the memory to meet the requirements of the drive circuit. This method results in more uniform phase mixing spatial distribution and fewer defect clusters, thereby effectively reducing operating voltage and improving memory durability.
[0023] The advantages of this invention are as follows:
[0024] (1) The multi-state memory of the present invention includes an electrode layer and a multi-state ferroelectric layer. The multi-state ferroelectric layer has stable polymorphisms for storing multi-bit data and can quickly switch between different storage states; the electrode layer is used to provide electric field driving force and simultaneously regulate stress and oxygen vacancy spatial distribution in the electrode-ferroelectric interface layer; the distribution and concentration of elements are controlled by doping elements and the combined effect of electrodes to adjust the distribution between the material phase composition and oxygen vacancy in the ferroelectric layer; at the same time, the stability of polarization states and the driving electric field strength of each bit polarization state are optimized. This regulation method can optimize lattice stability and polarization stability, and improve the rewrite performance and long-term stability of the memory.
[0025] (2) Data durability can reach 1E11, which is close to the current durability index of DRAM.
[0026] (3) The uniformity of the devices can meet the requirements of the array and can be applied to large-scale memory.
[0027] (4) It is fully compatible with current CMOS technology and does not require the introduction of additional doping elements and process equipment. Attached Figure Description
[0028] Figure 1 A schematic structural diagram of a ferroelectric storage capacitor provided in an embodiment of this application;
[0029] Figure 2 This is a schematic diagram of the current continuous polarization multistate problem;
[0030] Figure 3 A schematic structural diagram of the ferroelectric memory cell provided in the embodiments of this application;
[0031] Figure 4 A schematic diagram of the ferroelectric memory cell provided in the embodiments of this application;
[0032] Figure 5 Schematic polarization current and polarization state of the ferroelectric memory cell provided in the embodiments of this application;
[0033] Figure 6 This is a schematic result of the ferroelectric memory cell provided in the embodiments of this application.
[0034] The attached figures are labeled as follows:
[0035] 1-First electrode, 2-Second electrode, 3-Multi-state ferroelectric layer. Detailed Implementation
[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.
[0037] Some exemplary embodiments of the invention have been described for illustrative purposes. It should be understood that the invention may be implemented in other ways not specifically shown in the accompanying drawings.
[0038] like Figure 1 As shown, the device structure of the doped hafnium zirconium oxide multi-bit ferroelectric memory cell provided in this embodiment includes a sandwich structure formed by a first electrode 1, a second electrode 2, and a multi-state ferroelectric layer 3. The sandwich structure can be a metal electrode-ferroelectric thin film-metal electrode (MFM) structure, but is not limited thereto. In some embodiments, electrodes 1 and 2 can also be made of materials other than metals, such as metal oxide semiconductors. In this embodiment, the materials of the two electrodes are not limited.
[0039] The ferroelectric material of the ferroelectric layer in this application is a solid solution of hafnium oxide (HfO2) and zirconium oxide (ZrO2) doped with single or multiple elements, thereby ensuring the compatibility of ferroelectric devices with CMOS processes and their scalability.
[0040] Since polymorphic memory plays a positive role in reducing memory power consumption and improving integration density, the remnant polarization (Pr) of most hafnium oxide-based ferroelectric materials exhibits a linear increase in Pr value with increasing electric field after the applied electric field exceeds the coercive electric field (see reference). Figure 2-01), this phenomenon can occur in multi-state polarization. However, due to the removal of oxygen from the ferroelectric film by the metal electrode during the bottom electrode and post-annealing process, a certain number of oxygen vacancies are generated at the metal-ferroelectric layer interface, causing a built-in electric field. Initially, this pins some ferroelectric dipoles, and may even cause the opposite polarization direction. Due to the instability of oxygen vacancy pinning and the ease with which oxygen vacancies move under an electric field, and because oxygen vacancies also play a role in stabilizing the ferroelectric phase, when oxygen vacancies begin to diffuse and transfer to the bulk phase of the ferroelectric film, they can cause some non-ferroelectric phase (M-phase) to transform into ferroelectric phase (O-phase), further increasing Pr (see reference). Figure 2 -02). As the electric field continues to cycle, oxygen is continuously lost from the ferroelectric thin film, the electrode interface is continuously oxidized, and more defects and oxygen vacancies begin to form. The interface begins to divide the applied electric field, causing a decrease in the electric field experienced by the ferroelectric layer. At the same time, the charges and vacancies trapped by defects also begin to pin some ferroelectric dipoles, preventing them from flipping, resulting in a decrease in Pr. This is known as "fatigue" (see reference). Figure 2 -02). Therefore, using linear incomplete polarization for polymorphic storage will cause logical ambiguity of polymorphism during looping for the reasons mentioned above (see reference). Figure 2 -02).
[0041] In contrast, this application (reference) Figure 3 An embodiment provides a ferroelectric device in which one or more doping elements are added to a non-fixed proportion of hafnium zirconium oxide solid solution in a multi-state ferroelectric layer 3. Figure 3 The doping configuration shown is for illustrative purposes only; actual doping can be layered or uniformly mixed.
[0042] After annealing, this configuration, through the interaction of doping elements and electrodes, can generate a structure in which the aforementioned O-phase and antiferroelectric T-phase are uniformly mixed within the ferroelectric layer 3.
[0043] A suitable ratio of O / T-phase will exhibit a single-peak behavior in the ferroelectric polarization during the reversal process, distinct from the O-phase-dominated behavior, resulting in multiple stable polarization current peaks in the ferroelectric memory cells processed by this application (see reference). Figure 5 -01), thus enabling the polarization state to maintain a stable polarization window during long-term flipping.
[0044] The stable multi-bit state in this configuration utilizes the O-phase in the stack to first generate an initial polarization current peak (half-polarized state) with a relatively small polarization voltage. As the electric field continues to increase, when the polarization condition of the T-phase in the stack is reached, another polarization current peak appears. At this point, the state of the multi-state ferroelectric layer 3 can be considered as a fully polarized state. Storing the half-polarized and fully polarized states in both positive and negative directions in memory generates a stable two-bit four-state configuration.
[0045] It is important to note that the difference in the magnitude of these two polarization electric fields is caused by the polarization electric field strength required by the O / T-phase itself. Therefore, the O / T-phase mixed ferroelectric layer 3 will naturally split into two polarization states with different electric field phases.
[0046] Those skilled in the art will understand that the polarization state of an antiferroelectric layer alone cannot be maintained when the electric field is removed. Therefore, a pure antiferroelectric layer is not used for non-volatile storage. Figure 4 As shown in this setup, when full polarization is completed, the O-phase generates half polarization, which will generate charge pinning in the electrode. Even after the external electric field is removed, part of the polarization electric field generated by the O-phase polarization can still be maintained in the capacitor. When the electric field of the O-phase is greater than the depolarization field of the T-phase, the polarization charge in the full polarization state can still be maintained when the electric field is 0, thereby realizing two storage states in each direction.
[0047] It should be understood that by changing the proportions of various elements, the phase composition and stability can be controlled, thereby meeting the device parameter adjustment requirements in practical applications.
[0048] On the other hand, electrode stress also plays a significant role in the proportion and durability of phase components. The stacking ratio, thickness, and sequence of the polymorphic ferroelectric layer 3 in this configuration will be adjusted accordingly based on the electrodes.
[0049] It should be noted that this setting has more prominent advantages than other O / T phase component control methods, such as being fully compatible with current CMOS processes and not requiring the introduction of additional doping elements and process equipment.
[0050] On the other hand, this configuration, even when thinned to 5nm, still maintains higher Pr and lower operating voltage. This allows for high integration and low power consumption.
[0051] On the other hand, such as Figure 6 As shown, the durability of this configuration can reach 1E11, which is close to the current durability index of DRAM.
[0052] On the other hand, the uniformity of the devices in this configuration can meet the requirements of the array.
[0053] In one specific embodiment:
[0054] like Figure 3 As shown, this embodiment provides a hafnium-zirconium-oxygen multi-bit ferroelectric memory cell, which includes: a first electrode 1 and a second electrode 2, with a multi-state ferroelectric layer 3 disposed between them. The first electrode is made of indium and has a thickness of 10 nm; the second electrode is made of chromium and has a thickness of 20 nm.
[0055] The fabrication method of this device includes the following steps:
[0056] S1: An insulating material is grown on the surface of a semiconductor by chemical vapor deposition as an insulating dielectric layer;
[0057] S2: The first electrode is fabricated on the surface of the insulating dielectric layer by magnetron sputtering;
[0058] S3: A multi-state ferroelectric layer is prepared on the surface of the first electrode by chemical vapor deposition;
[0059] S4: The second electrode is fabricated on the multi-state ferroelectric layer by magnetron sputtering;
[0060] S5: The device undergoes high-temperature annealing, which, under the combined action of dopant elements and electrode stress, causes a phase transformation in the multi-state ferroelectric layer, forming a mixed crystal of ferroelectric, antiferroelectric, and nonferroelectric phases. In step S5, the high-temperature annealing temperature is 350–650°C.
[0061] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A hafnium-zirconium-oxygen multi-bit ferroelectric memory cell, characterized in that... include: A multi-state ferroelectric layer is disposed between the first electrode and the second electrode; The multi-state ferroelectric layer includes a hafnium-zirconium oxide solid solution and doping elements; The multi-state ferroelectric layer undergoes high-temperature annealing, and under the combined action of doping elements and electrode stress, the material of the multi-state ferroelectric layer undergoes a phase transformation to form a mixed crystal of ferroelectric, antiferroelectric, and nonferroelectric phases. The ferroelectric phase and the antiferroelectric phase enable the multi-state ferroelectric layer to have multiple polarization current peaks, thereby forming multiple storage states; The doped elements in the multi-state ferroelectric layer include: Group II elements calcium, strontium, or barium; Or group III elements scandium, yttrium, aluminum, gallium, and indium; or doped with lanthanide elements lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; In the multi-state ferroelectric layer, the ratio of hafnium oxide to zirconium oxide in the hafnium-zirconium oxide solid solution is 0.1~10; the concentration of doping elements is 0.1%~20%; and the thickness of the multi-state ferroelectric layer is 1.5~30 nm.
2. The hafnium-zirconium-oxygen multi-bit ferroelectric memory cell according to claim 1, characterized in that, The thickness of the first electrode and the second electrode is 2 to 50 nm.
3. The hafnium-zirconium-oxygen multi-bit ferroelectric memory cell according to claim 1, characterized in that, The materials of the first electrode and the second electrode are any one of ruthenium, molybdenum, titanium, gold, silver, nickel, platinum, tungsten, aluminum, indium, tin, and chromium, or any one of the alloys of the above materials, oxynitrides, and metal oxide semiconductors.
4. A method for fabricating a doped hafnium-zirconium oxide multi-bit ferroelectric memory cell, used to fabricate the doped hafnium-zirconium oxide multi-bit ferroelectric memory cell according to any one of claims 1 to 3, characterized in that... Includes the following steps: S1: Growing an insulating material on the surface of a semiconductor as an insulating dielectric layer; S2: Prepare the first electrode on the surface of the insulating dielectric layer; S3: Prepare a multi-state ferroelectric layer on the surface of the first electrode; S4: Fabrication of a second electrode on a multi-state ferroelectric layer; S5: The device is subjected to high-temperature annealing treatment. Under the combined action of doping elements and electrode stress, the material of the multistate ferroelectric layer undergoes a phase transformation to form a mixed crystal of ferroelectric, antiferroelectric and nonferroelectric phases. The high-temperature annealing temperature is 350–650°C; the ferroelectric phase and the antiferroelectric phase enable the multi-state ferroelectric layer to have multiple polarization current peaks, thereby forming multiple storage states.