IGBT structure and semiconductor devices

Abstract

The present application discloses an IGBT structure and semiconductor device. The IGBT structure includes: a substrate; a drift region of a first conductivity type; a collector region of a second conductivity type; a first dummy gate; a second dummy gate, the first dummy gate and the second dummy gate being spaced apart in a second direction; a first well region of a second conductivity type, the first well region being disposed on a side of the drift region facing a second main surface and between the first dummy gate and the second dummy gate; an insulating layer disposed on the second main surface; an emitter metal covering the insulating layer; a first floating region of the first conductivity type and a second floating region, respectively disposed on either side of the first well region of the second conductivity type in the second direction, with the first floating region and the second floating region both contacting the drift region on their sides facing the first main surface; and a first contact region of the second conductivity type disposed on their side facing the second main surface. The IGBT structure and semiconductor device of the present application can effectively reduce both conduction loss and turn-off loss.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to an IGBT structure and a semiconductor device. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is widely used in various power switching applications due to its excellent electrical characteristics and high tolerance to destructive device failures.

[0003] To adjust the capacitance of IGBT devices, dummy gates and active gates are typically placed in the cell region of the IGBT device. The semiconductor material between adjacent active gates is connected to the emitter metal through contact regions and contact holes. To reduce the on-state voltage drop, the P-well region between adjacent dummy gates is typically set to a floating state. However, this reduces the channel for hole extraction during device shutdown, increasing tail current and reducing switching speed.

[0004] Therefore, improvements are needed to at least partially solve the above problems. Summary of the Invention

[0005] The present invention aims to at least partially address the above-mentioned problems. To this end, one object of the present invention is to provide an IGBT structure that reduces both conduction and turn-off losses. Another object of the present invention is to provide a semiconductor device having the IGBT structure.

[0006] The IGBT structure includes:

[0007] a substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface and the second main surface are spaced apart in a first direction;

[0008] a drift region of a first conductivity type, the drift region being provided between the first main surface and the second main surface;

[0009] a collector region of a second conductivity type, the collector region being provided on a side of the drift region facing the first main surface, and a side of the collector region away from the drift region constituting at least a portion of the first main surface;

[0010] a first dummy gate extending from the second main surface to the first main surface into the drift region;

[0011] a second dummy gate, the second dummy gate extending from the second main surface to the first main surface into the drift region, the first dummy gate and the second dummy gate being spaced apart in a second direction, the second direction being perpendicular to the first direction;

[0012] a first well region of a second conductivity type, the first well region being provided on a side of the drift region facing the second main surface and between the first dummy gate and the second dummy gate, the side of the first well region facing the second main surface constituting a portion of the second main surface;

[0013] an insulating layer, provided on the second main surface;

[0014] an emitter metal covering the insulating layer;

[0015] a first floating region of a first conductivity type;

[0016] a second floating region of a first conductivity type, wherein the first floating region and the second floating region are respectively arranged on both sides of a first well region of the second conductivity type in the second direction, a side of the first floating region away from the second floating region contacts the first dummy gate, a side of the second floating region away from the second floating region contacts the second dummy gate, and a side of the first floating region facing the first main surface and a side of the second floating region facing the first main surface both contact the drift region;

[0017] a first contact region of the second conductivity type, the first contact region being provided on a side of the first well region facing the second main surface, the side of the first contact region facing the second main surface constituting a portion of the second main surface, a first contact hole being provided on the insulating layer at a position corresponding to the first contact region, the emitter metal being in contact with the first contact region through the first contact hole;

[0018] The doping concentration of the first floating region and the doping concentration of the second floating region are both greater than the doping concentration of the drift region.

[0019] The above technical solution has the following advantages and beneficial effects: when the IGBT structure is turned on, due to the existence of the first floating region and the second floating region, the holes injected from the collector region can be accelerated to cross the PN junction and reach the first well region under the action of conductivity modulation, thereby increasing the current capacity and reducing the conduction loss; when the IGBT structure is turned off, under the action of conductivity modulation, the first floating region and the second floating region will accelerate the extraction of minority carriers (holes) remaining in the drift region, eliminate the remaining minority carriers through the first contact region, accelerate the shutdown, reduce the tail current, and reduce the shutdown loss.

[0020] In some embodiments, there are multiple first floating areas, and the multiple first floating areas are arranged at intervals in the third direction;

[0021] There are a plurality of the second floating areas, and the plurality of the second floating areas are arranged at intervals in the third direction;

[0022] The third direction is perpendicular to the first direction and the second direction.

[0023] The above technical solution has the following advantages and beneficial effects: it can make the current pass more efficiently and increase the current carrying capacity.

[0024] In some embodiments, the doping concentration of the first floating region is more than 100 times the doping concentration of the drift region;

[0025] The doping concentration of the second floating region is more than 100 times the doping concentration of the drift region.

[0026] The above technical solution has the following advantages and beneficial effects: setting the doping concentrations of the first floating region and the second floating region within the above range can more effectively increase the flow capacity and the speed of extracting minority carriers.

[0027] In some embodiments, a length of the first floating region in the second direction is less than one eighth of a distance between the first dummy gate and the second dummy gate;

[0028] A length of the second floating region in the second direction is less than one eighth of a distance between the first dummy gate and the second dummy gate.

[0029] The above technical solution has the following advantages and beneficial effects: setting the lengths of the first floating region and the second floating region in the second direction within the above range can enable holes to be extracted more effectively.

[0030] In some embodiments, the length of the first floating region in the first direction is less than one quarter of the length of the first well region in the first direction;

[0031] A length of the second floating region in the first direction is less than one quarter of a length of the first well region in the first direction.

[0032] The above technical solution has the following advantages and beneficial effects: it can effectively avoid a significant increase in resistance caused by the provision of the first floating region and the second floating region.

[0033] In some embodiments, the IGBT structure further includes:

[0034] a first active gate, extending from the second main surface toward the first main surface into the drift region, and disposed on a side of the first dummy gate away from the second dummy gate;

[0035] a second active gate, the second active gate extending from the second main surface toward the first main surface into the drift region, the second active gate being disposed on a side of the second dummy gate away from the first dummy gate;

[0036] a second well region of a second conductivity type, the second well region being provided on a side of the drift region facing the second main surface and between the first dummy gate and the first active gate, the side of the second well region facing the second main surface constituting a portion of the second main surface;

[0037] a third well region of the second conductivity type, the third well region being provided on a side of the drift region facing the second main surface and between the second dummy gate and the second active gate, wherein a side of the third well region facing the second main surface constitutes a portion of the second main surface;

[0038] a second contact region of a second conductivity type, the second contact region being provided on a side of the second well region facing the second main surface, the side of the second contact region facing the second main surface constituting a portion of the second main surface, a second contact hole being provided on the insulating layer at a position corresponding to the second contact region, and the emitter metal being in contact with the second contact region through the second contact hole;

[0039] a third contact region of the second conductivity type, the third contact region being provided on a side of the second well region facing the second main surface, the side of the third contact region facing the second main surface constituting a portion of the second main surface, a third contact hole being provided on the insulating layer at a position corresponding to the third contact region, and the emitter metal being in contact with the third contact region through the third contact hole;

[0040] a first emitter region of a first conductivity type, the first emitter region being disposed on a side of the second well region facing the second main surface and between the first active gate and the second contact region, the side of the first emitter region facing the second main surface constituting a portion of the second main surface;

[0041] A second emitter region of the first conductivity type is provided on the side of the second well region facing the second main surface and is located between the second active gate and the third contact region. The side of the second emitter region facing the second main surface constitutes part of the second main surface.

[0042] The above technical solution has the following advantages and beneficial effects: it can provide a channel for hole extraction, reduce tail current, and increase switching speed.

[0043] In some embodiments, the IGBT structure further includes a field stop region of a first conductivity type, wherein the field stop region is disposed between the collector region and the drift region.

[0044] The above technical solution has the following advantages and beneficial effects: it can effectively improve the voltage resistance of the IGBT structure.

[0045] In some embodiments, the first conductivity type is N-type;

[0046] The second conductivity type is P type.

[0047] In some embodiments, the first dummy gate includes a first gate trench extending from the second main surface to the first main surface to the drift region, a first gate dielectric layer located on an inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench, wherein the first polysilicon gate is a floating gate;

[0048] The second dummy gate includes a second gate trench extending from the second main surface to the first main surface to the drift region, a second gate dielectric layer located on an inner surface of the second gate trench, and a second polysilicon gate located on a side of the second gate dielectric layer away from the inner surface of the second gate trench, wherein the second polysilicon gate is a floating gate;

[0049] The side of the first floating region away from the second floating region contacts the side of the first gate dielectric layer away from the first polysilicon gate, and the side of the second floating region away from the second floating region contacts the side of the second gate dielectric layer away from the second polysilicon gate.

[0050] The semiconductor device includes the IGBT structure described above.

[0051] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The following drawings of this application are hereby incorporated as part of this application for understanding this application. The drawings show the embodiments of this application and their descriptions, and are used to explain the device and principle of this application. In the drawings,

[0053] Figure 1 is a schematic diagram of an IGBT structure according to an embodiment of the present application;

[0054] Figure 2 for Figure 1 Schematic cross-sectional view at AA in the middle.

[0055] Description of reference numerals:

[0056] 100 - substrate, 101 - first main surface, 102 - second main surface, 110 - drift region, 111 - collector region, 112 - first dummy gate, 113 - second dummy gate, 114 - first well region, 115 - first floating region, 116 - second floating region, 117 - first contact region, 118 - first active gate, 119 - second active gate, 120 - second well region, 121 - third well region, 122 - second contact region, 123 - third contact region, 124 - first emitter region, 125 - second emitter region;

[0057] 200-insulation layer;

[0058] 300-emitter metal;

[0059] 400-Collector Metal. DETAILED DESCRIPTION

[0060] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some technical features well known in the art are not described in order to avoid confusion with the present application.

[0061] It should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present application to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0062] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0063] Spatially relative terms, such as "below," "beneath," "beneath," "above," "upper," etc., may be used herein for convenience to describe the relationship of one element or feature to other elements or features illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientations depicted in the figures.

[0064] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0065] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present application should not be limited to the specific shapes shown herein, but rather include shape deviations due to, for example, manufacturing. Therefore, what is shown in the figures is schematic in nature, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of the present application.

[0066] Refer to the attached Figure 1 、 2 An IGBT structure according to an embodiment of the present application is exemplarily described. In the following description, N and P represent the conductivity type of a semiconductor. In this embodiment, the first conductivity type is set to N type and the second conductivity type is set to P type.

[0067] The IGBT structure mainly includes a base 100, a drift region 110 of the first conductive type, a collector region 111 of the second conductive type, a first virtual gate 112, a second virtual gate 113, a first well region 114 of the second conductive type, an insulating layer 200, an emitter metal 300, a collector metal 400, a first floating region 115 of the first conductive type, a second floating region 116 of the first conductive type and a first contact region 117 of the second conductive type.

[0068] The base 100 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101 . The first main surface 101 and the second main surface 102 are spaced apart in a first direction.

[0069] The drift region 110 of the first conductivity type is provided between the first main surface 101 and the second main surface 102. The drift region 110 generally has a relatively low doping concentration, and therefore has a relatively high resistance and can withstand a relatively high voltage.

[0070] The collector region 111 of the second conductivity type is provided on the side of the drift region 110 facing the first main surface 101 , and the side of the collector region 111 away from the drift region 110 constitutes at least a portion of the first main surface 101

[0071] The first dummy gate 112 extends from the second main surface 102 toward the first main surface 101 into the drift region 110. The first dummy gate 112 includes a first gate trench extending from the second main surface 102 toward the first main surface 101 into the drift region 110, a first gate dielectric layer located on the inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench. The first polysilicon gate is a floating gate. That is, the first polysilicon gate is not connected to an external drive signal source, and its potential is not directly controlled by an external drive signal.

[0072] The second virtual gate 113 extends from the second main surface 102 to the first main surface 101 into the drift region 110. The second virtual gate 113 includes a second gate trench extending from the second main surface 102 to the first main surface 101 into the drift region 110, a second gate dielectric layer located on the inner surface of the second gate trench, and a second polysilicon gate located on the side of the second gate dielectric layer away from the inner surface of the second gate trench. The second polysilicon gate is a floating gate. That is, the second polysilicon gate is not connected to an external drive signal source, and its potential is not directly controlled by an external drive signal. The first virtual gate 112 and the second virtual gate 113 are spaced apart in a second direction, and the second direction is perpendicular to the first direction.

[0073] The first well region 114 of the second conductivity type is provided on the side of the drift region 110 facing the second main surface 102 and is located between the first dummy gate 112 and the second dummy gate 113 . The side of the first well region 114 facing the second main surface 102 constitutes a portion of the second main surface 102 .

[0074] The insulating layer 200 is provided on the second main surface 102. For example, the insulating layer 200 may be a silicon dioxide layer.

[0075] The emitter metal 300 covers the side of the insulating layer 200 away from the second main surface 102 .

[0076] The collector metal 400 is provided on the first main surface 101 .

[0077] A first floating region 115 of the first conductivity type and a second floating region 116 of the first conductivity type are respectively disposed on opposite sides of the first well region 114 of the second conductivity type in the second direction. The side of the first floating region 115 facing away from the second floating region 116 contacts the first dummy gate 112, while the side of the second floating region 116 facing away from the second floating region 116 contacts the second dummy gate 113. Specifically, the side of the first floating region 115 facing away from the second floating region 116 contacts the side of the first gate dielectric layer facing away from the first polysilicon gate, while the side of the second floating region 116 facing away from the second floating region 116 contacts the side of the second gate dielectric layer facing away from the second polysilicon gate. The side of the first floating region 115 facing the first main surface 101 and the side of the second floating region 116 facing the first main surface 101 both contact the drift region 110. The doping concentration of both the first floating region 115 and the second floating region 116 is significantly greater than the doping concentration of the drift region 110.

[0078] A first contact region 117 of the second conductivity type is provided on a side of the first well region 114 facing the second main surface 102. The side of the first contact region 117 facing the second main surface 102 constitutes a portion of the second main surface 102. A first contact hole is provided on the insulating layer 200 at a position corresponding to the first contact region 117. The emitter metal 300 contacts the first contact region 117 through the first contact hole. The doping concentration of the first contact region 117 is greater than the doping concentration of the first well region 114.

[0079] According to the IGBT structure of this embodiment, when the IGBT structure is turned on (i.e., when the semiconductor device having this IGBT structure is turned on), the presence of the highly doped first floating region 115 and second floating region 116 accelerates holes injected from the collector region 111 through conductivity modulation, crossing the PN junction and reaching the first well region 114, thereby increasing current flow capacity and reducing conduction losses. When the IGBT structure is turned off (i.e., when the semiconductor device having this IGBT structure is turned off), the first floating region 115 and second floating region 116 accelerate the extraction of minority carriers (holes) remaining in the drift region 110 under the effect of conductivity modulation, and remove the remaining minority carriers through the first contact region 117, accelerating shutdown, reducing tail current, and lowering turn-off losses. Furthermore, the losses and heat generation of the IGBT structure during switching can be effectively reduced, thereby improving its reliability.

[0080] In some embodiments, see Appendix Figure 2 There are multiple first floating areas 115, and the multiple first floating areas 115 are arranged at intervals in the third direction. There are multiple second floating areas 116, and the multiple second floating areas 116 are arranged at intervals in the third direction. The third direction is perpendicular to the first direction and the second direction.

[0081] By arranging a plurality of first floating areas 115 and a plurality of second floating areas 116 at intervals in the third direction, the active areas of the first floating areas 115 and the second floating areas 116 can be effectively expanded, so that current can pass more efficiently, the current carrying capacity is increased, and the conduction loss is reduced.

[0082] In some embodiments, the doping concentration of the first floating region 115 is more than 100 times the doping concentration of the drift region 110 , and the doping concentration of the second floating region 116 is more than 100 times the doping concentration of the drift region 110 .

[0083] By setting the doping concentrations of the first floating region 115 and the second floating region 116 within the above range, the current flow capacity and the speed of extracting minority carriers can be more effectively increased.

[0084] In some embodiments, see Appendix Figure 2 The length L1 of the first floating region 115 in the second direction is less than one-eighth of the distance D1 between the first dummy gate 112 and the second dummy gate 113, and the length L2 of the second floating region 116 in the second direction is less than one-eighth of the distance D1 between the first dummy gate 112 and the second dummy gate 113. That is, the sum of the length L1 of the first floating region 115 in the second direction and the length L2 of the second floating region 116 in the second direction is less than one-quarter of the distance D1 between the first dummy gate 112 and the second dummy gate 113. It should be noted that the length L1 (L2) of the first floating region 115 (second floating region 116) in the second direction is its maximum length in the second direction, i.e., its longest length in the second direction. The distance D1 between the first dummy gate 112 and the second dummy gate 113 is the distance between the side of the first dummy gate 112 facing the second dummy gate 113 and the side of the second dummy gate 113 facing the first dummy gate 112, where the drift region 110 contacts the first well region 114.

[0085] By setting the length of the first floating region 115 and the second floating region 116 in the second direction within the above range, holes can be more effectively extracted, thereby accelerating shutdown, reducing tail current, and lowering turn-off losses. If the length of the first floating region 115 and the second floating region 116 in the second direction is too long, it may adversely affect the movement path of holes and the electric field distribution, interfere with the normal movement of holes, and hinder the extraction of holes.

[0086] In some embodiments, the length of the first floating region 115 in the first direction is less than one-quarter the length of the first well region 114 in the first direction, and the length of the second floating region 116 in the first direction is less than one-quarter the length of the first well region 114 in the first direction. It should be noted that the length of the first floating region 115 (second floating region 116) in the first direction is its maximum length in the first direction, that is, its longest length in the second direction. The length of the first well region 114 in the first direction is the distance between the side of the first well region 114 that contacts the drift region 110 and the second main surface 102.

[0087] By setting the lengths of the first floating region 115 and the second floating region 116 in the first direction within the above range, a significant increase in resistance caused by the setting of the first floating region 115 and the second floating region 116 can be effectively avoided, and a significant increase in conduction loss can be avoided.

[0088] See attached Figure 1 In some embodiments, the IGBT structure further includes a first active gate 118, a second active gate 119, a second well region 120 of the second conductivity type, a third well region 121 of the second conductivity type, a second contact region 112 of the second conductivity type, a third contact region 123 of the second conductivity type, a first emitter region 124 of the first conductivity type, and a second emitter region 125 of the first conductivity type.

[0089] The first active gate 118 extends from the second main surface 102 to the first main surface 101 into the drift region 110. The first active gate 118 includes a third gate trench extending from the second main surface 102 to the first main surface 101 into the drift region 110, a third gate dielectric layer located on the inner surface of the third gate trench, and a third polysilicon gate located on a side of the third gate dielectric layer away from the inner surface of the third gate trench. The third polysilicon gate is an active gate. That is, the third polysilicon gate is connected to an external drive signal source, and its potential is directly controlled by the external drive signal. The first active gate 118 is arranged on the side of the first dummy gate 112 away from the second dummy gate 113.

[0090] The second active gate 119 extends from the second main surface 102 to the first main surface 101 into the drift region 110. The second active gate 119 includes a fourth gate trench extending from the second main surface 102 to the second main surface 102 into the drift region 110, a fourth gate dielectric layer located on the inner surface of the fourth gate trench, and a fourth polysilicon gate located on the side of the fourth gate dielectric layer away from the inner surface of the fourth gate trench. The fourth polysilicon gate is an active gate. That is, the fourth polysilicon gate is connected to an external drive signal source, and its potential is directly controlled by the external drive signal. The second active gate 119 is arranged on the side of the second dummy gate 113 away from the first dummy gate 112, and the second active gate 119 is spaced apart from the second dummy gate 113.

[0091] The second well region 120 of the second conductivity type is provided on the side of the drift region 110 facing the second main surface 102 and is located between the first dummy gate 112 and the first active gate 118 . The side of the second well region 120 facing the second main surface 102 constitutes a portion of the second main surface 102 .

[0092] The third well region 121 of the second conductivity type is provided on the side of the drift region 110 facing the second main surface 102 and is located between the second dummy gate 113 and the second active gate 119 . The side of the third well region 121 facing the second main surface 102 constitutes part of the second main surface 102 .

[0093] A second contact region 112 of the second conductivity type is provided on a side of the second well region 120 facing the second main surface 102. The side of the second contact region 112 facing the second main surface 102 constitutes a portion of the second main surface 102. A second contact hole is provided on the insulating layer 200 at a position corresponding to the second contact region 112. The emitter metal 300 contacts the second contact region 112 through the second contact hole. The doping concentration of the second contact region 112 is greater than that of the second well region 120.

[0094] A third contact region 123 of the second conductivity type is provided on the side of the second well region 120 facing the second main surface 102. The side of the third contact region 123 facing the second main surface 102 constitutes a portion of the second main surface 102. A third contact hole is provided on the insulating layer 200 at a position corresponding to the third contact region 123. The emitter metal 300 contacts the third contact region 123 through the third contact hole. The doping concentration of the third contact region 123 is greater than that of the third well region 121.

[0095] A first emitter region 124 of the first conductivity type is disposed on a side of the second well region 120 facing the second main surface 102 and is located between the first active gate 118 and the second contact region 112. The side of the first emitter region 124 facing the second main surface 102 constitutes a portion of the second main surface 102. The first emitter region 124 is in contact with the first active gate 118 and the second contact region 112. The doping concentration of the first emitter region 124 is greater than the doping concentration of the drift region 110.

[0096] A second emitter region 125 of the first conductivity type is disposed on a side of the third well region 121 facing the second main surface 102 and is located between the second active gate 119 and the third contact region 123. The side of the second emitter region 125 facing the second main surface 102 constitutes a portion of the second main surface 102. The second emitter region 125 is in contact with the second active gate 119 and the third contact region 123. The doping concentration of the second emitter region 125 is greater than the doping concentration of the drift region 110.

[0097] The above-mentioned structural arrangement can provide a channel for hole extraction, reduce tail current, and increase switching speed.

[0098] See attached Figure 1 In some embodiments, the IGBT structure further includes a field stop region of the first conductivity type, and the field stop region is provided between the collector region 111 and the drift region 110. The doping concentration of the field stop region is higher than the doping concentration of the drift region 110. The main function of the field stop region is to terminate the electric field when the IGBT is in the off state, preventing the electric field from penetrating into the collector region 111, thereby improving the withstand voltage capability. When a high voltage is applied, the field stop region can withstand a portion of the electric field, so that the electric field gradually weakens before reaching the collector region 111, thereby avoiding breakdown of the collector region 111. The field stop region can also reduce the duration and amplitude of the tail current by adjusting the carrier distribution and extraction speed. The reduction of the tail current helps to reduce the turn-off loss.

[0099] The present application also provides a semiconductor device including the above IGBT structure. Exemplarily, the semiconductor device may be a RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) device.

[0100] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely illustrative and are not intended to limit the scope of the present application. Various changes and modifications may be made therein by those skilled in the art without departing from the scope and spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as required by the appended claims.

[0101] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0102] Similarly, it should be understood that in order to streamline the present application and aid in understanding one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together into a single embodiment, figure, or description thereof. However, this approach of the present application should not be interpreted as reflecting the intention that the application claimed for protection requires more features than those explicitly recited in each claim. More precisely, as reflected in the corresponding claims, the inventive point is that the corresponding technical problem can be solved with fewer features than all the features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim itself serving as a separate embodiment of the present application.

[0103] Those skilled in the art will understand that, except where mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus disclosed herein may be combined in any combination. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0104] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of this application and to form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

[0105] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. An IGBT structure, characterized in that: include: a substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface and the second main surface are spaced apart in a first direction; a drift region of a first conductivity type, the drift region being provided between the first main surface and the second main surface; a collector region of a second conductivity type, the collector region being provided on a side of the drift region facing the first main surface, and a side of the collector region away from the drift region constituting at least a portion of the first main surface; a first dummy gate extending from the second main surface to the first main surface into the drift region; a second dummy gate, the second dummy gate extending from the second main surface to the first main surface into the drift region, the first dummy gate and the second dummy gate being spaced apart in a second direction, the second direction being perpendicular to the first direction; a first well region of a second conductivity type, the first well region being provided on a side of the drift region facing the second main surface and between the first dummy gate and the second dummy gate, the side of the first well region facing the second main surface constituting a portion of the second main surface; an insulating layer, provided on the second main surface; an emitter metal covering a side of the insulating layer away from the second main surface; a first floating region of a first conductivity type; a second floating region of a first conductivity type, wherein the first floating region and the second floating region are respectively arranged on both sides of a first well region of the second conductivity type in the second direction, a side of the first floating region away from the second floating region contacts the first dummy gate, a side of the second floating region away from the second floating region contacts the second dummy gate, and a side of the first floating region facing the first main surface and a side of the second floating region facing the first main surface both contact the drift region; a first contact region of the second conductivity type, the first contact region being provided on a side of the first well region facing the second main surface, the side of the first contact region facing the second main surface constituting a portion of the second main surface, a first contact hole being provided on the insulating layer at a position corresponding to the first contact region, the emitter metal being in contact with the first contact region through the first contact hole; The doping concentration of the first floating region and the doping concentration of the second floating region are both greater than the doping concentration of the drift region.

2. The IGBT structure according to claim 1, characterized in that: There are a plurality of the first floating areas, and the plurality of the first floating areas are arranged at intervals in the third direction; There are a plurality of the second floating areas, and the plurality of the second floating areas are arranged at intervals in the third direction; The third direction is perpendicular to the first direction and the second direction.

3. The IGBT structure according to claim 1 or 2, characterized in that: The doping concentration of the first floating region is more than 100 times the doping concentration of the drift region; The doping concentration of the second floating region is more than 100 times the doping concentration of the drift region.

4. The IGBT structure according to claim 1 or 2, characterized in that: The length of the first floating region in the second direction is less than one eighth of the distance between the first dummy gate and the second dummy gate; A length of the second floating region in the second direction is less than one eighth of a distance between the first dummy gate and the second dummy gate.

5. The IGBT structure according to claim 1 or 2, characterized in that: The length of the first floating region in the first direction is less than one quarter of the length of the first well region in the first direction; A length of the second floating region in the first direction is less than one quarter of a length of the first well region in the first direction.

6. The IGBT structure according to claim 1 or 2, characterized in that: The IGBT structure further includes: a first active gate, extending from the second main surface toward the first main surface into the drift region, and disposed on a side of the first dummy gate away from the second dummy gate; a second active gate, the second active gate extending from the second main surface toward the first main surface into the drift region, the second active gate being disposed on a side of the second dummy gate away from the first dummy gate; a second well region of a second conductivity type, the second well region being provided on a side of the drift region facing the second main surface and between the first dummy gate and the first active gate, the side of the second well region facing the second main surface constituting a portion of the second main surface; a third well region of the second conductivity type, the third well region being provided on a side of the drift region facing the second main surface and between the second dummy gate and the second active gate, wherein a side of the third well region facing the second main surface constitutes a portion of the second main surface; a second contact region of a second conductivity type, the second contact region being provided on a side of the second well region facing the second main surface, the side of the second contact region facing the second main surface constituting a portion of the second main surface, a second contact hole being provided on the insulating layer at a position corresponding to the second contact region, and the emitter metal being in contact with the second contact region through the second contact hole; a third contact region of the second conductivity type, the third contact region being provided on a side of the second well region facing the second main surface, the side of the third contact region facing the second main surface constituting a portion of the second main surface, a third contact hole being provided on the insulating layer at a position corresponding to the third contact region, and the emitter metal being in contact with the third contact region through the third contact hole; a first emitter region of a first conductivity type, the first emitter region being disposed on a side of the second well region facing the second main surface and between the first active gate and the second contact region, the side of the first emitter region facing the second main surface constituting a portion of the second main surface; A second emitter region of the first conductivity type is provided on a side of the third well region facing the second main surface and is located between the second active gate and the third contact region, and a side of the second emitter region facing the second main surface constitutes part of the second main surface.

7. The IGBT structure according to claim 1 or 2, characterized in that: The IGBT structure further includes a field stop region of a first conductivity type, wherein the field stop region is disposed between the collector region and the drift region.

8. The IGBT structure according to claim 1 or 2, characterized in that: The first conductivity type is N type; The second conductivity type is P type.

9. The IGBT structure according to claim 1 or 2, characterized in that: The first dummy gate includes a first gate trench extending from the second main surface to the first main surface to the drift region, a first gate dielectric layer located on an inner surface of the first gate trench, and a first polysilicon gate located on a side of the first gate dielectric layer away from the inner surface of the first gate trench, wherein the first polysilicon gate is a floating gate; The second dummy gate includes a second gate trench extending from the second main surface to the first main surface to the drift region, a second gate dielectric layer located on an inner surface of the second gate trench, and a second polysilicon gate located on a side of the second gate dielectric layer away from the inner surface of the second gate trench, wherein the second polysilicon gate is a floating gate; The side of the first floating region away from the second floating region contacts the side of the first gate dielectric layer away from the first polysilicon gate, and the side of the second floating region away from the second floating region contacts the side of the second gate dielectric layer away from the second polysilicon gate.

10. A semiconductor device, characterized in that: The invention comprises the IGBT structure according to any one of claims 1 to 9.

Images