Image sensing device

Abstract

The image sensing device includes a semiconductor substrate, a first pixel region, and a second gate. The semiconductor substrate includes: a first pixel region including at least one first photoelectric conversion region that converts incident light into photocharges and at least one first floating diffusion region that stores the photocharges generated by the at least one first photoelectric conversion region; a second pixel region adjacent to the first pixel region in the first direction, the second pixel region including at least one second photoelectric conversion region converting incident light into photocharges and at least one second floating diffusion region storing the photocharges generated by the at least one second photoelectric conversion region; and a first inter-pixel isolation structure between the first pixel region and the second pixel region. A first gate on the semiconductor substrate extends to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region. A second gate on a side of the first gate on the semiconductor substrate extends to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region.

Description

Technical Field

[0001] The techniques and implementations disclosed in this patent document generally relate to an image sensing device. Background Art

[0002] Image sensors are used in electronic devices to convert optical images into electrical signals. With the development of the automotive, medical, computer and communication industries, the demand for highly integrated, higher performance image sensors in various electronic devices such as digital cameras, camcorders, personal communication systems (PCS), video game consoles, surveillance cameras, medical micro cameras, robots, etc. is rapidly increasing.

[0003] CCD image sensing devices can be driven more easily than CCD sensing devices. CMOS image sensing devices enable conventional circuits to be integrated into a single chip, so that CMOS image sensing devices can be easily manufactured into small products, and have a higher degree of integration and very low power consumption. In addition, CMOS image sensing devices are compatible with CMOS manufacturing technology, resulting in reduced production costs. In recent years, CMOS image sensing devices have been intensively studied and rapidly used widely. Summary of the invention

[0004] Various embodiments of the disclosed technology relate to an image sensing device capable of improving operating characteristics of a pixel transistor.

[0005] According to an embodiment of the disclosed technology, an image sensing device may include a semiconductor substrate, a first pixel region, and a second gate. The semiconductor substrate may include: a first pixel region, which is configured to include at least one first photoelectric conversion region that converts incident light into photocharges and at least one first floating diffusion region configured to store photocharges generated by at least one first photoelectric conversion region; a second pixel region, which is adjacent to the first pixel region in a first direction and is configured to include at least one second photoelectric conversion region that converts incident light into photocharges and at least one second floating diffusion region that stores photocharges generated by at least one second photoelectric conversion region; and a first inter-pixel isolation structure, which is disposed between the first pixel region and the second pixel region. The first gate may be disposed on the semiconductor substrate and may extend to overlap with the first pixel region, the first inter-pixel isolation structure, and the second pixel region. The second gate may be disposed on one side of the first gate on the semiconductor substrate and may extend to overlap with the first pixel region, the first inter-pixel isolation structure, and the second pixel region.

[0006] According to another embodiment of the disclosed technology, an image sensing device may include: a unit pixel group including a plurality of unit pixels arranged adjacent to each other in a first direction and a second direction perpendicular to the first direction, each unit pixel including at least one photoelectric conversion region generating photocharges by conversion of incident light and at least one floating diffusion region storing photocharges generated by at least one photoelectric conversion region. The unit pixel group may include a central portion, a left portion located on one side of the central portion, and a right portion located on the other side of the central portion opposite to the one side. Each of the left portion and the right portion may include a plurality of first gates extending in the first direction to intersect with a plurality of unit pixels adjacent to each other in the first direction, and the central portion may include a plurality of second gates having an island shape and isolated from each other.

[0007] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features and advantageous aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0010] Figure 2 Some implementations based on the disclosed technology are shown in Figure 1 A schematic diagram of an example of the structure of a unit pixel group is shown.

[0011] Figure 3A is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel group taken along line X1 - X1 ′ is shown.

[0012] Figure 3B is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel group taken along line X2 - X2 ′ is shown.

[0013] Figure 3C is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel group taken along line YY' is shown.

[0014] Figure 4 Some implementations based on the disclosed technology are shown in Figure 1 FIG. 1 is a schematic diagram of another example of the structure of a unit pixel group shown in FIG.

[0015] Figure 5 Some implementations based on the disclosed technology are shown in Figure 1 FIG. 1 is a schematic diagram of another example of the structure of a unit pixel group shown in FIG. DETAILED DESCRIPTION

[0016] This patent document provides implementations and examples of image sensing devices that can be used to substantially solve one or more technical or engineering problems and alleviate some limitations or disadvantages encountered in other image sensing devices. Some implementations of the disclosed technology provide examples of image sensing devices that can improve the operating characteristics of pixel transistors. The disclosed technology provides various implementations of image sensing devices that can improve not only their operating characteristics, but also their random telegraph signal (RTS) characteristics.

[0017] Reference will now be made in detail to specific embodiments, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the accompanying drawings to represent the same or similar parts. In the following description, detailed descriptions of related known configurations or functions contained herein will be omitted to avoid obscuring the subject matter.

[0018] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to a specific embodiment, but includes various modifications, equivalents and / or substitutions of the embodiments. The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0019] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0020] Reference Figure 1 , the image sensing device may include a pixel array 100 , a row driver 200 , a correlated double sampler (CDS) 300 , an analog-to-digital converter (ADC) 400 , an output buffer 500 , a column driver 600 , and a timing controller 700 . Figure 1 The components of the image sensing device shown are discussed as examples only, and this patent document encompasses numerous other changes, substitutions, variations, alterations, and modifications. In this patent document, the word "pixel" may be used to indicate an image sensing pixel configured to detect incident light to generate an electrical signal carrying an image in the incident light and a phase detection pixel configured to generate a second electrical signal for calculating a phase difference between images.

[0021] The pixel array 100 may include a plurality of unit pixel groups (PXG) arranged in rows and columns. In one example, a plurality of unit pixels (PX) may be arranged in a two-dimensional (2D) pixel array including rows and columns. Each unit pixel group (PXG) may include a plurality of unit pixels, each unit pixel generating an electrical signal (pixel signal) for photoelectrically converting incident light to generate an image signal corresponding to a target object to be captured. For example, each unit pixel group (PXG) may include four unit pixels arranged adjacent to each other in a (2×2) matrix structure. Each unit pixel may include a photoelectric conversion region configured to generate photocharges by photoelectric conversion of incident light and a pixel transistor configured to generate a pixel signal corresponding to the photocharges generated by the photoelectric conversion region. Each unit pixel may include a plurality of photoelectric conversion regions separated from each other.

[0022] The pixel array 100 may receive a driving signal (eg, a row selection signal, a reset signal, a transmission (or transfer) signal, etc.) from the row driver 200. Upon receiving the driving signal, the unit pixel may be enabled to perform operations corresponding to the row selection signal, the reset signal, and the transfer signal.

[0023] The row driver 200 may enable the pixel array 100 to perform a specific operation on the unit pixel in the corresponding row based on a control signal provided by a controller circuit such as the timing controller 700. In some implementations, the row driver 200 may select one or more pixel groups arranged in one or more rows of the pixel array 100. The row driver 200 may generate a row selection signal to select one or more rows from a plurality of rows. The row driver 200 may sequentially enable a reset signal and a transfer signal for the unit pixel arranged in the selected row. The pixel signal generated by the unit pixel arranged in the selected row may be output to a correlated double sampler (CDS) 300.

[0024] The correlated double sampler (CDS) 300 may use correlated double sampling to remove an undesired offset value of a unit pixel. In one example, the correlated double sampler (CDS) 300 may remove an undesired offset value of a unit pixel by comparing the output voltage of a pixel signal (of a unit pixel) obtained before and after the photocharge generated by the incident light is accumulated in a sensing node (i.e., a floating diffusion (FD) node). As a result, the CDS 300 may obtain a pixel signal generated only by the incident light without causing noise. In some implementations, upon receiving a clock signal from the timing controller 700, the CDS 300 may sequentially sample and maintain the voltage levels of a reference signal and a pixel signal provided to each of a plurality of column lines from the pixel array 10. That is, the CDS 300 may sample and maintain the voltage levels of a reference signal and a pixel signal corresponding to each column of the pixel array 100. In some implementations, the CDS 300 may transmit the reference signal and the pixel signal of each column as a correlated double sampling (CDS) signal to the ADC 400 based on a control signal from the timing controller 700.

[0025] The ADC 400 is used to convert the analog CDS signal received from the CDS 300 into a digital signal. In some implementations, the ADC 400 may be implemented as a ramp comparison type ADC. The analog-to-digital converter (ADC) 400 may compare the ramp signal received from the timing controller 700 with the CDS signal received from the CDS 300, and thus may output a comparison signal indicating a comparison result between the ramp signal and the CDS signal. The analog-to-digital converter (ADC) 400 may count the level transition time of the comparison signal in response to the ramp signal received from the timing controller 700, and may output a count value indicating the counted level transition time to the output buffer 500.

[0026] The output buffer 500 may temporarily store the column-based image data provided from the ADC 400 based on the control signal of the timing controller 700. The image data received from the ADC 400 may be temporarily stored in the output buffer 500 based on the control signal of the timing controller 700. The output buffer 500 may provide an interface to compensate for a data rate difference or a transmission rate difference between the image sensing device and other devices.

[0027] The column driver 600 may select a column of the output buffer 500 upon receiving a control signal from the timing controller 700, and sequentially output image data temporarily stored in the selected column of the output buffer 500. In some implementations, upon receiving an address signal from the timing controller 700, the column driver 600 may generate a column selection signal based on the address signal, may select a column of the output buffer 500 using the column selection signal, and may control the image data received from the selected column of the output buffer 500 to be output as an output signal.

[0028] The timing controller 700 may generate signals for controlling the operations of the row driver 200, the ADC 400, the output buffer 500, and the column driver 600. The timing controller 700 may provide clock signals required for the operations of the various components of the image sensing device, control signals for timing control, and address signals for selecting rows or columns to the row driver 200, the column driver 600, the ADC 400, and the output buffer 500. In some implementations, the timing controller 700 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0029] Figure 2 Some implementations based on the disclosed technology are shown in Figure 1 A schematic diagram of an example of the structure of a unit pixel group (PXG) is shown.

[0030] Reference Figure 2 , each unit pixel group (PXG) may include a plurality of unit pixels (PX1 to PX4). The unit pixels (PX1 to PX4) may be arranged adjacent to each other in a first direction (e.g., Y-axis direction) and a second direction perpendicular to the first direction (e.g., X-axis direction). For example, each unit pixel group (PXG) may include four unit pixels (PX1 to PX4) arranged in a (2×2) matrix structure. The unit pixels (PX1 to PX4) may be formed to have a backside illumination (BSI) structure, which receives incident light through a surface (e.g., rear surface) facing or opposite to a surface (e.g., front surface) on which a driving element (e.g., pixel transistor) is formed in a semiconductor substrate.

[0031] Each unit pixel (PX1-PX4) can be physically isolated from an adjacent unit pixel by an inter-pixel isolation structure ISO1. In addition, each unit pixel (PX1-PX4) can be divided into two sub-unit pixels (PXa, PXb) by an intra-pixel isolation structure ISO2. However, the isolation structures (ISO1, ISO2) are not limited to Figure 2 The example structure shown, other implementations are also possible. In some implementations, it should be noted that some parts of the isolation structure can also be omitted as needed.

[0032] The intra-pixel isolation structure ISO2 may be formed to extend in the second direction between the sub-unit pixels (PXa, PXb). At this time, both ends of the intra-pixel isolation structure ISO2 may not contact the inter-pixel isolation structure ISO1, only one end of the intra-pixel isolation structure ISO2 may contact the inter-pixel isolation structure ISO1, and the other end of the intra-pixel isolation structure ISO2 may be spaced apart from the inter-pixel isolation structure IOS1. A device isolation region 114 containing high-concentration P-type impurities may be formed in a region that contacts the other end of the intra-pixel isolation structure ISO2 and extends in a direction away from the other end of the intra-pixel isolation structure ISO2. Therefore, the device isolation region 114 is spaced apart from the inter-pixel isolation structure IOS1.

[0033] Each of the inter-pixel isolation structure ISO1 and the intra-pixel isolation structure ISO2 may include a trench-shaped isolation structure in which an insulating material is buried in a trench etched in a substrate. In some implementations, the trench-shaped isolation structure may include a deep trench isolation (DTI) structure or a structure formed by a combination of a DTI structure and a shallow trench isolation (STI) structure. For example, each inter-pixel isolation structure ISO1 and each intra-pixel isolation structure ISO2 may include a front deep trench isolation (FDTI) structure. Each inter-pixel isolation structure ISO1 and each intra-pixel isolation structure ISO2 may include the same insulating material.

[0034] Electrical connection between elements belonging to different unit pixels may be achieved through conductive lines (eg, metal lines) formed over a substrate.

[0035] In the unit pixel group (PXG), the unit pixels (PX1-PX4) may be identical in structure to each other. For example, the unit pixels disposed adjacent to each other in the first direction or the second direction may be formed symmetrically with respect to the inter-pixel isolation structure ISO1 between the corresponding unit pixels.

[0036] Each unit pixel (PX1-PX4) may include a 2-photodiode (2PD) structure, and the 2PD structure includes two photoelectric conversion regions (112a, 112b). Each unit pixel (PX1-PX4) may include two sub-unit pixels (PXa, PXb), and each sub-unit pixel (PXa, PXb) may include a photoelectric conversion region, a floating diffusion region, and a transfer gate.

[0037] For example, the sub-unit pixel (PXa) may include a photoelectric conversion region 112a, a floating diffusion region FD1, and a transfer gate TG1, and the sub-unit pixel (PXb) may include a photoelectric conversion region 112b, a floating diffusion region FD2, and a transfer gate TG2. The transfer gate TG1 may transfer the photocharges generated by the photoelectric conversion region 112a to the floating diffusion region FD1 based on the transfer signal. The transfer gate TG2 may transfer the photocharges generated by the photoelectric conversion region 112b to the floating diffusion region FD2 based on the transfer signal.

[0038] In addition, each unit pixel (PX1~PX4) may include a reset transistor, a source follower transistor and a selection transistor. The reset transistor may include a reset gate (RG1, RG2). The reset gate (RG1, RG2) may be set between the power supply voltage (VDD) and the floating diffusion area (FD1, FD2), and the floating diffusion area (FD1, FD2) may be reset to the power supply voltage (VDD) based on the reset signal. The source follower transistor may include a drive gate (DG1, DG2) connected to the floating diffusion area (FD1, FD2). The source follower transistor may generate a pixel signal corresponding to the magnitude of the voltage generated by the floating diffusion area (FD1, FD2), and the pixel signal may be output to the selection transistor. The selection transistor may be connected in series to the source follower transistor and may include a selection gate (SG1, SG2). Each selection gate (SG1, SG2) may output a pixel signal to the output terminal (VOUT) based on the row selection signal.

[0039] In each unit pixel group (PXG), each selection gate (SG1, SG2), each drive gate (DG1, DG2), and each reset gate (RG1, RG2) may be formed per unit pixel without being isolated from each other. In some implementations, gates having the same characteristics in adjacent unit pixels may be integrally connected to each other to form a single strip that crosses the corresponding unit pixel. In some implementations, gates having the same characteristics in adjacent unit pixels may be integrally formed to have a single strip that completely crosses the corresponding unit pixel.

[0040] For example, the unit pixel group (PXG) may include a central portion (CP), a left portion (LP) located on one side (e.g., left side) of the central portion (CP), and a right portion (RP) located on a side (e.g., right side) opposite to the central portion (CP).

[0041] Some gates (SG1, DG1, RG1) of the gates (SG1, SG2, DG1, DG2, RG1, RG2) of the pixel transistors may be arranged in parallel with each other on the left side (LP) of the unit pixel group (PXG), and may extend longer to continuously cross the unit pixels (PX1, PX3) adjacent to each other in the first direction. For example, Figure 2 As shown, those gates (SG1, DG1, RG1) may overlap the unit pixels (PX1 and PX3) adjacent to each other in the first direction. Each gate (SG1, DG1, RG1) may be formed in a strip shape overlapping the four photoelectric conversion regions (112a, 112b) of the unit pixels (PX1, PX3), the intra-pixel isolation structure (ISO2) disposed between the photoelectric conversion regions (112a, 112b), and the inter-pixel isolation structure (ISO1) disposed between the unit pixels (PX1, PX3).

[0042] In some implementations, the remaining gates (SG2, DG2, RG2) among the gates (SG1, SG2, DG1, DG2, RG1, RG2) of the pixel transistors may be arranged in parallel to each other on the right side (RP) of the unit pixel group (PXG), and may extend longer to sequentially cross the unit pixels (PX2, PX4) adjacent to each other in the first direction. For example, those gates (SG2, DG2, RG2) may overlap the unit pixels (PX2 and PX4) adjacent to each other in the first direction. Each gate (SG2, DG2, RG2) may be formed into a strip shape overlapping the four photoelectric conversion regions (112a, 112b) of the unit pixel (PX2, PX4), the intra-pixel isolation structure (ISO2) disposed between the photoelectric conversion regions (112a, 112b), and the inter-pixel isolation structure (ISO1) disposed between the unit pixels (PX2, PX4).

[0043] The gate electrodes (SG1, DG1, RG1) of the left side portion (LP) and the gate electrodes (SG2, DG2, RG2) of the right side portion (RP) may be arranged symmetrically with respect to the central portion (CP). The gate electrodes (SG1, SG2, DG1, DG2, RG1, RG2) may be formed to have the same width or may be formed to have different widths.

[0044] Among the gates (SG1, DG1, RG1) of the left portion (LP) and the gates (SG2, DG2, RG2) of the right portion (RP), some gates having the same characteristics may be electrically connected to each other through conductive lines (eg, metal lines).

[0045] The gates (e.g., transfer gates) TG1 and TG2 of the transfer transistors may be located at a central portion (CP) of the unit pixel group (PXG). When viewed in a plane, each transfer gate (TG1, TG2) may be formed in an island shape isolated for each sub-unit pixel (PXa, PXb), and the transfer gates (TG1, TG2) may be arranged in two columns in a first direction.

[0046] As described above, each gate (SG1, DG1, RG1) of the pixel transistor may be formed in a strip shape at the left side portion (LP) of the unit pixel group (PXG), and each gate (SG2, DG2, SG2) of the pixel transistor may be formed in a strip shape at the right side portion (RP) of the unit pixel group (PXG). Specifically, the gates (SG1, DG1, RG1) in the left side portion (LP) of the unit pixel group (PXG) may be arranged symmetrically with the gates (SG2, DG2, SG2) in the right side portion (RP) of the unit pixel group (PXG). As a result, the size of the corresponding pixel transistor within the unit pixel group (PXG) may be maximized. In particular, as the size of the source follower transistor increases, the random telegraph signal (RTS) characteristic of the image sensing device may be improved. In this way, the image sensing device according to the present embodiment may minimize the size of the pixel transistor, so that the operating characteristics (in particular, the RTS characteristics) of the image sensing device may be improved.

[0047] In the sub-unit pixels (PXa, PXb), the floating diffusion region (FD1, FD2) may be formed in a region between the reset gates (RG1, RG2) and the transfer gates (TG1, TG2). For example, in pixels PX1 and PX3, the floating diffusion region (FD1) may be formed between the reset gate (RG1) and the transfer gate (TG1), and the floating diffusion region (FD2) may be formed between the reset gate (RG1) and the transfer gate (TG2). For example, in pixels PX2 and PX4, the floating diffusion region (FD1) may be formed between the reset gate (RG2) and the transfer gate (TG1), and the floating diffusion region (FD2) may be formed between the reset gate (RG2) and the transfer gate (TG2).

[0048] An area (e.g., a source / drain area) between each reset gate (RG1, RG2) and each drive gate (DG1, DG2) can be connected to a power supply voltage (VDD), and an area (e.g., a source / drain area) of each select gate (SG1, SG2) can be connected to an output terminal (VOUT) for outputting a pixel signal.

[0049] In each unit pixel (PX1-PX4), a device isolation region 114 may be formed between transfer gates (TG1, TG2). The device isolation region 114 may include a junction isolation structure in which P-type impurities are implanted in an upper region of a substrate. Alternatively, the device isolation region 114 may include a shallow trench isolation (STI) structure formed to have a depth smaller than that of the intra-pixel isolation structure ISO2.

[0050] Although for the sake of convenience, Figure 2An example case is shown in which sub-unit pixels (PXa, PXb) are arranged symmetrically with each other in the first direction within a unit pixel (PX), but other implementations are also possible. It should be noted that the sub-unit pixels (PXa, PXb) may also be arranged symmetrically with each other in the second direction while being spaced apart from each other.

[0051] Figure 3A is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel group taken along line X1 - X1 ′ is shown. Figure 3B is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel group taken along line X2 - X2 ′ is shown. Figure 3C is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel group taken along line YY' is shown.

[0052] Reference FIG. 3A to FIG. 3C The substrate 110 may include a first surface (eg, a rear surface) and a second surface (eg, a front surface) facing or opposite to the first surface. The substrate 110 may include a single crystal silicon substrate or an epitaxially grown single crystal silicon substrate.

[0053] In the substrate 110, pixel regions respectively corresponding to the unit pixels (PX1, PX3) may be physically isolated from each other by an inter-pixel isolation structure ISO1. The inter-pixel isolation structure ISO1 may include a deep trench isolation (DTI) structure, and may be formed to penetrate the substrate 110. The inter-pixel isolation structure ISO1 may include a front deep trench isolation (FDTI) structure in which an insulating material (e.g., silicon oxide or silicon nitride) is buried in a trench etched from the front surface toward the rear surface of the substrate 110.

[0054] In each pixel region, the photoelectric conversion regions (112a, 112b) of the sub-unit pixels (PXa, PXb) may be physically isolated from each other by an intra-pixel isolation structure (ISO2). Each intra-pixel isolation structure (ISO2) may include a DTI or STI structure formed to have a smaller depth than the inter-pixel isolation structure (ISO1). Each intra-pixel isolation structure (ISO2) may be formed to a predetermined depth so that the intra-pixel isolation structure (ISO2) does not penetrate the substrate 110.

[0055] In each pixel region, the device isolation region 114 may be formed in a region where the intra-pixel isolation structure (ISO2) is not formed and in a boundary region between sub-unit pixels (PXa, PXb) (e.g., a region between the inter-pixel isolation structure ISO1 and the intra-pixel isolation structure ISO2). In addition, the device isolation region 114 may be formed between the transfer gate (TG1) and the inter-pixel isolation structure (ISO1). The device isolation region 114 may include a junction isolation structure that injects impurities into an upper region of the substrate 110. For example, the device isolation region 114 may include an impurity region that contacts the top surface of the substrate 110 and injects P-type impurities from the top surface of the substrate 110 to a predetermined depth. The device isolation region 114 may include a P-type impurity with a higher concentration than the well region.

[0056] The photoelectric conversion region 112a may be formed in the lower region of the substrate 110 within the sub-unit pixel (PXa) region, and the photoelectric conversion region 112b may be formed in the lower region of the substrate 110 within the sub-unit pixel (PXb) region. In order to increase light reception (Rx) efficiency, the photoelectric conversion regions (112a, 112b) may be arranged within the corresponding sub-unit pixels (PXa, PXb) to occupy as large an area as possible in the lower region of the substrate 110. The photoelectric conversion regions (112a, 112b) may include N-type impurities. A well region including P-type impurities may be formed above the photoelectric conversion regions (112a, 112b) within the substrate of the sub-unit pixel (PXa, PXb).

[0057] The gates (TG1, SG1, DG1, RG1) of the pixel transistors may be formed over the second surface of the substrate 110. That is, each unit pixel (PX1, PX3) may include a backside illumination (BSI) structure in which the driving elements (TG1, SG1, DG1, RG1) are formed on a side (e.g., a second surface) opposite to a side (e.g., a first surface) on which light is incident from the outside.

[0058] The gates (TG1, SG1, DG1, RG1) of the pixel transistors may include a conductive material 116 and a gate insulating layer 118 disposed between the conductive material 116 and the substrate 110. The conductive material 116 may include, for example, metal or doped polysilicon. The gate insulating layer 118 may include an oxide layer formed by oxidation of the surface of the substrate 110.

[0059] The transfer gate (TG1) may transfer the photocharges generated by the photoelectric conversion region 112a to the floating diffusion region (FD1) based on the transfer signal. The transfer gate (TG1) may include a recessed gate formed in a groove etched in the substrate 110 to form a vertical channel in the well region and a planar gate formed on the second surface of the substrate 110 to form a horizontal channel in the well region.

[0060] In the upper region of the substrate 110, the floating diffusion region FD1 may be formed between the reset gate RG1 and the transfer gate TG1. The floating diffusion region FD1 may include N-type impurities. The reset gate RG1 may connect the floating diffusion region FD1 to a power supply voltage (VDD) based on a reset signal, and may reset the floating diffusion region FD1 to the power supply voltage (VDD).

[0061] Each source / drain region (S / D) between the reset gate (RG1) and the drive gate (DG1) may be connected to a power supply voltage (VDD), and one source / drain region (S / D) located on one side of the selection gate (SG1) may be connected to an output terminal (VOUT) for outputting a pixel signal. The source / drain region (S / D) may include N-type impurities.

[0062] Although for the sake of convenience, Figure 3A Only the cross-sectional structure of the sub-unit pixel (PXa) is shown in FIG. 1 , but the sub-unit pixel (PXb) may also be formed to have the same structure as the sub-unit pixel (PXa).

[0063] Figure 4 Some implementations based on the disclosed technology are shown in Figure 1 FIG. 2 is a schematic diagram of another example of the structure of a unit pixel group (PXG) shown in FIG.

[0064] Reference Figure 4 , in the left side portion (LP) and the right side portion (RP) of the unit pixel group (PXG), each driving gate (DG3, DG4) may be formed to have a greater width than each selection gate (SG3, SG4) or each reset gate (RG3, RG4). Figure 2 compared to, Figure 4 The respective driving gates (DG3, DG4) shown can be formed to have a ratio Figure 2 As the width of each driving gate (DG3, DG4) increases, Figure 4 Each selection gate (SG3, SG4) can be formed to have a ratio Figure 2 The width of each selection gate (SG1, SG3) is smaller, and Figure 4 Each reset gate (RG3, RG4) can be formed to have a ratio Figure 2 The width of each reset gate (RG1, RG1) is smaller.

[0065] As described above, as the size of the source follower transistor becomes larger, the random telegraph signal (RTS) characteristic may be improved, so that each driving gate ( DG3 , DG4 ) may be formed to have a larger width, resulting in an improvement in the RTS characteristic.

[0066] and Figure 2 Compared with the implementation method, although Figure 4 The gates shown (SG3, SG4, DG3, DG4, RG3, RG4) are different in width from Figure 2 Gate (SG1, SG2, DG1, DG2, RG1, RG2), but except Figure 4 The gate and Figure 2 Except for the difference in gate width, the remaining components are Figure 2 The components are the same, so for the sake of brevity, their redundant descriptions will be omitted in this article.

[0067] Figure 5 Some implementations based on the disclosed technology are shown in Figure 1 FIG. 2 is a schematic diagram of another example of the structure of a unit pixel group (PXG) shown in FIG.

[0068] Reference Figure 5 , each unit pixel of the unit pixel group (PXG) may include a single photoelectric conversion region 112, a single floating diffusion region FD, and a single transfer gate TG.

[0069] although Figure 2 and Figure 4 The above embodiment discloses an example of a 2PD structure in which each unit pixel (PX1 to PX4) of a unit pixel group (PXG) includes two photoelectric conversion regions (112a, 112b), but other implementations are also possible. However, the structure of the above gates (SG1 to SG4, DG1 to DG4, and RG1 to RG4) can also be applied to a structure including Figure 5 Shown are unit pixel groups (PXG) of unit pixels (PX1 to PX4) each including one photoelectric conversion region 112 and one transfer gate (TG).

[0070] As is apparent from the above description, an image sensing device based on some implementations of the disclosed technology can improve its operating characteristics. In particular, the image sensing device can improve its random telegraph signal (RTS) characteristics.

[0071] The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the above-mentioned patent documents.

[0072] Although a number of exemplary embodiments have been described, it should be understood that various modifications or enhancements of the disclosed embodiments and other embodiments are contemplated based on what is described and / or illustrated in this patent document.

[0073] CROSS-REFERENCE TO RELATED APPLICATIONS

[0074] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0117994, filed on September 5, 2023, which is hereby incorporated by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: A semiconductor substrate, comprising: a first pixel region including at least one first photoelectric conversion region that converts incident light into photocharges and at least one first floating diffusion region that stores photocharges generated by the at least one first photoelectric conversion region, a second pixel region, the second pixel region being disposed adjacent to the first pixel region in a first direction and comprising at least one second photoelectric conversion region and at least one second floating diffusion region, the at least one second photoelectric conversion region converting incident light into photocharges, the at least one second floating diffusion region storing photocharges generated by the at least one second photoelectric conversion region, and a first inter-pixel isolation structure, the first inter-pixel isolation structure being arranged between the first pixel region and the second pixel region; a first gate disposed over the semiconductor substrate and extending to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region; and A second gate is disposed on the semiconductor substrate at one side of the first gate and extends to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region.

2. The image sensing device according to claim 1, wherein: Each of the first gate and the second gate has a bar shape, and the first gate and the second gate are arranged parallel to each other.

3. The image sensing device according to claim 2, wherein: The first gate and the second gate have the same width.

4. The image sensing device according to claim 2, wherein: The first gate and the second gate have different widths from each other.

5. The image sensing device according to claim 1, wherein: The first gate comprises: A driving gate is connected to the at least one first floating diffusion region and the at least one second floating diffusion region.

6. The image sensing device according to claim 1, wherein: The second gate comprises: A reset gate is provided at one side of each of the first floating diffusion region and the second floating diffusion region and resets the first floating diffusion region and the second floating diffusion region based on a reset signal.

7. The image sensing device according to claim 1, further comprising: The third gate is disposed at an opposite side of the first gate and extends across the first pixel region, the first pixel isolation structure and the second pixel region.

8. The image sensing device according to claim 7, wherein: Each of the first gate, the second gate, and the third gate has a bar shape, and the first gate, the second gate, and the third gate are arranged parallel to each other.

9. The image sensing device according to claim 8, wherein: The first gate, the second gate, and the third gate have the same width.

10. The image sensing device according to claim 8, wherein: The first gate, the second gate, and the third gate have different widths from each other.

11. The image sensing device according to claim 1, wherein: Each of the first photoelectric conversion region and the second photoelectric conversion region includes: a first sub-photoelectric conversion region; and The second sub-photoelectric conversion region is arranged at one side of the first sub-photoelectric conversion region in the direction in which the first gate and the second gate extend, and is isolated from the first sub-photoelectric conversion region by an intra-pixel isolation structure.

12. The image sensing device according to claim 1, wherein: The semiconductor substrate further comprises: a third pixel region, the third pixel region being disposed adjacent to the first pixel region in a second direction perpendicular to the first direction and comprising at least one third photoelectric conversion region and at least one third floating diffusion region, the at least one third photoelectric conversion region converting incident light into photocharges, the at least one third floating diffusion region storing the photocharges generated by the at least one third photoelectric conversion region; a fourth pixel region, the fourth pixel region being disposed adjacent to the third pixel region in the first direction and comprising at least one fourth photoelectric conversion region that converts incident light into photocharges and at least one fourth floating diffusion region that stores the photocharges generated by the at least one fourth photoelectric conversion region; and A second inter-pixel isolation structure is disposed between the third pixel region and the fourth pixel region.

13. The image sensing device according to claim 12, further comprising: a third gate, which is disposed on the semiconductor substrate and extends in a strip shape to cross the third pixel region, the second inter-pixel isolation structure, and the fourth pixel region; as well as A fourth gate is disposed on the semiconductor substrate at one side of the third gate and extends in a strip shape to cross the third pixel region, the second inter-pixel isolation structure and the fourth pixel region.

14. The image sensing device according to claim 13, further comprising: at least one first transfer gate disposed between the second gate and the fourth gate in the first pixel region and transferring photocharges generated by the at least one first photoelectric conversion region to the at least one first floating diffusion region based on a transfer signal; at least one second transfer gate disposed between the second gate and the fourth gate in the second pixel region and transferring photocharges generated by the at least one second photoelectric conversion region to the at least one second floating diffusion region based on a transfer signal; at least one third transfer gate, the at least one third transfer gate being disposed between the second gate and the fourth gate in the third pixel region and transferring photocharges generated by the at least one third photoelectric conversion region to the at least one third floating diffusion region based on a transfer signal; as well as at least one fourth transfer gate which is disposed between the second gate and the fourth gate in the fourth pixel region and transfers photocharges generated by the at least one fourth photoelectric conversion region to the at least one fourth floating diffusion region based on a transfer signal.

15. An image sensing device, comprising: A unit pixel group, the unit pixel group includes a plurality of unit pixels arranged adjacent to each other in a first direction and in a second direction perpendicular to the first direction, each unit pixel includes at least one photoelectric conversion region and at least one floating diffusion region, the at least one photoelectric conversion region generates photocharges by conversion of incident light, and the at least one floating diffusion region stores the photocharges generated by the at least one photoelectric conversion region, The unit pixel group includes a central portion, a left portion located on one side of the central portion, and a right portion located on another side of the central portion opposite to the one side. wherein each of the left portion and the right portion includes a plurality of first gates extending in a first direction to cross a plurality of unit pixels adjacent to each other in the first direction, and The central portion includes a plurality of second gate electrodes having an island shape and isolated from each other.

16. The image sensing device according to claim 15, wherein: Each of the first gates has a bar shape, and the first gates are arranged parallel to each other.

17. The image sensing device according to claim 15, wherein: The first gate comprises: a driving gate connected to the at least one floating diffusion region; a reset gate disposed at one side of the driving gate and resetting the floating diffusion region based on a reset signal; and A selection gate is provided on the other side of the driving gate opposite to the one side and outputs a pixel signal to an output terminal based on a row selection signal.

18. The image sensing device according to claim 17, wherein: The driving gate, the reset gate, and the selection gate extend to have the same width.

19. The image sensing device according to claim 17, wherein: The driving gate, the reset gate, and the selection gate have different widths from each other.

20. The image sensing device according to claim 15, wherein: The second gate comprises: A plurality of transfer gates transfer photocharges generated by the at least one photoelectric conversion region to the at least one floating diffusion region based on a transfer signal.

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