Josephson radio frequency envelope-direct current converter

Abstract

A method of converting an envelope of a radio frequency signal into a baseband control pulse using a Josephson junction includes injecting a bias current into an envelope detector circuit. A bias current is identified based on first and second critical currents of a superconducting device in an envelope detector circuit. The first critical current corresponds to the envelope detector circuit not receiving the RF signal. The second critical current corresponds to an envelope detector circuit that receives a maximum RF signal. The method further includes receiving, at an envelope detector circuit, a modulated radio frequency (RF) signal to detect an envelope of the received RF signal. The output of the envelope detector circuit is used to drive an output load. The output is generated based on the envelope detected by the envelope detector circuit.

Description

Background Art Technical Field

[0001] The present disclosure relates generally to quantum computing systems.

[0002] Description of Related Technology

[0003] For flux applications in superconducting quantum interference devices (SQUIDs), the generation of spectrally broad baseband signals (DC–1 GHz) is prominent. The inclusion of SQUIDs into quantum computing (QC) architectures typically involves radio frequency (RF) digital-to-analog converters (DACs) and baseband DACs to generate qubit control pulses and SQUID flux pulses. Currently, these signals are generated by DACs at room temperature and sent via high-bandwidth cables to a dilution refrigerator (DR), where they experience dispersion and distortion due to the finite skin depth and slight impedance mismatch of the signal carriers. This presents significant challenges when combined with the technical overhead in dual DAC types, designs, and bandwidth, especially if the electronics are to be incorporated inside the DR. Summary of the invention

[0004] Some embodiments provide a method for converting an envelope of a radio frequency signal into a baseband control pulse using a Josephson junction. The system injects a bias current into an envelope detector circuit. The bias current is identified based on first and second critical currents of a superconducting device in the envelope detector circuit. The first critical current corresponds to the envelope detector circuit not receiving an RF signal. The second critical current corresponds to the envelope detector circuit receiving a maximum RF signal. The system receives an amplitude modulated RF signal at an input of the envelope detector circuit. The output of the envelope detector circuit is a voltage waveform that is a reconstruction of the detected amplitude envelope of the RF signal. The output of the envelope detector circuit is configured to drive an appropriate load. In some embodiments, the envelope detector circuit includes a plurality of Josephson junction (JJ) devices, the plurality of Josephson junction (JJ) devices being arranged in one or more parallel JJ device stacks for providing an output current and an output voltage to an output load. The parallel JJ device stacks are interconnected at a center node with a bias current source. When the envelope detector circuit does not receive an RF signal, the JJ device is in a supercurrent state with zero static power dissipation. When the envelope detector circuit receives an RF signal, the JJ device is in a voltage state.

[0005] In some embodiments, the output load comprises a quantum processing unit (QPU) housed in a cryostat, and the envelope detector circuit is physically in the cryostat. The output of the envelope detector circuit can be used as a current pulse that is mutually coupled to a superconducting quantum interference device (SQUID). In some embodiments, the system applies a low pass filter to the output of the envelope detector circuit.

[0006] Having near-zero static dissipation allows the envelope detector to be physically close to the computational payload (e.g., inside a cryostat housing the qubits). The proximity of the envelope detector to the payload significantly reduces (e.g., minimizes) the dispersion and distortion of the detected baseband signal. Using a JJ envelope detector circuit also eliminates the need for separate digital-to-analog converters (DACs) for the RF signal and for the baseband signal.

[0007] The foregoing summary is intended to serve as a brief introduction to some embodiments of the present disclosure. It is not meant to be an introduction or overview of all inventive subject matter disclosed herein. The following detailed description and the drawings referenced in the detailed description will further describe the embodiments described in the summary as well as other embodiments. Therefore, an overview, detailed description, and drawings are provided in order to understand all embodiments described by this document. In addition, the claimed subject matter is not limited by the illustrative details in the summary, specific embodiments, and drawings, but is defined by the appended claims, because the claimed subject matter may be embodied in other specific forms without departing from the spirit of the present subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are illustrative embodiments. They do not show all embodiments. In addition or alternatively, other embodiments may be used. Details that may be obvious or unnecessary may be omitted to save space or for more effective description. Some embodiments may be implemented with additional parts or steps and / or without all parts or steps shown. When the same number appears in different drawings, it refers to the same or similar parts or steps.

[0009] Figure 1 A quantum computing system is conceptually illustrated according to an exemplary embodiment in which a Josephson junction circuit is used as a radio frequency envelope detector to extract a baseband signal from an amplitude modulated RF signal.

[0010] Figure 2 An example of a Josephson junction envelope detector circuit is shown.

[0011] Figure 3 Conceptual illustration of the voltage-current behavior of a Josephson junction stack array when biased near the critical current.

[0012] Figure 4 The reduction of the critical current of a Joseph junction device due to the presence of a radio frequency signal is shown.

[0013] Figure 5 A digitally simulated input RF signal and a corresponding output signal generated based on the detected envelope are shown.

[0014] Figure 6A process for generating control pulses for a quantum computing payload using a Josephson junction device based on an input modulated radio frequency signal is conceptually shown, consistent with an illustrative embodiment. DETAILED DESCRIPTION

[0015] In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the relevant teachings. However, it should be appreciated that the present teachings may be practiced without these details. In other instances, well-known methods, procedures, components, and / or circuits have been described at a relatively high level without detail in order to avoid unnecessarily obscuring aspects of the present teachings.

[0016] Some embodiments of the present disclosure provide a Josephson junction (JJ) circuit that is used as an envelope detector to detect amplitude modulation of a high frequency radio frequency (RF) input signal. Control of the amplitude modulation is achieved through an RF trigger or input. The detected amplitude modulation is used as a baseband signal for a quantum computing payload (e.g., qubit control pulses and flux pulses for a SQUID system). The JJ circuit is current biased to minimize its static dissipation. This allows the envelope detector to be physically close to the computing payload (e.g., inside a cryostat housing the qubits). The proximity of the envelope detector to the payload significantly reduces (e.g., minimizes) the dispersion and distortion of the detected baseband signal.

[0017] Figure 1 A quantum computing system 100 is conceptually illustrated according to an exemplary embodiment, in which a JJ circuit is used as an RF envelope detector to extract a baseband signal from an amplitude modulated RF signal.

[0018] As shown, the signal generator 105 generates an RF signal 120 at room temperature (T ~ 300 Kelvin). (The signal generator 105 may also operate at other temperatures.) The RF signal 120 may be amplitude modulated according to a modulation signal 115, which may include a control pulse or flux pulse to a quantum processing unit (QPU) 140. The RF envelope detector 110 receives the modulated RF signal 120, performs envelope detection, and outputs the detected envelope as a baseband signal 130. The RF envelope detector 110 is a JJ-based circuit that can operate at cryogenic temperatures (e.g., T < 4 Kelvin) and is current biased to operate in a supercurrent state when not receiving an RF signal, and therefore has zero or near-zero static dissipation. The baseband signal 130 is in turn provided to the QPU 140. In an embodiment, the QPU 140 operates at milliKelvin temperatures in a cryostat. Because the RF envelope detector 110 has zero static dissipation, it may be physically located near or within the cryostat enclosure QPU 140. This allows the baseband signal 130 to be applied to the QPU 140 with substantially reduced (eg, minimal) distortion and dispersion.

[0019] Figure 2 An exemplary JJ envelope detector circuit 200 is shown that can be configured to have zero static dissipation when not receiving an RF signal. For some embodiments, the JJ envelope detector circuit 200 is an implementation of the RF envelope detector 110. As illustrated, the JJ envelope detector circuit 200 includes a bias current source 210, a JJ stack array 220, and input and output impedances 230 and 240. The JJ envelope detector circuit 200 receives an RF signal (e.g., the RF signal 120 from the RF signal source 105) and reproduces the envelope of the incoming high frequency (~GHz) signal as a baseband output current driven into a load (e.g., a 50 ohm system). The large output inductor L0 250 (~1+nH) stabilizes the current noise level where Φ0 is the superconducting flux quantum. In addition, the JJs in the envelope detector circuit 200 are critically damped because each JJ has its own external parallel shunt resistor (not illustrated) that damps the JJ IV response so that it is not lagging.

[0020] It is known that each individual JJ produces a small voltage across it and has very limited current sourcing capability. This small voltage and current sourcing capability may limit device performance when placed in a typical 50 ohm impedance environment. To circumvent such limitations, the JJ envelope detector circuit 200 employs multiple JJs to meet voltage and current requirements. As illustrated, the JJ stack array 220 includes several parallel series stacked JJ paths. When the JJ is switched to a limited voltage state during an RF application, the series stacked JJs are used to increase the voltage. The parallel stacking of JJs is used to increase the total current sourcing capacity of the device.

[0021] The JJ stack array 220 is an array of one or more parallel stacks of nominally identical JJs connected in series. Different stacks of JJs are connected to a central node 205, where a DC current is injected by a bias current source 210 to bias the stack array up to 90%+ of the critical current of the individual JJ. The stacking of JJ devices increases the output voltage. Each JJ has a characteristic voltage Vc~700uV. For a 50 ohm load, there can be 70 or more JJs in series per stack. The stack of parallel JJs supplies the output current to the load together. Therefore, for example, in order to provide a current of ~1mA, an order of magnitude of 70JJs in each series stack is required to generate a voltage of 50mV required to drive a 50 ohm load. In order to provide the appropriate current, multiple parallel stacks are required so that the source load is shared. For example, if 10 parallel stacks are implemented, each stack will only need to provide 100uA, significantly reducing the source load of each stack. The voltage produced by the JJ stack is configured to provide current (~1 mA) into a Z=50 ohm load / ambient for mutually (1-2 pH) coupled SQUIDs. This allows the output voltage of the JJ envelope detector circuit 200 to drive appreciable output current and act as an RF-DC flux bias circuit.

[0022] The amplitude modulated RF is fed into the JJ stack array 220 via a second high bandwidth line 215 connected to the centralized bias point 205. As mentioned, the JJ envelope detector circuit 200 is biased to have zero static power dissipation, i.e., when no RF signal enters the JJ envelope detector circuit 200, the JJ devices in the JJ stack array 220 are in a supercurrent state, enabling current to flow without power dissipation.

[0023] In some embodiments, the JJ envelope detector circuit 200 is DC biased according to or near the critical current of the JJ devices in the JJ stack array 220. The critical current is defined as the maximum supercurrent that a given superconducting device can carry before switching from a supercurrent state to a normal state (where the JJ device operates according to a voltage regime). Since the JJ stack array 220 is current biased near its critical current, the JJs in the stack array 220 will maintain their supercurrent state in the absence of an RF signal and switch to a normal voltage state when an RF signal is received.

[0024] A JJ that is current biased near its critical current will respond to an amplitude modulated RF input signal by switching to a voltage state via a reduction in its critical current. In an embodiment, when an amplitude modulated RF wave is applied to the JJ, the critical current of the JJ decreases in proportion to the time-dependent amplitude of the RF signal. Combined with the current bias, this reduction in critical current forces the JJ to switch to a finite voltage state in which the amplitude of the voltage output is proportional to the amplitude of the input RF signal. The envelope detector circuit 200 thereby extracts the envelope of the RF input.

[0025] Thus, when the bias current source 210 provides a DC current to bias the JJ stack array 220 to near the critical current of the JJ stack, the RF signal 120 together with the DC bias current forces the JJ stack array 220 into a voltage range where the output voltage 130 of the JJ envelope detector circuit 200 mirrors the output voltage of the RF amplitude envelope. This allows the JJ stack array to operate as an envelope detector in its voltage state.

[0026] Figure 3 The voltage-current behavior of the JJ stack array 220 when biased near a critical current is conceptually illustrated. The figure includes two IV curves 301 and 302. IV curve 301 shows the voltage-current behavior when the envelope detector circuit 200 is not receiving an RF signal. IV curve graph 302 shows the voltage-current behavior when the envelope detector circuit 200 is receiving a maximum RF signal (with a maximum amplitude). As shown in the IV curve graph, when the bias current is below the critical current, the JJ circuit is in a supercurrent state with no voltage drop (and no power dissipation), and when the bias current is above the critical current, the JJ circuit is in a voltage state with a voltage drop (and with power dissipation). The presence of the RF input signal reduces the critical current, causing the critical current I cA (When there is no input RF signal) higher than the critical current I cB (When the RF signal is at maximum amplitude).

[0027] In some embodiments, the DC bias current I bias (generated by bias current source 210) is selected to be at IcA >I bias >I cB In other words, when there is no incoming RF signal, the bias is used to put the JJ stack array 220 in a supercurrent state, and when the RF signal is greater than a certain threshold amplitude, the bias is used to put it in a voltage state. This allows the JJ envelope detector circuit 200 to detect the envelope of the target RF signal and output the detected envelope as an output voltage. This also allows the JJ envelope detector circuit 200 to have zero static power dissipation when there is no input RF signal.

[0028] Figure 4 The reduction of the critical current of the Joseph junction device due to the presence of the RF signal is shown. As described above, when an amplitude modulated RF wave is applied to the JJ, the critical current of the JJ is reduced in proportion to the time-dependent amplitude of the RF signal. The figure shows an IV curve diagram 405 of an amplitude modulated RF signal 400 and a JJ device (e.g., a JJ stack array 220) receiving the RF signal. The figure identifies four different envelope amplitudes 410, 411, 412, and 413 in the RF signal 400. The IV diagram 405 shows four different IV curves 420 and 423 corresponding to the four amplitudes 410 and 413, respectively. Specifically, each IV curve represents a measurement of the JJ device when an RF tone of a corresponding amplitude is applied. The different envelope amplitudes 410 to 413 also correspond to four different critical current levels Icc0, Icc1, Icc2, and Icc3, respectively. Ic0 represents the original critical current level (amplitude 410) without an RF signal. Ic1, Ic2, and Ic3 represent the reduced critical currents caused by RF signals of amplitudes 411, 412, and 413, respectively.

[0029] Figure 5 2 shows a simulated input RF signal and a corresponding output signal generated based on the detected envelope. The figure shows three time domain voltage or current graphs 501, 502 and 503. Graph 501 shows an exemplary amplitude modulated 5 GHz signal (e.g., Figure 1 Graph 502 shows the output of the JJ envelope detector circuit 200 entering a 50 ohm load. The output is generated based on the detected envelope of the example input modulated RF signal. In some embodiments, a low pass filter may be applied to remove high frequency components from the output of the JJ envelope detector circuit 200. Graph 503 shows the simulated output after applying a 100 MHz low pass filter. Therefore, the JJ envelope detector circuit 200 is similar to a voltage source, where the amplitude of the voltage driving the input load depends on the amplitude of the RF wave.

[0030] Figure 6A process 600 is conceptually shown for generating control pulses for a quantum computing payload based on an input modulated RF signal using a JJ device consistent with an illustrative embodiment. In some embodiments, process 600 describes operations performed by a quantum computing system 100 that uses an envelope detector circuit to convert a modulated RF signal into a control or flux pulse for a SQUID.

[0031] The system injects (at block 610) a bias current into an envelope detector circuit. The bias current may be identified based on first and second critical currents of a superconducting device in the envelope detector circuit. The first critical current may correspond to the envelope detector not receiving an RF signal. The second critical current may correspond to the envelope detector circuit receiving a maximum RF signal. The critical current of the superconducting device in the envelope detector circuit decreases in proportion to the time-dependent amplitude of the RF signal. The envelope detector circuit includes a plurality of Josephson junction (JJ) devices arranged as one or more parallel JJ device stacks for providing an output current and an output voltage to an output load. The parallel JJ device stacks are interconnected at a center node with a bias current source.

[0032] The system determines (at block 620) whether the envelope detector circuit is receiving an RF signal at the envelope detector circuit. When the envelope detector circuit is not receiving an RF signal, the JJ device in the envelope detector circuit remains (at block 630) in a super current state with zero quiescent power consumption.

[0033] When the envelope detector circuit is receiving an RF signal, a JJ device in the envelope detector circuit switches (at block 640) into a normal voltage state. The envelope detector circuit may detect (at block 650) the envelope of the amplitude modulated RF signal. The envelope detector circuit then generates (at block 660) an output based on the envelope detected by the envelope detector circuit. The system may apply (at block 665) a low pass filter to the output of the envelope detector circuit. The system uses (at block 670) the output of the envelope detector circuit to drive an output load. The output load may include a quantum processing unit (QPU) housed in a cryostat, and the envelope detector circuit is physically in the cryostat. The output of the envelope detector circuit may be used as a flux pulse or control pulse to a superconducting quantum interference device (SQUID).

[0034] Figure 6 The flowcharts in the figure illustrate possible implementations of the system, method, or computer program product according to various embodiments of the present disclosure. In this regard, each box in the flowchart may represent a module, segment, or portion of instructions for implementing the specified operation. In some alternative implementations, the operations marked in the boxes may not be marked in the order specified. Figure 6For example, two blocks shown in succession may occur in the order noted in the drawings, for example, may actually be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the operations involved.

[0035] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0036] The description of various embodiments of the present teachings has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements existing in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

[0037] Although the above has described what is considered to be the best state and / or other examples, it should be understood that various modifications may be made therein, and the subject matter disclosed herein may be implemented in various forms and examples, and the teachings may be applied to many applications, only some of which are described herein. The appended claims are intended to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.

[0038] The components, steps, features, objects, benefits, and advantages discussed herein are merely illustrative. None of them, or the discussion related to them, is intended to limit the scope of protection. Although various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise indicated, all measurements, values, ratings, positions, sizes, dimensions, and other specifications in this specification, including those set forth in the appended claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions to which they are related and the customary practices of the field to which they belong.

[0039] Many other embodiments are also contemplated. These include embodiments with fewer, additional and / or different components, steps, features, objects, benefits and advantages. These also include embodiments in which components and / or steps are arranged and / or ordered in different ways.

[0040] Although the foregoing has been described in conjunction with exemplary embodiments, it should be understood that the term "exemplary" is meant only as an example, rather than the best or optimal. Except as immediately stated above, nothing stated or illustrated is intended or should be construed to cause any component, step, feature, object, benefit, advantage, or equivalent to be dedicated to the public, whether or not stated in the claims.

[0041] It should be understood that, unless a specific meaning is elaborated in addition herein, the terms and expressions used herein have the common meaning consistent with these terms and expressions about their corresponding respective investigation and research fields. Relational terms such as the first and second etc. can be used only to distinguish one entity or action from another, without requiring or implying any actual such relationship or order between these entities or actions. The term "comprise", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only include those elements, but also may include other elements that are not clearly listed or are inherent to such process, method, article or device. In the absence of further constraints, the element with "one" or "an" in front does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0042] The abstract of the present disclosure is provided to allow the reader to quickly determine the nature of the technical disclosure. It should be understood that it is not used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing detailed description, it can be seen that in order to make the present disclosure smooth, various features are grouped together in various embodiments. This method of disclosure should not be interpreted as reflecting the intention that the claimed embodiments require more features than the features explicitly recited in each claim. On the contrary, as reflected in the attached claims, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the specific implementation mode, wherein each claim is independently a subject matter claimed separately.

Claims

1. A device comprising: an envelope detector circuit configured to receive an amplitude modulated radio frequency (RF) signal and detect an envelope of the received RF signal; a bias current source configured to inject a bias current into the envelope detector circuit, wherein the bias current is identified based on a first critical current and a second critical current of a superconducting device in the envelope detector circuit; as well as An output load is configured to receive an output of the envelope detector circuit generated based on the detected envelope.

2. The apparatus of claim 1, wherein the envelope detector circuit comprises a plurality of Josephson junction (JJ) devices. 3 . The apparatus of claim 2 , wherein the plurality of JJ devices comprises a stack of JJ devices connected in series for supplying an output voltage to the output load.

4. The apparatus according to claim 3, wherein: The plurality of JJ devices are arranged as a plurality of parallel JJ device stacks for providing an output current to the output load; and The parallel JJ device stack is interconnected to the bias current source at a central node.

5. The apparatus of any one of claims 2 to 4, wherein the plurality of JJ devices are configured to be in a supercurrent state when the envelope detector circuit does not receive an RF signal.

6. The apparatus of any one of claims 2 to 5, wherein the plurality of JJ devices are configured to have zero static power dissipation when the envelope detector circuit does not receive an RF signal.

7. The apparatus of any one of claims 2 to 6, wherein when the envelope detector circuit receives an RF signal, the plurality of JJ devices are configured to be in a voltage state.

8. The apparatus of any one of claims 2 to 7, wherein the plurality of JJ devices are critically damped by shunt resistors.

9. The apparatus of any preceding claim, wherein the output load comprises a quantum processing unit (QPU) housed in a cryostat.

10. The apparatus of claim 9, wherein the envelope detector circuit is physically within the cryostat.

11. The apparatus of any of the preceding claims, wherein the first critical current corresponds to the envelope detector circuit receiving no RF signal, and the second critical current corresponds to the envelope detector circuit receiving a nearly maximum RF signal.

12. Apparatus according to any preceding claim, wherein the critical current of the superconducting device in the envelope detector circuit is reduced in proportion to the time-dependent amplitude of the RF signal.

13. The apparatus of any preceding claim, further comprising a low pass filter configured to filter the output of the envelope detector circuit.

14. Apparatus according to any preceding claim, wherein the output of the envelope detector circuit is used as a flux pulse to a superconducting quantum interference device (SQUID).

15. A method comprising: injecting a bias current into an envelope detector circuit, wherein the bias current is identified based on a first critical current and a second critical current of a superconducting device in the envelope detector circuit; receiving a modulated radio frequency (RF) signal at the envelope detector circuit; detecting an envelope of the received RF signal based on the received RF signal; as well as An output of the envelope detector circuit is used to drive an output load, wherein the output is generated based on the envelope detected by the envelope detector circuit.

16. The method of claim 15, wherein the envelope detector circuit comprises a plurality of Josephson junction (JJ) devices arranged as one or more parallel JJ device stacks for providing an output current and an output voltage to the output load, wherein the parallel JJ device stacks are interconnected to the bias current source at a center node.

17. The method of claim 16, wherein: When the envelope detector circuit does not receive an RF signal, the plurality of JJ devices are in a supercurrent state with zero static power dissipation; When the envelope detector circuit receives an RF signal, the plurality of JJ devices are in a voltage state.

18. The method according to any one of claims 15 to 17, wherein: The first critical current corresponds to the envelope detector circuit not receiving an RF signal; and The second critical current corresponds to the envelope detector circuit receiving a nearly maximum RF signal.

19. A method according to any one of claims 15 to 18, further comprising applying a low pass filter to the output of the envelope detector circuit.

20. The method according to any one of claims 15 to 19, further comprising: using the output of the envelope detector circuit as a flux pulse to a quantum processing unit (QPU); housing the quantum processing unit (QPU) in a cryostat; as well as The envelope detector circuit is housed in the cryostat.

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