Display device and method of manufacturing same

Abstract

A display device is provided. The display device includes a display area and a peripheral area. In the display area, the display device comprises a pixel driving circuit substrate, a plurality of light-emitting elements located on the pixel driving circuit substrate, a packaging layer located on the sides, away from the pixel driving circuit substrate, of the light-emitting elements, and an inorganic insulating layer located on the side, away from the light-emitting elements, of the packaging layer. In the binding pin area of the peripheral area, the display device comprises a substrate and a plurality of binding pins located on the substrate. The orthographic projection of the inorganic insulating layer on the substrate is at least partially not overlapped with the orthographic projections of the plurality of binding pins on the substrate.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to a display device and a method for manufacturing the display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units, which are configured with a pixel driving circuit arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate signal line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] On the one hand, the present disclosure provides a display device, including a display area and a peripheral area; wherein, in the display area, the display device includes a pixel driving circuit substrate, a plurality of light-emitting elements located on the pixel driving circuit substrate, an encapsulation layer located on a side of the plurality of light-emitting elements away from the pixel driving circuit substrate; and an inorganic insulating layer located on a side of the encapsulation layer away from the plurality of light-emitting elements; in the binding pin area of ​​the peripheral area, the display device includes: a substrate; a plurality of binding pins located on the substrate substrate; and an orthographic projection of the inorganic insulating layer on the substrate substrate and a projection of the plurality of binding pins on the substrate substrate that at least partially does not overlap.

[0004] Optionally, the display device further includes in the display area: a buffer layer located on a side of the inorganic insulating layer away from the encapsulation layer; a first touch layer located on a side of the buffer layer away from the inorganic insulating layer; a touch insulating layer located on a side of the first touch layer away from the buffer layer; a second touch layer located on a side of the touch insulating layer away from the first touch layer; and a coating layer located on a side of the second touch layer away from the touch insulating layer; wherein the buffer layer, the touch insulating layer and the coating layer are made of polymeric organic material.

[0005] Optionally, the display device further comprises a black matrix and a color film in the display area, which are located on a side of the cover layer away from the second touch layer; wherein the black matrix and the color film are in direct contact with the cover layer.

[0006] Optionally, an orthographic projection of the inorganic insulating layer on the base substrate does not overlap at all with an orthographic projection of the plurality of binding pins on the base substrate.

[0007] Optionally, the display device also includes a plurality of touch signal lines at least partially located in the peripheral area; wherein each of the plurality of touch signal lines extends at least through the touch insulation layer, the buffer layer and the inorganic insulation layer to be connected to a corresponding binding pin among the plurality of binding pins; and each of the touch signal lines is at least partially located in the second touch layer.

[0008] Optionally, each of the binding pins includes a first edge, a second edge, a third edge and a fourth edge; the orthographic projection of the touch insulation layer on the substrate substantially covers the orthographic projection of the first edge on the substrate, substantially covers the orthographic projection of the second edge on the substrate, substantially covers the orthographic projection of the third edge on the substrate, and substantially covers the orthographic projection of the fourth edge on the substrate; the first edge, the second edge, the third edge and the fourth edge surround the central part of each of the binding pins; and the orthographic projection of the touch insulation layer on the substrate does not at least partially overlap with the orthographic projection of the central part of each of the binding pins on the substrate.

[0009] Optionally, each of the binding pins includes a first edge, a second edge, a third edge and a fourth edge; the orthographic projection of the touch insulating layer on the substrate substrate at least partially does not overlap with the orthographic projection of the first edge on the substrate substrate, does not overlap with the orthographic projection of the second edge on the substrate substrate at least partially, does not overlap with the orthographic projection of the third edge on the substrate substrate at least partially, and does not overlap with the orthographic projection of the fourth edge on the substrate substrate; the first edge, the second edge, the third edge and the fourth edge surround the central part of each of the binding pins; and the orthographic projection of the touch insulating layer on the substrate substrate does not overlap with the orthographic projection of the central part of each of the binding pins on the substrate substrate at least partially.

[0010] Optionally, the display device also includes a first via; wherein each touch signal line is connected to the corresponding binding pin through the first via; the insulating layer between the exposed surface of the corresponding binding pin and the first via includes an inclined portion and a non-inclined portion; along the direction from the exposed surface of the corresponding binding pin to the first via, the width of the non-inclined portion is greater than the maximum width of the first via.

[0011] Optionally, the display device further includes a second via and a third via; wherein each touch signal line includes a first part located in the first touch layer and a second part located in the second touch layer; the second part is connected to the first part through the second via; and the first part is connected to the corresponding binding pin through the third via.

[0012] Optionally, the display device further includes a second via, a third via and a fourth via; wherein each touch signal line includes a first part located in the first touch layer and a second part located in the second touch layer; the second part is connected to the first part through the second via; the first part is connected to the corresponding binding pin through the third via and the fourth via, respectively.

[0013] Optionally, the fourth distance is greater than the fifth distance; the fourth distance represents the minimum distance between the orthographic projection of the portion of the first portion located in the third via on the substrate substrate and the orthographic projection of the portion of the first portion located in the fourth via on the substrate substrate; and the fifth distance represents the minimum distance between the orthographic projection of the portion of the first portion located in the third via on the substrate substrate and the orthographic projection of a portion of the corresponding binding pin on the substrate substrate, at which position the surface of the portion transitions from being covered by the insulating layer to being exposed.

[0014] Optionally, the display device further includes a first via hole; wherein each of the touch signal lines is connected to the corresponding binding pin through the first via hole; and the first via hole extends through the touch insulating layer, the buffer layer and the inorganic insulating layer.

[0015] Optionally, the display device further includes a fifth via hole; wherein each touch signal line is connected to the corresponding binding pin through the fifth via hole; and the fifth via hole extends through the touch insulation layer, the buffer layer, the inorganic insulation layer and the first planarization layer.

[0016] Optionally, the display device also includes in the peripheral area a first voltage supply line configured to provide a first voltage supply signal to the display area and a second voltage supply line configured to provide a second voltage supply signal to the display area; wherein, the orthographic projection of at least one of the first voltage supply line or the second voltage supply line on the substrate at least partially overlaps with the orthographic projection of the multiple binding pins on the substrate.

[0017] Optionally, in the binding pin area of ​​the peripheral area, the display device includes: a first signal line layer, which is located on the base substrate; a passivation layer, which is located on a side of the first signal line layer away from the base substrate; a second signal line layer, which is located on a side of the passivation layer away from the first signal line layer; a first planarization layer, which is located on a side of the second signal line layer away from the passivation layer; and the plurality of binding pins, which are located on a side of the first planarization layer away from the second signal line layer.

[0018] Optionally, each of the multiple binding pins is in direct contact with the first planarization layer; the first planarization layer is in direct contact with the each binding pin in a first area and is not in contact with the each binding pin in a second area, wherein the second area is adjacent to the first area; the surface of the first planarization layer away from the substrate substrate includes a first part that is in direct contact with the each binding pin and a second part that is not in contact with the each binding pin, and the first part and the second part are located on the same side of the first planarization layer; relative to the same horizontal plane, the first relative height is greater than the second relative height; the first relative height is the height of the first part relative to the same horizontal plane; and the second relative height is the height of the second part relative to the same horizontal plane.

[0019] Optionally, in the binding pin area of ​​the peripheral area, the display device includes: a first signal line layer, which is located on the base substrate; a passivation layer, which is located on a side of the first signal line layer away from the base substrate; the multiple binding pins located on a second signal line layer, and the second signal line layer is located on a side of the passivation layer away from the first signal line layer; and a first planarization layer, which is located on a side of the second signal line layer away from the passivation layer.

[0020] On the other hand, the present disclosure provides a method for manufacturing a display device, wherein the display device has a display area and a peripheral area, and the peripheral area includes a binding pin area; wherein the method includes: in the display area, forming a pixel driving circuit substrate, forming a plurality of light-emitting elements on the pixel driving circuit substrate, and forming an encapsulation layer on a side of the plurality of light-emitting elements away from the pixel driving circuit substrate; in the binding pin area, forming a plurality of binding pins; forming an inorganic insulating layer on a side of the encapsulation layer in the display area away from the base substrate, and on a side of the plurality of binding pins in the binding pin area in the peripheral area away from the base substrate; after forming the inorganic insulating layer, forming a black matrix and a color film on a side of the plurality of light-emitting elements away from the pixel driving circuit substrate in the display area; and after forming the black matrix and the color film, at least partially removing the portion of the inorganic insulating layer located in the binding pin area to expose at least a portion of each of the plurality of binding pins.

[0021] Optionally, the method also includes, in the binding pin area: forming a first signal line layer on the base substrate; forming a passivation layer on a side of the first signal line layer away from the base substrate; forming a second signal line layer on a side of the passivation layer away from the first signal line layer; forming a first planarization layer on a side of the second signal line layer away from the passivation layer; and forming the plurality of binding pins on a side of the first planarization layer away from the second signal line layer.

[0022] On the other hand, the present disclosure provides a display device, including a display area and a peripheral area; wherein, in the display area, the display device includes a pixel driving circuit substrate, a plurality of light-emitting elements located on the pixel driving circuit substrate, an encapsulation layer located on a side of the plurality of light-emitting elements away from the pixel driving circuit substrate; and an inorganic insulating layer located on a side of the encapsulation layer away from the plurality of light-emitting elements; in the binding pin area of ​​the peripheral area, the display device includes: a substrate; a plurality of binding pins located on the substrate substrate; and the orthographic projection of the inorganic insulating layer on the substrate substrate and the orthographic projection of the plurality of binding pins on the substrate substrate at least partially do not overlap; wherein the display device also includes: a plurality of touch signal lines, which are at least partially located in the peripheral area; and a plurality of first vias; wherein each touch signal line is connected to a corresponding binding pin among the plurality of binding pins through a first via among the plurality of first vias; and an exposed surface of the corresponding binding pin is spaced apart from the first via. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0024] Figure 1 Detailed structures in a display area of ​​a display device according to some embodiments of the present disclosure are shown.

[0025] Figure 2 is a schematic diagram showing the structure of a display device in some embodiments of the present disclosure.

[0026] Figure 3 is a schematic diagram showing the structure of a display device in some embodiments of the present disclosure.

[0027] Figure 4 is a schematic diagram showing a display area and a peripheral area in a display device according to some embodiments of the present disclosure.

[0028] Figure 5 is a diagram illustrating a portion of a peripheral area in a display device according to some embodiments of the present disclosure.

[0029] Figure 6 is a schematic diagram showing the structure of a display device in some embodiments of the present disclosure.

[0030] Figure 7 Shows undercut erosion occurring at the edge of a bond pin.

[0031] FIG. 8A to FIG. 8G A process of manufacturing a display device according to some embodiments of the present disclosure is shown.

[0032] Fig. 9 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0033] Fig.10 is a plan view of a portion of a display device located in a binding pin area according to some embodiments of the present disclosure.

[0034] Fig.11A The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0035] Fig. 11B The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0036] Fig.12 The structure of corresponding binding pins in a display device according to some embodiments of the present disclosure is shown.

[0037] Fig.13is a plan view of a portion of a display device located in a binding pin area according to some embodiments of the present disclosure.

[0038] Fig.14 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0039] Fig.15 is a plan view of a portion of a display device located in a binding pin area according to some embodiments of the present disclosure.

[0040] Fig.16 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0041] Fig.17 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0042] Fig.18 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0043] Fig.19 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0044] FIG. 20A to FIG. 20F A process of manufacturing a display device according to some embodiments of the present disclosure is shown.

[0045] Fig.21 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0046] Fig. 22 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0047] Fig.23 The structure of corresponding binding pins in a display device according to some embodiments of the present disclosure is shown.

[0048] Fig.24 is a plan view of a portion of a display device located in a binding pin area according to some embodiments of the present disclosure.

[0049] Fig.25 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0050] Fig.26is a plan view of a portion of a display device located in a binding pin area according to some embodiments of the present disclosure.

[0051] Fig. 27 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0052] Fig.28 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown.

[0053] Fig.29 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0054] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0055] The present disclosure particularly provides a display device and a method for manufacturing a display device, which substantially overcomes one or more problems caused by the limitations and shortcomings of the prior art. On the one hand, the present disclosure provides a display device. In some embodiments, the display device includes a display area and a peripheral area. Optionally, in the display area, the display device includes a pixel driving circuit substrate, a plurality of light-emitting elements located on the pixel driving circuit substrate, an encapsulation layer located on a side of the plurality of light-emitting elements away from the pixel driving circuit substrate, and an inorganic insulating layer located on a side of the encapsulation layer away from the plurality of light-emitting elements. Optionally, in the binding pin area of ​​the peripheral area, the display device includes a substrate substrate and a plurality of binding pins located on the substrate substrate. Optionally, the orthographic projection of the inorganic insulating layer on the substrate substrate does not overlap at least partially with the orthographic projection of the plurality of binding pins on the substrate substrate.

[0056] Figure 1 Detailed structures in the display area of ​​the display device in some embodiments of the present disclosure are shown. Figure 1In some embodiments, the display device includes in the display area: a base substrate BS (for example, a flexible base substrate); an interlayer ITL located on the base substrate BS; an active layer ACT of each thin film transistor among a plurality of thin film transistors TFT located on a side of the interlayer ITL away from the base substrate BS; a gate insulating layer GI located on a side of the active layer ACT away from the base substrate BS; a gate G and a first capacitor electrode Ce1 (both are parts of the first conductive layer) located on a side of the gate insulating layer GI away from the base substrate BS; an insulating layer IN located on a side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (a part of the second conductive layer) located on a side of the insulating layer IN away from the gate insulating layer GI; and a second capacitor electrode Ce2 an interlayer dielectric layer ILD located on a side away from the gate insulating layer GI; a source S and a drain D (part of the first signal line layer) located on a side of the interlayer dielectric layer ILD away from the gate insulating layer GI; a passivation layer PVX located on a side of the source S and the drain D away from the interlayer dielectric layer ILD; a first planarization layer PLN1 located on a side of the passivation layer PVX away from the interlayer dielectric layer ILD; a relay electrode RE (part of the second signal line layer) located on a side of the first planarization layer PLN1 away from the passivation layer PVX; a second planarization layer PLN2 located on a side of the relay electrode RE away from the first planarization layer PLN1; a pixel defining layer PDL that defines a sub-pixel opening and is located on a side of the second planarization layer PLN2 away from the substrate BS; and a light emitting element LE located in the sub-pixel opening. The light emitting element LE includes: an anode AD located on a side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light emitting layer EL located on a side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD located on a side of the light emitting layer EL away from the anode AD. The display device also includes an encapsulation layer EN in the display area, which encapsulates the light emitting element LE and is located on a side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 located on a side of the cathode layer CD away from the substrate BS, an organic encapsulation sublayer IJP located on a side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS, and a second inorganic encapsulation sublayer CVD2 located on a side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1.The display device further includes a buffer layer BUF located on a side of the encapsulation layer EN away from the substrate BS, a plurality of second electrode bridges BR2 located on a side of the buffer layer BUF away from the encapsulation layer EN, a touch insulating layer TI located on a side of the plurality of second electrode bridges BR2 away from the buffer layer BUF, a plurality of first touch electrodes TE1 located on a side of the touch insulating layer TI away from the buffer layer BUF, and an overcoat layer OC located on a side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI in the display area. Optionally, in the display area, the display device does not include a passivation layer PVX, for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0057] Reference Figure 1 The display device includes a semiconductor material layer SML, a first conductive layer CT1, a second conductive layer CT2, a first signal line layer SL1, and a second signal line layer SL2. The display device also includes an insulating layer IN between the first conductive layer CT1 and the second conductive layer CT2, an interlayer dielectric layer ILD between the second conductive layer CT2 and the first signal line layer SL1, and at least a passivation layer PVX or a first planarization layer PLN1 between the first signal line layer SL1 and the second signal line layer SL2.

[0058] Reference Figure 1 , a plurality of second electrode bridges BR2 are located on the first touch layer ML1 , and a plurality of first touch electrodes TE1 are located on the second touch layer ML2 .

[0059] Figure 2 Schematic diagram showing the structure of a display panel in some embodiments of the present disclosure. Figure 2 In some embodiments, the touch structure includes a plurality of first grid electrodes TE1 arranged in a plurality of rows and a plurality of second grid electrodes TE2 arranged in a plurality of columns. The plurality of first grid electrodes TE1 are arranged in a plurality of rows, and each row in the plurality of rows is a corresponding first grid electrode in the plurality of first grid electrodes TE1. The plurality of second grid electrodes TE2 are arranged in a plurality of columns, and each column in the plurality of columns is a corresponding second grid electrode in the plurality of second grid electrodes TE2. Optionally, the touch structure is a mutual capacitive touch structure. Optionally, the plurality of first grid electrodes TE1 are a plurality of touch sensing electrodes, and the plurality of second grid electrodes TE2 are a plurality of touch scanning electrodes. Optionally, the plurality of first grid electrodes TE1 are a plurality of touch scanning electrodes, and the plurality of second grid electrodes TE2 are a plurality of touch sensing electrodes.

[0060] like Figure 2As shown, each of the plurality of first grid electrodes TE1 includes a plurality of first grid blocks MB1 electrically connected in sequence along a first direction DR1 in a corresponding row, and each of the plurality of second grid electrodes TE2 includes a plurality of second grid blocks MB2 electrically connected in sequence along a second direction DR2 in a corresponding column. Figure 2 , a corresponding one of the plurality of first grid blocks MB1 and a corresponding one of the plurality of second grid blocks MB2 are depicted as blocks respectively surrounded by dotted lines.

[0061] Figure 3 Schematic diagram showing the structure of a display device in some embodiments of the present disclosure. Figure 3 The display device includes a pixel driving circuit substrate PCS, which includes a plurality of pixel driving circuits for driving the display device to emit light, a plurality of light emitting elements LE connected to the plurality of pixel driving circuits, an encapsulation layer EN located on a side of the plurality of light emitting elements LE away from the pixel driving circuit substrate PCS, a buffer layer BUF located on a side of the encapsulation layer EN away from the plurality of light emitting elements LE, a first touch layer ML1 located on a side of the buffer layer BUF away from the encapsulation layer EN, a touch insulating layer TI located on a side of the first touch layer ML1 away from the buffer layer BUF, a second touch layer ML2 located on a side of the touch insulating layer TI away from the first touch layer ML1, a covering layer OC located on a side of the second touch layer ML2 away from the touch insulating layer TI, a black matrix BM and a color film CF located on a side of the covering layer OC away from the second touch layer ML2, and a planarization layer PLN located on a side of the black matrix BM and the color film CF away from the covering layer OC.

[0062] Figure 4 Schematic diagram showing a display area and a peripheral area of ​​a display device according to some embodiments of the present disclosure. Figure 4 In some embodiments, the peripheral area PA includes a first sub-area PA1 located at the first side S1 of the display area DA, a second sub-area PA2 located at the second side S2 of the display area DA, a third sub-area PA3 located at the third side S3 of the display area DA, and a fourth sub-area PA4 located at the fourth side S4 of the display area DA. Optionally, the first side S1 and the fourth side S4 are opposite to each other. Optionally, the second side S2 and the third side S3 are opposite to each other. Optionally, the first sub-area PA1 is a sub-area where a plurality of signal lines are connected to an integrated circuit (e.g., an integrated touch circuit).

[0063] In some embodiments, the first sub-region PA1 includes a side region SR and one or more corner regions (e.g., a first corner region CR1 and a second corner region CR2). The one or more corner regions are respectively located at the corners of the array substrate. The one or more corner regions connect the side region SR to one or more adjacent sub-regions of the peripheral region PA. For example, the first corner region CR1 connects the side region SR to the second sub-region PA2, and the second corner region CR2 connects the side region SR to the third sub-region PA3.

[0064] Figure 5 is a diagram showing a portion of a peripheral area in a display device according to some embodiments of the present disclosure. Figure 5 , the display device includes a plurality of binding pins BPS in the peripheral area, which are configured to be bound to a touch integrated circuit or a flexible printed circuit. The plurality of binding pins BPS are located in the binding pin area BPR. The display device also includes various signal lines in the peripheral area, such as a first voltage supply line VDD configured to provide a first voltage supply signal to the display area and a second voltage supply line VSS configured to provide a second voltage supply signal to the display area. In some embodiments, the first voltage supply line VDD extends at least partially in the binding pin area BPR, for example, extending through the binding pin area BPR. In some embodiments, the second voltage supply line VSS extends at least partially in the binding pin area BPR, for example, extending through the binding pin area BPR. In some embodiments, the orthographic projection of the first voltage supply line VDD on the substrate substrate at least partially overlaps with the orthographic projection of the plurality of binding pins BPS on the substrate substrate. In some embodiments, the orthographic projection of the second voltage supply line VSS on the substrate substrate at least partially overlaps with the orthographic projection of the plurality of binding pins BPS on the substrate substrate. In one example, Figure 5 Show Figure 4 The first sub-area PA1 of the peripheral area represented in FIG.

[0065] Figure 6 Schematic diagram showing the structure of a display device in some embodiments of the present disclosure. Figure 6 In some embodiments, the display device includes a plurality of touch signal lines TSL located in the peripheral area PA. The plurality of touch signal lines TSL are connected to touch electrodes located in the display area (eg, touch electrodes located in the first touch layer ML1 or the second touch layer ML2), and are connected to a plurality of binding pins.

[0066] Reference Figure 6, the peripheral area PA of the display device includes a binding pin area BPR having a plurality of binding pins BPS. The plurality of binding pins BPS are connected to a plurality of touch signal lines TSL in the peripheral area PA. The plurality of binding pins BPS are configured to be bound to a touch integrated circuit or a flexible printed circuit. In some embodiments, the peripheral area PA of the display device also includes at least one of a first signal line layer SL1 located on the substrate BS and a second signal line layer SL2 located on a side of the first signal line layer SL1 away from the substrate BS. The second signal line layer SL2 is located on a side of the plurality of binding pins BPS close to the substrate BS. In some embodiments, electrodes in the second signal line layer SL2 and / or electrodes in the first signal line layer SL1 are connected to one or more binding pins of the plurality of binding pins BPS and serve as relay electrodes for connecting one or more binding pins to signal lines.

[0067] Reference Figure 3 and Figure 6 In some embodiments, the display device is a flexible display device. In order to achieve enhanced flexibility in the display device, some insulating layers in the display device are made of polymeric organic materials. For example, referring to Figure 3 and Figure 6 In some embodiments, the touch insulating layer TI and the overcoat layer OC are made of a polymerized flexible organic material. When the touch insulating layer TI and the overcoat layer OC are made of a polymerized flexible organic material, they are not present in the bonding pin region BPR.

[0068] Reference Figure 3 In some embodiments, the display device is a color filter on encapsulation (COE) display device, wherein the color filter CF and the black matrix BM are directly formed on the cover layer OC of the display device located in the display area. Since there is no touch insulating layer TI and the cover layer OC in the binding pin region BPR, the plurality of binding pins BPS are at least partially exposed to the alkaline developing solution used in the process of forming at least one of the color filter CF and the black matrix BM. In particular, the edges of the plurality of binding pins BPS are susceptible to undercut erosion caused by the alkaline developing solution. Figure 7 Figure 1 shows undercut erosion occurring at the edge of a bonding pin. The undercut erosion causes the effective width of the bonding pin to be reduced, and when the bonding pin is bonded to an integrated circuit or a flexible printed circuit, a defective black spot problem occurs.

[0069] The inventors of the present disclosure have discovered that the display device according to the present disclosure avoids the above-mentioned problems. FIG. 8A to FIG. 8G The process of manufacturing a display device according to some embodiments of the present disclosure is shown. Fig. 8A, a plurality of light emitting elements LE are formed in the display area DA of the display device, and an encapsulation layer EN is formed on the side of the plurality of light emitting elements LE away from the pixel driving circuit substrate PCS. In the binding pin area BPR of the peripheral area PA, a first signal line layer SL1 is formed on the base substrate BS, a passivation layer PVX is formed on the side of the first signal line layer SL1 away from the base substrate BS, a second signal line layer SL2 is formed on the side of the passivation layer PVX away from the base substrate BS, a first planarization layer PLN1 is formed on the side of the second signal line layer SL2 away from the base substrate BS, and a plurality of binding pins BPS are formed on the side of the first planarization layer PLN1 away from the base substrate BS. In this step, the plurality of binding pins BPS are not protected, and the surfaces of the plurality of binding pins BPS are exposed.

[0070] In one example, a plurality of binding pins BPS and a conductive component located on the encapsulation layer EN or the second planarization layer PLN2 are located on the same layer. As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when a plurality of binding pins BPS and a conductive component located on the encapsulation layer EN are formed due to one or more steps of the same patterning process performed in the same material layer, they are located on the same layer. In another example, by simultaneously performing the steps of forming a plurality of binding pins BPS and forming the conductive component located on the encapsulation layer EN, a plurality of binding pins BPS and a conductive component located on the encapsulation layer EN can be formed on the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0071] In another example, the plurality of bonding pins BPS and the anode of the light emitting element are located at the same layer.

[0072] Reference Figure 8B An inorganic insulating layer IOL is formed on a side of the encapsulation layer EN in the display area DA away from the base substrate BS, and on a side of the plurality of binding pins BPS in the binding pin area BPR in the peripheral area PA away from the base substrate BS. After the inorganic insulating layer IOL is formed, the plurality of binding pins BPS are protected by the inorganic insulating layer IOL to prevent corrosion in a subsequent manufacturing process.

[0073] In some embodiments, a first relative height between each of the plurality of binding pins BPS and the surface of the substrate BS in the binding pin region of the peripheral area PA is less than a second relative height between the inorganic insulating layer IOL and the surface of the same substrate extending from the peripheral area PA to the display area DA. The inventors of the present disclosure have found that by making the first relative height less than the second relative height, damage to the plurality of binding pins BPS by the mask during the manufacturing process can be avoided.

[0074] Reference Figure 8C In the display area DA, a buffer layer BUF is formed on a side of the inorganic insulating layer IOL away from the encapsulation layer EN.

[0075] Reference Fig.8D In the display area DA, a first touch layer ML1 is formed on a side of the buffer layer BUF away from the inorganic insulating layer IOL.

[0076] Reference Fig. 8E In the display area DA, a touch insulating layer TI is formed on a side of the first touch layer ML1 away from the buffer layer BUF, a second touch layer ML2 is formed on a side of the touch insulating layer TI away from the buffer layer BUF, and a cover layer OC is formed on a side of the second touch layer ML2 away from the touch insulating layer TI. Optionally, the buffer layer BUF, the touch insulating layer TI and the cover layer OC are made of polymeric organic materials.

[0077] Reference Fig.8F In the display area DA, a black matrix BM and a color film CF are formed on the side of the cover layer OC away from the touch insulating layer TI, and a planarization layer PLN is formed on the side of the black matrix BM and the color film CF away from the cover layer OC. In this process, as described above, an alkaline developing solution is used to pattern the black matrix BM and / or the color film CF. The plurality of binding pins BPS in the binding pin region BPR of the peripheral area PA are covered by the inorganic insulating layer IOL and are protected from the alkaline developing solution. Undercut erosion of the plurality of binding pins BPS can be avoided.

[0078] Reference Figure 8G After forming the black matrix BM and the color film CF, the inorganic insulating layer IOL in the binding pin region BPR of the peripheral area PA is at least partially removed, thereby exposing at least a portion of each of the plurality of binding pins BPS.

[0079] In some embodiments, the display device includes a display area and a peripheral area. In some embodiments, in the display area, the display device includes a pixel driving circuit substrate PCS, a plurality of light emitting elements LE located on the pixel driving circuit substrate PCS, an encapsulation layer EN located on a side of the plurality of light emitting elements LE away from the pixel driving circuit substrate PCS, an inorganic insulating layer IOL located on a side of the encapsulation layer EN away from the plurality of light emitting elements LE, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on a side of the first touch layer ML1 away from the buffer layer BUF, a second touch layer ML2 located on a side of the touch insulating layer TI away from the first touch layer ML1, a covering layer OC located on a side of the second touch layer ML2 away from the touch insulating layer TI, and a black matrix BM and a color film CF located on a side of the covering layer OC away from the second touch layer ML2.

[0080] In some embodiments, the thickness of at least two of the touch insulating layer TI, the inorganic insulating layer IOL, and the buffer layer BUF are different from each other. Optionally, the thickness of the touch insulating layer TI is greater than the thickness of the inorganic insulating layer IOL, and greater than the thickness of the buffer layer BUF. Optionally, the thickness of the buffer layer BUF is greater than the thickness of the inorganic insulating layer IOL.

[0081] In some embodiments, in the display area, the display device further includes a planarization layer PLN located on a side of the black matrix BM and the color film CF away from the cladding layer OC.

[0082] In some embodiments, the buffer layer BUF, the touch insulation layer TI and the overcoat layer OC are made of polymeric organic materials.

[0083] In some embodiments, in the binding pin area BPR of the peripheral area PA, the display device includes a substrate base BS, a first signal line layer SL1 located on the substrate base BS, a passivation layer PVX located on a side of the first signal line layer SL1 away from the substrate base BS, a second signal line layer SL2 located on a side of the passivation layer PVX away from the first signal line layer SL1, a first planarization layer PLN1 located on a side of the second signal line layer SL2 away from the passivation layer PVX, and a plurality of binding pins BPS located on a side of the first planarization layer PLN1 away from the second signal line layer SL2.

[0084] In some embodiments, the inorganic insulating layer is at least partially absent in the binding pin region BPR. Optionally, the inorganic insulating layer IOL does not exist at all in the binding pin region BPR. Optionally, the orthographic projection of the inorganic insulating layer IOL on the substrate substrate does not overlap with the orthographic projection of the multiple binding pins BPS on the substrate substrate at least in part (for example, at least 50% does not overlap, at least 60% does not overlap, at least 70% does not overlap, at least 80% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap). Optionally, the orthographic projection of the inorganic insulating layer IOL on the substrate substrate does not overlap with the orthographic projection of the multiple binding pins BPS on the substrate substrate at all. By having this fine structure, during the manufacturing process of the black matrix BM and the color film CF, the multiple binding pins BPS remain substantially intact, avoiding the undercut problem.

[0085] Fig. 9 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown. Fig.10 is a plan view of a portion of a display device located in a binding pin area according to some embodiments of the present disclosure. Fig. 9 and Fig.10 In some embodiments, the binding pin area BPR of the display device in the peripheral area PA includes a base substrate BS, a first signal line layer SL1 located on the base substrate BS, a passivation layer PVX located on a side of the first signal line layer SL1 away from the base substrate BS, a second signal line layer SL2 located on a side of the passivation layer PVX away from the first signal line layer SL1, a first planarization layer PLN1 located on a side of the second signal line layer SL2 away from the passivation layer PVX, and a plurality of binding pins BPS located on a side of the first planarization layer PLN1 away from the second signal line layer SL2.

[0086] In some embodiments, the display device includes a plurality of touch signal lines TSL at least partially located in the peripheral area PA. In some embodiments, in the peripheral area PA and outside the binding pin area BPR, the display device includes a substrate BS, a passivation layer PVX located on the substrate BS, a first planarization layer PLN1 located on a side of the passivation layer PVX away from the substrate BS, an inorganic insulating layer IOL located on a side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a touch insulating layer TI located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, and a plurality of touch signal lines TSL located on a side of the touch insulating layer TI away from the buffer layer BUF.

[0087] In some embodiments, in the display area DA, the display device includes a pixel driving circuit substrate PCS, a plurality of light emitting elements LE located on the pixel driving circuit substrate PCS, an encapsulation layer EN located on a side of the plurality of light emitting elements LE away from the pixel driving circuit substrate PCS, an inorganic insulating layer IOL located on a side of the encapsulation layer EN away from the plurality of light emitting elements LE, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on a side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on a side of the touch insulating layer TI away from the first touch layer ML1.

[0088] In some embodiments, a plurality of touch signal lines TSL are located in the second touch layer ML2.

[0089] In some embodiments, the orthographic projection of the inorganic insulating layer IOL on the base substrate BS at least partially overlaps with the orthographic projection of the plurality of binding pins BPS on the base substrate BS. In some embodiments, each of the plurality of touch signal lines TSL extends through the touch insulating layer TI, the buffer layer BUF, and the inorganic insulating layer IOL to be connected to a corresponding binding pin in the plurality of binding pins BPS. Optionally, the display device includes a first via v1. Each of the plurality of touch signal lines TSL is connected to a corresponding binding pin in the plurality of binding pins BPS through the first via v1. In one example, the first via v1 extends through the touch insulating layer TI, the buffer layer BUF, and the inorganic insulating layer IOL.

[0090] Fig.11A The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown. Fig.12 The structure of corresponding binding pins in a display device according to some embodiments of the present disclosure is shown. Fig.13 is a plan view of a portion of a display device located in a binding pin area according to some embodiments of the present disclosure. Fig.11A , Fig.12 and Fig.13In some embodiments, the binding pin area BPR of the display device in the peripheral area PA includes a base substrate BS, a first signal line layer SL1 located on the base substrate BS, a passivation layer PVX located on a side of the first signal line layer SL1 away from the base substrate BS, a second signal line layer SL2 located on a side of the passivation layer PVX away from the first signal line layer SL1, a first planarization layer PLN1 located on a side of the second signal line layer SL2 away from the passivation layer PVX, a plurality of binding pins BPS located on a side of the first planarization layer PLN1 away from the second signal line layer SL2, and a touch insulation layer TI located on a side of the plurality of binding pins BPS away from the first planarization layer PLN1.

[0091] In some embodiments, the display device includes a plurality of touch signal lines TSL at least partially located in the peripheral area PA. In some embodiments, in the peripheral area PA and outside the binding pin area BPR, the display device includes a substrate BS, a passivation layer PVX located on the substrate BS, a first planarization layer PLN1 located on a side of the passivation layer PVX away from the substrate BS, an inorganic insulating layer IOL located on a side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a touch insulating layer TI located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, and a plurality of touch signal lines TSL located on a side of the touch insulating layer TI away from the buffer layer BUF.

[0092] In some embodiments, in the display area DA, the display device includes a pixel driving circuit substrate PCS, a plurality of light emitting elements LE located on the pixel driving circuit substrate PCS, an encapsulation layer EN located on a side of the plurality of light emitting elements LE away from the pixel driving circuit substrate PCS, an inorganic insulating layer IOL located on a side of the encapsulation layer EN away from the plurality of light emitting elements LE, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on a side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on a side of the touch insulating layer TI away from the first touch layer ML1. In some embodiments, a plurality of touch signal lines TSL are located on the second touch layer ML2.

[0093] In some embodiments, the orthographic projection of the inorganic insulating layer IOL on the base substrate BS at least partially overlaps with the orthographic projection of the plurality of binding pins BPS on the base substrate BS. In some embodiments, each of the plurality of touch signal lines TSL extends through the touch insulating layer TI, the buffer layer BUF, and the inorganic insulating layer IOL to be connected to a corresponding binding pin in the plurality of binding pins BPS. Optionally, the display device includes a first via v1. Each of the plurality of touch signal lines TSL is connected to a corresponding binding pin in the plurality of binding pins BPS through the first via v1. In one example, the first via v1 extends through the touch insulating layer TI, the buffer layer BUF, and the inorganic insulating layer IOL.

[0094] In some embodiments, each of the plurality of binding pins BPS includes a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4. Optionally, the first edge E1 and the second edge E2 are opposite to each other. Optionally, the third edge E3 and the fourth edge E4 are opposite to each other. The first edge E1 and the second edge E2 are connected by the third edge E3 and by the fourth edge E4. The third edge E3 and the fourth edge E4 are connected by the first edge E1 and by the second edge E2. The first edge E1, the second edge E2, the third edge E3, and the fourth edge E4 surround a central portion CP of each binding pin.

[0095] In some embodiments, the orthographic projection of the touch insulation layer TI on the substrate BS substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the first edge E1 on the substrate BS, substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the second edge E2 on the substrate BS, substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the third edge E3 on the substrate BS, and substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95%, at least 99% coverage, or complete coverage) the orthographic projection of the fourth edge E4 on the substrate BS.

[0096] In some embodiments, the orthographic projection of the touch insulation layer TI on the substrate BS does not overlap at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%) with the orthographic projection of the central portion CP of each binding pin on the substrate BS.

[0097] Reference Fig.11A In a sub-region of the binding pin region BPR located on a side of the plurality of binding pins BPS away from the display area DA, there is no inorganic insulating layer IOL and no buffer layer BUF, and only a portion of the touch insulating layer TI exists.

[0098] Fig. 11B FIG. 4 shows the connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure. Fig. 11B , Fig.12 and Fig.13 In some embodiments, the touch insulating layer TI, the inorganic insulating layer IOL and the buffer layer BUF exist in a sub-region of the binding pin region BPR located on a side of the plurality of binding pins BPS away from the display area DA.

[0099] In some embodiments, the orthographic projection of the inorganic insulating layer IOL on the substrate BS substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the first edge E1 on the substrate BS, substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the second edge E2 on the substrate BS, substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the third edge E3 on the substrate BS, and substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95%, at least 99% coverage, or complete coverage) the orthographic projection of the third edge E4 on the substrate BS.

[0100] In some embodiments, the orthographic projection of the inorganic insulating layer IOL on the substrate BS does not overlap at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%) with the orthographic projection of the central portion CP of each binding pin on the substrate BS.

[0101] In some embodiments, the orthographic projection of the buffer layer BUF on the substrate BS substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the first edge E1 on the substrate BS, substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the second edge E2 on the substrate BS, substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the third edge E3 on the substrate BS, and substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95%, at least 99% coverage, or complete coverage) the orthographic projection of the fourth edge E4 on the substrate BS.

[0102] In some embodiments, the orthographic projection of the buffer layer BUF on the substrate substrate BS does not overlap at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%) with the orthographic projection of the central portion CP of each binding pin on the substrate substrate BS.

[0103] In some embodiments, reference Fig.11A , Fig. 11B , Fig.12 and Fig.13 , the array substrate includes a plurality of central portion vias CPV. Each of the plurality of central portion vias CPV extends at least through the touch insulating layer TI, exposing at least a portion of the central portion CP of the plurality of central portions. In some embodiments, the extension directions of the plurality of central portions are substantially parallel to each other. In some embodiments, the extension directions of the plurality of central portion vias CPV are substantially parallel to each other. As used herein, the term "substantially parallel" refers to an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, 0 degrees to about 30 degrees.

[0104] In some embodiments, the array substrate further includes a plurality of dummy binding pins DBPS and a plurality of dummy central portion vias DCPV. Each dummy central portion via in the plurality of dummy central portion vias DCPV extends at least through the touch insulating layer TI, thereby exposing at least a portion of the dummy central portion in the plurality of dummy central portions. Optionally, the extension direction of the plurality of binding pins BPS is substantially parallel to the extension direction of the plurality of dummy binding pins DBPS. Optionally, the extension direction of the plurality of central portion vias CPV is substantially parallel to the extension direction of the plurality of dummy central portion vias DCPV. In some embodiments, along the extension direction of each binding pin or the extension direction of each dummy binding pin, the length of each binding pin in the plurality of binding pins BPS is greater than the length of each dummy binding pin in the plurality of dummy binding pins DBPS. In some embodiments, along the extension direction of each central portion via or the extension direction of each dummy central portion via, the length of each central portion via in the plurality of central portion vias CPV is substantially the same as the length of each dummy central portion via in the plurality of dummy central portion vias DCPV.

[0105] Fig.14 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown. Fig.15 is a plan view of a portion of a display device located in a binding pin area according to some embodiments of the present disclosure. Fig.14 and Fig.15 as well as Fig.12In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the first edge E1 on the substrate BS at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%). In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the second edge E2 on the substrate BS at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%). In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the third edge E3 on the substrate BS at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%). In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the fourth edge E4 on the substrate BS at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%). In some embodiments, the orthographic projection of the touch insulation layer TI on the substrate BS does not overlap with the orthographic projection of the central portion CP on the substrate BS at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%).

[0106] In some embodiments, Fig.14 As shown, the edge Eti of the touch insulating layer TI located in the binding pin region BPR is spaced apart from the exposed surface of each binding pin by a first spacing distance sd1, and is spaced apart from the first via v1 by a second spacing distance sd2. Optionally, the second spacing distance sd2 is greater than the first spacing distance sd1.

[0107] In some embodiments, Fig.14 As shown, the display device includes: a plurality of touch signal lines TSL at least partially located in the peripheral area PA; and a plurality of first vias. Each of the plurality of touch signal lines TSL is connected to a corresponding binding pin in a plurality of binding pins BPS through a first via v1 in the plurality of first vias. Optionally, the exposed surface of the corresponding binding pin is spaced apart from the first via v1. Optionally, the orthographic projection of the exposed surface of each binding pin on the substrate substrate does not overlap with the orthographic projection of the portion of the corresponding touch signal line located in the first via v1 on the substrate substrate.

[0108] In some embodiments, Fig.15 As shown, a portion of the touch insulating layer TI located in the binding pin region BPR is spaced apart from a portion of the touch insulating layer TI located in the display area DA.

[0109] In an alternative embodiment, the portion of the touch insulating layer TI located in the binding pin region BPR is connected to the portion of the touch insulating layer TI located in the display area DA. Optionally, the portion of the touch insulating layer TI located in the binding pin region BPR and the portion of the touch insulating layer TI located in the display area DA are part of an integral structure.

[0110] In some embodiments, Fig.15 As shown, the portion of the touch insulating layer TI located in the binding pin region BPR at least partially surrounds the plurality of binding pins BPS.

[0111] In an alternative embodiment, the portion of the touch insulating layer TI located in the binding pin region BPR includes a plurality of teeth extending respectively into regions between adjacent binding pins of the plurality of binding pins BPS. In one example, the portion of the touch insulating layer TI located in the binding pin region BPR is comb-shaped.

[0112] In an alternative embodiment, a portion of the touch insulation layer TI located in the bonding pin region BPR has a thickness smaller than a thickness of a portion of the touch insulation layer TI located in the display area DA.

[0113] In an alternative embodiment, the array substrate further includes the following portion of the overcoat layer OC: the portion is located on a side of the portion of the touch insulating layer TI located in the binding pin region BPR away from the base substrate.

[0114] Fig.16 FIG. 4 shows the connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure. Fig.16 , in some embodiments, the first distance d1 is greater than or equal to the sum of the second distance d2 and the third distance d3. In some embodiments, the first distance d1 represents the minimum distance between the orthographic projection of the portion of the corresponding touch signal line located in the first via v1 on the substrate substrate and the orthographic projection of the position of a portion of the corresponding binding pin on the substrate substrate, at which position the surface of the portion changes from being covered by the insulating layer to being exposed. In one example, the insulating layer includes an inorganic insulating layer IOL, a buffer layer BUF, and a touch insulating layer TI. The second distance d2 is the minimum distance between the orthographic projection of the position of a portion of the corresponding binding pin (at which position the surface of the portion changes from being covered by the insulating layer to being exposed) on the substrate substrate and a position of the insulating layer (at which position the slope angle of the insulating layer covering the portion of the corresponding binding pin changes from a positive value to substantially zero) on the substrate substrate.

[0115] In some embodiments, the third distance d3 is greater than the maximum width of the first via v1. By making the third distance d3 greater than the maximum width of the first via v1, a safe distance between the first via and the exposed surface of the corresponding binding pin can be ensured.

[0116] In some embodiments, the third distance d3 represents the maximum process deviation of the display device. As used herein, the term "process deviation" refers to the difference between a component and its design requirements caused by various factors during the manufacturing process. Process deviation may be caused by factors such as materials, processing technology, equipment and environment.

[0117] In some embodiments, the insulating layer includes an inclined portion (corresponding to d2) and a non-inclined portion (corresponding to d3) between the exposed surface of the corresponding binding pin and the first via v1. Fig.16 In some embodiments, the width of the non-inclined portion is greater than the maximum width of the first via v1 along a direction from the exposed surface of the corresponding binding pin to the first via v1.

[0118] Fig.17 FIG. 4 shows the connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure. Fig.17 In some embodiments, the binding pin area BPR of the display device in the peripheral area PA includes a base substrate BS, a first signal line layer SL1 located on the base substrate BS, a passivation layer PVX located on a side of the first signal line layer SL1 away from the base substrate BS, a second signal line layer SL2 located on a side of the passivation layer PVX away from the first signal line layer SL1, a first planarization layer PLN1 located on a side of the second signal line layer SL2 away from the passivation layer PVX, and a plurality of binding pins BPS located on a side of the first planarization layer PLN1 away from the second signal line layer SL2.

[0119] In some embodiments, the display device includes a plurality of touch signal lines TSL at least partially located in the peripheral area PA. In some embodiments, each of the plurality of touch signal lines TSL includes a first portion P1 and a second portion P2 connected to each other. Optionally, the second portion P2 is connected to a corresponding binding pin in a plurality of binding pins BPS through the first portion P1. Optionally, the first portion P1 is located in the first touch layer ML1, and the second portion P2 is located in the second touch layer ML2.

[0120] In some embodiments, in the peripheral area PA and outside the binding pin area BPR, the display device includes a base substrate BS, a passivation layer PVX located on the base substrate BS, a first planarization layer PLN1 located on a side of the passivation layer PVX away from the base substrate BS, an inorganic insulating layer IOL located on a side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a first portion P1 of each touch signal line among a plurality of touch signal lines TSL located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on a side of the first portion P1 away from the buffer layer BUF, and a second portion of each touch signal line among the plurality of touch signal lines TSL located on a side of the touch insulating layer TI away from the first portion P1.

[0121] In some embodiments, in the display area DA, the display device includes a pixel driving circuit substrate PCS, a plurality of light emitting elements LE located on the pixel driving circuit substrate PCS, an encapsulation layer EN located on a side of the plurality of light emitting elements LE away from the pixel driving circuit substrate PCS, an inorganic insulating layer IOL located on a side of the encapsulation layer EN away from the plurality of light emitting elements LE, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on a side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on a side of the touch insulating layer TI away from the first touch layer ML1.

[0122] In some embodiments, the display device includes a second via hole v2. The second portion P2 is connected to the first portion P1 through the second via hole v2. In one example, the second via hole v2 extends through the touch insulating layer TI.

[0123] In some embodiments, the display device further includes a third via v3. The first portion P1 is connected to a corresponding binding pin among a plurality of binding pins BPS through the third via v3. In one example, the third via v3 extends through the buffer layer BUF and the inorganic insulating layer IOL. Optionally, the minimum distance between the exposed surface of the corresponding binding pin and the third via v3 is less than the minimum distance between the third via v3 and the second via v2. Optionally, the depth of the second via v2 is greater than the depth of the third via v3. Optionally, the thickness of the touch insulating layer TI is greater than the sum of the thicknesses of the inorganic insulating layer IOL and the buffer layer BUF.

[0124] In some embodiments, the orthographic projection of the inorganic insulating layer IOL on the base substrate BS at least partially overlaps with the orthographic projection of the plurality of binding pins BPS on the base substrate BS.

[0125] Fig.18 FIG. 4 shows the connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure. Fig.18 , the display device includes a plurality of touch signal lines TSL at least partially located in the peripheral area PA. In some embodiments, each of the plurality of touch signal lines TSL includes a first portion P1 and a second portion P2 connected to each other. Optionally, the second portion P2 is connected to a corresponding binding pin in a plurality of binding pins BPS through the first portion P1. Optionally, the first portion P1 is located in the first touch layer ML1, and the second portion P2 is located in the second touch layer ML2.

[0126] In some embodiments, the display device includes a second via hole v2. The second portion P2 is connected to the first portion P1 through the second via hole v2. In one example, the second via hole v2 extends through the touch insulating layer TI.

[0127] In some embodiments, the display device further includes a third via hole v3. The first portion P1 is connected to a corresponding binding pin among the plurality of binding pins BPS through the third via hole v3. In one example, the third via hole v3 extends through the buffer layer BUF and the inorganic insulating layer IOL.

[0128] In some embodiments, the display device further includes a fourth via hole v4. The first portion P1 is connected to a corresponding binding pin among the plurality of binding pins BPS through the fourth via hole v4. In one example, the fourth via hole v4 extends through the buffer layer BUF and the inorganic insulating layer IOL.

[0129] In some embodiments, reference Fig.18 , the fourth distance d4 is greater than the fifth distance d5, wherein the fourth distance d4 represents the minimum distance between the orthographic projection of the portion of the first portion P1 located in the third via hole v3 on the substrate substrate and the orthographic projection of the portion of the first portion P1 located in the fourth via hole v4 on the substrate substrate; the fifth distance d5 represents the minimum distance between the orthographic projection of the portion of the first portion P1 located in the third via hole v3 on the substrate substrate and the orthographic projection of a portion of the corresponding binding pin BPS on the substrate substrate, at which position the surface of the portion changes from being covered by the insulating layer to being exposed.

[0130] In some embodiments, reference Fig.18, the array substrate includes a binding pin via BPV, which at least extends through the touch insulation layer TI to expose the surface of the corresponding binding pin. Optionally, the array substrate also includes a connecting via CV extending at least through the first planarization layer PLN1, and the corresponding binding pin is connected to the second signal line layer SL2 through the connecting via CV. Optionally, the maximum width of the binding pin via BPV is greater than the maximum width of the connecting via CV. Optionally, the maximum width of the binding pin via BPV is greater than the maximum width of the third via v3. Optionally, the maximum width of the binding pin via BPV is greater than the maximum width of the fourth via v4. Optionally, the binding pin via BPV, the connecting via CV, the third via v3 and the fourth via v4 are located on the side of the contact interface between the encapsulation layer EN and the first planarization layer PLN1 away from the display area DA.

[0131] Fig.19 FIG. 4 shows the connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure. Fig.19 In some embodiments, each of the plurality of bonding pins BPS is in direct contact with the first planarization layer PLN1.

[0132] In some embodiments, the first planarization layer PLN1 is in direct contact with each binding pin in the first region R1 and is not in contact with each binding pin in the second region R2, wherein the second region R2 is adjacent to the first region R1. The surface of the first planarization layer PLN1 away from the substrate BS includes a first portion S1 that is in direct contact with each binding pin and a second portion S2 that is not in contact with each binding pin, and the first portion S1 and the second portion S2 are located on the same side of the first planarization layer PLN1. Relative to the same horizontal plane (for example, the surface of the passivation layer PVX located below the first planarization layer PLN1), the first relative height h1 is greater than the second relative height h2, wherein the first relative height h1 is the height of the first portion S1 relative to the same horizontal plane, and the second relative height h2 is the height of the second portion S2 relative to the same horizontal plane.

[0133] In one example, each binding pin has a thickness substantially the same as the thickness of a touch electrode or a touch signal line located in the first touch layer ML1. In another example, the thickness of the first portion P1 is substantially the same as the thickness of a touch electrode or a touch signal line located in the first touch layer ML1. As used herein, the term "substantially the same" means that the difference between two values ​​does not exceed 10% of a base value (e.g., one of the two values), such as no more than 8% of the base value, no more than 6%, no more than 4%, no more than 2%, no more than 1%, no more than 0.5%, no more than 0.1%, no more than 0.05%, and no more than 0.01%.

[0134] In an alternative example, each of the binding pins has a thickness different from the thickness of the touch electrodes or touch signal lines located in the first touch layer ML1 .

[0135] In another example, each binding pin has a thickness substantially the same as that of a touch electrode or a touch signal line located in the second touch layer ML2. In another example, the thickness of the second portion P2 is substantially the same as that of a touch electrode or a touch signal line located in the second touch layer ML2.

[0136] In an alternative example, each of the binding pins has a thickness different from the thickness of the touch electrodes or touch signal lines located in the second touch layer ML2 .

[0137] Various suitable embodiments can be practiced according to the present disclosure. FIG. 20A to FIG. 20F The process of manufacturing a display device according to some embodiments of the present disclosure is shown. Fig. 20A A plurality of light emitting elements LE are formed in the display area DA of the display device, and an encapsulation layer EN is formed on a side of the plurality of light emitting elements LE away from the pixel driving circuit substrate PCS. In the binding pin area BPR of the peripheral area PA, a first signal line layer SL1 is formed on the base substrate BS, a passivation layer PVX is formed on a side of the first signal line layer SL1 away from the base substrate BS, and a plurality of binding pins BPS are formed on a side of the passivation layer PVX away from the base substrate BS. A plurality of binding pins BPS are formed in the second signal line layer SL2.

[0138] In some embodiments, an inorganic insulating layer IOL is formed on a side of the encapsulation layer EN in the display area DA away from the base substrate BS, and on a side of the plurality of binding pins BPS in the binding pin area BPR in the peripheral area PA away from the base substrate BS. After the inorganic insulating layer IOL is formed, the plurality of binding pins BPS are protected by the inorganic insulating layer IOL to prevent corrosion in subsequent manufacturing processes.

[0139] Reference Fig. 20B In the display area DA, a buffer layer BUF is formed on a side of the inorganic insulating layer IOL away from the encapsulation layer EN.

[0140] Reference Fig. 20C In the display area DA, a first touch layer ML1 is formed on a side of the buffer layer BUF away from the inorganic insulating layer IOL.

[0141] Reference Fig.20DIn the display area DA, a touch insulating layer TI is formed on a side of the first touch layer ML1 away from the buffer layer BUF, a second touch layer ML2 is formed on a side of the touch insulating layer TI away from the buffer layer BUF, and a cover layer OC is formed on a side of the second touch layer ML2 away from the touch insulating layer TI. Optionally, the buffer layer BUF, the touch insulating layer TI and the cover layer OC are made of polymeric organic materials.

[0142] Reference Fig.20E In the display area DA, a black matrix BM and a color film CF are formed on the side of the cover layer OC away from the touch insulating layer TI, and a planarization layer PLN is formed on the side of the black matrix BM and the color film CF away from the cover layer OC. In this process, as described above, an alkaline developing solution is used to pattern the black matrix BM and / or the color film CF. The plurality of binding pins BPS in the binding pin region BPR of the peripheral area PA are covered by the inorganic insulating layer IOL and are protected from the alkaline developing solution. Undercut erosion of the plurality of binding pins BPS can be avoided.

[0143] Reference Fig.20F After forming the black matrix BM and the color film CF, the inorganic insulating layer IOL in the binding pin region BPR of the peripheral area PA is at least partially removed, thereby exposing at least a portion of each of the plurality of binding pins BPS.

[0144] In some embodiments, the display device includes a display area and a peripheral area. In some embodiments, in the display area, the display device includes a pixel driving circuit substrate PCS, a plurality of light emitting elements LE located on the pixel driving circuit substrate PCS, an encapsulation layer EN located on a side of the plurality of light emitting elements LE away from the pixel driving circuit substrate PCS, an inorganic insulating layer IOL located on a side of the encapsulation layer EN away from the plurality of light emitting elements LE, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on a side of the first touch layer ML1 away from the buffer layer BUF, a second touch layer ML2 located on a side of the touch insulating layer TI away from the first touch layer ML1, a covering layer OC located on a side of the second touch layer ML2 away from the touch insulating layer TI, and a black matrix BM and a color film CF located on a side of the covering layer OC away from the second touch layer ML2.

[0145] In some embodiments, in the display area, the display device further includes a planarization layer PLN located on a side of the black matrix BM and the color film CF away from the cladding layer OC.

[0146] In some embodiments, the buffer layer BUF, the touch insulation layer TI and the overcoat layer OC are made of polymeric organic materials.

[0147] In some embodiments, in the binding pin area BPR of the peripheral area PA, the display device includes a base substrate BS, a first signal line layer SL1 located on the base substrate BS, a passivation layer PVX located on a side of the first signal line layer SL1 away from the base substrate BS, a plurality of binding pins BPS in a second signal line layer SL2 located on a side of the passivation layer PVX away from the first signal line layer SL1, and a first planarization layer PLN1 located on a side of the plurality of binding pins BPS away from the passivation layer PVX.

[0148] In some embodiments, the inorganic insulating layer is at least partially absent in the binding pin region BPR. Optionally, the inorganic insulating layer IOL does not exist at all in the binding pin region BPR. Optionally, the orthographic projection of the inorganic insulating layer IOL on the substrate substrate does not overlap with the orthographic projection of the multiple binding pins BPS on the substrate substrate at least in part (for example, at least 50% does not overlap, at least 60% does not overlap, at least 70% does not overlap, at least 80% does not overlap, at least 90% does not overlap, at least 95% does not overlap, at least 99% does not overlap). Optionally, the orthographic projection of the inorganic insulating layer IOL on the substrate substrate does not overlap with the orthographic projection of the multiple binding pins BPS on the substrate substrate at all. By having this fine structure, during the manufacturing process of the black matrix BM and the color film CF, the multiple binding pins BPS remain substantially intact, avoiding the undercut problem.

[0149] Fig.21 FIG. 4 shows the connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure. Fig.21 In some embodiments, the binding pin area BPR of the display device in the peripheral area PA includes a substrate substrate BS, a first signal line layer SL1 located on the substrate substrate BS, a passivation layer PVX located on a side of the first signal line layer SL1 away from the substrate substrate BS, a plurality of binding pins BPS in a second signal line layer SL2 located on a side of the passivation layer PVX away from the first signal line layer SL1, and a first planarization layer PLN1 located on a side of the second signal line layer SL2 away from the passivation layer PVX.

[0150] In some embodiments, the display device includes a plurality of touch signal lines TSL at least partially located in the peripheral area PA. In some embodiments, in the peripheral area PA and outside the binding pin area BPR, the display device includes a substrate BS, a passivation layer PVX located on the substrate BS, a first planarization layer PLN1 located on a side of the passivation layer PVX away from the substrate BS, an inorganic insulating layer IOL located on a side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a touch insulating layer TI located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, and a plurality of touch signal lines TSL located on a side of the touch insulating layer TI away from the buffer layer BUF.

[0151] In some embodiments, in the display area DA, the display device includes a pixel driving circuit substrate PCS, a plurality of light emitting elements LE located on the pixel driving circuit substrate PCS, an encapsulation layer EN located on a side of the plurality of light emitting elements LE away from the pixel driving circuit substrate PCS, an inorganic insulating layer IOL located on a side of the encapsulation layer EN away from the plurality of light emitting elements LE, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on a side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on a side of the touch insulating layer TI away from the first touch layer ML1.

[0152] In some embodiments, a plurality of touch signal lines TSL are located in the second touch layer ML2.

[0153] In some embodiments, the orthographic projection of the inorganic insulating layer IOL on the base substrate BS at least partially overlaps with the orthographic projection of the plurality of binding pins BPS on the base substrate BS. In some embodiments, each of the plurality of touch signal lines TSL extends through the touch insulating layer TI, the buffer layer BUF, the inorganic insulating layer IOL and the first planarization layer PLN1 to be connected to a corresponding binding pin in the plurality of binding pins BPS. Optionally, the display device includes a fifth via v5. Each of the plurality of touch signal lines TSL is connected to a corresponding binding pin in the plurality of binding pins BPS through the fifth via v5. In one example, the fifth via v5 extends through the touch insulating layer TI, the buffer layer BUF, the inorganic insulating layer IOL and the first planarization layer PLN1.

[0154] Fig. 22 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown. Fig.23The structure of corresponding binding pins in a display device according to some embodiments of the present disclosure is shown. Fig.24 is a plan view of a portion of a display device located in a binding pin area according to some embodiments of the present disclosure. Figure 22 to Figure 24 In some embodiments, the binding pin area BPR of the display device in the peripheral area PA includes a base substrate BS, a first signal line layer SL1 located on the base substrate BS, a passivation layer PVX located on a side of the first signal line layer SL1 away from the base substrate BS, a plurality of binding pins BPS in the second signal line layer SL2 located on a side of the passivation layer PVX away from the first signal line layer SL1, a first planarization layer PLN1 located on a side of the second signal line layer SL2 away from the passivation layer PVX, and a touch insulation layer TI located on a side of the first planarization layer PLN1 away from the plurality of binding pins BPS.

[0155] In some embodiments, the display device includes a plurality of touch signal lines TSL at least partially located in the peripheral area PA. In some embodiments, in the peripheral area PA and outside the binding pin area BPR, the display device includes a substrate BS, a passivation layer PVX located on the substrate BS, a first planarization layer PLN1 located on a side of the passivation layer PVX away from the substrate BS, an inorganic insulating layer IOL located on a side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a touch insulating layer TI located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, and a plurality of touch signal lines TSL located on a side of the touch insulating layer TI away from the buffer layer BUF.

[0156] In some embodiments, in the display area DA, the display device includes a pixel driving circuit substrate PCS, a plurality of light emitting elements LE located on the pixel driving circuit substrate PCS, an encapsulation layer EN located on a side of the plurality of light emitting elements LE away from the pixel driving circuit substrate PCS, an inorganic insulating layer IOL located on a side of the encapsulation layer EN away from the plurality of light emitting elements LE, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on a side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on a side of the touch insulating layer TI away from the first touch layer ML1. In some embodiments, a plurality of touch signal lines TSL are located on the second touch layer ML2.

[0157] In some embodiments, the orthographic projection of the inorganic insulating layer IOL on the base substrate BS at least partially overlaps with the orthographic projection of the plurality of binding pins BPS on the base substrate BS. In some embodiments, each of the plurality of touch signal lines TSL extends through the touch insulating layer TI, the buffer layer BUF, the inorganic insulating layer IOL and the first planarization layer PLN1 to be connected to a corresponding binding pin in the plurality of binding pins BPS. Optionally, the display device includes a fifth via v5. Each of the plurality of touch signal lines TSL is connected to a corresponding binding pin in the plurality of binding pins BPS through the fifth via v5. In one example, the fifth via v5 extends through the touch insulating layer TI, the buffer layer BUF, the inorganic insulating layer IOL and the first planarization layer PLN1.

[0158] In some embodiments, each of the plurality of binding pins BPS includes a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4. Optionally, the first edge E1 and the second edge E2 are opposite to each other. Optionally, the third edge E3 and the fourth edge E4 are opposite to each other. The first edge E1 and the second edge E2 are connected by the third edge E3 and by the fourth edge E4. The third edge E3 and the fourth edge E4 are connected by the first edge E1 and by the second edge E2. The first edge E1, the second edge E2, the third edge E3, and the fourth edge E4 surround a central portion CP of each binding pin.

[0159] In some embodiments, the orthographic projection of the touch insulation layer TI on the substrate BS substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the first edge E1 on the substrate BS, substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the second edge E2 on the substrate BS, substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or complete coverage) the orthographic projection of the third edge E3 on the substrate BS, and substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95%, at least 99% coverage, or complete coverage) the orthographic projection of the fourth edge E4 on the substrate BS.

[0160] In some embodiments, the orthographic projection of the touch insulation layer TI on the substrate BS does not overlap at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%) with the orthographic projection of the central portion CP of each binding pin on the substrate BS.

[0161] Fig.25 The connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure is shown. Fig.26 is a plan view of a portion of a display device located in a binding pin area according to some embodiments of the present disclosure. Fig.25 and Fig.26 as well as Fig.23 In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the first edge E1 on the substrate BS at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%). In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the second edge E2 on the substrate BS at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%). In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the third edge E3 on the substrate BS at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%). In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the fourth edge E4 on the substrate BS at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%). In some embodiments, the orthographic projection of the touch insulation layer TI on the substrate BS does not overlap with the orthographic projection of the central portion CP on the substrate BS at least partially (for example, at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 95%).

[0162] Fig. 27 FIG. 4 shows the connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure. Fig. 27, in some embodiments, the first distance d1 is greater than or equal to the sum of the second distance d2 and the third distance d3. In some embodiments, the first distance d1 represents the minimum distance between the orthographic projection of the portion of the corresponding touch signal line located in the fifth via v5 on the substrate substrate and the orthographic projection of the position of a portion of the corresponding binding pin on the substrate substrate, at which position the surface of the portion changes from being covered by the insulating layer to being exposed. In one example, the insulating layer includes an inorganic insulating layer IOL, a buffer layer BUF, a touch insulating layer TI, and a first planarization layer PLN1. The second distance d2 is the minimum distance between the orthographic projection of the position of a portion of the corresponding binding pin (at which position the surface of the portion changes from being covered by the insulating layer to being exposed) on the substrate substrate and the orthographic projection of a position of the corresponding binding pin (at which position the slope angle of the insulating layer covering the portion of the corresponding binding pin changes from a positive value to substantially zero) on the substrate substrate. The third distance d3 represents the maximum process deviation of the display device. As used herein, the term "process deviation" refers to the difference between a component and its design requirements caused by various factors during the manufacturing process. Process deviations may be caused by factors such as materials, processing technology, equipment, and environment.

[0163] Fig.28 FIG. 4 shows the connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure. Fig.28 In some embodiments, the binding pin area BPR of the display device in the peripheral area PA includes a substrate substrate BS, a first signal line layer SL1 located on the substrate substrate BS, a passivation layer PVX located on a side of the first signal line layer SL1 away from the substrate substrate BS, a plurality of binding pins BPS in a second signal line layer SL2 located on a side of the passivation layer PVX away from the first signal line layer SL1, and a first planarization layer PLN1 located on a side of the second signal line layer SL2 away from the passivation layer PVX.

[0164] In some embodiments, the display device includes a plurality of touch signal lines TSL at least partially located in the peripheral area PA. In some embodiments, each of the plurality of touch signal lines TSL includes a first portion P1 and a second portion P2 connected to each other. Optionally, the second portion P2 is connected to a corresponding binding pin in a plurality of binding pins BPS through the first portion P1. Optionally, the first portion P1 is located in the first touch layer ML1, and the second portion P2 is located in the second touch layer ML2.

[0165] In some embodiments, in the peripheral area PA and outside the binding pin area BPR, the display device includes a base substrate BS, a passivation layer PVX located on the base substrate BS, a first planarization layer PLN1 located on a side of the passivation layer PVX away from the base substrate BS, an inorganic insulating layer IOL located on a side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a first portion P1 of each touch signal line among a plurality of touch signal lines TSL located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on a side of the first portion P1 away from the buffer layer BUF, and a second portion of each touch signal line among the plurality of touch signal lines TSL located on a side of the touch insulating layer TI away from the first portion P1.

[0166] In some embodiments, in the display area DA, the display device includes a pixel driving circuit substrate PCS, a plurality of light emitting elements LE located on the pixel driving circuit substrate PCS, an encapsulation layer EN located on a side of the plurality of light emitting elements LE away from the pixel driving circuit substrate PCS, an inorganic insulating layer IOL located on a side of the encapsulation layer EN away from the plurality of light emitting elements LE, a buffer layer BUF located on a side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on a side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on a side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on a side of the touch insulating layer TI away from the first touch layer ML1.

[0167] In some embodiments, the display device includes a sixth via hole v6. The second portion P2 is connected to the first portion P1 through the sixth via hole v6. In one example, the sixth via hole v6 extends through the touch insulating layer TI.

[0168] In some embodiments, the display device further includes a seventh via v7. The first portion P1 is connected to a corresponding binding pin of the plurality of binding pins BPS through the seventh via v7. In one example, the seventh via v7 extends through the buffer layer BUF, the inorganic insulating layer IOL, and the first planarization layer PLN1.

[0169] In some embodiments, the orthographic projection of the inorganic insulating layer IOL on the base substrate BS at least partially overlaps with the orthographic projection of the plurality of binding pins BPS on the base substrate BS.

[0170] Fig.29 FIG. 4 shows the connection between the binding pins and the touch signal lines in the display device according to some embodiments of the present disclosure. Fig.29, the display device includes a plurality of touch signal lines TSL at least partially located in the peripheral area PA. In some embodiments, each of the plurality of touch signal lines TSL includes a first portion P1 and a second portion P2 connected to each other. Optionally, the second portion P2 is connected to a corresponding binding pin in a plurality of binding pins BPS through the first portion P1. Optionally, the first portion P1 is located in the first touch layer ML1, and the second portion P2 is located in the second touch layer ML2.

[0171] In some embodiments, the display device includes a sixth via hole v6. The second portion P2 is connected to the first portion P1 through the sixth via hole v6. In one example, the sixth via hole v6 extends through the touch insulating layer TI.

[0172] In some embodiments, the display device further includes a seventh via v7. The first portion P1 is connected to a corresponding binding pin among the plurality of binding pins BPS through the seventh via v7. In one example, the third via v3 extends through the buffer layer BUF, the inorganic insulating layer IOL and the first planarization layer PLN1.

[0173] In some embodiments, the display device further includes an eighth via v8. The first portion P1 is connected to a corresponding binding pin among the plurality of binding pins BPS through the eighth via v8. In one example, the eighth via v8 extends through the buffer layer BUF, the inorganic insulating layer IOL, and the first planarization layer PLN1.

[0174] In some embodiments, reference Fig.29 , the fourth distance d4 is greater than the fifth distance d5, wherein the fourth distance d4 represents the minimum distance between the orthographic projection of the portion of the first portion P1 located in the seventh hole v7 on the substrate substrate and the orthographic projection of the portion of the first portion P1 located in the eighth hole v8 on the substrate substrate; the fifth distance d5 represents the minimum distance between the orthographic projection of the portion of the first portion P1 located in the seventh via v7 on the substrate substrate and the orthographic projection of a portion of the corresponding binding pin BPS on the substrate substrate, at which position the surface of the portion changes from being covered by the insulating layer to being exposed.

[0175] On the other hand, the present disclosure also provides a method for manufacturing a display device having a display area and a peripheral area. The peripheral area includes a binding pin area. In some embodiments, the method includes: forming a pixel drive circuit substrate in the display area, forming a plurality of light-emitting elements on the pixel drive circuit substrate, and forming an encapsulation layer on a side of the plurality of light-emitting elements away from the pixel drive circuit substrate.

[0176] In some embodiments, the method further includes: forming a plurality of binding pins in a binding pin area of ​​the peripheral area.

[0177] In some embodiments, the method further includes: forming an inorganic insulating layer on a side of the encapsulation layer in the display area away from the base substrate and on a side of the plurality of binding pins in the binding pin area in the peripheral area away from the base substrate.

[0178] In some embodiments, the method further comprises: in the display area, forming a buffer layer on a side of the inorganic insulating layer away from the encapsulation layer, forming a first touch layer on a side of the buffer layer away from the inorganic insulating layer, forming a touch insulating layer on a side of the first touch layer away from the buffer layer, forming a second touch layer on a side of the touch insulating layer away from the buffer layer, forming a coating layer on a side of the second touch layer away from the touch insulating layer, and forming a black matrix and a color film on a side of the coating layer away from the touch insulating layer. Optionally, a polymerized organic material is used to form the buffer layer, the touch insulating layer, and the coating layer.

[0179] In some embodiments, the method further includes: at least partially removing a portion of the inorganic insulating layer located in the bonding pin region to expose at least a portion of each of the plurality of bonding pins.

[0180] In some embodiments, the method also includes: forming a first signal line layer on the substrate in the binding pin area; forming a passivation layer on a side of the first signal line layer away from the substrate; forming a second signal line layer on a side of the passivation layer away from the first signal line layer; forming a first planarization layer on a side of the second signal line layer away from the passivation layer; and forming a plurality of binding pins on a side of the first planarization layer away from the second signal line layer.

[0181] In some embodiments, the method also includes: forming a first signal line layer on the substrate in the binding pin area; forming a passivation layer on a side of the first signal line layer away from the substrate; forming a plurality of binding pins in a second signal line layer on a side of the passivation layer away from the first signal line layer; and forming a first planarization layer on a side of the second signal line layer away from the passivation layer.

[0182] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. A display device comprising a display area and a peripheral area; in, In the display area, the display device includes a pixel driving circuit substrate, a plurality of light emitting elements located on the pixel driving circuit substrate, and a packaging layer located on a side of the plurality of light emitting elements away from the pixel driving circuit substrate; and an inorganic insulating layer located on a side of the encapsulation layer away from the plurality of light emitting elements; In the binding pin region of the peripheral region, the display device comprises: a base substrate; a plurality of binding pins located on the base substrate; and An orthographic projection of the inorganic insulating layer on the base substrate and an orthographic projection of the plurality of binding pins on the base substrate at least partially do not overlap.

2. The display device according to claim 1, further comprising in the display area: a buffer layer, which is located on a side of the inorganic insulating layer away from the encapsulation layer; A first touch layer, which is located on a side of the buffer layer away from the inorganic insulating layer; a touch insulating layer, located on a side of the first touch layer away from the buffer layer; A second touch layer located on a side of the touch insulating layer away from the first touch layer; and A covering layer, which is located on a side of the second touch layer away from the touch insulating layer; Wherein, the buffer layer, the touch insulating layer and the coating layer are made of polymerized organic materials.

3. The display device according to claim 2, further comprising, in the display area, a black matrix and a color film located on a side of the cover layer away from the second touch layer; in, The black matrix and the color film are in direct contact with the coating layer.

4. The display device according to any one of claims 1 to 3, wherein: The orthographic projection of the inorganic insulating layer on the base substrate does not overlap at all with the orthographic projection of the plurality of binding pins on the base substrate.

5. The display device according to claim 1, further comprising a plurality of touch signal lines at least partially located in the peripheral area; in, Each of the plurality of touch signal lines at least extends through the touch insulating layer, the buffer layer and the inorganic insulating layer to be connected to a corresponding binding pin of the plurality of binding pins; Each of the touch signal lines is at least partially located in the second touch layer.

6. The display device according to claim 5, wherein: Each of the binding pins includes a first edge, a second edge, a third edge and a fourth edge; The orthographic projection of the touch insulating layer on the base substrate substantially covers the orthographic projection of the first edge on the base substrate, substantially covers the orthographic projection of the second edge on the base substrate, substantially covers the orthographic projection of the third edge on the base substrate, and substantially covers the orthographic projection of the fourth edge on the base substrate; The first edge, the second edge, the third edge and the fourth edge surround a central portion of each of the binding pins; as well as The orthographic projection of the touch insulating layer on the base substrate and the orthographic projection of the central portion of each binding pin on the base substrate at least partially do not overlap.

7. The display device according to claim 5, wherein: Each of the binding pins includes a first edge, a second edge, a third edge and a fourth edge; The orthographic projection of the touch insulating layer on the base substrate at least partially does not overlap with the orthographic projection of the first edge on the base substrate, at least partially does not overlap with the orthographic projection of the second edge on the base substrate, at least partially does not overlap with the orthographic projection of the third edge on the base substrate, and at least partially does not overlap with the orthographic projection of the fourth edge on the base substrate; The first edge, the second edge, the third edge and the fourth edge surround a central portion of each of the binding pins; as well as The orthographic projection of the touch insulating layer on the base substrate and the orthographic projection of the central portion of each binding pin on the base substrate at least partially do not overlap.

8. The display device according to claim 5, further comprising a first via hole; in, Each of the touch signal lines is connected to the corresponding binding pin through the first via hole; The insulating layer between the exposed surface of the corresponding binding pin and the first via hole includes an inclined portion and a non-inclined portion; Along a direction from an exposed surface of the corresponding binding pin to the first via hole, a width of the non-inclined portion is greater than a maximum width of the first via hole.

9. The display device according to claim 5, further comprising a second via hole and a third via hole; in, Each of the touch signal lines includes a first portion located in the first touch layer and a second portion located in the second touch layer; the second portion is connected to the first portion through the second via; and The first portion is connected to the corresponding binding pin through the third via.

10. The display device according to claim 5, further comprising a second via hole, a third via hole and a fourth via hole; in, Each of the touch signal lines includes a first portion located in the first touch layer and a second portion located in the second touch layer; the second portion is connected to the first portion through the second via; The first portion is connected to the corresponding binding pin through the third via hole and the fourth via hole, respectively.

11. The display device according to claim 10, wherein: The fourth distance is greater than the fifth distance; The fourth distance represents a minimum distance between an orthographic projection of a portion of the first portion located in the third via hole on the substrate and an orthographic projection of a portion of the first portion located in the fourth via hole on the substrate; as well as The fifth distance represents a minimum distance between an orthographic projection of a portion of the first portion located in the third via on the substrate substrate and an orthographic projection of a portion of the corresponding binding pin on the substrate substrate, at which position the surface of the portion transitions from being covered by the insulating layer to being exposed.

12. The display device according to claim 5, further comprising a first via hole; in, Each of the touch signal lines is connected to the corresponding binding pin through the first via hole; and The first via hole extends through the touch insulating layer, the buffer layer and the inorganic insulating layer.

13. The display device according to claim 5, further comprising a fifth via hole; in, Each of the touch signal lines is connected to the corresponding binding pin through the fifth via hole; and The fifth via hole extends through the touch insulating layer, the buffer layer, the inorganic insulating layer and the first planarization layer.

14. The display device according to any one of claims 1 to 13, further comprising, in the peripheral region, a first voltage supply line configured to provide a first voltage supply signal to the display region and a second voltage supply line configured to provide a second voltage supply signal to the display region; in, An orthographic projection of at least one of the first voltage supply line or the second voltage supply line on the base substrate at least partially overlaps with an orthographic projection of the plurality of bonding pins on the base substrate.

15. The display device according to any one of claims 1 to 3, wherein: In the binding pin area of ​​the peripheral area, the display device includes: A first signal line layer, which is located on the substrate; A passivation layer, located on a side of the first signal line layer away from the substrate; A second signal line layer, which is located on a side of the passivation layer away from the first signal line layer; A first planarization layer located on a side of the second signal line layer away from the passivation layer; and The plurality of binding pins are located on a side of the first planarization layer away from the second signal line layer.

16. The display device according to claim 15, wherein: Each of the plurality of binding pins is in direct contact with the first planarization layer; The first planarization layer is in direct contact with each of the binding pins in a first region and is not in contact with each of the binding pins in a second region, wherein the second region is adjacent to the first region; The surface of the first planarization layer away from the base substrate comprises a first portion directly in contact with each binding pin and a second portion not in contact with each binding pin, wherein the first portion and the second portion are located on the same side of the first planarization layer; Relative to the same horizontal plane, the first relative height is greater than the second relative height; The first relative height is the height of the first portion relative to the same horizontal plane; and The second relative height is a height of the second portion relative to the same horizontal plane.

17. The display device according to any one of claims 1 to 3, wherein: In the binding pin area of ​​the peripheral area, the display device includes: A first signal line layer, which is located on the substrate; A passivation layer, located on a side of the first signal line layer away from the substrate; The plurality of binding pins are located in a second signal line layer, the second signal line layer is located on a side of the passivation layer away from the first signal line layer; and The first planarization layer is located on a side of the second signal line layer away from the passivation layer.

18. A method for manufacturing a display device, the display device having a display area and a peripheral area, the peripheral area including a binding pin area; in, The method comprises: In the display area, a pixel driving circuit substrate is formed, a plurality of light emitting elements are formed on the pixel driving circuit substrate, and a packaging layer is formed on a side of the plurality of light emitting elements away from the pixel driving circuit substrate; In the binding pin area, a plurality of binding pins are formed; forming an inorganic insulating layer on a side of the encapsulation layer in the display area away from the base substrate and on a side of the plurality of binding pins in the binding pin area in the peripheral area away from the base substrate; After forming the inorganic insulating layer, forming a black matrix and a color film on a side of the plurality of light emitting elements away from the pixel driving circuit substrate in the display region; and After forming the black matrix and the color film, the portion of the inorganic insulating layer located in the binding pin area is at least partially removed to expose at least a portion of each of the plurality of binding pins.

19. The method according to claim 18, further comprising, in the binding pin area: forming a first signal line layer on the base substrate; forming a passivation layer on a side of the first signal line layer away from the base substrate; forming a second signal line layer on a side of the passivation layer away from the first signal line layer; forming a first planarization layer on a side of the second signal line layer away from the passivation layer; as well as The plurality of binding pins are formed on a side of the first planarization layer away from the second signal line layer.

20. A display device comprising a display area and a peripheral area; in, In the display area, the display device includes a pixel driving circuit substrate, a plurality of light emitting elements located on the pixel driving circuit substrate, and a packaging layer located on a side of the plurality of light emitting elements away from the pixel driving circuit substrate; and an inorganic insulating layer located on a side of the encapsulation layer away from the plurality of light emitting elements; In the binding pin region of the peripheral region, the display device comprises: a base substrate; a plurality of binding pins located on the base substrate; and The orthographic projection of the inorganic insulating layer on the base substrate and the orthographic projection of the plurality of binding pins on the base substrate at least partially do not overlap; Wherein, the display device further includes: a plurality of touch signal lines, which are at least partially located in the peripheral area; and a plurality of first via holes; Wherein, each touch signal line is connected to a corresponding binding pin among the plurality of binding pins through a first via hole among the plurality of first via holes; and An exposed surface of the corresponding bonding pin is spaced apart from the first via hole.

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