Display device and method for manufacturing display device

Abstract

A display device is provided. The display device includes a display area and a peripheral area. In the display area, the display device includes a pixel driving circuit substrate, a plurality of light-emitting elements located on the pixel driving circuit substrate, an encapsulation layer located on a side of the plurality of light-emitting elements away from the pixel driving circuit substrate, and an inorganic insulating layer located on a side of the encapsulation layer away from the plurality of light-emitting elements. In the bonding pin area of ​​the peripheral area, the display device includes a substrate and a plurality of bonding pins located on the substrate. The orthographic projection of the inorganic insulating layer on the substrate does not at least partially overlap with the orthographic projection of the plurality of bonding pins on the substrate.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a display device and a method for manufacturing the display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control illuminance. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate signal line in each row and a drain terminal connected to a data line in each column. When the row in which the pixel unit is selected is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. This drives the OLED device to emit light of a corresponding brightness. Summary of the Invention

[0003] On one hand, this disclosure provides a display device including a display area and a peripheral area; wherein, in the display area, the display device includes a pixel driving circuit substrate, a plurality of light-emitting elements located on the pixel driving circuit substrate, an encapsulation layer located on the side of the plurality of light-emitting elements away from the pixel driving circuit substrate; and an inorganic insulating layer located on the side of the encapsulation layer away from the plurality of light-emitting elements; in the bonding pin area of ​​the peripheral area, the display device includes: a substrate; a plurality of bonding pins located on the substrate; and the orthographic projection of the inorganic insulating layer on the substrate and the orthographic projection of the plurality of bonding pins on the substrate do not overlap at least partially.

[0004] Optionally, the display device further includes, in the display area: a buffer layer located on the side of the inorganic insulating layer away from the encapsulation layer; a first touch layer located on the side of the buffer layer away from the inorganic insulating layer; a touch insulating layer located on the side of the first touch layer away from the buffer layer; a second touch layer located on the side of the touch insulating layer away from the first touch layer; and a covering layer located on the side of the second touch layer away from the touch insulating layer; wherein the buffer layer, the touch insulating layer, and the covering layer are made of polymeric organic materials.

[0005] Optionally, the display device further includes a black matrix and a color filter located on the side of the cover layer away from the second touch layer in the display area; wherein the black matrix and the color filter are in direct contact with the cover layer.

[0006] Optionally, the orthographic projection of the inorganic insulating layer on the substrate does not overlap with the orthographic projection of the plurality of bonding pins on the substrate.

[0007] Optionally, the display device further includes a plurality of touch signal lines at least partially located in the peripheral area; wherein each of the plurality of touch signal lines extends at least through the touch insulating layer, the buffer layer and the inorganic insulating layer to connect with a corresponding bonding pin among the plurality of bonding pins; and each touch signal line is at least partially located in the second touch layer.

[0008] Optionally, each bonding pin includes a first edge, a second edge, a third edge, and a fourth edge; the orthographic projection of the touch insulating layer on the substrate substantially covers the orthographic projection of the first edge on the substrate, substantially covers the orthographic projection of the second edge on the substrate, substantially covers the orthographic projection of the third edge on the substrate, and substantially covers the orthographic projection of the fourth edge on the substrate; the first edge, the second edge, the third edge, and the fourth edge surround the central portion of each bonding pin; and the orthographic projection of the touch insulating layer on the substrate does not at least partially overlap with the orthographic projection of the central portion of each bonding pin on the substrate.

[0009] Optionally, each bonding pin includes a first edge, a second edge, a third edge, and a fourth edge; the orthographic projection of the touch insulating layer on the substrate does not at least partially overlap with the orthographic projection of the first edge on the substrate, does not at least partially overlap with the orthographic projection of the second edge on the substrate, does not at least partially overlap with the orthographic projection of the third edge on the substrate, and does not at least partially overlap with the orthographic projection of the fourth edge on the substrate; the first edge, the second edge, the third edge, and the fourth edge surround the central portion of each bonding pin; and the orthographic projection of the touch insulating layer on the substrate does not at least partially overlap with the orthographic projection of the central portion of each bonding pin on the substrate.

[0010] Optionally, the display device further includes a first via; wherein each touch signal line is connected to the corresponding bonding pin through the first via; an insulating layer between the exposed surface of the corresponding bonding pin and the first via includes a sloping portion and a non-sloping portion; the width of the non-sloping portion is greater than the maximum width of the first via along the direction from the exposed surface of the corresponding bonding pin to the first via.

[0011] Optionally, the display device further includes a second via and a third via; wherein each touch signal line includes a first portion located in a first touch layer and a second portion located in a second touch layer; the second portion is connected to the first portion through the second via; and the first portion is connected to the corresponding bonding pin through the third via.

[0012] Optionally, the display device further includes a second via, a third via, and a fourth via; wherein each touch signal line includes a first portion located in the first touch layer and a second portion located in the second touch layer; the second portion is connected to the first portion through the second via; and the first portion is connected to the corresponding bonding pin through the third via and the fourth via, respectively.

[0013] Optionally, the fourth distance is greater than the fifth distance; the fourth distance represents the minimum distance between the orthographic projection of the portion of the first part located in the third via on the substrate and the orthographic projection of the portion of the first part located in the fourth via on the substrate; and the fifth distance represents the minimum distance between the orthographic projection of the portion of the first part located in the third via on the substrate and the orthographic projection of the position of a portion of the corresponding bonding pin on the substrate, at which the surface of the portion transitions from being covered by an insulating layer to being exposed.

[0014] Optionally, the display device further includes a first via; wherein each touch signal line is connected to the corresponding bonding pin through the first via; and the first via extends through the touch insulating layer, the buffer layer, and the inorganic insulating layer.

[0015] Optionally, the display device further includes a fifth via; wherein each touch signal line is connected to the corresponding bonding pin through the fifth via; and the fifth via extends through the touch insulating layer, the buffer layer, the inorganic insulating layer, and the first planarization layer.

[0016] Optionally, the display device further includes a first voltage supply line configured to provide a first voltage supply signal to the display area and a second voltage supply line configured to provide a second voltage supply signal to the display area in the peripheral region; wherein at least one of the first voltage supply line or the second voltage supply line has its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the plurality of bonding pins on the substrate.

[0017] Optionally, in the bonding pin region of the peripheral region, the display device includes: a first signal line layer located on the substrate; a passivation layer located on the side of the first signal line layer away from the substrate; a second signal line layer located on the side of the passivation layer away from the first signal line layer; a first planarization layer located on the side of the second signal line layer away from the passivation layer; and the plurality of bonding pins located on the side of the first planarization layer away from the second signal line layer.

[0018] Optionally, each of the plurality of bonding pins is in direct contact with the first planarization layer; the first planarization layer is in direct contact with each of the bonding pins in a first region and is not in contact with each of the bonding pins in a second region, wherein the second region is adjacent to the first region; the surface of the first planarization layer away from the substrate includes a first portion in direct contact with each of the bonding pins and a second portion not in contact with each of the bonding pins, the first portion and the second portion being located on the same side of the first planarization layer; a first relative height is greater than a second relative height relative to the same horizontal plane; the first relative height is the height of the first portion relative to the same horizontal plane; and the second relative height is the height of the second portion relative to the same horizontal plane.

[0019] Optionally, in the bonding pin region of the peripheral region, the display device includes: a first signal line layer located on the substrate; a passivation layer located on the side of the first signal line layer away from the substrate; the plurality of bonding pins located on a second signal line layer, the second signal line layer being located on the side of the passivation layer away from the first signal line layer; and a first planarization layer located on the side of the second signal line layer away from the passivation layer.

[0020] On the other hand, this disclosure provides a method for manufacturing a display device having a display area and a peripheral area, the peripheral area including a bonding pin area; wherein the method includes: forming a pixel driving circuit substrate in the display area, forming a plurality of light-emitting elements on the pixel driving circuit substrate, and forming an encapsulation layer on a side of the plurality of light-emitting elements away from the pixel driving circuit substrate; forming a plurality of bonding pins in the bonding pin area; forming an inorganic insulating layer on a side of the encapsulation layer in the display area away from the substrate and on a side of the plurality of bonding pins in the bonding pin area of ​​the peripheral area away from the substrate; after forming the inorganic insulating layer, forming a black matrix and a color filter in the display area on a side of the plurality of light-emitting elements away from the pixel driving circuit substrate; and after forming the black matrix and the color filter, at least partially removing a portion of the inorganic insulating layer located in the bonding pin area to expose at least a portion of each of the plurality of bonding pins.

[0021] Optionally, the method further includes, in the bonding pin region: forming a first signal line layer on the substrate; forming a passivation layer on the side of the first signal line layer away from the substrate; forming a second signal line layer on the side of the passivation layer away from the first signal line layer; forming a first planarization layer on the side of the second signal line layer away from the passivation layer; and forming the plurality of bonding pins on the side of the first planarization layer away from the second signal line layer.

[0022] On the other hand, this disclosure provides a display device including a display area and a peripheral area; wherein, in the display area, the display device includes a pixel driving circuit substrate, a plurality of light-emitting elements located on the pixel driving circuit substrate, an encapsulation layer located on a side of the plurality of light-emitting elements away from the pixel driving circuit substrate; and an inorganic insulating layer located on a side of the encapsulation layer away from the plurality of light-emitting elements; in the bonding pin area of ​​the peripheral area, the display device includes: a substrate; a plurality of bonding pins located on the substrate; and the orthographic projection of the inorganic insulating layer on the substrate and the orthographic projection of the plurality of bonding pins on the substrate at least partially do not overlap; wherein, the display device further includes: a plurality of touch signal lines located at least partially in the peripheral area; and a plurality of first vias; wherein each touch signal line is connected to a corresponding bonding pin among the plurality of bonding pins through a first via of the plurality of first vias; and the exposed surface of the corresponding bonding pin is spaced apart from the first via. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 The detailed structure of a display area in a display device according to some embodiments of the present disclosure is shown.

[0025] Figure 2 This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure.

[0026] Figure 3 This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure.

[0027] Figure 4 This is a schematic diagram illustrating the display area and surrounding area in a display device according to some embodiments of the present disclosure.

[0028] Figure 5 This is a diagram illustrating a portion of a peripheral area in a display device according to some embodiments of the present disclosure.

[0029] Figure 6 This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure.

[0030] Figure 7 This shows undercut erosion occurring at the edge of the bonding pin.

[0031] Figures 8A to 8G The process of manufacturing a display device according to some embodiments of the present disclosure is illustrated.

[0032] Figure 9 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0033] Figure 10 This is a plan view of a portion of the display device located in the bonding pin region according to some embodiments of the present disclosure.

[0034] Figure 11A The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0035] Figure 11B The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0036] Figure 12 The structure of corresponding bonding pins in a display device according to some embodiments of the present disclosure is shown.

[0037] Figure 13This is a plan view of a portion of the display device located in the bonding pin region according to some embodiments of the present disclosure.

[0038] Figure 14 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0039] Figure 15 This is a plan view of a portion of the display device located in the bonding pin region according to some embodiments of the present disclosure.

[0040] Figure 16 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0041] Figure 17 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0042] Figure 18 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0043] Figure 19 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0044] Figures 20A to 20F The process of manufacturing a display device according to some embodiments of the present disclosure is illustrated.

[0045] Figure 21 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0046] Figure 22 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0047] Figure 23 The structure of corresponding bonding pins in a display device according to some embodiments of the present disclosure is shown.

[0048] Figure 24 This is a plan view of a portion of the display device located in the bonding pin region according to some embodiments of the present disclosure.

[0049] Figure 25 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0050] Figure 26This is a plan view of a portion of the display device located in the bonding pin region according to some embodiments of the present disclosure.

[0051] Figure 27 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0052] Figure 28 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure.

[0053] Figure 29 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure. Detailed Implementation

[0054] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0055] This disclosure provides, in particular, a display device and a method of manufacturing a display device, which substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a display device. In some embodiments, the display device includes a display area and a peripheral area. Optionally, in the display area, the display device includes a pixel driving circuit substrate, a plurality of light-emitting elements located on the pixel driving circuit substrate, an encapsulation layer located on a side of the plurality of light-emitting elements away from the pixel driving circuit substrate, and an inorganic insulating layer located on a side of the encapsulation layer away from the plurality of light-emitting elements. Optionally, in the bonding pin area of ​​the peripheral area, the display device includes a substrate and a plurality of bonding pins located on the substrate. Optionally, the orthographic projection of the inorganic insulating layer on the substrate and the orthographic projection of the plurality of bonding pins on the substrate do not overlap at least partially.

[0056] Figure 1 Detailed structures in a display area of ​​a display device according to some embodiments of the present disclosure are shown. (Refer to...) Figure 1In some embodiments, the display device includes the following in the display area: a substrate BS (e.g., a flexible substrate); an interlayer layer ITL on the substrate BS; an active layer ACT of each of a plurality of thin-film transistors (TFTs) on the side of the interlayer layer ITL away from the substrate BS; a gate insulating layer GI on the side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both part of a first conductive layer) on the side of the gate insulating layer GI away from the substrate BS; an insulating layer IN on the side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (part of a second conductive layer) on the side of the insulating layer IN away from the gate insulating layer GI; and a second capacitor electrode Ce2 on the side of the second capacitor electrode Ce2. An interlayer dielectric layer (ILD) located on the side of the interlayer dielectric layer (ILD) away from the gate insulating layer (GI); a source (S) and a drain (D) (part of the first signal line layer) located on the side of the interlayer dielectric layer (ILD) away from the gate insulating layer (GI); a passivation layer (PVX) located on the side of the source (S) and the drain (D) away from the interlayer dielectric layer (ILD); a first planarization layer (PLN1) located on the side of the passivation layer (PVX) away from the interlayer dielectric layer (ILD); a relay electrode (RE) (part of the second signal line layer) located on the side of the first planarization layer (PLN1) away from the passivation layer (PVX); a second planarization layer (PLN2) located on the side of the relay electrode (RE) away from the first planarization layer (PLN1); a pixel defining layer (PDL) defining a sub-pixel opening and located on the side of the second planarization layer (PLN2) away from the substrate (BS); and a light-emitting element (LE) located in the sub-pixel opening. The light-emitting element LE includes: an anode AD located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light-emitting layer EL located on the side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD located on the side of the light-emitting layer EL away from the anode AD. The display device further includes an encapsulation layer EN in the display area, which encapsulates the light-emitting element LE and is located on the side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 located on the side of the cathode layer CD away from the substrate BS, an organic encapsulation sublayer IJP located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS, and a second inorganic encapsulation sublayer CVD2 located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1.The display device further includes, in the display area, a buffer layer BUF located on the side of the encapsulation layer EN away from the substrate BS, a plurality of second electrode bridges BR2 located on the side of the buffer layer BUF away from the encapsulation layer EN, a touch insulating layer TI located on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF, a plurality of first touch electrodes TE1 located on the side of the touch insulating layer TI away from the buffer layer BUF, and an overcoat layer OC located on the side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI. Optionally, in the display area, the display device does not include a passivation layer PVX; for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0057] Reference Figure 1 The display device includes a semiconductor material layer SML, a first conductive layer CT1, a second conductive layer CT2, a first signal line layer SL1, and a second signal line layer SL2. The display device also includes an insulating layer IN located between the first conductive layer CT1 and the second conductive layer CT2, an interlayer dielectric layer ILD located between the second conductive layer CT2 and the first signal line layer SL1, and at least a passivation layer PVX or a first planarization layer PLN1 located between the first signal line layer SL1 and the second signal line layer SL2.

[0058] Reference Figure 1 Multiple second electrode bridges BR2 are located in the first touch layer ML1, and multiple first touch electrodes TE1 are located in the second touch layer ML2.

[0059] Figure 2 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 2 In some embodiments, the touch structure includes a plurality of first grid electrodes TE1 arranged in multiple rows and a plurality of second grid electrodes TE2 arranged in multiple columns. The plurality of first grid electrodes TE1 are arranged in multiple rows, with each row representing a corresponding first grid electrode among the plurality of first grid electrodes TE1. The plurality of second grid electrodes TE2 are arranged in multiple columns, with each column representing a corresponding second grid electrode among the plurality of second grid electrodes TE2. Optionally, the touch structure is a mutual capacitance touch structure. Optionally, the plurality of first grid electrodes TE1 are multiple touch sensing electrodes, and the plurality of second grid electrodes TE2 are multiple touch scanning electrodes. Optionally, the plurality of first grid electrodes TE1 are multiple touch scanning electrodes, and the plurality of second grid electrodes TE2 are multiple touch sensing electrodes.

[0060] like Figure 2As shown, each of the plurality of first grid electrodes TE1 includes a plurality of first grid blocks MB1 sequentially electrically connected along a first direction DR1 in a corresponding row, and each of the plurality of second grid electrodes TE2 includes a plurality of second grid blocks MB2 sequentially electrically connected along a second direction DR2 in a corresponding column. Figure 2 In the diagram, a corresponding first grid block in a plurality of first grid blocks MB1 and a corresponding second grid block in a plurality of second grid blocks MB2 are depicted as blocks respectively surrounded by dashed lines.

[0061] Figure 3 This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure. (Refer to...) Figure 3 The display device includes a pixel driving circuit substrate PCS, which includes a plurality of pixel driving circuits for driving the display device to emit light, a plurality of light-emitting elements LE connected to the plurality of pixel driving circuits, an encapsulation layer EN located on the side of the plurality of light-emitting elements LE away from the pixel driving circuit substrate PCS, a buffer layer BUF located on the side of the encapsulation layer EN away from the plurality of light-emitting elements LE, a first touch layer ML1 located on the side of the buffer layer BUF away from the encapsulation layer EN, a touch insulating layer TI located on the side of the first touch layer ML1 away from the buffer layer BUF, a second touch layer ML2 located on the side of the touch insulating layer TI away from the first touch layer ML1, a cover layer OC located on the side of the second touch layer ML2 away from the touch insulating layer TI, a black matrix BM and a color filter CF located on the side of the cover layer OC away from the second touch layer ML2, and a planarization layer PLN located on the side of the black matrix BM and the color filter CF away from the cover layer OC.

[0062] Figure 4 This is a schematic diagram illustrating the display area and surrounding area of ​​a display device according to some embodiments of the present disclosure. (Refer to...) Figure 4 In some embodiments, the peripheral area PA includes a first sub-region PA1 located on a first side S1 of the display area DA, a second sub-region PA2 located on a second side S2 of the display area DA, a third sub-region PA3 located on a third side S3 of the display area DA, and a fourth sub-region PA4 located on a fourth side S4 of the display area DA. Optionally, the first side S1 and the fourth side S4 are opposite to each other. Optionally, the second side S2 and the third side S3 are opposite to each other. Optionally, the first sub-region PA1 is a sub-region where multiple signal lines are connected to an integrated circuit (e.g., an integrated touch circuit).

[0063] In some embodiments, the first sub-region PA1 includes a side region SR and one or more corner regions (e.g., a first corner region CR1 and a second corner region CR2). The one or more corner regions are located at the corners of the array substrate. The one or more corner regions connect the side region SR to one or more adjacent sub-regions of the peripheral region PA. For example, the first corner region CR1 connects the side region SR to the second sub-region PA2, while the second corner region CR2 connects the side region SR to the third sub-region PA3.

[0064] Figure 5 This is a diagram illustrating a portion of a peripheral area in a display device according to some embodiments of the present disclosure. (Refer to...) Figure 5 The display device includes a plurality of bonding pins (BPS) in a peripheral region configured to bond to a touch integrated circuit or flexible printed circuit. The plurality of bonding pins (BPS) are located in a bonding pin region (BPR). The display device also includes various signal lines in the peripheral region, such as a first voltage supply line (VDD) configured to provide a first voltage supply signal to a display area and a second voltage supply line (VSS) configured to provide a second voltage supply signal to a display area. In some embodiments, the first voltage supply line (VDD) extends at least partially in the bonding pin region (BPR), for example, extending through the bonding pin region (BPR). In some embodiments, the second voltage supply line (VSS) extends at least partially in the bonding pin region (BPR), for example, extending through the bonding pin region (BPR). In some embodiments, the orthographic projection of the first voltage supply line (VDD) on the substrate at least partially overlaps with the orthographic projection of the plurality of bonding pins (BPS) on the substrate. In some embodiments, the orthographic projection of the second voltage supply line (VSS) on the substrate at least partially overlaps with the orthographic projection of the plurality of bonding pins (BPS) on the substrate. In one example, Figure 5 Show Figure 4 PA1 represents the first sub-region of the surrounding area.

[0065] Figure 6 This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure. (Refer to...) Figure 6 In some embodiments, the display device includes a plurality of touch signal lines TSL located in the peripheral region PA. The plurality of touch signal lines TSL are connected to touch electrodes located in the display area (e.g., touch electrodes located in the first touch layer ML1 or the second touch layer ML2) and are connected to a plurality of bonding pins.

[0066] Reference Figure 6The peripheral region PA of the display device includes a bonding pin region BPR with a plurality of bonding pins BPS. The plurality of bonding pins BPS are connected in the peripheral region PA to a plurality of touch signal lines TSL. The plurality of bonding pins BPS are configured to bond to a touch integrated circuit or flexible printed circuit. In some embodiments, the peripheral region PA of the display device further includes at least one of a first signal line layer SL1 located on a substrate BS and a second signal line layer SL2 located on the side of the first signal line layer SL1 away from the substrate BS. The second signal line layer SL2 is located on the side of the plurality of bonding pins BPS closer to the substrate BS. In some embodiments, electrodes in the second signal line layer SL2 and / or electrodes in the first signal line layer SL1 are connected to one or more bonding pins of the plurality of bonding pins BPS and serve as relay electrodes for connecting one or more bonding pins to signal lines.

[0067] Reference Figure 3 and Figure 6 In some embodiments, the display device is a flexible display device. To achieve enhanced flexibility in the display device, certain insulating layers in the display device are made of polymeric organic materials. For example, see reference... Figure 3 and Figure 6 In some embodiments, the touch insulating layer TI and the overlay layer OC are made of a polymeric flexible organic material. When the touch insulating layer TI and the overlay layer OC are made of a polymeric flexible organic material, they are not present in the bonding pin region BPR.

[0068] Reference Figure 3 In some embodiments, the display device is a color filter on encapsulation (COE) display device, wherein the color filter (CF) and black matrix (BM) are formed directly on the cladding layer (OC) of the display device located in the display area. Since the touch insulating layer (TI) and cladding layer (OC) are absent in the bonding pin region (BPR), the plurality of bonding pins (BPS) are at least partially exposed to the alkaline developing solution used in the formation of at least one of the color filter (CF) and black matrix (BM). In particular, the edges of the plurality of bonding pins (BPS) are susceptible to undercut erosion caused by the alkaline developing solution. Figure 7 This illustrates undercut erosion occurring at the edge of the bonding pin. Undercut erosion reduces the effective width of the bonding pin and causes defective black spots when the bonding pin is bonded to an integrated circuit or flexible printed circuit.

[0069] The inventors of this disclosure have discovered that the display device according to this disclosure avoids the aforementioned problems. Figures 8A to 8G The process of manufacturing a display device according to some embodiments of the present disclosure is illustrated. (Refer to...) Figure 8AMultiple light-emitting elements (LEs) are formed in the display area DA of the display device, and an encapsulation layer EN is formed on the side of the multiple light-emitting elements LEs away from the pixel driving circuit substrate PCS. In the bonding pin area BPR of the peripheral area PA, a first signal line layer SL1 is formed on the substrate BS. A passivation layer PVX is formed on the side of the first signal line layer SL1 away from the substrate BS. A second signal line layer SL2 is formed on the side of the passivation layer PVX away from the substrate BS. A first planarization layer PLN1 is formed on the side of the second signal line layer SL2 away from the substrate BS. Multiple bonding pins BPS are formed on the side of the first planarization layer PLN1 away from the substrate BS. In this step, the multiple bonding pins BPS are not protected, and the surfaces of the multiple bonding pins BPS are exposed.

[0070] In one example, multiple bonded pins (BPS) and conductive components located on the package layer EN or the second planarization layer PLN2 are located on the same layer. As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple bonded pins (BPS) and conductive components located on the package layer EN are located on the same layer when they are formed due to one or more steps of the same patterning process performed in the same material layer. In another example, multiple bonded pins (BPS) and conductive components located on the package layer EN can be formed on the same layer by simultaneously performing the steps of forming multiple bonded pins (BPS) and forming conductive components on the package layer EN. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0071] In another example, multiple bonded pins (BPS) are located on the same layer as the anode of the light-emitting element.

[0072] Reference Figure 8B An inorganic insulating layer IOL is formed on the side of the encapsulation layer EN in the display area DA that is away from the substrate BS, and on the side of the multiple bonding pins BPS in the bonding pin area BPR in the peripheral area PA that is away from the substrate BS. After the inorganic insulating layer IOL is formed, the multiple bonding pins BPS are protected by the inorganic insulating layer IOL to prevent them from being eroded in subsequent manufacturing processes.

[0073] In some embodiments, a first relative height between each of the plurality of bonded pins BPS and the surface of the substrate BS in the bonded pin region of the peripheral region PA is less than a second relative height between the inorganic insulating layer IOL and the surface of the same substrate extending from the peripheral region PA to the display region DA. The inventors of this disclosure have discovered that by making the first relative height less than the second relative height, damage to the plurality of bonded pins BPS by the mask during the manufacturing process can be avoided.

[0074] Reference Figure 8C In the display area DA, a buffer layer BUF is formed on the side of the inorganic insulating layer IOL away from the encapsulation layer EN.

[0075] Reference Figure 8D In the display area DA, a first touch layer ML1 is formed on the side of the buffer layer BUF away from the inorganic insulating layer IOL.

[0076] Reference Figure 8E In the display area DA, a touch insulating layer TI is formed on the side of the first touch layer ML1 away from the buffer layer BUF, a second touch layer ML2 is formed on the side of the touch insulating layer TI away from the buffer layer BUF, and a covering layer OC is formed on the side of the second touch layer ML2 away from the touch insulating layer TI. Optionally, the buffer layer BUF, the touch insulating layer TI, and the covering layer OC are made of polymeric organic materials.

[0077] Reference Figure 8F In the display area DA, a black matrix BM and a color filter CF are formed on the side of the cladding layer OC away from the touch insulating layer TI, and a planarization layer PLN is formed on the side of the black matrix BM and the color filter CF away from the cladding layer OC. During this process, as described above, an alkaline developing solution is used to pattern the black matrix BM and / or the color filter CF. Multiple bonding pins BPS in the bonding pin area BPR of the peripheral area PA are covered by an inorganic insulating layer IOL and protected from the alkaline developing solution. Undercutting of the multiple bonding pins BPS can be avoided.

[0078] Reference Figure 8G After forming the black matrix BM and the color filter CF, the inorganic insulating layer IOL in the bonding pin region BPR of the peripheral region PA is at least partially removed, thereby exposing at least a portion of each bonding pin in the plurality of bonding pins BPS.

[0079] In some embodiments, the display device includes a display area and a peripheral area. In some embodiments, in the display area, the display device includes a pixel driving circuit board PCS, a plurality of light-emitting elements LE located on the pixel driving circuit board PCS, an encapsulation layer EN located on the side of the plurality of light-emitting elements LE away from the pixel driving circuit board PCS, an inorganic insulating layer IOL located on the side of the encapsulation layer EN away from the plurality of light-emitting elements LE, a buffer layer BUF located on the side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on the side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on the side of the first touch layer ML1 away from the buffer layer BUF, a second touch layer ML2 located on the side of the touch insulating layer TI away from the first touch layer ML1, a cover layer OC located on the side of the second touch layer ML2 away from the touch insulating layer TI, and a black matrix BM and a color filter CF located on the side of the cover layer OC away from the second touch layer ML2.

[0080] In some embodiments, the thicknesses of at least two of the touch insulating layer TI, the inorganic insulating layer IOL, and the buffer layer BUF are different from each other. Optionally, the thickness of the touch insulating layer TI is greater than the thickness of the inorganic insulating layer IOL, and also greater than the thickness of the buffer layer BUF. Optionally, the thickness of the buffer layer BUF is greater than the thickness of the inorganic insulating layer IOL.

[0081] In some embodiments, in the display area, the display device further includes a planarization layer PLN located on the side of the black matrix BM and the color filter CF away from the overlay layer OC.

[0082] In some embodiments, the buffer layer BUF, the touch insulating layer TI, and the covering layer OC are made of polymeric organic materials.

[0083] In some embodiments, in the bonding pin region BPR of the peripheral region PA, the display device includes a substrate BS, a first signal line layer SL1 located on the substrate BS, a passivation layer PVX located on the side of the first signal line layer SL1 away from the substrate BS, a second signal line layer SL2 located on the side of the passivation layer PVX away from the first signal line layer SL1, a first planarization layer PLN1 located on the side of the second signal line layer SL2 away from the passivation layer PVX, and a plurality of bonding pins BPS located on the side of the first planarization layer PLN1 away from the second signal line layer SL2.

[0084] In some embodiments, the inorganic insulating layer is at least partially absent in the bonding pin region BPR. Optionally, the inorganic insulating layer IOL is completely absent in the bonding pin region BPR. Optionally, the orthographic projection of the inorganic insulating layer IOL onto the substrate does not at least partially overlap with the orthographic projection of the plurality of bonding pins BPS onto the substrate (e.g., at least 50% non-overlap, at least 60% non-overlap, at least 70% non-overlap, at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap). Optionally, the orthographic projection of the inorganic insulating layer IOL onto the substrate does not completely overlap with the orthographic projection of the plurality of bonding pins BPS onto the substrate. With this fine structure, the plurality of bonding pins BPS remain substantially intact during the fabrication of the black matrix BM and color filter CF, avoiding undercutting issues.

[0085] Figure 9 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure. Figure 10 This is a plan view of a portion of the bonding pin region of a display device according to some embodiments of the present disclosure. (Refer to...) Figure 9 and Figure 10 In some embodiments, the bonding pin region BPR of the peripheral region PA of the display device includes a substrate BS, a first signal line layer SL1 located on the substrate BS, a passivation layer PVX located on the side of the first signal line layer SL1 away from the substrate BS, a second signal line layer SL2 located on the side of the passivation layer PVX away from the first signal line layer SL1, a first planarization layer PLN1 located on the side of the second signal line layer SL2 away from the passivation layer PVX, and a plurality of bonding pins BPS located on the side of the first planarization layer PLN1 away from the second signal line layer SL2.

[0086] In some embodiments, the display device includes a plurality of touch signal lines TSL located at least partially in a peripheral region PA. In some embodiments, in the peripheral region PA and outside the bonding pin region BPR, the display device includes a substrate BS, a passivation layer PVX on the substrate BS, a first planarization layer PLN1 on the side of the passivation layer PVX away from the substrate BS, an inorganic insulating layer IOL on the side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF on the side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a touch insulating layer TI on the side of the buffer layer BUF away from the inorganic insulating layer IOL, and a plurality of touch signal lines TSL on the side of the touch insulating layer TI away from the buffer layer BUF.

[0087] In some embodiments, in the display area DA, the display device includes a pixel driving circuit board PCS, a plurality of light-emitting elements LE located on the pixel driving circuit board PCS, an encapsulation layer EN located on the side of the plurality of light-emitting elements LE away from the pixel driving circuit board PCS, an inorganic insulating layer IOL located on the side of the encapsulation layer EN away from the plurality of light-emitting elements LE, a buffer layer BUF located on the side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on the side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on the side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on the side of the touch insulating layer TI away from the first touch layer ML1.

[0088] In some embodiments, a plurality of touch signal lines TSL are located in the second touch layer ML2.

[0089] In some embodiments, the orthographic projection of the inorganic insulating layer IOL onto the substrate BS at least partially overlaps with the orthographic projection of the plurality of bonding pins BPS onto the substrate BS. In some embodiments, each touch signal line in the plurality of touch signal lines TSL extends through the touch insulating layer TI, the buffer layer BUF, and the inorganic insulating layer IOL to connect to a corresponding bonding pin in the plurality of bonding pins BPS. Optionally, the display device includes a first via v1. Each touch signal line in the plurality of touch signal lines TSL is connected to a corresponding bonding pin in the plurality of bonding pins BPS through the first via v1. In one example, the first via v1 extends through the touch insulating layer TI, the buffer layer BUF, and the inorganic insulating layer IOL.

[0090] Figure 11A The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure. Figure 12 The structure of corresponding bonding pins in a display device according to some embodiments of the present disclosure is shown. Figure 13 This is a plan view of a portion of the bonding pin region of a display device according to some embodiments of the present disclosure. (Refer to...) Figure 11A , Figure 12 and Figure 13In some embodiments, the bonding pin region BPR of the peripheral region PA of the display device includes a substrate BS, a first signal line layer SL1 on the substrate BS, a passivation layer PVX on the side of the first signal line layer SL1 away from the substrate BS, a second signal line layer SL2 on the side of the passivation layer PVX away from the first signal line layer SL1, a first planarization layer PLN1 on the side of the second signal line layer SL2 away from the passivation layer PVX, a plurality of bonding pins BPS on the side of the first planarization layer PLN1 away from the second signal line layer SL2, and a touch insulating layer TI on the side of the plurality of bonding pins BPS away from the first planarization layer PLN1.

[0091] In some embodiments, the display device includes a plurality of touch signal lines TSL located at least partially in a peripheral region PA. In some embodiments, in the peripheral region PA and outside the bonding pin region BPR, the display device includes a substrate BS, a passivation layer PVX on the substrate BS, a first planarization layer PLN1 on the side of the passivation layer PVX away from the substrate BS, an inorganic insulating layer IOL on the side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF on the side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a touch insulating layer TI on the side of the buffer layer BUF away from the inorganic insulating layer IOL, and a plurality of touch signal lines TSL on the side of the touch insulating layer TI away from the buffer layer BUF.

[0092] In some embodiments, in the display area DA, the display device includes a pixel driving circuit board PCS, a plurality of light-emitting elements LE located on the pixel driving circuit board PCS, an encapsulation layer EN located on the side of the plurality of light-emitting elements LE away from the pixel driving circuit board PCS, an inorganic insulating layer IOL located on the side of the encapsulation layer EN away from the plurality of light-emitting elements LE, a buffer layer BUF located on the side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on the side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on the side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on the side of the touch insulating layer TI away from the first touch layer ML1. In some embodiments, a plurality of touch signal lines TSL are located in the second touch layer ML2.

[0093] In some embodiments, the orthographic projection of the inorganic insulating layer IOL onto the substrate BS at least partially overlaps with the orthographic projection of the plurality of bonding pins BPS onto the substrate BS. In some embodiments, each touch signal line in the plurality of touch signal lines TSL extends through the touch insulating layer TI, the buffer layer BUF, and the inorganic insulating layer IOL to connect to a corresponding bonding pin in the plurality of bonding pins BPS. Optionally, the display device includes a first via v1. Each touch signal line in the plurality of touch signal lines TSL is connected to a corresponding bonding pin in the plurality of bonding pins BPS through the first via v1. In one example, the first via v1 extends through the touch insulating layer TI, the buffer layer BUF, and the inorganic insulating layer IOL.

[0094] In some embodiments, each of the multiple bonding pins (BPS) includes a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4. Optionally, the first edge E1 and the second edge E2 are opposite to each other. Optionally, the third edge E3 and the fourth edge E4 are opposite to each other. The first edge E1 and the second edge E2 are connected via the third edge E3 and via the fourth edge E4. The third edge E3 and the fourth edge E4 are connected via the first edge E1 and via the second edge E2. The first edge E1, the second edge E2, the third edge E3, and the fourth edge E4 surround the central portion CP of each bonding pin.

[0095] In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the first edge E1 on the substrate BS, substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the second edge E2 on the substrate BS, substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the third edge E3 on the substrate BS, and substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the fourth edge E4 on the substrate BS.

[0096] In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS and the orthographic projection of the central portion CP of each bonding pin on the substrate BS are at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%) non-overlapping.

[0097] Reference Figure 11A In the sub-region of the bonding pin area BPR, located on the side of the multiple bonding pins BPS away from the display area DA, there is no inorganic insulating layer IOL and buffer layer BUF, only a part of the touch insulating layer TI.

[0098] Figure 11B The diagram illustrates the connection between the bonding pins and the touch signal line in a display device according to some embodiments of the present disclosure. (Refer to...) Figure 11B , Figure 12 and Figure 13 In some embodiments, the touch insulating layer TI, the inorganic insulating layer IOL, and the buffer layer BUF are located in a sub-region of the bonding pin region BPR on the side of the plurality of bonding pins BPS away from the display region DA.

[0099] In some embodiments, the orthographic projection of the inorganic insulating layer IOL onto the substrate BS substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the first edge E1 onto the substrate BS, substantially covering (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the second edge E2 onto the substrate BS, substantially covering (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the third edge E3 onto the substrate BS, and substantially covering (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the third edge E4 onto the substrate BS.

[0100] In some embodiments, the orthographic projection of the inorganic insulating layer IOL on the substrate BS does not overlap with the orthographic projection of the central portion CP of each bonding pin on the substrate BS at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%).

[0101] In some embodiments, the orthographic projection of the buffer layer BUF onto the substrate BS substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the first edge E1 onto the substrate BS, substantially covering (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the second edge E2 onto the substrate BS, substantially covering (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the third edge E3 onto the substrate BS, and substantially covering (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the fourth edge E4 onto the substrate BS.

[0102] In some embodiments, the orthographic projection of the buffer layer BUF onto the substrate BS does not overlap with the orthographic projection of the central portion CP of each bonding pin onto the substrate BS at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%).

[0103] In some embodiments, refer to Figure 11A , Figure 11B , Figure 12 and Figure 13 The array substrate includes a plurality of central portion vias (CPVs). Each central portion via in the plurality of central portion vias (CPVs) extends at least through the touch insulating layer TI, exposing at least a portion of the central portion CP of the plurality of central portions. In some embodiments, the extension directions of the plurality of central portions are substantially parallel to each other. In some embodiments, the extension directions of the plurality of central portion vias (CPVs) are substantially parallel to each other. As used herein, the term “substantially parallel” means an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, and 0 degrees to about 30 degrees.

[0104] In some embodiments, the array substrate further includes a plurality of dummy bond pins (DBPS) and a plurality of dummy central portion vias (DCPV). Each dummy central portion via in the plurality of dummy central portion vias (DCPV) extends at least through the touch insulating layer (TI), thereby exposing at least a portion of the dummy central portion of the plurality of dummy central portions. Optionally, the extension direction of the plurality of bond pins (BPS) is substantially parallel to the extension direction of the plurality of dummy bond pins (DBPS). Optionally, the extension direction of the plurality of central portion vias (CPV) is substantially parallel to the extension direction of the plurality of dummy central portion vias (DCPV). In some embodiments, along the extension direction of the respective bond pins or the extension direction of the respective dummy bond pins, the length of each bond pin in the plurality of bond pins (BPS) is greater than the length of each dummy bond pin in the plurality of dummy bond pins (DBPS). In some embodiments, along the extension direction of the respective central portion vias or the extension direction of the respective dummy central portion vias, the length of each central portion via in the plurality of central portion vias (CPV) is substantially the same as the length of each dummy central portion via in the plurality of dummy central portion vias (DCPV).

[0105] Figure 14 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure. Figure 15 This is a plan view of a portion of the bonding pin region of a display device according to some embodiments of the present disclosure. (Refer to...) Figure 14 and Figure 15 as well as Figure 12In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the first edge E1 on the substrate BS at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%). In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the second edge E2 on the substrate BS at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%). In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS and the orthographic projection of the third edge E3 on the substrate BS are at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%) non-overlapping. In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS and the orthographic projection of the fourth edge E4 on the substrate BS are at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%) non-overlapping. In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS and the orthographic projection of the central portion CP on the substrate BS are at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%) non-overlapping.

[0106] In some embodiments, such as Figure 14 As shown, the edge Eti of the touch insulating layer TI located in the bonding pin region BPR is spaced apart from the exposed surface of each bonding pin by a first spacing distance sd1, and is spaced apart from the first via v1 by a second spacing distance sd2. Optionally, the second spacing distance sd2 is greater than the first spacing distance sd1.

[0107] In some embodiments, such as Figure 14 As shown, the display device includes: a plurality of touch signal lines TSL at least partially located in a peripheral region PA; and a plurality of first vias. Each touch signal line in the plurality of touch signal lines TSL is connected to a corresponding bonding pin in a plurality of bonding pins BPS through a first via v1 of the plurality of first vias. Optionally, the exposed surface of the corresponding bonding pin is spaced apart from the first via v1. Optionally, the orthographic projection of the exposed surface of each bonding pin on the substrate does not overlap with the orthographic projection of the portion of the corresponding touch signal line located in the first via v1 on the substrate.

[0108] In some embodiments, such as Figure 15 As shown, the portion of the touch insulating layer TI located in the bonding pin area BPR is spaced apart from the portion of the touch insulating layer TI located in the display area DA.

[0109] In an alternative embodiment, a portion of the touch insulating layer TI located in the bonding pin region BPR is connected to a portion of the touch insulating layer TI located in the display region DA. Optionally, the portion of the touch insulating layer TI located in the bonding pin region BPR and the portion of the touch insulating layer TI located in the display region DA are parts of an integral structure.

[0110] In some embodiments, such as Figure 15 As shown, a portion of the touch insulating layer TI located in the bonding pin region BPR at least partially surrounds multiple bonding pins BPS.

[0111] In an alternative embodiment, the portion of the touch insulating layer TI located in the bonding pin region BPR includes multiple teeth extending into regions between adjacent bonding pins in a plurality of bonding pins BPS. In one example, the portion of the touch insulating layer TI located in the bonding pin region BPR is comb-shaped.

[0112] In an alternative embodiment, the portion of the touch insulating layer TI located in the bonding pin region BPR has a smaller thickness than the portion of the touch insulating layer TI located in the display region DA.

[0113] In an alternative embodiment, the array substrate further includes a portion of the cladding layer OC located on the side of the touch insulating layer TI away from the substrate, in the portion of the bonding pin region BPR.

[0114] Figure 16 The diagram illustrates the connection between the bonding pins and the touch signal line in a display device according to some embodiments of the present disclosure. (Refer to...) Figure 16 In some embodiments, the first distance d1 is greater than or equal to the sum of the second distance d2 and the third distance d3. In some embodiments, the first distance d1 represents the minimum distance between the orthographic projection of the portion of the corresponding touch signal line located in the first via v1 onto the substrate and the orthographic projection of the location of a portion of the corresponding bonding pin onto the substrate, at which point the surface of the portion changes from being covered by an insulating layer to being exposed. In one example, the insulating layer includes an inorganic insulating layer IOL, a buffer layer BUF, and a touch insulating layer TI. The second distance d2 is the minimum distance between the orthographic projection of the location of a portion of the corresponding bonding pin (at which point the surface of the portion changes from being covered by an insulating layer to being exposed) onto the substrate and the orthographic projection of a location of the insulating layer (at which point the slope angle of the insulating layer covering the portion of the corresponding bonding pin changes from a positive value to substantially zero) onto the substrate.

[0115] In some embodiments, the third distance d3 is greater than the maximum width of the first via v1. By making the third distance d3 greater than the maximum width of the first via v1, a safe distance can be ensured between the exposed surface of the first via and the corresponding bonding pin.

[0116] In some embodiments, the third distance d3 represents the maximum process deviation of the display device. As used herein, the term "process deviation" refers to the difference between a component and its design requirements due to various factors during the manufacturing process. Process deviations can be caused by factors such as materials, processing techniques, equipment, and environment.

[0117] In some embodiments, the insulating layer includes a sloping portion (corresponding to d2) and a non-sloping portion (corresponding to d3) between the exposed surface of the corresponding bonding pin and the first via v1, such as... Figure 16 As shown in the figure. In some embodiments, the width of the non-sloping portion is greater than the maximum width of the first via v1 along the direction from the exposed surface of the corresponding bonding pin to the first via v1.

[0118] Figure 17 The diagram illustrates the connection between the bonding pins and the touch signal line in a display device according to some embodiments of the present disclosure. (Refer to...) Figure 17 In some embodiments, the bonding pin region BPR of the peripheral region PA of the display device includes a substrate BS, a first signal line layer SL1 located on the substrate BS, a passivation layer PVX located on the side of the first signal line layer SL1 away from the substrate BS, a second signal line layer SL2 located on the side of the passivation layer PVX away from the first signal line layer SL1, a first planarization layer PLN1 located on the side of the second signal line layer SL2 away from the passivation layer PVX, and a plurality of bonding pins BPS located on the side of the first planarization layer PLN1 away from the second signal line layer SL2.

[0119] In some embodiments, the display device includes a plurality of touch signal lines TSL at least partially located in a peripheral region PA. In some embodiments, each touch signal line in the plurality of touch signal lines TSL includes a first portion P1 and a second portion P2 connected to each other. Optionally, the second portion P2 is connected to a corresponding bonding pin in a plurality of bonding pins BPS via the first portion P1. Optionally, the first portion P1 is located in a first touch layer ML1, and the second portion P2 is located in a second touch layer ML2.

[0120] In some embodiments, within the peripheral region PA and outside the bonding pin region BPR, the display device includes a substrate BS, a passivation layer PVX on the substrate BS, a first planarization layer PLN1 on the side of the passivation layer PVX away from the substrate BS, an inorganic insulating layer IOL on the side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF on the side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a first portion P1 of each touch signal line in a plurality of touch signal lines TSL on the side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI on the side of the first portion P1 away from the buffer layer BUF, and a second portion of each touch signal line in a plurality of touch signal lines TSL on the side of the touch insulating layer TI away from the first portion P1.

[0121] In some embodiments, in the display area DA, the display device includes a pixel driving circuit board PCS, a plurality of light-emitting elements LE located on the pixel driving circuit board PCS, an encapsulation layer EN located on the side of the plurality of light-emitting elements LE away from the pixel driving circuit board PCS, an inorganic insulating layer IOL located on the side of the encapsulation layer EN away from the plurality of light-emitting elements LE, a buffer layer BUF located on the side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on the side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on the side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on the side of the touch insulating layer TI away from the first touch layer ML1.

[0122] In some embodiments, the display device includes a second via v2. A second portion P2 is connected to a first portion P1 via the second via v2. In one example, the second via v2 extends through the touch insulating layer TI.

[0123] In some embodiments, the display device further includes a third via v3. The first portion P1 is connected to a corresponding bonding pin in a plurality of bonding pins BPS via the third via v3. In one example, the third via v3 extends through the buffer layer BUF and the inorganic insulating layer IOL. Optionally, the minimum distance between the exposed surface of the corresponding bonding pin and the third via v3 is less than the minimum distance between the third via v3 and the second via v2. Optionally, the depth of the second via v2 is greater than the depth of the third via v3. Optionally, the thickness of the touch insulating layer TI is greater than the sum of the thicknesses of the inorganic insulating layer IOL and the buffer layer BUF.

[0124] In some embodiments, the orthographic projection of the inorganic insulating layer IOL on the substrate BS at least partially overlaps with the orthographic projection of the plurality of bonding pins BPS on the substrate BS.

[0125] Figure 18 The diagram illustrates the connection between the bonding pins and the touch signal line in a display device according to some embodiments of the present disclosure. (Refer to...) Figure 18 The display device includes a plurality of touch signal lines TSLs at least partially located in a peripheral region PA. In some embodiments, each touch signal line in the plurality of touch signal lines TSLs includes a first portion P1 and a second portion P2 connected to each other. Optionally, the second portion P2 is connected to a corresponding bonding pin in a plurality of bonding pins BPS through the first portion P1. Optionally, the first portion P1 is located in a first touch layer ML1, and the second portion P2 is located in a second touch layer ML2.

[0126] In some embodiments, the display device includes a second via v2. A second portion P2 is connected to a first portion P1 via the second via v2. In one example, the second via v2 extends through the touch insulating layer TI.

[0127] In some embodiments, the display device further includes a third via v3. The first portion P1 is connected to a corresponding bonding pin in a plurality of bonding pins BPS via the third via v3. In one example, the third via v3 extends through the buffer layer BUF and the inorganic insulating layer IOL.

[0128] In some embodiments, the display device further includes a fourth via v4. The first portion P1 is connected via the fourth via v4 to a corresponding bonding pin in a plurality of bonding pins BPS. In one example, the fourth via v4 extends through the buffer layer BUF and the inorganic insulating layer IOL.

[0129] In some embodiments, refer to Figure 18 The fourth distance d4 is greater than the fifth distance d5, where the fourth distance d4 represents the minimum distance between the orthographic projection of the portion of the first part P1 located in the third via v3 on the substrate and the orthographic projection of the portion of the first part P1 located in the fourth via v4 on the substrate; the fifth distance d5 represents the minimum distance between the orthographic projection of the portion of the first part P1 located in the third via v3 on the substrate and the orthographic projection of the position of a portion of the corresponding bonding pin BPS on the substrate, at which the surface of the portion changes from being covered by an insulating layer to being exposed.

[0130] In some embodiments, refer to Figure 18The array substrate includes a bonding pin via (BPV) that extends at least through the touch insulating layer (TI) to expose the surface of the corresponding bonding pin. Optionally, the array substrate also includes a connection via (CV) that extends at least through the first planarization layer (PLN1), and the corresponding bonding pin is connected to the second signal line layer (SL2) via the connection via (CV). Optionally, the maximum width of the bonding pin via (BPV) is greater than the maximum width of the connection via (CV). Optionally, the maximum width of the bonding pin via (BPV) is greater than the maximum width of the third via (v3). Optionally, the maximum width of the bonding pin via (BPV) is greater than the maximum width of the fourth via (v4). Optionally, the bonding pin via (BPV), the connection via (CV), the third via (v3), and the fourth via (v4) are located on the side of the contact interface between the package layer (EN) and the first planarization layer (PLN1) away from the display area (DA).

[0131] Figure 19 The diagram illustrates the connection between the bonding pins and the touch signal line in a display device according to some embodiments of the present disclosure. (Refer to...) Figure 19 In some embodiments, each of the multiple bonded pins (BPS) is in direct contact with the first planarization layer (PLN1).

[0132] In some embodiments, the first planarization layer PLN1 is in direct contact with each bonding pin in a first region R1 and is not in contact with each bonding pin in a second region R2, wherein the second region R2 is adjacent to the first region R1. The surface of the first planarization layer PLN1 away from the substrate BS includes a first portion S1 in direct contact with each bonding pin and a second portion S2 not in contact with each bonding pin, the first portion S1 and the second portion S2 being located on the same side of the first planarization layer PLN1. Relative to the same horizontal plane (e.g., the surface of the passivation layer PVX located below the first planarization layer PLN1), a first relative height h1 is greater than a second relative height h2, wherein the first relative height h1 is the height of the first portion S1 relative to the same horizontal plane, and the second relative height h2 is the height of the second portion S2 relative to the same horizontal plane.

[0133] In one example, each bonding pin has a thickness substantially the same as the thickness of the touch electrode or touch signal line located in the first touch layer ML1. In another example, the thickness of the first portion P1 is substantially the same as the thickness of the touch electrode or touch signal line located in the first touch layer ML1. As used herein, the term "substantially the same" means that the difference between two values ​​does not exceed 10% of a base value (e.g., one of the two values), such as not exceeding 8%, 6%, 4%, 2%, 1%, 0.5%, 0.1%, 0.05%, and 0.01% of the base value.

[0134] In an alternative example, each bonding pin has a thickness different from the thickness of the touch electrode or touch signal line located in the first touch layer ML1.

[0135] In another example, each bonding pin has a thickness substantially the same as the thickness of the touch electrode or touch signal line located in the second touch layer ML2. In another example, the thickness of the second portion P2 is substantially the same as the thickness of the touch electrode or touch signal line located in the second touch layer ML2.

[0136] In an alternative example, each bonding pin has a thickness different from that of the touch electrodes or touch signal lines located in the second touch layer ML2.

[0137] Various suitable implementation methods can be practiced based on this disclosure. Figures 20A to 20F The process of manufacturing a display device according to some embodiments of the present disclosure is illustrated. (Refer to...) Figure 20A Multiple light-emitting elements (LEs) are formed in the display area DA of the display device, and an encapsulation layer EN is formed on the side of the multiple light-emitting elements LEs away from the pixel driving circuit substrate PCS. In the bonding pin area BPR of the peripheral area PA, a first signal line layer SL1 is formed on the substrate BS, a passivation layer PVX is formed on the side of the first signal line layer SL1 away from the substrate BS, and multiple bonding pins BPS are formed on the side of the passivation layer PVX away from the substrate BS. Multiple bonding pins BPS are formed in the second signal line layer SL2.

[0138] In some embodiments, an inorganic insulating layer IOL is formed on the side of the encapsulation layer EN in the display area DA that is away from the substrate BS, and on the side of a plurality of bonding pins BPS in the bonding pin area BPR of the peripheral area PA that is away from the substrate BS. After the inorganic insulating layer IOL is formed, the plurality of bonding pins BPS are protected by the inorganic insulating layer IOL to prevent them from being eroded in subsequent manufacturing processes.

[0139] Reference Figure 20B In the display area DA, a buffer layer BUF is formed on the side of the inorganic insulating layer IOL away from the encapsulation layer EN.

[0140] Reference Figure 20C In the display area DA, a first touch layer ML1 is formed on the side of the buffer layer BUF away from the inorganic insulating layer IOL.

[0141] Reference Figure 20DIn the display area DA, a touch insulating layer TI is formed on the side of the first touch layer ML1 away from the buffer layer BUF, a second touch layer ML2 is formed on the side of the touch insulating layer TI away from the buffer layer BUF, and a covering layer OC is formed on the side of the second touch layer ML2 away from the touch insulating layer TI. Optionally, the buffer layer BUF, the touch insulating layer TI, and the covering layer OC are made of polymeric organic materials.

[0142] Reference Figure 20E In the display area DA, a black matrix BM and a color filter CF are formed on the side of the cladding layer OC away from the touch insulating layer TI, and a planarization layer PLN is formed on the side of the black matrix BM and the color filter CF away from the cladding layer OC. During this process, as described above, an alkaline developing solution is used to pattern the black matrix BM and / or the color filter CF. Multiple bonding pins BPS in the bonding pin area BPR of the peripheral area PA are covered by an inorganic insulating layer IOL and protected from the alkaline developing solution. Undercutting of the multiple bonding pins BPS can be avoided.

[0143] Reference Figure 20F After forming the black matrix BM and the color filter CF, the inorganic insulating layer IOL in the bonding pin region BPR located in the peripheral region PA is at least partially removed, thereby exposing at least a portion of each bonding pin in the plurality of bonding pins BPS.

[0144] In some embodiments, the display device includes a display area and a peripheral area. In some embodiments, in the display area, the display device includes a pixel driving circuit board PCS, a plurality of light-emitting elements LE located on the pixel driving circuit board PCS, an encapsulation layer EN located on the side of the plurality of light-emitting elements LE away from the pixel driving circuit board PCS, an inorganic insulating layer IOL located on the side of the encapsulation layer EN away from the plurality of light-emitting elements LE, a buffer layer BUF located on the side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on the side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on the side of the first touch layer ML1 away from the buffer layer BUF, a second touch layer ML2 located on the side of the touch insulating layer TI away from the first touch layer ML1, a cover layer OC located on the side of the second touch layer ML2 away from the touch insulating layer TI, and a black matrix BM and a color filter CF located on the side of the cover layer OC away from the second touch layer ML2.

[0145] In some embodiments, in the display area, the display device further includes a planarization layer PLN located on the side of the black matrix BM and the color filter CF away from the overlay layer OC.

[0146] In some embodiments, the buffer layer BUF, the touch insulating layer TI, and the covering layer OC are made of polymeric organic materials.

[0147] In some embodiments, in the bonding pin region BPR of the peripheral region PA, the display device includes a substrate BS, a first signal line layer SL1 located on the substrate BS, a passivation layer PVX located on the side of the first signal line layer SL1 away from the substrate BS, a plurality of bonding pins BPS in a second signal line layer SL2 located on the side of the passivation layer PVX away from the first signal line layer SL1, and a first planarization layer PLN1 located on the side of the plurality of bonding pins BPS away from the passivation layer PVX.

[0148] In some embodiments, the inorganic insulating layer is at least partially absent in the bonding pin region BPR. Optionally, the inorganic insulating layer IOL is completely absent in the bonding pin region BPR. Optionally, the orthographic projection of the inorganic insulating layer IOL onto the substrate does not at least partially overlap with the orthographic projection of the plurality of bonding pins BPS onto the substrate (e.g., at least 50% non-overlap, at least 60% non-overlap, at least 70% non-overlap, at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap). Optionally, the orthographic projection of the inorganic insulating layer IOL onto the substrate does not completely overlap with the orthographic projection of the plurality of bonding pins BPS onto the substrate. With this fine structure, the plurality of bonding pins BPS remain substantially intact during the fabrication of the black matrix BM and color filter CF, avoiding undercutting issues.

[0149] Figure 21 The diagram illustrates the connection between the bonding pins and the touch signal line in a display device according to some embodiments of the present disclosure. (Refer to...) Figure 21 In some embodiments, the bonding pin region BPR of the peripheral region PA of the display device includes a substrate BS, a first signal line layer SL1 located on the substrate BS, a passivation layer PVX located on the side of the first signal line layer SL1 away from the substrate BS, a plurality of bonding pins BPS in a second signal line layer SL2 located on the side of the passivation layer PVX away from the first signal line layer SL1, and a first planarization layer PLN1 located on the side of the second signal line layer SL2 away from the passivation layer PVX.

[0150] In some embodiments, the display device includes a plurality of touch signal lines TSL located at least partially in a peripheral region PA. In some embodiments, in the peripheral region PA and outside the bonding pin region BPR, the display device includes a substrate BS, a passivation layer PVX on the substrate BS, a first planarization layer PLN1 on the side of the passivation layer PVX away from the substrate BS, an inorganic insulating layer IOL on the side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF on the side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a touch insulating layer TI on the side of the buffer layer BUF away from the inorganic insulating layer IOL, and a plurality of touch signal lines TSL on the side of the touch insulating layer TI away from the buffer layer BUF.

[0151] In some embodiments, in the display area DA, the display device includes a pixel driving circuit board PCS, a plurality of light-emitting elements LE located on the pixel driving circuit board PCS, an encapsulation layer EN located on the side of the plurality of light-emitting elements LE away from the pixel driving circuit board PCS, an inorganic insulating layer IOL located on the side of the encapsulation layer EN away from the plurality of light-emitting elements LE, a buffer layer BUF located on the side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on the side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on the side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on the side of the touch insulating layer TI away from the first touch layer ML1.

[0152] In some embodiments, a plurality of touch signal lines TSL are located in the second touch layer ML2.

[0153] In some embodiments, the orthographic projection of the inorganic insulating layer IOL onto the substrate BS at least partially overlaps with the orthographic projection of the plurality of bonding pins BPS onto the substrate BS. In some embodiments, each touch signal line in the plurality of touch signal lines TSL extends through the touch insulating layer TI, the buffer layer BUF, the inorganic insulating layer IOL, and the first planarization layer PLN1 to connect to a corresponding bonding pin in the plurality of bonding pins BPS. Optionally, the display device includes a fifth via v5. Each touch signal line in the plurality of touch signal lines TSL is connected to a corresponding bonding pin in the plurality of bonding pins BPS through the fifth via v5. In one example, the fifth via v5 extends through the touch insulating layer TI, the buffer layer BUF, the inorganic insulating layer IOL, and the first planarization layer PLN1.

[0154] Figure 22 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure. Figure 23The structure of corresponding bonding pins in a display device according to some embodiments of the present disclosure is shown. Figure 24 This is a plan view of a portion of the bonding pin region of a display device according to some embodiments of the present disclosure. (Refer to...) Figures 22 to 24 In some embodiments, the bonding pin region BPR of the peripheral region PA of the display device includes a substrate BS, a first signal line layer SL1 on the substrate BS, a passivation layer PVX on the side of the first signal line layer SL1 away from the substrate BS, a plurality of bonding pins BPS in a second signal line layer SL2 on the side of the passivation layer PVX away from the first signal line layer SL1, a first planarization layer PLN1 on the side of the second signal line layer SL2 away from the passivation layer PVX, and a touch insulating layer TI on the side of the first planarization layer PLN1 away from the plurality of bonding pins BPS.

[0155] In some embodiments, the display device includes a plurality of touch signal lines TSL located at least partially in a peripheral region PA. In some embodiments, in the peripheral region PA and outside the bonding pin region BPR, the display device includes a substrate BS, a passivation layer PVX on the substrate BS, a first planarization layer PLN1 on the side of the passivation layer PVX away from the substrate BS, an inorganic insulating layer IOL on the side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF on the side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a touch insulating layer TI on the side of the buffer layer BUF away from the inorganic insulating layer IOL, and a plurality of touch signal lines TSL on the side of the touch insulating layer TI away from the buffer layer BUF.

[0156] In some embodiments, in the display area DA, the display device includes a pixel driving circuit board PCS, a plurality of light-emitting elements LE located on the pixel driving circuit board PCS, an encapsulation layer EN located on the side of the plurality of light-emitting elements LE away from the pixel driving circuit board PCS, an inorganic insulating layer IOL located on the side of the encapsulation layer EN away from the plurality of light-emitting elements LE, a buffer layer BUF located on the side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on the side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on the side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on the side of the touch insulating layer TI away from the first touch layer ML1. In some embodiments, a plurality of touch signal lines TSL are located in the second touch layer ML2.

[0157] In some embodiments, the orthographic projection of the inorganic insulating layer IOL onto the substrate BS at least partially overlaps with the orthographic projection of the plurality of bonding pins BPS onto the substrate BS. In some embodiments, each touch signal line in the plurality of touch signal lines TSL extends through the touch insulating layer TI, the buffer layer BUF, the inorganic insulating layer IOL, and the first planarization layer PLN1 to connect to a corresponding bonding pin in the plurality of bonding pins BPS. Optionally, the display device includes a fifth via v5. Each touch signal line in the plurality of touch signal lines TSL is connected to a corresponding bonding pin in the plurality of bonding pins BPS through the fifth via v5. In one example, the fifth via v5 extends through the touch insulating layer TI, the buffer layer BUF, the inorganic insulating layer IOL, and the first planarization layer PLN1.

[0158] In some embodiments, each of the multiple bonding pins (BPS) includes a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4. Optionally, the first edge E1 and the second edge E2 are opposite to each other. Optionally, the third edge E3 and the fourth edge E4 are opposite to each other. The first edge E1 and the second edge E2 are connected via the third edge E3 and via the fourth edge E4. The third edge E3 and the fourth edge E4 are connected via the first edge E1 and via the second edge E2. The first edge E1, the second edge E2, the third edge E3, and the fourth edge E4 surround the central portion CP of each bonding pin.

[0159] In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the first edge E1 on the substrate BS, substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the second edge E2 on the substrate BS, substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the third edge E3 on the substrate BS, and substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the fourth edge E4 on the substrate BS.

[0160] In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS and the orthographic projection of the central portion CP of each bonding pin on the substrate BS are at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%) non-overlapping.

[0161] Figure 25 The diagram illustrates the connection between the bonding pin and the touch signal line in a display device according to some embodiments of the present disclosure. Figure 26 This is a plan view of a portion of the bonding pin region of a display device according to some embodiments of the present disclosure. (Refer to...) Figure 25 and Figure 26 as well as Figure 23 In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the first edge E1 on the substrate BS at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%). In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS does not overlap with the orthographic projection of the second edge E2 on the substrate BS at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%). In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS and the orthographic projection of the third edge E3 on the substrate BS are at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%) non-overlapping. In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS and the orthographic projection of the fourth edge E4 on the substrate BS are at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%) non-overlapping. In some embodiments, the orthographic projection of the touch insulating layer TI on the substrate BS and the orthographic projection of the central portion CP on the substrate BS are at least partially (e.g., at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, or at least 95%) non-overlapping.

[0162] Figure 27 The diagram illustrates the connection between the bonding pins and the touch signal line in a display device according to some embodiments of the present disclosure. (Refer to...) Figure 27In some embodiments, the first distance d1 is greater than or equal to the sum of the second distance d2 and the third distance d3. In some embodiments, the first distance d1 represents the minimum distance between the orthographic projection of the portion of the corresponding touch signal line located in the fifth via v5 onto the substrate and the orthographic projection of the location of a portion of the corresponding bonding pin onto the substrate, where the surface of the portion changes from being covered by an insulating layer to being exposed. In one example, the insulating layer includes an inorganic insulating layer IOL, a buffer layer BUF, a touch insulating layer TI, and a first planarization layer PLN1. The second distance d2 is the minimum distance between the orthographic projection of the location of a portion of the corresponding bonding pin (where the surface of the portion changes from being covered by an insulating layer to being exposed) onto the substrate and the orthographic projection of a location of the corresponding bonding pin (where the slope angle of the insulating layer covering the portion of the corresponding bonding pin changes from a positive value to substantially zero) onto the substrate. The third distance d3 represents the maximum process deviation of the display device. As used herein, the term "process deviation" refers to the difference between a component and its design requirements due to various factors during the manufacturing process. Process deviations can be caused by factors such as materials, processing techniques, equipment, and environment.

[0163] Figure 28 The diagram illustrates the connection between the bonding pins and the touch signal line in a display device according to some embodiments of the present disclosure. (Refer to...) Figure 28 In some embodiments, the bonding pin region BPR of the peripheral region PA of the display device includes a substrate BS, a first signal line layer SL1 located on the substrate BS, a passivation layer PVX located on the side of the first signal line layer SL1 away from the substrate BS, a plurality of bonding pins BPS in a second signal line layer SL2 located on the side of the passivation layer PVX away from the first signal line layer SL1, and a first planarization layer PLN1 located on the side of the second signal line layer SL2 away from the passivation layer PVX.

[0164] In some embodiments, the display device includes a plurality of touch signal lines TSL at least partially located in a peripheral region PA. In some embodiments, each touch signal line in the plurality of touch signal lines TSL includes a first portion P1 and a second portion P2 connected to each other. Optionally, the second portion P2 is connected to a corresponding bonding pin in a plurality of bonding pins BPS via the first portion P1. Optionally, the first portion P1 is located in a first touch layer ML1, and the second portion P2 is located in a second touch layer ML2.

[0165] In some embodiments, within the peripheral region PA and outside the bonding pin region BPR, the display device includes a substrate BS, a passivation layer PVX on the substrate BS, a first planarization layer PLN1 on the side of the passivation layer PVX away from the substrate BS, an inorganic insulating layer IOL on the side of the first planarization layer PLN1 away from the passivation layer PVX, a buffer layer BUF on the side of the inorganic insulating layer IOL away from the first planarization layer PLN1, a first portion P1 of each touch signal line in a plurality of touch signal lines TSL on the side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI on the side of the first portion P1 away from the buffer layer BUF, and a second portion of each touch signal line in a plurality of touch signal lines TSL on the side of the touch insulating layer TI away from the first portion P1.

[0166] In some embodiments, in the display area DA, the display device includes a pixel driving circuit board PCS, a plurality of light-emitting elements LE located on the pixel driving circuit board PCS, an encapsulation layer EN located on the side of the plurality of light-emitting elements LE away from the pixel driving circuit board PCS, an inorganic insulating layer IOL located on the side of the encapsulation layer EN away from the plurality of light-emitting elements LE, a buffer layer BUF located on the side of the inorganic insulating layer IOL away from the encapsulation layer EN, a first touch layer ML1 located on the side of the buffer layer BUF away from the inorganic insulating layer IOL, a touch insulating layer TI located on the side of the first touch layer ML1 away from the buffer layer BUF, and a second touch layer ML2 located on the side of the touch insulating layer TI away from the first touch layer ML1.

[0167] In some embodiments, the display device includes a sixth via v6. The second portion P2 is connected to the first portion P1 via the sixth via v6. In one example, the sixth via v6 extends through the touch insulating layer TI.

[0168] In some embodiments, the display device further includes a seventh via v7. The first portion P1 is connected to a corresponding bonding pin of a plurality of bonding pins BPS via the seventh via v7. In one example, the seventh via v7 extends through the buffer layer BUF, the inorganic insulating layer IOL, and the first planarization layer PLN1.

[0169] In some embodiments, the orthographic projection of the inorganic insulating layer IOL on the substrate BS at least partially overlaps with the orthographic projection of the plurality of bonding pins BPS on the substrate BS.

[0170] Figure 29 The diagram illustrates the connection between the bonding pins and the touch signal line in a display device according to some embodiments of the present disclosure. (Refer to...) Figure 29The display device includes a plurality of touch signal lines TSLs at least partially located in a peripheral region PA. In some embodiments, each touch signal line in the plurality of touch signal lines TSLs includes a first portion P1 and a second portion P2 connected to each other. Optionally, the second portion P2 is connected to a corresponding bonding pin in a plurality of bonding pins BPS through the first portion P1. Optionally, the first portion P1 is located in a first touch layer ML1, and the second portion P2 is located in a second touch layer ML2.

[0171] In some embodiments, the display device includes a sixth via v6. The second portion P2 is connected to the first portion P1 via the sixth via v6. In one example, the sixth via v6 extends through the touch insulating layer TI.

[0172] In some embodiments, the display device further includes a seventh via v7. The first portion P1 is connected to a corresponding bonding pin in a plurality of bonding pins BPS via the seventh via v7. In one example, a third via v3 extends through the buffer layer BUF, the inorganic insulating layer IOL, and the first planarization layer PLN1.

[0173] In some embodiments, the display device further includes an eighth via v8. The first portion P1 is connected to a corresponding bonding pin in a plurality of bonding pins BPS via the eighth via v8. In one example, the eighth via v8 extends through the buffer layer BUF, the inorganic insulating layer IOL, and the first planarization layer PLN1.

[0174] In some embodiments, refer to Figure 29 The fourth distance d4 is greater than the fifth distance d5, where the fourth distance d4 represents the minimum distance between the orthographic projection of the portion of the first part P1 located in the seventh hole v7 on the substrate and the orthographic projection of the portion of the first part P1 located in the eighth hole v8 on the substrate; the fifth distance d5 represents the minimum distance between the orthographic projection of the portion of the first part P1 located in the seventh via v7 on the substrate and the orthographic projection of the position of a portion of the corresponding bonding pin BPS on the substrate, at which the surface of the portion changes from being covered by an insulating layer to being exposed.

[0175] On the other hand, this disclosure also provides a method for manufacturing a display device having a display area and a peripheral area. The peripheral area includes a bonding pin area. In some embodiments, the method includes: forming a pixel driving circuit substrate in the display area, forming a plurality of light-emitting elements on the pixel driving circuit substrate, and forming an encapsulation layer on the side of the plurality of light-emitting elements away from the pixel driving circuit substrate.

[0176] In some embodiments, the method further includes forming a plurality of bonding pins in the bonding pin region of the peripheral region.

[0177] In some embodiments, the method further includes forming an inorganic insulating layer on the side of the encapsulation layer in the display area away from the substrate, and on the side of a plurality of bonding pins in the bonding pin area of ​​the peripheral area away from the substrate.

[0178] In some embodiments, the method further includes: forming a buffer layer on the side of the inorganic insulating layer away from the encapsulation layer in the display area; forming a first touch layer on the side of the buffer layer away from the inorganic insulating layer; forming a touch insulating layer on the side of the first touch layer away from the buffer layer; forming a second touch layer on the side of the touch insulating layer away from the buffer layer; forming a cover layer on the side of the second touch layer away from the touch insulating layer; and forming a black matrix and a color filter on the side of the cover layer away from the touch insulating layer. Optionally, a polymeric organic material is used to form the buffer layer, the touch insulating layer, and the cover layer.

[0179] In some embodiments, the method further includes: at least partially removing a portion of the inorganic insulating layer located in the bonding pin region to expose at least a portion of each of the plurality of bonding pins.

[0180] In some embodiments, the method further includes: forming a first signal line layer on a substrate in the bonding pin region; forming a passivation layer on the side of the first signal line layer away from the substrate; forming a second signal line layer on the side of the passivation layer away from the first signal line layer; forming a first planarization layer on the side of the second signal line layer away from the passivation layer; and forming a plurality of bonding pins on the side of the first planarization layer away from the second signal line layer.

[0181] In some embodiments, the method further includes: forming a first signal line layer on a substrate in a bonding pin region; forming a passivation layer on the side of the first signal line layer away from the substrate; forming a plurality of bonding pins in a second signal line layer on the side of the passivation layer away from the first signal line layer; and forming a first planarization layer on the side of the second signal line layer away from the passivation layer.

[0182] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A display device, comprising a display area and a peripheral area; wherein In the display area, the display device includes a pixel driving circuit board, a plurality of light-emitting elements located on the pixel driving circuit board, and an encapsulation layer located on the side of the plurality of light-emitting elements away from the pixel driving circuit board; And an inorganic insulating layer located on the side of the encapsulation layer away from the plurality of light-emitting elements; In the bonding pin region of the peripheral area, the display device includes: a substrate; a plurality of bonding pins located on the substrate; and The orthographic projection of the inorganic insulating layer on the substrate does not overlap at least partially with the orthographic projection of the plurality of bonding pins on the substrate; The display area also includes: A buffer layer is located on the side of the inorganic insulating layer that is away from the encapsulation layer; The first touch layer is located on the side of the buffer layer away from the inorganic insulating layer; A touch-insulating layer is located on the side of the first touch layer away from the buffer layer; A second touch layer, located on the side of the touch insulating layer away from the first touch layer; and A covering layer is located on the side of the second touch layer away from the touch insulating layer; The buffer layer, the touch insulating layer, and the covering layer are made of polymeric organic materials. The display area also includes a black matrix and a color filter located on the side of the covering layer away from the second touch layer; The black matrix and the color filter are in direct contact with the coating layer.

2. The display device according to claim 1, wherein The orthographic projection of the inorganic insulating layer on the substrate does not overlap with the orthographic projection of the plurality of bonding pins on the substrate.

3. The display device according to claim 1, further comprising a plurality of touch signal lines at least partially located in the peripheral area; wherein Each of the plurality of touch signal lines extends at least through the touch insulating layer, the buffer layer, and the inorganic insulating layer to connect with a corresponding bonding pin among the plurality of bonding pins; Each of the touch signal lines is located at least partially in the second touch layer.

4. The display device according to claim 3, wherein Each of the bonding pins includes a first edge, a second edge, a third edge, and a fourth edge; The orthographic projection of the touch insulating layer on the substrate substantially covers the orthographic projection of the first edge on the substrate, substantially covers the orthographic projection of the second edge on the substrate, substantially covers the orthographic projection of the third edge on the substrate, and substantially covers the orthographic projection of the fourth edge on the substrate; The first edge, the second edge, the third edge, and the fourth edge surround the central portion of each bonding pin; as well as The orthographic projection of the touch insulating layer on the substrate does not at least partially overlap with the orthographic projection of the central portion of each bonding pin on the substrate.

5. The display device according to claim 3, wherein Each of the bonding pins includes a first edge, a second edge, a third edge, and a fourth edge; The orthographic projection of the touch insulating layer on the substrate does not overlap at least partially with the orthographic projection of the first edge on the substrate, does not overlap at least partially with the orthographic projection of the second edge on the substrate, does not overlap at least partially with the orthographic projection of the third edge on the substrate, and does not overlap at least partially with the orthographic projection of the fourth edge on the substrate. The first edge, the second edge, the third edge, and the fourth edge surround the central portion of each bonding pin; as well as The orthographic projection of the touch insulating layer on the substrate does not at least partially overlap with the orthographic projection of the central portion of each bonding pin on the substrate.

6. The display device according to claim 3, further comprising a first via; wherein Each touch signal line is connected to the corresponding bonding pin through the first via; The insulating layer between the exposed surface of the corresponding bonding pin and the first via includes a sloped portion and a non-sloping portion; Along the direction from the exposed surface of the corresponding bonding pin to the first via, the width of the non-sloping portion is greater than the maximum width of the first via.

7. The display device according to claim 3, further comprising a second via and a third via; in, Each touch signal line includes a first part located in the first touch layer and a second part located in the second touch layer; The second part is connected to the first part through the second via; and The first part is connected to the corresponding bonding pin through the third via.

8. The display device according to claim 3, further comprising a second via, a third via, and a fourth via; in, Each touch signal line includes a first part located in the first touch layer and a second part located in the second touch layer; The second part is connected to the first part through the second via; The first part is connected to the corresponding bonding pin through the third via and the fourth via, respectively.

9. The display device according to claim 8, wherein, The fourth distance is greater than the fifth distance; The fourth distance represents the minimum distance between the orthographic projection of the portion of the first part located in the third via on the substrate and the orthographic projection of the portion of the first part located in the fourth via on the substrate. as well as The fifth distance represents the minimum distance between the orthographic projection of the portion of the first part located in the third via on the substrate and the orthographic projection of the position of a portion of the corresponding bonding pin on the substrate, at which the surface of the portion transitions from being covered by an insulating layer to being exposed.

10. The display device according to claim 3, further comprising a first via; in, Each touch signal line is connected to its corresponding bonding pin via the first via; and The first via extends through the touch insulating layer, the buffer layer, and the inorganic insulating layer.

11. The display device according to claim 3, further comprising a fifth via; in, Each touch signal line is connected to its corresponding bonding pin via the fifth via; and The fifth via extends through the touch insulating layer, the buffer layer, the inorganic insulating layer, and the first planarization layer, the first planarization layer being located on the side of the inorganic insulating layer away from the buffer layer.

12. The display device according to any one of claims 1 to 11, wherein in the peripheral region, it further includes a first voltage supply line configured to provide a first voltage supply signal to the display area and a second voltage supply line configured to provide a second voltage supply signal to the display area; in, The orthographic projection of at least one of the first voltage supply line or the second voltage supply line on the substrate at least partially overlaps with the orthographic projection of the plurality of bonding pins on the substrate.

13. The display device according to any one of claims 1 to 3, wherein, In the bonding pin area of ​​the peripheral region, the display device includes: The first signal line layer is located on the substrate. A passivation layer is located on the side of the first signal line layer away from the substrate. The second signal line layer is located on the side of the passivation layer away from the first signal line layer; A first planarization layer is located on the side of the second signal line layer away from the passivation layer; and The plurality of bonding pins are located on the side of the first planarization layer away from the second signal line layer.

14. The display device according to claim 13, wherein, Each of the plurality of bonding pins is in direct contact with the first planarization layer; The first planarization layer is in direct contact with each of the bonding pins in a first region and is not in contact with each of the bonding pins in a second region, wherein the second region is adjacent to the first region; The surface of the first planarization layer away from the substrate includes a first portion that is in direct contact with each of the bonding pins and a second portion that is not in contact with each of the bonding pins, the first portion and the second portion being located on the same side of the first planarization layer; Relative to the same horizontal plane, the first relative height is greater than the second relative height; The first relative height is the height of the first portion relative to the same horizontal plane; and The second relative height is the height of the second part relative to the same horizontal plane.

15. The display device according to any one of claims 1 to 3, wherein, In the bonding pin area of ​​the peripheral region, the display device includes: The first signal line layer is located on the substrate. A passivation layer is located on the side of the first signal line layer away from the substrate. The plurality of bonded pins located on a second signal line layer, the second signal line layer being located on the side of the passivation layer away from the first signal line layer; and A first planarization layer is located on the side of the second signal line layer away from the passivation layer.

16. A method of manufacturing a display device, the display device having a display area and a peripheral area, the peripheral area including a bonding pin area; in, The method includes: In the display area, a pixel driving circuit substrate is formed, a plurality of light-emitting elements are formed on the pixel driving circuit substrate, and an encapsulation layer is formed on the side of the plurality of light-emitting elements away from the pixel driving circuit substrate; In the bonding pin region, a plurality of bonding pins are formed on the substrate. An inorganic insulating layer is formed on the side of the encapsulation layer away from the substrate in the display area, and on the side of the plurality of bonding pins away from the substrate in the bonding pin area of ​​the peripheral area; After forming the inorganic insulating layer, a black matrix and a color filter are formed on the side of the plurality of light-emitting elements away from the pixel driving circuit substrate in the display area; and After forming the black matrix and the color filter, at least a portion of the inorganic insulating layer located in the bonding pin region is removed to expose at least a portion of each of the plurality of bonding pins.

17. The method of claim 16, further comprising, in the bonding pin region: A first signal line layer is formed on the substrate. A passivation layer is formed on the side of the first signal line layer away from the substrate. A second signal line layer is formed on the side of the passivation layer away from the first signal line layer; A first planarization layer is formed on the side of the second signal line layer away from the passivation layer; as well as The plurality of bonding pins are formed on the side of the first planarization layer away from the second signal line layer.

18. A display device, comprising a display area and a peripheral area; in, In the display area, the display device includes a pixel driving circuit board, a plurality of light-emitting elements located on the pixel driving circuit board, and an encapsulation layer located on the side of the plurality of light-emitting elements away from the pixel driving circuit board; And an inorganic insulating layer located on the side of the encapsulation layer away from the plurality of light-emitting elements; In the bonding pin region of the peripheral area, the display device includes: a substrate; a plurality of bonding pins located on the substrate; and The orthographic projection of the inorganic insulating layer on the substrate does not overlap at least partially with the orthographic projection of the plurality of bonding pins on the substrate; The display device further includes: Multiple touch signal lines, at least partially located in the surrounding area; and Multiple first vias; Each touch signal line is connected to a corresponding bonding pin among the plurality of bonding pins through a first via among the plurality of first vias; and The exposed surface of the corresponding bonding pin is spaced apart from the first via.

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